JP2011216918A - Resin sealed type semiconductor device and circuit member for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resin sealed type semiconductor device where the number of pins can be increased and reliability is high, and to provide a circuit member for a semiconductor device for stably manufacturing such a resin sealed type semiconductor device.SOLUTION: The resin sealed type semiconductor device comprises a plurality of terminal parts that are arranged so that the surfaces of outer terminals form one plane, a semiconductor element that is electrically connected with the surface of an inner terminal of each terminal part by wires, and a resin member for sealing the terminal parts and the semiconductor element so that at least part of the surface of the outer terminal of each terminal is exposed outside, the terminal part having a protruding portion at the periphery of the surface of the inner terminal, and the surface of the inner terminal being in a concave shape.

Description

  The present invention relates to a surface-mount type resin-encapsulated semiconductor device and a circuit member for a semiconductor device having a circuit portion formed thin by plating.

  In recent years, semiconductor devices have been increasingly integrated and highly functional, as represented by LSI ASICs, due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter and shorter electronic devices. It is going on. In such highly integrated and highly functional semiconductor devices, it is required to increase the total sum of external terminals (pins) and further increase the number of terminals (pins).

  In order to meet the demand for multi-terminals (pins) as described above, multi-terminal (pin) ICs, particularly ASICs typified by gate arrays and standard cells, or semiconductor devices such as microcomputers, DSPs (Digital Signal Processors), etc. In some cases, a lead frame member is used in the manufacture. Specifically, there is a surface mount type package such as QFP (Quad Flat Package), and the QFP has been put into practical use up to the 300 pin class.

  The QFP has a cross-sectional structure as shown in FIG. 13, and is manufactured using the lead frame member shown in FIG. That is, the semiconductor element 120 is mounted on the die pad 111 of the lead frame member 110, and the inner lead distal end portion 112 and the terminal (electrode pad) 121 of the semiconductor element 120 that are subjected to processing such as silver plating and gold plating are connected to the wire 130. Connect. After that, the resin 140 is sealed, the dam bar portion of the lead frame member 110 is cut, and the outer lead portion 113 is bent into a gull wing shape to produce a QFP. Such a QFP has a structure in which outer leads for electrical connection with an external circuit are provided in four directions of the package, and has been developed as one that can cope with the increase in the number of terminals (pins). The lead frame member 110 uses a metal plate having excellent electrical conductivity and high strength such as Kovar, 42 alloy (42% Ni-Fe alloy), copper alloy, etc., and its outer shape processing is a stamping method or a comparison. For a high-definition one, it is performed by an etching method using a photolithography technique. In QFP, by reducing the pitch of the external terminals (outer leads), the number of terminals has been increased without increasing the package size.

  However, in the case of the etching method described above, the outer lead itself becomes thinner and narrower and the strength decreases as the plate thickness of the outer lead is reduced and the pitch is reduced. This makes it difficult to cope with skew and to maintain flatness, and it is difficult to maintain package mounting accuracy during mounting.

  On the other hand, by reducing the thickness of the lead frame material, using a two-step etching method, devising the pattern shape, and performing external processing while partially thinning the internal terminals (inner leads) In order to cope with the increase in the number of terminals, it is possible to reduce the pitch of the inner leads.

  However, in such a lead frame member, during wire bonding between the terminal of the semiconductor element and the inner lead, due to insufficient mechanical strength of the thin part, it is pulled to the capillary (hereinafter, this phenomenon is called up), and the thin part There is a problem that is deformed.

  Resin sealing called BGA (Ball Grid Array), which is a surface mount type package having solder balls as external terminals of the package in order to avoid the mounting efficiency and mountability problems of the conventional QFP package as described above Type semiconductor devices have been developed. BGA is a generic term for surface-mount semiconductor devices (plastic packages) in which solder balls as external terminals are arranged in a matrix (array) on the back surface.

  In order to increase the number of input terminals, a BGA usually has a semiconductor element mounted on one side of a double-sided wiring board and an external terminal electrode with a solder ball mounted on the other side. The continuity was taken. By arranging the solder balls in an array, the terminal pitch interval can be made wider than that of a conventional semiconductor device using a lead frame member. As a result, the mounting process of the semiconductor device is not made difficult and the number of input / output terminals is increased. We were able to cope with.

  However, this BGA has a circuit connected to a semiconductor element to be mounted with a wire on one surface of the substrate, and an external terminal electrode for mounting on a printed circuit board after forming a semiconductor device on the other surface of the substrate, This is a complicated configuration in which these are electrically connected through the through-hole, and the through-hole may be disconnected due to the thermal expansion of the resin, resulting in many problems in terms of production reliability.

  For this reason, a method of manufacturing a semiconductor device as shown in FIGS. 15 and 16 corresponding to simplification of the manufacturing process of the BGA, avoiding deterioration in reliability, increasing the number of pins, and downsizing of the package has been proposed. . In the semiconductor device according to this method, like a conventional BGA using a double-sided wiring board, a part of the external terminals for connecting to an external circuit is arranged on one surface of the semiconductor device so as to be exposed from the sealing resin. It can be a new PBGA (Plastic Ball Grid Array) or CSP (Chip Size Package).

  The semiconductor device manufacturing method shown in FIG. 15 prepares a circuit member 200 in which a circuit part 210 made of a conductive metal is formed on a conductive substrate 220 by plating (FIG. 15A). A semiconductor element 250 is mounted on an insulating member 260 and necessary electrical connection is performed using a wire 255 (FIG. 15B). After that, sealing is performed on the conductive substrate 220 using the resin member 270 (FIG. 15C), and the resin-sealed semiconductor device 280 is peeled from the conductive substrate 220 (FIG. 15D). ). In addition, a solder ball 290 is attached over the exposed circuit portion 210 which is an external terminal to form the semiconductor device 280 (FIG. 15E).

  In the manufacturing method of the semiconductor device, a surface treatment is performed in advance so as to make the one surface of the conductive substrate 220 uneven so that the circuit portion 210 made of the conductive metal formed on the conductive substrate 220 is easily peeled off, and Then, a measure such as performing a peeling treatment to give peelability is taken. Here, examples of the surface treatment include blasting by sandblasting, and examples of the peeling treatment include a method of forming an oxide film on the surface of the conductive substrate.

  In the method for manufacturing the semiconductor device shown in FIG. 16, a conductive substrate 320 is used in which a metal layer 323 is provided on one surface of a substrate 321 by plating or the like, and the metal layer 323 is conductive by plating. A circuit member 300 on which a circuit portion 310 made of metal is formed is prepared (FIG. 16A). Then, the semiconductor element 350 is mounted on the conductive substrate 320 so as to be positioned at the center of the arrangement of the circuit portions 310, and necessary electrical connection is performed using the wires 355 (FIG. 16B). Thereafter, sealing is performed on the conductive substrate 320 using the resin member 370 (FIG. 16C), and the metal layer 323 is dissolved and removed, whereby the resin-sealed semiconductor device 380 is removed from the conductive substrate 320. It is obtained by peeling (FIG. 16D). In addition, a solder ball 390 is attached over the exposed circuit portion 310 that is an external terminal to form the semiconductor device 380 (FIG. 16E).

  However, in the manufacture of a resin-sealed semiconductor device using a conventional circuit member, when the semiconductor device is peeled from the conductive substrate, the sealing resin member and the circuit portion are peeled off by the force applied, or the circuit portion Cracks easily occur, which is a problem in terms of reliability.

  The present invention has been made in view of the circumstances as described above. A resin-encapsulated semiconductor device that can cope with an increase in the number of pins and has high reliability, and such a resin-encapsulated semiconductor device can be stably provided. An object of the present invention is to provide a circuit member for a semiconductor device to be manufactured.

  In order to achieve such an object, the resin-encapsulated semiconductor device includes a plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other so that the external terminal surface forms a plane, and The semiconductor element electrically connected to the internal terminal surface of each terminal portion with a wire, and the terminal portion and the semiconductor element are sealed so that at least a part of the external terminal surface of each terminal portion is exposed to the outside. The terminal portion has a protrusion around the inner terminal surface, and the inner terminal surface has a concave shape.

  In addition, a preferable aspect of the resin-encapsulated semiconductor device of the present invention includes a die pad on one plane formed by the terminal portion, and the semiconductor element is mounted on the inner surface of the die pad via an electrically insulating material, The die pad is configured to have a protrusion around the inner surface, and the semiconductor element is mounted on a part of the inner terminal surface of each terminal portion via an electrically insulating material. Furthermore, a preferable aspect of the resin-encapsulated semiconductor device according to the present invention is such that the terminal portion is a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or two or more kinds of metals. It was set as the structure which is the multilayer structure which becomes.

  The circuit member for a semiconductor device according to the present invention includes a substrate and a circuit portion provided on the substrate, the circuit portion includes a plurality of terminal portions, and the terminal portion has a contact surface with the substrate as an external terminal. A structure in which the surface opposite the external terminal surface constitutes an internal terminal surface, a protrusion is formed around the internal terminal surface, and the internal terminal surface is concave. It was. The circuit portion further includes a die pad. The surface of the die pad opposite to the contact surface with the substrate is an internal surface for mounting a semiconductor element, and a protrusion is formed around the internal surface. The configuration is as follows. Furthermore, in a preferred aspect of the circuit member for a semiconductor device of the present invention, the circuit portion is composed of a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or made of two or more kinds of metals. It was set as the structure which is a multilayer structure.

  According to the present invention, the protrusions around the inner terminal surface of the terminal part and the protrusions around the inner surface of the die pad are engaged with the resin member sealing them so that the terminal part and the die pad are securely Since the inner terminal surface to which the wire is connected is concave, the resin-encapsulated semiconductor device is highly reliable, and the terminal portion of the circuit portion of the circuit member for the semiconductor device is Since the protrusion is provided around the inner terminal surface opposite to the substrate contact surface, when the resin sealing is performed on the substrate of the circuit member, the protrusion engages with the resin member to cause the circuit. Since the part is securely fixed, it is possible to prevent the resin member and the circuit part from being peeled off and the circuit part from being cracked in the peeling process of the resin-encapsulated semiconductor device from the substrate. Highly reliable resin-sealed semiconductor device due to its shape It is possible to manufacture.

It is a schematic sectional drawing which shows one Embodiment of the resin sealing type semiconductor device of this invention. It is a schematic sectional drawing which shows other embodiment of the resin sealing type semiconductor device of this invention. It is a schematic sectional drawing which shows other embodiment of the resin sealing type semiconductor device of this invention. It is a top view which shows one Embodiment of the circuit member for semiconductor devices of this invention. It is a schematic sectional drawing in the AA of the circuit member for semiconductor devices shown by FIG. It is a schematic sectional drawing for demonstrating the projection part of the circuit part which comprises the circuit member for semiconductor devices of this invention. It is a top view which shows other embodiment of the circuit member for semiconductor devices of this invention. It is a schematic sectional drawing in the BB line of the circuit member for semiconductor devices shown by FIG. It is a top view which shows other embodiment of the circuit member for semiconductor devices of this invention. It is a schematic sectional drawing in the CC line of the circuit member for semiconductor devices shown by FIG. It is process drawing which shows an example of the manufacturing method of the circuit member for semiconductor devices of this invention. It is process drawing for demonstrating an example of the manufacturing method of the resin sealing type semiconductor device using the circuit member for semiconductor devices of this invention. It is a schematic sectional drawing which shows an example of the conventional QFP. It is a top view which shows an example of the lead frame member used for manufacture of the conventional QFP. It is process drawing for demonstrating the manufacturing method of the conventional resin-encapsulated semiconductor device. It is process drawing for demonstrating the manufacturing method of the conventional resin-encapsulated semiconductor device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Resin encapsulated semiconductor device>
The resin-encapsulated semiconductor device of the present invention will be described.
FIG. 1 is a schematic cross-sectional view showing an embodiment of a resin-encapsulated semiconductor device according to the present invention. In order to make the structure of the semiconductor device easier to understand, an encapsulating resin member is represented by a virtual line (two-dot chain line). ).

  In FIG. 1, a resin-encapsulated semiconductor device 1 is a PBGA type resin-encapsulated semiconductor device, and a plurality of terminal portions 3 are arranged such that their external terminal surfaces 3 c form a single plane. The die pad 2 is arranged at the approximate center of the array so that the external terminal surface 3c of the terminal portion 3 and the external surface 2c are in the same plane, and the semiconductor element 5 is disposed on the internal surface 2b of the die pad 2 via the electrically insulating material 6. The side opposite to the element surface is fixed and mounted. The terminal 5 a of the semiconductor element 5 is connected to the internal terminal surface 3 b of the terminal portion 3 by a wire 7. And the terminal part 3, the die pad 2, the semiconductor element 5, and the wire 7 are sealed by the resin member 8 so that the external terminal surface 3c of the terminal part 3 and the external surface 2c of the die pad 2 are exposed to the outside. The resin member 8 can be made of an electrically insulating resin material conventionally used in resin-encapsulated semiconductor devices, and is not particularly limited. A solder ball 9 is attached to the external terminal surface 3c of the terminal portion 3 exposed to the outside.

  In such a resin-encapsulated semiconductor device 1 of the present invention, the die pad 2 has the protrusions 2a around the inner surface 2b, and each terminal part 3 has the protrusions 3a around the inner terminal surface 3b. Structure. The protrusion 2a of the die pad 2 and the protrusion 3a of the terminal 3 are engaged with the resin member 8 sealing them, and the die pad 2 and the terminal 3 are securely fixed, and the resin sealing type The semiconductor device 1 has high reliability.

The die pad 2 and the terminal portion 3 can have a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more kinds of metals. Further, the protrusion 2a of the die pad 2 and the protrusion 3a of the terminal 3 are at least parallel to a plane formed by the die pad 2 and the terminal 3 (in FIG. 1, parallel to the back surface of the resin-encapsulated semiconductor device 1). It is preferable to project in a length of about 2 to 5 μm in any direction (left and right direction in the drawing).
The resin-encapsulated semiconductor device 1 may not include the solder balls 9. Moreover, a plating layer for connection may be provided on the internal terminal surface 3 b of the terminal portion 3. This connection plating layer can be single layer plating made of any of Au, Pt, Ag, etc., and the thickness is preferably about 0.1 to 10 μm.

FIG. 2 is a schematic cross-sectional view showing another embodiment of the resin-encapsulated semiconductor device of the present invention. In order to facilitate understanding of the structure of the semiconductor device, the encapsulating resin member is represented by virtual lines (two points). This is indicated by a chain line).
In FIG. 2, the resin-encapsulated semiconductor device 11 is a PBGA type resin-encapsulated semiconductor device, and a plurality of terminal portions 13 are arranged so that their external terminal surfaces 13 c form a single plane. A semiconductor element 15 is mounted on a part of the internal terminal surface 13b with an electrically insulating material 16 interposed between the semiconductor element 15 and the side opposite to the element surface. The terminal 15 a of the semiconductor element 15 is connected by a wire 17 to a connecting plating layer 14 formed on the internal terminal surface 13 b of the terminal portion 13. And the terminal part 13, the semiconductor element 15, and the wire 17 are sealed with the resin member 18 so that the external terminal surface 13c of the terminal part 13 may be exposed to the outside. The resin member 18 can be made of an electrically insulating resin material conventionally used in resin-encapsulated semiconductor devices, and is not particularly limited. A solder ball 19 is attached to the external terminal surface 13c of the terminal portion 13 exposed to the outside.

In such a resin-encapsulated semiconductor device 11 of the present invention, each terminal portion 13 has a structure having a protruding portion 13a around the internal terminal surface 13b. Therefore, since the protruding portion 13a of the terminal portion 13 is engaged with the resin member 18 sealing them and the terminal portion 13 is securely fixed, the resin-encapsulated semiconductor device 11 has high reliability. It will be a thing.
The terminal portion 13 can have a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more metals. The protruding portion 13a of the terminal portion 13 is at least 2 in the direction parallel to at least one plane formed by the terminal portion 13 (in FIG. 2, the direction parallel to the back surface of the resin-encapsulated semiconductor device 11 (the left-right direction in the drawing)). It is preferable to protrude with a length of about 5 μm.

Moreover, the plating layer 14 for connection can be made into single layer plating which consists of Au, Pt, Ag, etc., and thickness is preferable about 0.1-10 micrometers.
The resin-encapsulated semiconductor device 11 may not include the solder ball 19. Further, the connection plating layer 14 may not be provided on the internal terminal surface 13 b of the terminal portion 13.

FIG. 3 is a schematic cross-sectional view showing another embodiment of the resin-encapsulated semiconductor device of the present invention. In order to facilitate understanding of the structure of the semiconductor device, the encapsulating resin member is represented by virtual lines (two points). This is indicated by a chain line).
In FIG. 3, the resin-encapsulated semiconductor device 21 is a PBGA type resin-encapsulated semiconductor device, and a plurality of terminal portions 23 are arranged so that their external terminal surfaces 23 c form a single plane. The semiconductor element 25 is disposed at the approximate center of the array. The terminal 25 a of the semiconductor element 25 is connected by a wire 27 to a connection plating layer 24 formed on the internal terminal surface 23 b of the terminal portion 23. The terminal portion 23, the semiconductor element 25, and the wire 27 are sealed with a resin member 28 so that the external terminal surface 23 c of the terminal portion 23 and the side opposite to the element surface of the semiconductor element 25 are exposed to the outside. The resin member 28 can be made of an electrically insulating resin material conventionally used in resin-encapsulated semiconductor devices, and is not particularly limited. A solder ball 29 is attached to the external terminal surface 23c of the terminal portion 23 exposed to the outside.

  In such a resin-encapsulated semiconductor device 21 of the present invention, each terminal portion 23 has a structure having a protruding portion 23a around the internal terminal surface 23b. The projecting portion 23a of the terminal portion 23 can be engaged with the resin member 28 that seals the terminal portion 23 to securely fix the terminal portion 23, and the resin-encapsulated semiconductor device 21 has high reliability. It becomes.

  The terminal portion 23 can have a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more metals. The protruding portion 23a of the terminal portion 23 is at least 2 in the direction parallel to at least one plane formed by the terminal portion 23 (in FIG. 3, the direction parallel to the back surface of the resin-encapsulated semiconductor device 21 (the left-right direction in the drawing)). It is preferable to protrude with a length of about 5 μm.

Moreover, the plating layer 24 for connection can be made into single layer plating which consists of Au, Pt, Ag, etc., and thickness is preferable about 0.1-10 micrometers.
The resin-encapsulated semiconductor device 21 may not include the solder balls 29. Further, the connection plating layer 24 may not be provided on the internal terminal surface 23 b of the terminal portion 23.

<Circuit members for semiconductor devices>
4 is a plan view showing an embodiment of a circuit member for a semiconductor device of the present invention, and FIG. 5 is a schematic cross-sectional view taken along line AA of the circuit member for a semiconductor device shown in FIG.
4 and 5, the circuit member 51 for a semiconductor device of the present invention includes a substrate 52 and a circuit portion 53 provided on one surface of the substrate 52, and the circuit portion 53 is a rectangular die pad 54. And a plurality of terminal portions 55 arranged in one row in the four directions of the die pad 54 at predetermined intervals.

  The substrate 52 is made of a conductive substrate such as copper, iron-nickel alloy, iron-nickel-chromium alloy, iron-nickel-carbon alloy, Cu, Ni, Ag, Pd, Au or the like provided on at least the circuit portion 53. Any of the insulating substrates having a conductive layer made of these alloys may be used. In the method of manufacturing a circuit member for a semiconductor device described later, when the circuit portion 53 is formed by an electrolytic plating method, at least the circuit portion 53 is A substrate having a conductive surface is used. Further, in the manufacture of a resin-encapsulated semiconductor device using the circuit member for a semiconductor device of the present invention, a metal layer (for example, a copper layer) that can be dissolved and removed is used for peeling the semiconductor device after resin encapsulation. A previously formed substrate 52 may be used.

  The circuit portion 53 is formed with a protrusion around the surface opposite to the contact surface with the substrate 52, and in this embodiment, includes a die pad 54 and a terminal portion 55. Specifically, a protrusion 54 a is formed around the inner surface 54 b that is the semiconductor element mounting surface of the die pad 54. Further, a protrusion 55a is formed around the internal terminal surface 55b (connection portion with the semiconductor element) of the terminal portion 55. FIG. 6 is a diagram illustrating an example of a cross-sectional shape of the terminal portion 55. The terminal portion 55 has an internal terminal surface 55b that is substantially flat and a protruding portion 55a that protrudes in a direction parallel to the surface of the substrate 52. A so-called mushroom-shaped cross section (FIG. 6A) or a so-called Y-shaped cross section in which the internal terminal surface 55b has a concave shape and the protrusion 55a protrudes obliquely upward with respect to the surface of the substrate 52. (FIG. 6B) may be used. Regardless of the cross-sectional shape as described above, it is preferable that the protrusion 55 a protrudes in a direction parallel to the substrate 52 with a length of about 2 to 5 μm. The same applies to the protrusion 54a of the die pad 54.

  The circuit part 53 including the die pad 54 and the terminal part 55 may have a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more kinds of metals. it can. In the case of a multilayer structure, for example, a substrate in which Pd, Ni, and Pd can be laminated in this order from the substrate 52 side, and a metal layer (for example, a copper layer) that can be dissolved and removed as described above is formed in advance. When 52 is used, Au, Ni, and Pd can be laminated in this order from the substrate 52 (copper layer) side. The thickness of the circuit portion 53 including the die pad 54 and the terminal portion 55 is not particularly limited.

Moreover, the circuit member for semiconductor devices of this invention may not contain a die pad as a circuit part. 7 is a plan view showing an embodiment of a circuit member for a semiconductor device of the present invention that does not include a die pad, and FIG. 8 is a schematic cross-sectional view of the circuit member for a semiconductor device shown in FIG. is there.
7 and 8, the circuit member 61 for a semiconductor device of the present invention includes a substrate 62 and a circuit portion 63 provided on one surface of the substrate 62. The circuit portion 63 is a semiconductor element to be mounted. Are formed of a plurality of terminal portions 65 arranged in a corridor shape at a predetermined interval so as to correspond to the outer shape (shape indicated by a chain line in FIG. 7).
The substrate 62 constituting the semiconductor device circuit member 61 is the same as the substrate 52 described above.

  Further, the circuit part 63 is formed with a protrusion around the surface opposite to the contact surface with the substrate 62. Specifically, the circuit part 63 has an internal terminal surface 65b (connection to a semiconductor element) of the terminal part 65. A projection 65a is formed around the (part). The basic structure of the terminal portion 65 can be the same as that of the terminal portion 55 described above, except that the terminal portion 65 has a size capable of mounting a semiconductor element on a part of the internal terminal surface 65b.

FIG. 9 is a plan view showing another embodiment of the circuit member for a semiconductor device of the present invention that does not include a die pad, and FIG. 10 is a schematic view taken along line CC of the circuit member for a semiconductor device shown in FIG. It is sectional drawing.
9 and 10, a circuit member 71 for a semiconductor device according to the present invention includes a substrate 72 and a circuit portion 73 provided on one surface of the substrate 72. The circuit portion 73 has a semiconductor element at the center. Are arranged with a plurality of terminal portions 75 arranged at a predetermined interval in a corridor shape so as to surround the arrangement portion (the portion indicated by a chain line in FIG. 9).
The substrate 72 constituting the semiconductor device circuit member 71 is the same as the substrate 52 described above.

Further, the circuit portion 73 has a protrusion formed around the surface opposite to the contact surface with the substrate 72. Specifically, the circuit portion 73 has an internal terminal surface 75b (connection to a semiconductor element) of the terminal portion 75. A protrusion 75a is formed around the part. The structure of the terminal portion 75 can be the same as that of the terminal portion 55 described above.
In addition, the shape, arrangement, number, and the like of the circuit portion of the circuit member for a semiconductor device described above are examples, and the present invention is not limited thereto. The circuit member for a semiconductor device of the present invention may be a plurality of impositions in which a plurality of circuit portions are provided on a substrate.

<Method for Manufacturing Circuit Member for Semiconductor Device>
Next, the manufacturing method of the circuit member for semiconductor devices of this invention is demonstrated.
FIG. 11 is a process diagram showing an embodiment of a method for manufacturing a semiconductor device circuit member according to the present invention, taking the semiconductor device circuit member 51 shown in FIGS. 4 and 5 as an example.
In FIG. 11, first, a resist pattern 59 is formed on a substrate 52 (FIG. 11A). The resist pattern 59 has an opening 59a at a location corresponding to the formation site of the circuit portion 53, and the substrate 52 is exposed to the opening 59a. The substrate 52 includes a conductive substrate such as iron-nickel alloy, iron-nickel-chromium alloy, iron-nickel-carbon alloy, and a conductive layer made of Cu, Ni, Ag, Pd, Au, or an alloy thereof on the surface. Insulating substrates can be used.

  In order to facilitate the peeling of the circuit portion 53 from the substrate 52, which will be described later, a treatment such as performing a surface treatment that gives an uneven surface to the surface of the substrate 52 in advance and performing a peeling treatment that gives the peelability is performed. It is preferable to take. Examples of the surface treatment here include blasting by sandblasting, and examples of the peeling treatment include a method of forming an oxide film on the surface of the substrate 52.

  Next, a metal is deposited on the substrate 52 through the resist pattern 59 by electrolytic plating to form a circuit portion 53 including a die pad 54 and a plurality of terminal portions 55 (FIG. 11B). The circuit portion 53 can have a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more of these metals. In the case of a multilayer structure, for example, Pd, Ni, and Pd can be stacked in this order from the substrate 52 side. Further, when the substrate 52 on which a metal layer (for example, a copper layer) that can be dissolved and removed is used in advance, for example, the circuit portion 53 is formed by stacking Au, Ni, and Pd in this order from the substrate 52 side. Also good.

  In the present invention, in forming the circuit portion 53 by electrolytic plating, the metal is deposited to be thicker than the thickness of the resist pattern 59. As a result, the metal deposited in the opening 59a of the resist pattern 59 deposits upward along the inner wall of the opening 59a, and then deposits in the lateral direction along the surface of the resist pattern 59 while rising from the resist pattern 59. To do.

  Next, the resist pattern 59 is removed. The circuit portion 53 thus obtained is provided with protrusions around the surface opposite to the contact surface with the substrate 52 due to the metal deposition in the lateral direction. That is, the die pad 54 in which the protrusion 54a is formed around the inner surface 54b and the terminal portion 55 in which the protrusion 55a is formed around the internal terminal surface 55b are obtained (FIG. 11C).

Next, a method for manufacturing a resin-encapsulated semiconductor device using the circuit member for a semiconductor device of the present invention will be described with reference to FIG. 12 taking the circuit member for a semiconductor device shown in FIGS. 4 and 5 as an example.
First, the semiconductor element 5 is mounted on the die pad 54 of the circuit member 51 for a semiconductor device through the insulating member 6 (FIG. 12A). Next, the terminal 5a of the semiconductor element 5 and the internal terminal surface 55b of the terminal portion 55 of the semiconductor device circuit member 51 are connected using the wire 7 (FIG. 12B). Thereafter, the terminal portion 55, the die pad 54, the semiconductor element 5, and the wire 7 are sealed with the resin member 8 over the conductive substrate 52 (FIG. 12C).

  Next, the resin-encapsulated semiconductor device is peeled from the conductive substrate 52 (FIG. 12D), and then solder balls 9 are attached to the exposed external terminal surfaces of the terminal portions 3 (55) to form the resin-encapsulated type. The semiconductor device 1 is obtained. Since the protrusion 54a is formed around the internal surface 54b, which is the semiconductor element mounting surface of the die pad 54, and the protrusion 55a is formed around the internal terminal surface 55b of the terminal part 55, the above-described substrate 52 In the peeling process of the resin-encapsulated semiconductor device 1, the terminal portion 55 and the die pad 54 are prevented from peeling off from the resin member 8 and cracking.

Next, the present invention will be described in more detail with specific examples.
First, a 0.15 mm thick copper plate (TEC64T 1 / 2H) is prepared as a substrate, a photosensitive resist (AQ2558 manufactured by Asahi Kasei Co., Ltd.) is laminated on the conductive substrate, and a desired photomask is interposed therebetween. It exposed and developed and formed the resist pattern (25 micrometers in thickness).

Next, three plating layers were stacked in the order of the following (1) to (3).
(1) Dipping the substrate in an electrolytic plating solution (cyan Au potassium solution), using the substrate as a negative electrode, and using the anode (Ti / Pt electrode) as a positive electrode, electrolytic plating for 8 minutes at a current density of 0.3 A / dm ² And Au plating of about 0.5 μm was performed.
(2) Again, the substrate is immersed in an electrolytic plating solution (nickel sulfamate solution), the substrate is used as a negative electrode, and the anode (S round nickel; manufactured by Shimura Chemical Co., Ltd.) is used as a positive electrode to a current density of 3 A / dm ² Then, electrolytic plating was performed for 15 minutes, and Ni plating of about 6 to 15 μm was applied.
(3) Finally, the substrate is immersed in an electrolytic plating solution (copper sulfate solution), the substrate is used as the negative electrode, and the anode (phosphorus-containing copper; manufactured by Mitsubishi Materials Corporation) is used as the positive electrode to a current density of 3 A / dm ^2. Then, electrolytic plating was performed for 30 minutes, and Cu plating of about 12 to 30 μm was performed.

  Next, the resist pattern was dissolved and removed with an alkali or an organic solvent to produce a circuit member for a semiconductor device of the present invention as shown in FIGS. The die pad in this circuit member had a height of 30 μm, and was provided with protrusions protruding in the lateral direction with a length of 5 μm around the surface opposite to the contact surface with the substrate. Further, the terminal portion had a height of 32 μm, and was provided with a protrusion protruding in the lateral direction with a length of 6 μm around the surface opposite to the contact surface with the substrate.

  On the other hand, as a comparison, a circuit member for a semiconductor device was produced in the same manner as described above except that (3) Cu plating energization time was 10 minutes in the above three-layer configuration. The die pad in the semiconductor device circuit member had a height of 18 μm, and no protrusions exist around the surface opposite to the contact surface with the substrate. Further, the terminal portion had a height of 20 μm, and no protrusion was present around the surface opposite to the contact surface with the substrate.

  A semiconductor element (with a smaller area than the die pad) is mounted on the die pad of the circuit member for a semiconductor device manufactured as described above via an insulating member (die attach agent). The internal terminal surface of the terminal part of the circuit member was connected using a wire. Next, on the substrate, the die pad, the terminal portion, the semiconductor element, and the wire were sealed with a resin member (a novolac resin (MP-8000 manufactured by Nitto Denko Corporation)). Thereafter, the substrate was etched with an ammonia-based etching solution to separate the resin-encapsulated semiconductor device from the substrate, thereby obtaining a resin-encapsulated semiconductor device.

  When the semiconductor device circuit member of the present invention was used, the obtained resin-encapsulated semiconductor device had good adhesion between the die pad and the terminal portion and the resin member, but the comparative semiconductor device circuit member was used. In some cases, the resulting resin-encapsulated semiconductor device had some terminals dropped off when peeled from the substrate.

  This is useful in manufacturing a resin-encapsulated semiconductor device.

DESCRIPTION OF SYMBOLS 1, 11, 21 ... Resin sealing type semiconductor device 2 ... Die pad 2a ... Projection part 2b ... Internal surface 3, 13, 23 ... Terminal part 3a, 13a, 23a ... Projection part 3b, 13b, 23b ... Internal terminal surface 3c, 13c, 23c ... external terminal surface 5, 15, 25 ... semiconductor element 7, 17, 27 ... wire 8, 18, 28 ... resin member 9, 19, 29 ... solder ball 51, 61, 71 ... semiconductor device circuit member 52 , 62, 72 ... substrate 53, 63, 73 ... circuit part 54 ... die pad 54a ... projection part 55, 65, 75 ... terminal part 55a, 65, 75a ... projection part 55b, 65b, 75b ... internal terminal surface

Claims (7)

A semiconductor provided with a plurality of terminal portions each having an internal terminal surface and an external terminal surface integrated with each other so that the external terminal surface forms a flat surface, and electrically connected to the internal terminal surface of each terminal portion by a wire An element and a resin member encapsulating the semiconductor element to expose at least a part of the external terminal surface of each terminal part to the outside, and the terminal part is a protrusion around the internal terminal surface And a resin-encapsulated semiconductor device characterized in that the inner terminal surface is concave. A die pad is provided on one plane formed by the terminal portion, the semiconductor element is mounted on the inner surface of the die pad via an electrically insulating material, and the die pad has a protrusion around the inner surface. The resin-encapsulated semiconductor device according to claim 1. The resin-encapsulated semiconductor device according to claim 1, wherein the semiconductor element is mounted on a part of an internal terminal surface of each terminal portion via an electrically insulating material. The terminal portion has a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more metals. Item 4. The resin-encapsulated semiconductor device according to any one of Items 3 to 3. In circuit members for semiconductor devices,
A circuit unit provided on the substrate, the circuit unit includes a plurality of terminal units, and the terminal unit has a contact surface with the substrate constituting an external terminal surface, and the external terminal surface A circuit member for a semiconductor device, wherein a surface on the opposite side constitutes an internal terminal surface, a protrusion is formed around the internal terminal surface, and the internal terminal surface is concave. The circuit portion further includes a die pad, and the die pad has a surface opposite to the contact surface with the substrate as an inner surface for mounting a semiconductor element, and a protrusion is formed around the inner surface. The circuit member for a semiconductor device according to claim 5, wherein the circuit member is a semiconductor device. 6. The circuit unit according to claim 5, wherein the circuit portion has a single layer structure made of any one of Cu, Ni, Ag, Pd, and Au, or a multilayer structure made of two or more metals. Item 7. A semiconductor device circuit member according to Item 6.

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