JP2011216797A - Method of mounting electronic component on multi-piece substrate - Google Patents

Method of mounting electronic component on multi-piece substrate Download PDF

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JP2011216797A
JP2011216797A JP2010085614A JP2010085614A JP2011216797A JP 2011216797 A JP2011216797 A JP 2011216797A JP 2010085614 A JP2010085614 A JP 2010085614A JP 2010085614 A JP2010085614 A JP 2010085614A JP 2011216797 A JP2011216797 A JP 2011216797A
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board
group
defective
block
blocks
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JP5459852B2 (en
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Hitoshi Kobayashi
仁志 小林
Junichi Kako
純一 加古
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Fuji Corp
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Fuji Machine Manufacturing Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To improve the production efficiency of component mounting on a multi-piece substrate that includes defective blocks, to easily develop a production plan, and also to easily sort blocks mounted with components into acceptable substrate blocks and defective blocks.SOLUTION: The multi-piece substrates 11 are sorted into different groups according to the combination of the number of defective blocks and the locations thereof. The multi-piece substrates 11 sorted into groups are carried into an electronic component mounting line by group. The electronic component mounting line is run by a production program having a layer structure wherein the order of mounting components, arrangement of a common feeder, etc. are optimized for each group to mount electronic components on each substrate block 12 while skipping the defective blocks of the multi-piece substrates 11.

Description

本発明は、最終的に複数の回路基板に分割される複数の基板ブロックが一体に形成された多数個取り基板(多面取り基板ともいう)の各基板ブロックに電子部品を電子部品実装ラインで実装する多数個取り基板の電子部品実装方法に関する発明である。   The present invention mounts an electronic component on each board block of a multi-piece board (also referred to as a multi-sided board) integrally formed with a plurality of board blocks that are finally divided into a plurality of circuit boards on an electronic component mounting line. The invention relates to a method for mounting electronic components on a multi-chip substrate.

小型の回路基板への部品実装の生産能率を向上させるために、最終的に複数の回路基板に分割される複数の基板ブロックが一体に形成された多数個取り基板を電子部品実装ラインに搬入して、多数個取り基板の各基板ブロックに電子部品を実装することが一般に行われている。   In order to improve the production efficiency of component mounting on a small circuit board, a multi-unit board, in which a plurality of board blocks that are finally divided into a plurality of circuit boards, are integrally formed, is carried into an electronic component mounting line. In general, an electronic component is mounted on each board block of a multi-piece board.

この際、多数個取り基板に一体に形成された複数の基板ブロックの中には不良の基板ブロック(以下「不良ブロック」という)が存在する場合がある。この不良ブロックに他の基板ブロックと同様に電子部品を実装すると、不良ブロックに実装した電子部品が全て無駄になってしまうため、不良ブロックへの部品実装をスキップする必要がある。   At this time, a defective substrate block (hereinafter referred to as “defective block”) may exist among the plurality of substrate blocks integrally formed on the multi-piece substrate. If electronic components are mounted on the defective block in the same manner as other board blocks, all the electronic components mounted on the defective block are wasted, so it is necessary to skip mounting of components on the defective block.

そこで、特許文献1(特開2009−99886号公報)に記載されているように、多数個取り基板の所定位置に、部品実装をスキップする不良ブロックの情報(以下「スキップ情報」という)を表示又は記録するバーコードラベル、電子タグ等を設け、そのスキップ情報に基づいて不良ブロックの位置を認識して、多数個取り基板の不良ブロックをスキップして各基板ブロックに電子部品を実装するようにしたものがある。   Therefore, as described in Patent Document 1 (Japanese Patent Laid-Open No. 2009-99886), information on a defective block (hereinafter referred to as “skip information”) that skips component mounting is displayed at a predetermined position on the multi-cavity board. Alternatively, a barcode label to be recorded, an electronic tag, etc. are provided, the position of the defective block is recognized based on the skip information, and the electronic block is mounted on each board block by skipping the defective block of the multi-chip board. There is what I did.

特開2009−99886号公報JP 2009-99886 A

しかし、電子部品実装ラインに搬入する多数個取り基板の中に、不良ブロックが無い多数個取り基板と、不良ブロック数の異なる多数個取り基板がランダムに混ざり合っていると、多数個取り基板毎にスキップ情報を画像処理等で読み取って不良ブロック数を判定しなければならず、生産能率が悪くなるばかりか、予定枚数の多数個取り基板への部品実装を終了するまでの時間を予測するのが困難であり、生産計画が立案しにくいという欠点もある。しかも、部品実装後の良品の基板ブロックと不良ブロックとの仕分け作業も複雑にならざるを得ない。   However, if a multi-chip board with no defective blocks and a multi-chip board with a different number of defective blocks are randomly mixed in the multi-chip board to be carried into the electronic component mounting line, In addition, it is necessary to read the skip information by image processing etc. to determine the number of defective blocks, which not only deteriorates the production efficiency but also predicts the time until the completion of mounting the component on the multi-chip board of the planned number. However, it is difficult to make a production plan. In addition, the sorting operation of the non-defective board block and defective block after component mounting must be complicated.

そこで、本発明が解決しようとする課題は、不良ブロックを含む多数個取り基板への部品実装の生産能率を向上させると共に、生産計画を容易に立案でき、しかも、部品実装後の良品の基板ブロックと不良ブロックとの仕分け作業も容易に行うことができる多数個取り基板の電子部品実装方法を提供することである。   Therefore, the problem to be solved by the present invention is to improve the production efficiency of component mounting on a multi-piece substrate including a defective block, and to easily make a production plan, and in addition, a good substrate block after component mounting It is an object of the present invention to provide a method for mounting electronic components on a multi-chip substrate that can easily sort the defective blocks and the defective blocks.

上記課題を解決するために、請求項1に係る発明は、最終的に複数の回路基板に分割される複数の基板ブロックが一体に形成された多数個取り基板の各基板ブロックに電子部品を電子部品実装ラインで実装する多数個取り基板の電子部品実装方法において、多数の多数個取り基板の中から不良の基板ブロック(以下「不良ブロック」という)が無い多数個取り基板を1つのグループに仕分けると共に不良ブロックを含む多数個取り基板を該基板1枚当たりの不良ブロック数毎に異なるグループに仕分ける工程と、グループ分けされた多数個取り基板を、グループ毎に電子部品実装ラインに搬入して、各グループ毎に適合された生産プログラムで前記電子部品実装ラインを稼働させて多数個取り基板の不良ブロックをスキップして各基板ブロックに電子部品を実装する工程とを含むことを特徴とするものである。   In order to solve the above-mentioned problem, the invention according to claim 1 is directed to electronic components placed on each board block of a multi-chip board in which a plurality of board blocks that are finally divided into a plurality of circuit boards are integrally formed. In an electronic component mounting method for a multi-chip board to be mounted on a component mounting line, a multi-chip board having no defective board block (hereinafter referred to as “defective block”) is sorted into one group from among a large number of multi-chip boards. In addition, the process of sorting the multi-piece substrate including defective blocks into different groups for each number of defective blocks per board, and carrying the grouped multi-piece substrate to the electronic component mounting line for each group, Operate the electronic component mounting line with a production program adapted to each group to skip defective blocks on the multi-chip board and to block each board block. It is characterized in that a step of mounting an electronic component on.

このようにすれば、各多数個取り基板毎に不良ブロックの数を認識する処理を省略することができ、不良ブロックを含む多数個取り基板への部品実装の生産能率を向上させることができる。しかも、各グループ毎に多数個取り基板1枚当たりの不良ブロック数が同じであるため、各グループ毎に多数個取り基板1枚当たりの部品実装時間をほぼ同一とすることができ、予定枚数の多数個取り基板への部品実装を終了するまでの時間を容易に予測できて、生産計画の立案が容易である。しかも、各グループ毎に多数個取り基板1枚当たりの不良ブロック数が同じであれば、部品実装後の良品の基板ブロックと不良ブロックとの仕分け作業も容易である。   In this way, the process of recognizing the number of defective blocks for each multi-chip board can be omitted, and the production efficiency of component mounting on the multi-chip board including the defective block can be improved. Moreover, since the number of defective blocks per multi-ply board is the same for each group, the component mounting time per multi-pick board can be made substantially the same for each group. It is possible to easily predict the time until component mounting on the multi-chip substrate is completed, and it is easy to make a production plan. In addition, if the number of defective blocks per multi-chip substrate is the same for each group, it is easy to sort non-defective substrate blocks and defective blocks after component mounting.

本発明は、多数個取り基板を製造する業者と多数個取り基板に電子部品を実装する業者が異なる場合が多いことを考慮して、請求項2のように、予め不良ブロックが無い多数個取り基板のグループと多数個取り基板1枚当たりの不良ブロック数毎に異なるグループに仕分けられた多数個取り基板を入手し(つまり多数個取り基板の製造業者が不良ブロック数に応じてグループ分けしたものを部品実装業者が入手し)、グループ分けされた多数個取り基板を、グループ毎に電子部品実装ラインに搬入して、各グループ毎に適合された生産プログラムで電子部品実装ラインを稼働させて多数個取り基板の不良ブロックをスキップして基板ブロックに電子部品を実装するようにしても良い。   In consideration of the fact that there are many cases where a supplier that manufactures a multi-chip board and a supplier that mounts electronic components on the multi-chip board are different, the multi-chip board that has no defective blocks in advance is provided. Acquire a large number of multi-layered boards divided into different groups according to the number of defective blocks per group of substrates and the number of multi-layered boards (that is, those obtained by the manufacturer of multi-layered boards according to the number of defective blocks) Obtained by a component mounter), and the grouped multi-piece boards are carried into the electronic component mounting line for each group, and the electronic component mounting line is operated with a production program adapted for each group. Electronic components may be mounted on the substrate block by skipping defective blocks of the individual substrate.

更に、請求項3のように、多数個取り基板1枚当たりの不良ブロック数と不良ブロックの位置毎(不良ブロックの数と位置の組み合わせ毎)に異なるグループに仕分けるようにしても良い。同じグループに属する多数個取り基板の不良ブロックの数と位置の両方が同じであれば、各グループ毎に多数個取り基板1枚当たりの部品実装時間が完全に同一になると共に、各多数個取り基板毎に不良ブロックの位置を認識する処理が不要となり、生産能率をより一層向上させることができる。しかも、各グループ毎に不良ブロックの位置が同じであれば、部品実装後の良品の基板ブロックと不良ブロックとの仕分け作業もより一層容易となる。   Further, as in claim 3, the number of defective blocks per one multi-chip substrate and the position of each defective block (each combination of the number of defective blocks and the position) may be classified into different groups. If the number and position of the defective blocks of a multi-chip board belonging to the same group are the same, the component mounting time per multi-chip board for each group will be completely the same, and Processing for recognizing the position of the defective block for each substrate is not required, and the production efficiency can be further improved. In addition, if the position of the defective block is the same for each group, the sorting operation of the non-defective board block and the defective block after the component mounting is further facilitated.

図1は本発明の一実施例における多数個取り基板の平面図である。FIG. 1 is a plan view of a multi-piece substrate in one embodiment of the present invention. 図2は多数個取り基板グループ分け作業の手順を説明するフローチャートである。FIG. 2 is a flowchart for explaining the procedure for dividing the multi-piece board group. 図3は電子部品実装作業の手順を説明するフローチャートである。FIG. 3 is a flowchart for explaining the procedure of the electronic component mounting operation.

以下、本発明を実施するための形態を具体化した一実施例を説明する。
まず、図1に基づいて多数個取り基板11の構成を説明する。
多数個取り基板11は、複数の基板ブロック12が一体に形成された1枚の大型の基板であり、各基板ブロック12に電子部品を実装した後に各基板ブロック12を分割して複数の回路基板を形成する。各基板ブロック12の所定位置には、それぞれ当該基板ブロック12が不良ブロックであるか否かを識別するブロックスキップマーク13が設けられ、このブロックスキップマーク13の色、形状、数字、記号等によって不良ブロックを識別できるようになっている。
Hereinafter, an embodiment embodying a mode for carrying out the present invention will be described.
First, the configuration of the multi-chip substrate 11 will be described with reference to FIG.
The multi-chip substrate 11 is a single large substrate in which a plurality of substrate blocks 12 are integrally formed. After mounting electronic components on each substrate block 12, each substrate block 12 is divided into a plurality of circuit substrates. Form. A block skip mark 13 for identifying whether or not the substrate block 12 is a defective block is provided at a predetermined position of each substrate block 12, and the block skip mark 13 is defective depending on the color, shape, number, symbol, etc. The block can be identified.

更に、多数個取り基板11の所定位置には、当該多数個取り基板11がどのグループに配属されるのかを識別するグループマーク14が設けられ、このグループマーク14の数字、記号、色、形状等によってグループを認識できるようになっている。このグループマーク14の情報に基づいて、多数個取り基板11の1枚当たりの不良ブロック数と不良ブロックの位置毎(不良ブロックの数と位置の組み合わせ毎)に異なるグループに仕分けられる。従って、同じグループには、不良ブロックの数と位置の両方が同じ多数個取り基板11のみが属する。尚、ブロックスキップマーク13とグループマーク14は、印刷、塗布等で形成しても良いし、ラベル等の貼着によって形成しても良い。   Further, a group mark 14 for identifying which group the multi-chip substrate 11 is assigned to is provided at a predetermined position of the multi-chip substrate 11, and the numbers, symbols, colors, shapes, etc. of the group mark 14 are provided. The group can be recognized by. Based on the information of the group mark 14, the number of defective blocks per one multi-chip substrate 11 and the position of each defective block (each combination of the number of defective blocks and the position) are sorted into different groups. Accordingly, only the multi-chip substrate 11 having the same number and position of defective blocks belongs to the same group. The block skip mark 13 and the group mark 14 may be formed by printing, coating, or the like, or may be formed by attaching a label or the like.

次に、本実施例の多数個取り基板の電子部品実装方法を図2及び図3のフローチャートを用いて説明する。
図2のフローチャートは、多数個取り基板11を不良ブロックの数と位置の組み合わせ毎に異なるグループに仕分ける多数個取り基板グループ分け作業の手順を示している。この多数個取り基板グループ分け作業は、多数個取り基板を製造する業者が行っても良いし、多数個取り基板11に電子部品を実装する業者が行っても良い。
Next, a method for mounting electronic components on a multi-cavity board of this embodiment will be described with reference to the flowcharts of FIGS.
The flowchart of FIG. 2 shows a procedure for grouping multiple board substrates that sort the multiple board 11 into different groups for each combination of the number and position of defective blocks. The multi-piece board grouping operation may be performed by a manufacturer that manufactures a multi-piece board, or by a supplier that mounts electronic components on the multi-piece board 11.

多数個取り基板グループ分け作業では、まずステップ101で、カメラ(図示せず)で多数個取り基板11の全面を撮像して、その画像処理によりブロックスキップマーク13を認識し、次のステップ102で、多数個取り基板11の不良ブロックの数と位置を読み取る。   In the multi-chip board grouping operation, first, in step 101, the entire surface of the multi-chip board 11 is imaged by a camera (not shown), the block skip mark 13 is recognized by the image processing, and in the next step 102. Then, the number and position of defective blocks on the multi-chip substrate 11 are read.

その後、ステップ103に進み、不良ブロックの数と位置に基づいてどのグループに属するか否かを判定し、次のステップ104で、上記ステップ103で判定したグループを表すグループマーク14を多数個取り基板11の所定位置に設ける。この際、グループマーク14は、各グループの1枚目(先頭)の多数個取り基板11のみに設け、2枚目以降の多数個取り基板11にはグループマーク14を設けないようにしても良い(各グループは、不良ブロックの数と位置が同一であるためである)。この後、ステップ105に進み、多数個取り基板11を各グループ毎に仕分ける。   Thereafter, the process proceeds to step 103, where it is determined which group it belongs to based on the number and position of the defective blocks, and in the next step 104, a large number of group marks 14 representing the group determined in step 103 are obtained. 11 are provided at predetermined positions. At this time, the group mark 14 may be provided only on the first (first) multi-chip substrate 11 of each group, and the group mark 14 may not be provided on the second and subsequent multi-chip substrates 11. (This is because each group has the same number and position of defective blocks). Thereafter, the process proceeds to step 105, where the multi-chip substrate 11 is sorted into each group.

図3のフローチャートは、多数個取り基板11に電子部品を実装する作業の手順を示している。電子部品実装作業では、まずステップ201で、各グループ毎に最適化したレイヤー構造の生産プログラムを電子部品実装ラインの制御装置(図示せず)に伝送する。このレイヤー構造の生産プログラムは、各グループ毎に部品装着順、共通フィーダ配置等を最適化している。   The flowchart of FIG. 3 shows a procedure for mounting electronic components on the multi-chip substrate 11. In the electronic component mounting operation, first, in step 201, a production program having a layer structure optimized for each group is transmitted to a control device (not shown) of the electronic component mounting line. This layered production program optimizes the order of component placement, common feeder placement, etc. for each group.

この後、ステップ202に進み、各グループの多数個取り基板11の枚数を電子部品実装ラインの制御装置に入力した後、ステップ203に進み、グループ分けされた多数個取り基板11を、グループ毎に電子部品実装ラインに搬入する。   Thereafter, the process proceeds to step 202, and the number of the multi-chip boards 11 of each group is input to the control device of the electronic component mounting line. Then, the process proceeds to step 203, and the multi-chip boards 11 grouped are grouped. Carry into the electronic component mounting line.

この後、ステップ204に進み、各グループの先頭(1枚目)の多数個取り基板11のグループマーク14を画像認識して、当該グループの不良ブロックの数と位置を読み取り、次のステップ205で、各グループ毎に部品装着順、共通フィーダ配置等を最適化したレイヤー構造の生産プログラムによって、各グループの多数個取り基板11の不良ブロックをスキップして各基板ブロック12に電子部品を実装する。   Thereafter, the process proceeds to step 204, where the group mark 14 of the first (first) multi-chip substrate 11 of each group is image-recognized, and the number and position of defective blocks in the group are read. Then, the defective block of the multi-chip substrate 11 of each group is skipped by the production program having a layer structure in which the component mounting order, the common feeder arrangement, etc. are optimized for each group, and the electronic component is mounted on each substrate block 12.

例えば、グループ1が「N1」枚、グループ2が「N2」枚、グループ3が「N3」枚の場合、まずグループ1の多数個取り基板11を電子部品実装ラインに搬入し、グループ1に最適化されたプログラムで「N1」枚の多数個取り基板11に電子部品を実装し、次にグループ2の多数個取り基板11を電子部品実装ラインに搬入し、グループ2に最適化されたプログラムで「N2」枚の多数個取り基板11に電子部品を実装し、次にグループ3の多数個取り基板11を電子部品実装ラインに搬入し、グループ3に最適化されたプログラムで「N3」枚の多数個取り基板11に電子部品を実装する。   For example, if group 1 is “N1”, group 2 is “N2”, and group 3 is “N3”, the multi-chip board 11 of group 1 is first loaded into the electronic component mounting line and is optimal for group 1 The electronic program is mounted on the “N1” multi-chip board 11 with the optimized program, and then the multi-chip board 11 of group 2 is carried into the electronic component mounting line, and the program optimized for group 2 is used. The electronic components are mounted on the “N2” multi-chip substrate 11, and then the multi-chip substrate 11 of group 3 is loaded into the electronic component mounting line, and “N3” of the program is optimized for group 3. Electronic components are mounted on the multi-chip substrate 11.

尚、不良ブロックが無い多数個取り基板11で最適化された生産プログラムを用いて、不良ブロックが有る多数個取り基板11の不良ブロックをスキップして電子部品を実装した場合と、当該不良ブロックを考慮して最適化されたレイヤー構造の生産プログラムを用いて不良ブロックをスキップして電子部品を実装した場合とを比較して、前者の方がサイクルタイムが短くなるグループについては、不良ブロックがあっても、不良ブロックが無い多数個取り基板11で最適化された生産プログラムを用いて電子部品を実装するようにしても良い。   It should be noted that when an electronic component is mounted by skipping the defective block of the multi-cavity board 11 having a defective block using the production program optimized for the multi-cavity board 11 having no defective block, Compared with the case where electronic components are mounted by skipping bad blocks using a layer structure production program optimized in consideration of the former, there is a bad block for the group whose cycle time is shorter in the former. However, electronic components may be mounted using a production program optimized for the multi-chip substrate 11 having no defective blocks.

全てのグループの部品実装を行った後、ステップ206に進み、多数個取り基板11の各基板ブロック12を分割して、良品の基板ブロック12と不良ブロックとを仕分ける。 尚、各グループの全ての多数個取り基板11のグループマーク14を画像認識してグループが切り替わったか否かを監視するようにしても良い。このようにすれば、各グループの多数個取り基板11の枚数を電子部品実装ラインの制御装置に入力する作業(ステップ202)を省略できる。   After all the components are mounted, the process proceeds to step 206, where each board block 12 of the multi-chip board 11 is divided to classify the non-defective board block 12 and the defective block. Note that it is also possible to monitor whether or not the group has been switched by recognizing the group marks 14 of all the multi-chip substrates 11 of each group. In this way, it is possible to omit the operation (step 202) of inputting the number of the multi-chip substrates 11 of each group to the control device of the electronic component mounting line.

以上説明した本実施例によれば、不良ブロックの数と位置に応じてグループ分けされた多数個取り基板11を、グループ毎に電子部品実装ラインに搬入して、各グループ毎に部品装着順等が最適化されたレイヤー構造の生産プログラムで、電子部品実装ラインを稼働させて多数個取り基板11の不良ブロックをスキップして各基板ブロック12に電子部品を実装するようにしたので、各多数個取り基板11毎に不良ブロックの数と位置を認識する処理を省略することができ、不良ブロックを含む多数個取り基板11への部品実装の生産能率を向上させることができる。しかも、各グループ毎に多数個取り基板11の不良ブロックの数と位置が同じであるため、各グループ毎に多数個取り基板11の1枚当たりの部品実装時間を同一とすることができ、予定枚数の多数個取り基板11への部品実装を終了するまでの時間を容易に予測できて、生産計画の立案が容易である。しかも、各グループ毎に多数個取り基板11の不良ブロックの数と位置が同じであれば、部品実装後の良品の基板ブロック12と不良ブロックとの仕分け作業も容易である。また、各グループ毎に部品装着順等が最適化されたレイヤー構造の生産プログラムを用いれば、グループ毎に生産プログラムを切り替える必要がなく、生産プログラム切り替え時間を短縮できる利点もある。   According to the present embodiment described above, the multi-cavity boards 11 grouped according to the number and position of defective blocks are carried into the electronic component mounting line for each group, and the component mounting order for each group. In the production program with the optimized layer structure, the electronic component mounting line is operated to skip the defective block of the multi-piece board 11 and mount the electronic parts on each board block 12. The process of recognizing the number and position of defective blocks for each substrate 11 can be omitted, and the production efficiency of component mounting on the multi-device substrate 11 including defective blocks can be improved. Moreover, since the number and position of the defective blocks of the multi-chip substrate 11 are the same for each group, the component mounting time per one multi-chip substrate 11 can be made the same for each group, and the schedule It is possible to easily predict the time until the component mounting on the multi-chip substrate 11 is completed, and it is easy to make a production plan. In addition, if the number and position of the defective blocks of the multi-chip substrate 11 are the same for each group, it is easy to sort the non-defective substrate blocks 12 and defective blocks after component mounting. In addition, if a production program having a layer structure in which the order of component placement is optimized for each group is used, there is an advantage that it is not necessary to switch the production program for each group, and the production program switching time can be shortened.

尚、本実施例では、不良ブロックの数と位置の組み合わせ毎に異なるグループに仕分けるようにしたが、グループの数を少なくするために、多数個取り基板1枚当たりの不良ブロック数のみでグループ分けするようにしても良い。各グループ毎に多数個取り基板1枚当たりの不良ブロック数が同じであれば、各グループ毎に多数個取り基板1枚当たりの部品実装時間をほぼ同一とすることができ、予定枚数の多数個取り基板への部品実装を終了するまでの時間を容易に予測できて、生産計画の立案が容易である。   In this embodiment, different groups are classified for each combination of the number and position of defective blocks. However, in order to reduce the number of groups, grouping is performed only by the number of defective blocks per multi-chip substrate. You may make it do. If the number of defective blocks per multi-chip board is the same for each group, the component mounting time per multi-chip board can be made substantially the same for each group, and a large number of planned blocks It is possible to easily predict the time until component mounting on the take-off board is completed, and it is easy to make a production plan.

また、本実施例では、多数個取り基板11の各基板ブロック12毎にブロックスキップマーク13を設けるようにしたが、各基板ブロック12毎のブロックスキップマーク13を省略して、多数個取り基板11のグループマーク14に、不良ブロックの数と位置の情報を書き込み、グループマーク14を認識することで、グループ情報と不良ブロックの数と位置の情報を読み取るようにしても良い。また、グループマーク14をバーコードラベル、電子タグ等で構成しても良い。   Further, in this embodiment, the block skip mark 13 is provided for each substrate block 12 of the multi-chip substrate 11, but the block skip mark 13 for each substrate block 12 is omitted and the multi-chip substrate 11 is omitted. The group mark 14 may be written with information on the number and position of defective blocks, and the group mark 14 may be recognized so as to read the group information and information on the number and position of defective blocks. Further, the group mark 14 may be constituted by a bar code label, an electronic tag or the like.

11…多数個取り基板、12…基板ブロック、13…ブロックスキップマーク、14…グループマーク   11 ... Multi-chip substrate, 12 ... Board block, 13 ... Block skip mark, 14 ... Group mark

Claims (3)

最終的に複数の回路基板に分割される複数の基板ブロックが一体に形成された多数個取り基板の各基板ブロックに電子部品を電子部品実装ラインで実装する多数個取り基板の電子部品実装方法において、
多数の多数個取り基板の中から不良の基板ブロック(以下「不良ブロック」という)が無い多数個取り基板を1つのグループに仕分けると共に不良ブロックを含む多数個取り基板を該基板1枚当たりの不良ブロック数毎に異なるグループに仕分ける工程と、
グループ分けされた多数個取り基板を、グループ毎に電子部品実装ラインに搬入して、各グループ毎に適合された生産プログラムで前記電子部品実装ラインを稼働させて多数個取り基板の不良ブロックをスキップして各基板ブロックに電子部品を実装する工程と
を含むことを特徴とする多数個取り基板の電子部品実装方法。
In an electronic component mounting method for a multi-chip substrate, an electronic component is mounted on each board block of the multi-chip board in which a plurality of board blocks that are finally divided into a plurality of circuit boards are formed integrally. ,
A multi-chip board having no defective block (hereinafter referred to as “defective block”) is sorted into one group from a large number of multi-chip boards, and a multi-chip board including a defective block is defective per one board. The process of sorting into different groups for each number of blocks,
The grouped multi-piece boards are transferred to the electronic component mounting line for each group, and the electronic component mounting line is operated with a production program adapted for each group to skip defective blocks on the multi-piece board. And mounting electronic components on each substrate block. A method for mounting electronic components on a multi-chip substrate, comprising:
最終的に複数の回路基板に分割される複数の基板ブロックが一体に形成された多数個取り基板の各基板ブロックに電子部品を電子部品実装ラインで実装する多数個取り基板の電子部品実装方法において、
予め不良の基板ブロック(以下「不良ブロック」という)が無い多数個取り基板のグループと多数個取り基板1枚当たりの不良ブロック数毎に異なるグループに仕分けられた多数個取り基板を入手し、
グループ分けされた多数個取り基板を、グループ毎に前記電子部品実装ラインに搬入して、各グループ毎に適合された生産プログラムで電子部品実装ラインを稼働させて多数個取り基板の不良ブロックをスキップして各基板ブロックに電子部品を実装することを特徴とする多数個取り基板の電子部品実装方法。
In an electronic component mounting method for a multi-chip substrate, an electronic component is mounted on each board block of the multi-chip board in which a plurality of board blocks that are finally divided into a plurality of circuit boards are formed integrally. ,
Obtain a multi-chip substrate that has been sorted into different groups for each group of multi-block substrates that do not have defective substrate blocks (hereinafter referred to as “defective blocks”) and defective blocks per multi-chip substrate,
The grouped multi-unit board is carried into the electronic component mounting line for each group, and the electronic component mounting line is operated with a production program adapted to each group to skip defective blocks on the multi-unit board. A method for mounting electronic components on a multi-chip substrate, wherein electronic components are mounted on each substrate block.
多数個取り基板1枚当たりの不良ブロック数と不良ブロックの位置毎に異なるグループに仕分けることを特徴とする請求項1又は2に記載の多数個取り基板の電子部品実装方法。   3. The method of mounting electronic components on a multi-cavity board according to claim 1 or 2, wherein the number of defective blocks per multi-cavity board and the group of the defective blocks are classified into different groups.
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