CN105934091A - Assembled circuit board - Google Patents
Assembled circuit board Download PDFInfo
- Publication number
- CN105934091A CN105934091A CN201610380609.5A CN201610380609A CN105934091A CN 105934091 A CN105934091 A CN 105934091A CN 201610380609 A CN201610380609 A CN 201610380609A CN 105934091 A CN105934091 A CN 105934091A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- printed
- panel
- veneer
- test point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
Abstract
The invention discloses an assembled circuit board. The assembled circuit board comprises a plurality of single boards and process edges arranged on the edges of the single boards, wherein a plurality of bad mark points are arranged on the process edges and intensively arranged in an identification region; each bad mark point corresponds to one single board; and arrangement rules of the bad mark points and the single boards are same. The bad mark points are intensively arranged in the identification region, so that all bad mark points can be read only by identifying the identification region once during SMT (Surface Mount Technology) processing; the arrangement rules of the bad mark points and the single boards are same, so that non-defective single boards and defective single boards in the assembled circuit board can be judged; and the corresponding defective single boards are skipped and only the non-defective single boards are subjected to the SMT processing according to the identification of the bad mark points, so that the identification frequency of an SMT machine is reduced, the SMT processing efficiency is improved, and the processing cost is reduced.
Description
Technical field
The present invention relates to circuit board design techniques field, particularly relate to a kind of multiple-printed-panel for circuit board.
Background technology
Fast development along with the electronic product such as mobile phone, panel computer.The fuselage of product increasingly trend towards thin,
Light and handyization.The space layout of interiors of products also can be more and more compacter.Circuit board size in electronic product is less,
The general printed circuit board (PCB) using split type, i.e. multiple-printed-panel for circuit board (PCB jigsaw), by some less circuit
Plate is put together.Multiple veneers are fitted together by multiple-printed-panel for circuit board generally by technique edges and dowel.
In prior art, the corresponding test point (bad mark point) of each veneer, SMT (Surface Mount
Technology, surface mounting technology) paster identification time each veneer will first identify once corresponding test point,
If non-defective unit carries out SMT again, reexamine whether next veneer is non-defective unit if not non-defective unit, class successively
Pushing away, it is non-defective unit that each veneer will identify whether one by one.Affect SMT paster efficiency, production efficiency
Low.
Summary of the invention
The technical problem to be solved is, it is provided that a kind of multiple-printed-panel for circuit board, can disposably judge
Go out the non-defective unit in all veneers.
In order to solve above-mentioned technical problem, The embodiment provides a kind of multiple-printed-panel for circuit board, including many
Individual veneer and be arranged on the technique edges of multiple described veneer edge, described technique edges is provided with multiple test
Point, multiple described test points concentration is arranged in an identification region, veneer described in each described test point correspondence one,
Multiple described test points are identical with the arrangement rule of multiple described veneers.
Wherein, described multiple-printed-panel for circuit board also include many group echos group, each described labelling group comprise two identical
Marker character, two described marker characters are separately positioned on described veneer and described technique edges, corresponding with labelling
Described test point and described veneer；Marker character between each described labelling group is different.
Wherein, the described marker character being arranged on described technique edges is positioned at the side of corresponding described test point.
Wherein, the described marker character being arranged on described technique edges is positioned at corresponding described test point.
Wherein, described marker character is digital or alphabetical.
Wherein, equidistantly arrange between multiple described test points.
Wherein, any one during described test point is circle, triangle, square and prismatic.
Wherein, described test point is character shape.
Wherein, described technique edges is provided with the identification point for identifying region described in labelling.
Wherein, described identification region is square, and described identification point is four, lays respectively at described identification region
Four edges.
The multiple-printed-panel for circuit board that the embodiment of the present invention provides, owing to multiple test point concentrated settings are a cog region
In territory, have only to when carrying out SMT paster this identification region is once identified, i.e. can read all surveys
Pilot；Owing to multiple test points are identical with the arrangement rule of multiple veneers, can determine whether out to spell at this circuit board
In plate, which veneer is non-defective unit, and which veneer is defective products, skips corresponding defective products according to the identification of test point,
Only non-defective unit is carried out paster, thus reduces the identification number of times of SMT chip mounter, improve SMT paster efficiency, fall
Low processing cost.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, describe below
In accompanying drawing be only some embodiments of the present invention, for those of ordinary skill in the art, do not paying
On the premise of going out creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of the multiple-printed-panel for circuit board that the preferred embodiment of the present invention provides；
Fig. 2 is the partial enlarged drawing at the identification region of multiple-printed-panel for circuit board in Fig. 1.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by.
Seeing Fig. 1, a kind of multiple-printed-panel for circuit board provided for preferred embodiment in the present invention, including multiple veneers
10 and be arranged on the technique edges 20 of multiple veneer 10 edge, technique edges 20 is provided with multiple test point 30,
Multiple test points 30 are concentrated and are arranged in an identification region 40, and the corresponding veneer 10 of each test point 30 is multiple
Test point 30 is identical with the arrangement rule of multiple veneers 10.
Owing to multiple test point 30 concentrated settings identify in region 40 at one, when carrying out SMT paster only
Need this identification region 40 is once identified, i.e. can read all test points 30.Due to multiple test points
30 is identical with the arrangement rule of multiple veneers 10, can determine whether out which veneer 10 in this multiple-printed-panel for circuit board
Being non-defective unit, which veneer 10 is defective products.If entirely non-defective unit, successively paster, if any defective products, root
Skip corresponding defective products according to the identification of test point 30, only non-defective unit is carried out paster, thus reduces SMT chip mounter
Identification number of times, improve SMT paster efficiency, reduce processing cost.
When corresponding veneer 10 is defective products, by color in the color diagram of the test point 30 of veneer 10 correspondence,
It is typically black or white.When corresponding veneer 10 is non-defective unit, it is not necessary to test point 30 is carried out color
Mark.When SMT paster by disposably to identifying that in region 40, all test points 30 are identified, and sentence
Breaking, which is coated with color, coloured this veneer 10 automatically skipping correspondence.
In the present embodiment, in multiple-printed-panel for circuit board, the number of veneer 10 is four, and the number of test point 30 is also
Four, four the most corresponding four veneers 10 of test point 30.Four veneers 10 are in 2 × 2 array arrangements, phase
Answer four test points 30 also in 2 × 2 array arrangements.Each test point 30 position in its array and this test
Veneer 10 position in its array of point 30 correspondences is identical, in order to quickly at identification corresponding to each test point 30
Veneer 10.Herein, in other embodiments, the number of veneer 10 is not limited thereto, according to difference
Jigsaw situation can arrange different veneer 10 numbers；If veneer 10 number is 6, can become 2 × 3 or
3 × 2 array arrangements, veneer 10 number is 5, can a row 3, another row 2, veneer 10
Arranging rule is identical with the arrangement rule of test point 30.
In the present embodiment, technique edges 20 is yi word pattern, and it is two, lays respectively at multiple-printed-panel for circuit board relative
At both sides, multiple test points 30 and identification region 40 are disposed therein certain part of a technique edges 20
On.
Multiple-printed-panel for circuit board also includes that many group echos group, each labelling group comprise two identical marker characters 50, two
Marker character 50 is separately positioned on veneer 10 and technique edges 20, the test point 30 corresponding with labelling and veneer
10；Marker character 50 between each labelling group is different.By two identical marker characters 50, should at rapid identification
Veneer 10 corresponding to test point 30.The marker character 50 that each veneer 10 is had is different, in order to will
Multiple veneers 10 distinguish.
At the present embodiment, marker character 50 is numeral.Four test points 30 use respectively " 1 ", " 2 ", " 3 ",
" 4 " are marked.Four monolateral on also use " 1 ", " 2 ", " 3 ", " 4 " four marker characters 50 to mark
Note.Herein, in other embodiments, marker character 50 can also letter or other symbols.
Further, the marker character 50 being arranged on technique edges 20 is positioned at the side of corresponding test point 30,
To quickly recognize the marker character 50 of corresponding test point 30.Herein, in other embodiments, it is also possible to
It is that the marker character 50 being arranged on technique edges 20 is positioned at corresponding test point 30.
Equidistantly arrange between multiple test points 30, so that the array that multiple test point 30 arrangement is formed is more
Concentrate regular, reduce multiple test point 30 and form the scope of array, and then reduce the scope identifying region 40,
It is identified to facilitate.
Test point 30 can be any one in circle, triangle, square and prismatic.In the present embodiment,
Test point 30 is circular, in order to machine-shaping.Herein, in other embodiments, test point 30 also may be used
Think character shape, such that it is able to save the step arranging marker character 50 on technique edges 20, only at corresponding veneer
The character identical with this character shape is set on 10.
Technique edges 20 is provided with the identification point 60 for marker recognition region 40.SMT chip mounter is identified
Time, can be first according to the position in this identification region 40 at identification point 60 judgement, in order to follow-up to multiple tests
Point 30 quickly identifies.Further, in the present embodiment, identifying that region 40 is square, identification point 60 is
Four, laying respectively at four edges identifying region 40, all test points 30 are positioned at four identification points 60
In the region surrounded.When being identified, first-selected can judge to identify the model in region 40 according to identification point 60
Enclose size, in order to all test points 30 in this identification region 40 are identified, to avoid missing certain survey
Pilot 30.
On the width of described technique edges 20, described identification region 40 be smaller in size than described technique edges
The width of 20, thus reduce the size identifying region 40 as far as possible so that multiple test points 30 are more concentrated,
The most once identify.
Above embodiment, is not intended that the restriction to this technical scheme protection domain.Any in above-mentioned reality
Amendment, equivalent and the improvement etc. made within executing the spirit of mode and principle, should be included in this technology
Within the protection domain of scheme.
Claims (10)
1. a multiple-printed-panel for circuit board, it is characterised in that include multiple veneer and be arranged on multiple described veneer limit
Technique edges at edge, described technique edges is provided with multiple test point, and multiple described test points are concentrated and are arranged in
In one identifies region, veneer described in each described test point correspondence one, multiple described test points and multiple described lists
The arrangement rule of plate is identical.
Multiple-printed-panel for circuit board the most according to claim 1, it is characterised in that described multiple-printed-panel for circuit board also wraps
Including many group echos group, each described labelling group comprises two identical marker characters, and two described marker characters set respectively
Put on described veneer with described technique edges, the described test point corresponding with labelling and described veneer；Each institute
State the described marker character between labelling group different.
Multiple-printed-panel for circuit board the most according to claim 2, it is characterised in that be arranged on described technique edges
Described marker character be positioned at the side of corresponding described test point.
Multiple-printed-panel for circuit board the most according to claim 2, it is characterised in that be arranged on described technique edges
Described marker character be positioned at corresponding described test point.
Multiple-printed-panel for circuit board the most according to claim 2, it is characterised in that described marker character be numeral or
Letter.
Multiple-printed-panel for circuit board the most according to claim 1, it is characterised in that between multiple described test points
Equidistantly arrangement.
Multiple-printed-panel for circuit board the most according to claim 1, it is characterised in that described test point be circular,
Any one in triangle, square and prismatic.
Multiple-printed-panel for circuit board the most according to claim 1, it is characterised in that described test point is character shape.
Multiple-printed-panel for circuit board the most according to claim 1, it is characterised in that described technique edges is provided with use
In the identification point identifying region described in labelling.
Multiple-printed-panel for circuit board the most according to claim 9, it is characterised in that described identification region is square,
Described identification point is four, lays respectively at four edges in described identification region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610380609.5A CN105934091A (en) | 2016-05-31 | 2016-05-31 | Assembled circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610380609.5A CN105934091A (en) | 2016-05-31 | 2016-05-31 | Assembled circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105934091A true CN105934091A (en) | 2016-09-07 |
Family
ID=56832251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610380609.5A Pending CN105934091A (en) | 2016-05-31 | 2016-05-31 | Assembled circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105934091A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106535492A (en) * | 2016-11-17 | 2017-03-22 | 苏州河图电子科技有限公司 | SMT machine with fast identification of circuit board bad mark and identification method thereof |
| CN108322996A (en) * | 2018-03-07 | 2018-07-24 | 汕头超声印制板（二厂）有限公司 | A kind of circuit board and preparation method thereof of high jigsaw utilization rate |
| CN114745868A (en) * | 2021-12-29 | 2022-07-12 | 龙南骏亚电子科技有限公司 | Board splicing process and device for circuit board production |
| CN115226298A (en) * | 2022-06-15 | 2022-10-21 | 广东合通建业科技股份有限公司 | Intelligent charging high-density circuit board and manufacturing process thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201957342U (en) * | 2010-11-22 | 2011-08-31 | 代芳 | Novel printed circuit board word printing machine |
| CN102521437A (en) * | 2011-11-30 | 2012-06-27 | 中国航空工业集团公司第六三一研究所 | Method for producing printed board by using automatic typesetting |
| CN102711389A (en) * | 2012-05-31 | 2012-10-03 | 昆山市线路板厂 | Component mounting device and method for flexible circuit board |
| CN103068160A (en) * | 2012-12-25 | 2013-04-24 | 广东欧珀移动通信有限公司 | Split type circuit board |
| JP2013120853A (en) * | 2011-12-07 | 2013-06-17 | Fuji Mach Mfg Co Ltd | Operation machine for pair circuit board |
| CN203181404U (en) * | 2013-01-04 | 2013-09-04 | 富顺光电科技股份有限公司 | PCB panel easy for surface mounting LED paster identification and processing debugging |
-
2016
- 2016-05-31 CN CN201610380609.5A patent/CN105934091A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201957342U (en) * | 2010-11-22 | 2011-08-31 | 代芳 | Novel printed circuit board word printing machine |
| CN102521437A (en) * | 2011-11-30 | 2012-06-27 | 中国航空工业集团公司第六三一研究所 | Method for producing printed board by using automatic typesetting |
| JP2013120853A (en) * | 2011-12-07 | 2013-06-17 | Fuji Mach Mfg Co Ltd | Operation machine for pair circuit board |
| CN102711389A (en) * | 2012-05-31 | 2012-10-03 | 昆山市线路板厂 | Component mounting device and method for flexible circuit board |
| CN103068160A (en) * | 2012-12-25 | 2013-04-24 | 广东欧珀移动通信有限公司 | Split type circuit board |
| CN203181404U (en) * | 2013-01-04 | 2013-09-04 | 富顺光电科技股份有限公司 | PCB panel easy for surface mounting LED paster identification and processing debugging |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106535492A (en) * | 2016-11-17 | 2017-03-22 | 苏州河图电子科技有限公司 | SMT machine with fast identification of circuit board bad mark and identification method thereof |
| CN108322996A (en) * | 2018-03-07 | 2018-07-24 | 汕头超声印制板（二厂）有限公司 | A kind of circuit board and preparation method thereof of high jigsaw utilization rate |
| CN114745868A (en) * | 2021-12-29 | 2022-07-12 | 龙南骏亚电子科技有限公司 | Board splicing process and device for circuit board production |
| CN115226298A (en) * | 2022-06-15 | 2022-10-21 | 广东合通建业科技股份有限公司 | Intelligent charging high-density circuit board and manufacturing process thereof |
| CN115226298B (en) * | 2022-06-15 | 2023-05-09 | 广东合通建业科技股份有限公司 | Intelligent charging high-density circuit board and manufacturing process thereof |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160907 |