JP2011216348A - Electron source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electron source improved in the electron discharge characteristics, in comparison with those of conventional ones.SOLUTION: An electron passing layer 6 is provided between a lower electrode 2 and a surface electrode 7. The electron passing layer 6 includes a first electron passing part 6a on a lower electrode 2 side; and a second electron passing part 6b on a surface electrode 7 side. The second electron passing part 6b includes multiple second grains 32a formed along the thickness direction of the lower electrode 2; a first insulating thin film 35 formed in the surface of each of the second grains 32a; multiple nanometer-order fine crystalline semiconductors 33, interposed between the second grains 32a adjacent to each other; and a second insulating thick film 34 formed in the surface of each of the fine crystalline semiconductors 33 and formed smaller in the crystal grain diameter than the fine crystalline semiconductor 33. A region 36 of the second electron passing part 6b, in which the second grains 32a are formed in the thickness direction, and the first electron passing part 6a are mutually different in the crystal orientation, and the second grain 32a is higher than the first grain in the columnar structure.

Description

  The present invention relates to an electron source configured to emit an electron beam by field emission.

  Conventionally, an electron source has been proposed as an electronic device using a nanometer-order microcrystalline semiconductor (microcrystalline silicon) formed by anodizing a polycrystalline semiconductor layer (polycrystalline silicon layer) ( For example, see Patent Documents 1 and 2).

  This type of electron source is composed of a lower electrode, a surface electrode made of a metal thin film facing the lower electrode, and a lower electrode between the lower electrode and the surface electrode. And a strong electric field drift layer in which electrons drift from the lower electrode to the surface electrode due to an electric field applied when a voltage is applied. In this electron source, by applying a voltage between the surface electrode and the lower electrode with the surface electrode as a high potential side, electrons injected from the lower electrode and drifting through the strong electric field drift layer are emitted through the surface electrode. Here, in the electron source, the strong electric field drift layer includes a large number of microcrystalline silicon, and the surface electrode is formed of a metal thin film (for example, a gold thin film) having a thickness of about 10 nm. In the above-mentioned electron source, the lower electrode made of an ohmic electrode is formed on the back surface of the semiconductor substrate whose resistivity is relatively close to the resistivity of the conductor, or the lower electrode made of a conductive layer is formed on the glass substrate. There is something that was done.

  By the way, the above-mentioned strong electric field drift layer forms a porous polycrystalline silicon layer by anodizing the polycrystalline silicon layer in an electrolytic solution made of a hydrofluoric acid solution, and rapidly heats the porous polycrystalline silicon layer. It is formed by oxidation by the method. Therefore, the strong electric field drift layer includes columnar polycrystalline silicon grains, a thin first silicon oxide film formed on the surface of each grain, a number of nanometer order microcrystalline silicon interposed between the grains, And a second silicon oxide film formed on the surface of each microcrystalline silicon and having a thickness smaller than the crystal grain size of the microcrystalline silicon.

  In the above-described electron source, most of the electric field applied to the strong electric field drift layer is concentrated on the second silicon oxide film on the surface of the microcrystalline silicon, and the injected electrons are applied to the second silicon oxide film. It is accelerated by the strong electric field applied to the surface and drifts between the grains toward the surface. In short, the strong electric field drift layer interposed between the lower electrode and the surface electrode constitutes an electron passage layer through which electrons pass. The electron passage layer may be composed of a part of a polycrystalline silicon layer that is a base of the strong electric field drift layer and a strong electric field drift layer.

Japanese Patent Laid-Open No. 2000-100360 JP 2001-155622 A

  By the way, in order to obtain good electron emission characteristics in the above-mentioned electron source, microcrystalline silicon covered with the second silicon oxide film is formed continuously aligned from the lower electrode side to the surface electrode side. It is desirable that

  Here, in the electron sources disclosed in Patent Documents 1 and 2, since the polycrystalline silicon layer is formed by anodizing the microcrystalline silicon, the grain boundaries in the polycrystalline silicon layer are larger than the grain boundaries. The anodization reaction proceeds preferentially. Therefore, it is considered that the microcrystalline silicon is formed so as to be aligned along the surface of the polycrystalline silicon grain.

  Therefore, in order to improve the electron emission characteristics of the electron source described above, it is conceivable to improve the crystal orientation of the polycrystalline silicon layer that becomes the electron passage layer.

  However, as a result of intensive studies, the inventors of the present application have found that when the crystal orientation of the polycrystalline silicon layer is increased, pinholes are generated in the electron passage layer during the anodizing treatment, and the electron passage layer easily peels from the lower electrode. As a result, the process resistance to the anodizing treatment tends to be lowered, and it has been found that the dielectric breakdown due to a short circuit between the surface electrode and the lower electrode is likely to occur when the electron source is driven and the life is shortened. For this reason, it has been found that it is difficult to improve the electron emission characteristics only by improving the crystal orientation of the polycrystalline silicon layer.

  The present invention has been made in view of the above reasons, and an object of the present invention is to provide an electron source capable of improving electron emission characteristics as compared with the prior art.

  The electron source of the present invention includes an electron passage layer through which electrons pass by an electric field that acts when a voltage is applied between the lower electrode and the surface electrode with the surface electrode at a high potential side, and the electrons pass through the surface electrode. The electron passage layer includes a first electron passage portion formed of an aggregate of a plurality of first grains formed along a thickness direction of the lower electrode, and the first electron passage portion. A second electron passage portion provided on the electron passage portion, and the second electron passage portion includes at least a plurality of second grains formed along the thickness direction of the lower electrode, and A plurality of nanometer-order microcrystalline semiconductors interposed between the adjacent second grains, and an insulating film formed on each surface of the microcrystalline semiconductor and having a thickness smaller than the crystal grain size of the microcrystalline semiconductor. And said The region where the second grains are formed in the thickness direction of the second electron passing portion and the first electron passing portion are different in crystal orientation, and the second grain is more in the first grain. It is characterized by high columnarity compared to.

  In this electron source, an electron source element composed of the lower electrode, the electron passage layer, and the surface electrode is provided on one surface side, and the lower electrode is the one surface of the glass substrate. The region of the second electron passage portion has a value of [(111) orientation ratio] / [(220) orientation ratio] than the first electron passage portion. Larger is preferred.

  In this electron source, it is preferable that the first electron passage portion has a lower film stress than the region of the second electron passage portion.

  In the electron source of the present invention, the electron emission characteristics can be improved as compared with the prior art.

The electron source of embodiment is shown, (a) is a schematic sectional drawing, (b) is a principal part schematic block diagram. It is operation | movement explanatory drawing of an electron source same as the above. It is principal process sectional drawing for demonstrating the manufacturing method of an electron source same as the above. It is a cross-sectional TEM image figure of the various samples which changed the pressure at the time of film-forming of a polycrystalline-silicon film. FIG. 4 is an X-ray diffraction spectrum diagram of various samples in which the pressure during the formation of a polycrystalline silicon film is changed. FIG. 5 is an explanatory diagram of a relationship between pressure and film stress when forming a polycrystalline silicon film. It is explanatory drawing of the measuring method of a film | membrane stress. FIG. 6 is an explanatory diagram of a relationship between a pressure and a plane orientation when forming a polycrystalline silicon film. FIG. 6 is an explanatory diagram of a relationship between a pressure and a plane orientation when forming a polycrystalline silicon film. It is explanatory drawing of the in-plane distribution of the crystal orientation of a polycrystalline silicon film. It is explanatory drawing of the in-plane distribution of the crystal orientation of a polycrystalline silicon film.

  As shown in FIG. 1A, the electron source 10 of this embodiment has an electron source element 10 a formed on one surface side of a substrate 11. Here, the electron source element 10 a includes a lower electrode 2 formed on the one surface side of the substrate 11, an electron passage layer 6 formed on the lower electrode 2, and a surface electrode formed on the electron passage layer 6. 7. That is, in the electron source element 10 a, the surface electrode 7 and the lower electrode 2 face each other, and the electron passage layer 6 is sandwiched between the surface electrode 7 and the lower electrode 2. Although the thickness of the surface electrode 7 is set to 10 nm, this value is an example and is not particularly limited.

  The substrate 11 is made of an insulating glass substrate. As the glass substrate, for example, an alkali-free glass substrate or a quartz glass substrate can be used. As the substrate 11, an insulating ceramic substrate or the like can be used.

  The lower electrode 2 is composed of a metal layer made of a laminated film of a Ti film and a W film. The lower electrode 2 is not limited to this metal layer. For example, a single layer made of a metal material (for example, a metal such as Cr, W, Ti, Ta, Ni, Al, Cu, Au, Pt, or Mo, an alloy, silicide, or the like) A single layer composed of an intermetallic compound) or a multilayer (for example, a multilayer composed of a metal such as Cr, W, Ti, Ta, Ni, Al, Cu, Au, Pt, Mo or an alloy or an intermetallic compound such as silicide) What is necessary is just to comprise. In addition, although the thickness of the lower electrode 2 is set to 300 nm, this value is an example and is not particularly limited.

  As will be described later, the electron passage layer 6 includes a first polycrystalline semiconductor film 31 formed on the lower electrode 2 side and a second polycrystalline semiconductor film formed on the first polycrystalline silicon film 31. The semiconductor layer 3 is formed by subjecting the semiconductor layer 3 to 32 to an anodization process (nanocrystallization process) and then an oxidation process (oxidation process), and from at least a part of the first polycrystalline semiconductor film 31. The first electron passage portion 6a and the second electron passage portion 6b formed on the basis of at least the second polycrystalline semiconductor film 32 are provided. Here, the second electron passage portion 6 b is a part of or all of the second polycrystalline semiconductor film 32, or the second polycrystal in the second polycrystal semiconductor film 32 and the first polycrystal semiconductor film 31. The portion on the crystal semiconductor film 32 side may be formed by anodizing. In any case, the electron passage layer 6 includes a first electron passage portion 6a and a second electron passage portion 6b provided on the first electron passage portion 6a. In the present embodiment, the thickness of the semiconductor layer 3 is set to 2 μm, the thickness of the first polycrystalline semiconductor film 31 is set to 1.6 μm, and the thickness of the second polycrystalline semiconductor film 32 is set to 0.4 μm. However, these numerical values are merely examples, and are not particularly limited.

  The first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 are both composed of non-doped polycrystalline silicon films, but the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film The film formation conditions are different from those of the film 32 so that the crystal orientations are different from each other. Thus, in the thickness direction of the second electron passage portion 6b, the region 36 in which a later-described second grain 32a (see FIG. 1B) is formed and the first electron passage portion 6a have a crystal orientation. Different.

  The first electron passage portion 6 a is configured by an aggregate of a large number of first grains formed along the thickness direction of the lower electrode 2. Here, the first grain is composed of grains (crystal grains) of the first polycrystalline semiconductor film 31.

  The second electron passage 6b includes at least a plurality of second grains 32a formed along the thickness direction of the lower electrode 2 and each second grain 32a, as shown in FIG. 1B. A thin first insulating film 35 formed on each surface, a large number of nanometer-order microcrystalline semiconductors 33 interposed between the adjacent second grains 32a, and a microcrystalline semiconductor 33 formed on each surface. And a second insulating film 34 having a thickness smaller than the crystal grain size of the crystal semiconductor 33. In short, in the region 36 described above, a large number of microcrystalline semiconductors 33 existing near the grain boundaries of the second grain 32a and the adjacent second grain 32a are mixed. In the present embodiment, the microcrystalline semiconductor 33 is made of microcrystalline silicon, and the first insulating film 35 and the second insulating film 34 are made of a silicon oxide film. In the present embodiment, the second electron passage portion 6 b accelerates electrons injected from the lower electrode 2 by electric field excitation between the surface electrode 7 and the lower electrode 2 toward the surface electrode 7. Make up layer.

  The first electron passage section 6a and the second electron passage section 6b will be further described after the basic manufacturing method of the electron source 10 is described.

  The surface electrode 7 is made of a metal thin film made of a metal material such as Au. The metal material of the surface electrode 7 is not limited to Au, and may be any metal material that has a relatively high conductivity, a relatively low work function, excellent oxidation resistance, and is chemically stable. For example, Pt is used. Alternatively, the surface electrode 7 is not limited to a single layer structure, and may have a two layer structure.

In order to emit electrons from the electron source element 10a having the configuration shown in FIG. 1A, for example, as shown in FIG. 2, a collector electrode 9 disposed opposite to the surface electrode 7 is provided, and the surface electrode 7 and the collector electrode are provided. A DC voltage Vps is applied between the surface electrode 7 and the lower electrode 2 so that the surface electrode 7 is on the high potential side with respect to the lower electrode 2 in a state where the space between the collector electrode 9 and the collector electrode 9 A DC voltage Vc is applied between the collector electrode 9 and the surface electrode 7 so that is on the high potential side with respect to the surface electrode 7. If the DC voltages Vps and Vc are appropriately set, electrons injected from the lower electrode 2 drift through the electron passage layer 6 and are emitted through the surface electrode 7 (the chain line in FIG. 2 is emitted through the surface electrode 7). electrons e ^- shows the flow of). The electrons that reach the surface of the electron passage layer 6 are considered to be hot electrons, and are easily tunneled through the surface electrode 7 and emitted into the vacuum. That is, the electron passage layer 6 has a quantum effect in which electrons are accelerated and drifted in a direction from the lower electrode 2 to the surface electrode 7 by an electric field that acts when the surface electrode 7 is set to the high potential side with respect to the lower electrode 2. Will be expressed.

  In the electron source element 10a, the current flowing between the surface electrode 7 and the lower electrode 2 is called a diode current Ips, and the current flowing between the collector electrode 9 and the surface electrode 7 is called an emission current (emitted electron current) Ie. If so (see FIG. 2), the larger the ratio of the emission current Ie to the diode current Ips (= Ie / Ips), the higher the electron emission efficiency (= (Ie / Ips) × 100 [%]). Here, the electron source element 10a can emit electrons even when the DC voltage Vps applied between the surface electrode 7 and the lower electrode 2 is a low voltage of about 10 to 20 V, and the electron emission characteristics depend on the degree of vacuum. Therefore, no popping phenomenon occurs and electrons can be stably emitted.

In the above-described electron source element 10a, it is considered that electron emission occurs in the following model. In order to emit electrons from the electron source element 10a, for example, the DC voltage Vps is applied between the surface electrode 7 and the lower electrode 2 with the surface electrode 7 set to the high potential side, and the collector electrode 9 and the surface electrode 7 A DC voltage Vc is applied between the collector electrode 9 and the high potential side. Here, electrons e ⁻ are thermally excited from the lower electrode 2 and injected into the electron passage layer 6. On the other hand, when a DC voltage Vps is applied to the electron passage layer 6, most of the electric field is applied to the second insulating film 34. For this reason, the electrons e ⁻ injected into the electron passage layer 6 are accelerated by a strong electric field applied to the second insulating film 34, and a portion between the second grains 32 a in the electron passage layer 6 serves as the surface electrode 7. Drifts in the direction of the arrow in FIG. 1B (upward in FIG. 1B). Here, if the DC voltage Vps is equal to or higher than a predetermined value (for example, a voltage at which the potential of the surface electrode 7 is equal to or higher than the work function), the electrons e ⁻ that reach the surface electrode 7 tunnel through the surface electrode 7 and are emitted into the vacuum. Is done. Each microcrystalline semiconductor 33 in the electron passage layer 6 has a size of about the Bohr radius, and the electrons e ⁻ tunnel without being scattered by the microcrystalline semiconductor 33. For this reason, the electrons e ⁻ accelerated by the strong electric field applied to the thin second insulating film 34 on the surface of the microcrystalline semiconductor 33 drift without being scattered in the electron passage layer 6 and pass through the surface electrode 7. Released into vacuum. Further, since the heat generated in the electron passage layer 6 is dissipated through the second grain 32a, no popping phenomenon occurs at the time of electron emission, and electrons can be stably emitted. The electrons that reach the surface of the electron passage layer 6 are considered to be hot electrons, and are easily tunneled through the surface electrode 7 and emitted into the vacuum. The electron source element 10a having the operation principle described above is called a ballistic electron surface-emitting device. The electron source element 10 a applies a DC voltage Vps between the surface electrode 7 and the lower electrode 2 with the surface electrode 7 as a high potential side, and between the collector electrode 9 and the surface electrode 7. By applying a DC voltage Vc with a high potential side, electrons can be injected from the lower electrode 2 to the electron passage layer 6 and electrons can be stably emitted not only in a vacuum but also in the atmosphere.

  Hereinafter, a method for manufacturing the electron source 10 will be described with reference to FIG.

  First, the lower electrode 2 is formed on one surface side of the substrate 11, and then a predetermined film thickness composed of a laminated film of the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 on the lower electrode 2. By forming the semiconductor layer 3 (for example, 2 μm), the structure shown in FIG. Here, as a film formation method of the lower electrode 2, for example, a sputtering method or a vapor deposition method may be employed. Further, as a method for forming the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32, a plasma CVD method is employed. A method for forming the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 will be described later.

  After the semiconductor layer 3 is formed, at least the second grain 32a of the second polycrystalline semiconductor film 32 and the microcrystalline semiconductor 33 are mixed by performing the above-described anodizing treatment (nanocrystallization process). By forming the first composite layer 4, the structure shown in FIG. 3B is obtained. Here, in the anodizing process, a voltage is applied between a platinum electrode (not shown) and the lower electrode 2 using a processing tank containing a predetermined electrolytic solution, and a first predetermined current density is obtained. The first composite layer 4 is formed by allowing a constant current to flow for a first predetermined time. A portion of the semiconductor layer 3 that is left without the first composite layer 4 is formed as a first electron passage portion 6a. In the above-described anodic oxidation treatment, since the semiconductor material of the semiconductor layer 3 is silicon, a hydrofluoric acid-based solution made of a mixed solution in which 55 wt% aqueous hydrogen fluoride and ethanol are mixed at approximately 1: 1 is used as the electrolytic solution. ing. The concentration of the aqueous hydrogen fluoride solution and the mixing ratio with ethanol are not particularly limited. In addition, the liquid mixed with the aqueous hydrogen fluoride solution is not limited to ethanol, and is not particularly limited as long as it is a liquid that can remove bubbles generated in the anodizing reaction, such as alcohol such as methanol, propanol, and isopropanol (IPA). Absent. Note that the anodization reaction proceeds preferentially in the vicinity of the grain boundaries of the adjacent second grains 32 a, so that a large number of microcrystalline semiconductors 33 are formed continuously in the thickness direction of the second polycrystalline semiconductor film 32. The Further, as the electrolytic solution, an appropriate mixed solution may be used according to the semiconductor material of the semiconductor layer 3.

In the anodic oxidation treatment, the first predetermined current density is set to 12 mA / cm ² and the first predetermined time (anodic oxidation time) is set to 6 seconds or 12 seconds. There is no particular limitation. In the present embodiment, since each of the second polycrystalline semiconductor film 32 and the first polycrystalline semiconductor film 31 is composed of a non-doped polycrystalline silicon film, the semiconductor layer 3 is irradiated from the light source during the anodic oxidation process. Although current is allowed to flow while performing light irradiation, light irradiation is not necessary in the case of a p-type polycrystalline silicon film.

After the above-described anodic oxidation treatment is completed, the above-described oxidation treatment (oxidation process) is performed to form the second electron passage portion 6b having the region 36 as shown in FIG. The structure shown in c) is obtained. In the oxidation treatment, for example, an oxidation treatment tank containing an electrolyte solution made of a solution obtained by dissolving 0.04 mol / L potassium nitrate in an organic solvent made of ethylene glycol is used, and a platinum electrode (not shown) is used. A first composite layer is applied until a predetermined current is applied between the lower electrode 2 and a constant current having a second predetermined current density is applied, and the voltage between the platinum electrode and the lower electrode 2 is increased by a specified voltage. 4 is electrochemically oxidized to form a second electron passage portion 6b made of a second composite layer including at least the grain 32a, the microcrystalline semiconductor 33, the first insulating film 35, and the second insulating film 34. Is forming. Thereby, the electron passage layer 6 which consists of the 1st electron passage part 6a and the 2nd electron passage part 6b is formed. In the present embodiment, the second predetermined current density is 0.1 mA / cm ² and the specified voltage is 20 V. However, these numerical values are merely examples and are not particularly limited. The oxidation treatment is not limited to the electrochemical oxidation method, and for example, a rapid thermal oxidation method, a plasma oxidation method, an oxidation method using ozone, or the like may be employed.

  After the electron passage layer 6 is formed, the surface electrode 7 is formed on the electron passage layer 6 by vapor deposition or sputtering, thereby obtaining the electron source 10 having the structure shown in FIG.

  Hereinafter, a method for forming the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 will be described.

  The inventors of the present application provide process parameters (deposition conditions) at the time of forming a polycrystalline semiconductor film for controlling the crystal orientation of each of the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32. Attention was paid to the pressure during film formation by the plasma CVD method. Then, the process parameters other than the pressure at the time of film formation are kept constant, and the pressure at the time of film formation of the polycrystalline silicon film, which is a polycrystalline semiconductor film, is changed variously. Diffraction: XRD measurement, electron back scattering diffraction (EBSD) measurement, cross-sectional observation with a transmission electron microscope (TEM), surface observation with an optical microscope, stress (film stress) measurement, etc. went.

Here, as a plasma CVD apparatus for forming a polycrystalline silicon film, a low inductance inductively coupled plasma type plasma CVD apparatus having an antenna inside a plasma generation chamber of the chamber was used. Regarding the process parameters other than the pressure during film formation, the flow rate of SiH ₄ gas is 0.0025 L / min (2.5 sccm) in the standard state, and the flow rate of H ₂ gas is 0.030 L / min (30 sccm) in the standard state. ), The RF power was 1.7 kW, the substrate temperature was 420 ° C., and the pressure during film formation was variously changed in the range of 0.8 Pa to 2.4 Pa. Note that the RF power of 1.7 kW is 0.089 W / cm ³ when normalized by the volume of the plasma generation chamber. As the glass substrate used as the substrate 11, Corning 1737 glass (manufactured by Corning), which is a kind of alkali-free glass, or quartz glass was used. The thickness of the substrate 11 was 0.7 mm. Further, as the lower electrode 2 serving as the base of the polycrystalline silicon film, a laminated film of a Ti film having a thickness of 50 nm and a W film having a thickness of 250 nm was used.

  Here, the XRD measurement is performed by the θ-2θ method. As a result of this XRD measurement, as the pressure at the time of film formation of the polycrystalline silicon film by the plasma CVD method is increased, the diffraction line intensity of (220) orientation increases, whereas the diffraction line intensity of (111) orientation increases. The knowledge that it hardly changed was obtained.

  For a sample in which Corning 1737 glass (# 1737) was used as the glass substrate and the pressure during film formation was 1.8 Pa, the (111) direction appeared in the vicinity of 28.4 ° of 2θ in FIG. FIG. 4B shows the XRD spectrum of the diffraction line in the (220) direction that appears near 47.4 ° of 2θ. Here, in FIGS. 4A and 4B, the horizontal axis is 2θ (°), and the vertical axis is the diffraction line intensity I (cps). For other samples, diffraction lines in the (111) direction and diffraction lines in the (220) direction appeared.

  FIG. 5 is an explanatory diagram of the relationship between the pressure during film formation and the plane orientation, in which the horizontal axis represents pressure (Pa) and the vertical axis represents diffraction line intensity (cps). 5, A1 (black square) is the diffraction line intensity in the (111) direction of each sample when the substrate 11 is # 1737, and A2 (white square) is # 1737 for the substrate 11 # 1737. In the case of (220) direction. A3 (black triangle) is the diffraction line intensity in the (111) direction when the substrate 11 is quartz glass, and A4 (white triangle) is the diffraction in the (220) direction when the substrate 11 is quartz. Line strength.

  From FIG. 5, it can be seen that in both cases where the substrate 11 is # 1737 and quartz glass, the intensity of the (220) -oriented diffraction line increases as the pressure during deposition of the polycrystalline silicon film increases, whereas (111) ) It can be seen that the diffraction line intensity of the orientation hardly changes. It can also be seen that there is no great difference between the diffraction line intensity in the (111) orientation and the diffraction line intensity in the (220) direction due to the difference in the substrate 11.

  FIG. 6 is also an explanatory diagram of the relationship between the pressure during film formation and the plane orientation, but the vertical axis is different from FIG. The vertical axis in FIG. 6 indicates [I (111) when the diffraction line intensity (cps) in the (111) direction is I (111) and the diffraction line intensity (cps) in the (220) direction is I (222). ] / [I (220)]. Here, regarding FIG. 6, A1 (black rhombus) is the value of [I (111)] / [I (220)] of each sample when the substrate 11 is # 1737, and A3 (black square) Is the value of [I (111)] / [I (220)] for each sample when the substrate 11 is quartz glass.

  FIG. 6 shows that the value of [I (111)] / [I (220)] decreases as the pressure at the time of forming the polycrystalline silicon film increases. From the results shown in FIGS. 5 and 6, it is presumed that the (220) orientation ratio increases as the pressure during film formation increases.

  FIG. 7 shows an example of the result of the EBSD measurement. In the case where the polycrystalline silicon film is formed with the pressure at the time of film formation being 1.8 Pa, the film thickness of the polycrystalline silicon film is shown. 2 shows a crystal orientation map (crystal orientation in-plane distribution map) of a polycrystalline silicon film. Here, among the three crystal orientation maps, the leftmost one is the measurement result when the film thickness is 619 nm, the middle one is the measurement result when the film thickness is 1378 nm, and the rightmost one is the measurement result when the film thickness is 1924 nm. As shown in the schematic diagram on the right side of each of the three crystal orientation maps, as the film thickness increases, the size of the (111) -oriented grain is substantially constant, whereas the size of the (220) -oriented grain is It is getting bigger. In addition, the detection limit of the particle diameter by the EBSD measuring apparatus used for EBSD measurement is 20 nm.

  On the other hand, FIG. 8 shows a polycrystalline silicon film formed with a pressure of 1.8 Pa and a film thickness of 2 μm, and a pressure of 1.3 Pa and a film thickness of 2 μm. As a result of the EBSD measurement for each of the deposited polycrystalline silicon films, a crystal orientation map and a crystal grain size histogram are shown. From FIG. 8, it can be seen that when the pressure during film formation is 1.3 Pa, the size of the (220) -oriented crystal grains is smaller and the variation in crystal grain size is smaller than when the pressure is 1.8 Pa. .

  9A and 9B show a polycrystalline silicon film formed with a pressure of 1.8 Pa and a film thickness of 2 μm, a pressure of 1.3 Pa, and a film thickness of 1.3 Pa. The cross-sectional TEM image figure observed by TEM about each of the polycrystalline-silicon film formed into 1.6 micrometers is shown.

  From the results shown in FIGS. 5 to 9, as the pressure at the time of forming the polycrystalline silicon film is increased, the (220) oriented crystal grains grow in a wedge shape and the surrounding crystal structure is disturbed. It is presumed that the grain columnarity of the polycrystalline silicon film is increased by lowering the pressure during film formation. High columnarity means that there is little change in the size of crystal grains (grains) in the thickness direction of the lower electrode 2 (in other words, the normal direction of the base).

  However, in the case where a single-layer polycrystalline silicon film is employed as the semiconductor layer 3 described above, the pressure during film formation is reduced to 0.8 Pa, and the film thickness is 2 μm, anodizing treatment and oxidation treatment are performed. As a result of observation with an optical microscope after performing the above, it was found that pinholes were generated in the electron passage layer. Further, it has been found that the electron source 10 in which the surface electrode 7 is formed on the electron passing layer becomes a short-circuit defective product that does not operate normally. In addition, the inventors of the present application have found that the electron passing layer easily peels off from the lower electrode 2 as the pressure at the time of forming the polycrystalline silicon film is lowered. The inventors of the present application have also found that short-circuit defects due to pinholes in the electron passage layer are less likely to occur as the pressure of the polycrystalline silicon film is increased. The inventors of the present application have also found that the formation of pinholes in the electron passage layer 6 can be suppressed by forming the lower electrode 2 formed on the one surface of the substrate 11 in a stripe shape. In the observation with an optical microscope, no pinhole was found in the electron passage layer 6.

Also, the substrate 11 is # 1737, the lower electrode 2 is a laminated film of a Ti film and a W film, the RF power during the formation of the polycrystalline silicon film is 1.7 kW, the substrate temperature is 420 ° C., and the film thickness is 2 μm. The stress (film stress) of the polycrystalline silicon film was measured at room temperature for each sample with various pressures during film formation. In this measurement, a three-dimensional shape measuring apparatus manufactured by Zygo was used. Here, as shown in FIG. 10, regarding the structure 20 composed of the substrate 11, the lower electrode 2, and the polycrystalline silicon film, the horizontal span is 4 mm, and the displacement in the vertical direction is δ [mm]. Was measured by a three-dimensional shape measuring apparatus, and the stress was obtained from this displacement δ. In obtaining the stress, the Young's modulus of the substrate 11 is E [Pa], the thickness of the substrate 11 is t1 [mm], the Poisson's ratio of the substrate 11 is γ, the thickness of the polycrystalline silicon film is t2 [mm], and the horizontal Assuming that the span of the direction is x [mm] and the influence of the lower electrode 2 on the stress of the polycrystalline silicon film is negligible, the following equation (1) is used.
Stress [Pa] = E × t1 ² × δ / 3 / (1-γ) / x ² / t2 (1) Formula FIG. 11 shows the pressure at the time of forming the polycrystalline silicon film and the thickness after the film formation. The relationship with the film stress which is the stress of a polycrystalline silicon film is shown. In FIG. 11, the horizontal axis represents the pressure during film formation, the vertical axis represents the film stress, and “−” in the numerical value on the vertical axis represents a compressive stress value. From FIG. 11, it was confirmed that the stress (compressive stress) increases as the pressure during film formation decreases. Accordingly, it is presumed that as the pressure at the time of forming the polycrystalline silicon film is lowered, the adhesion of the polycrystalline silicon film to the lower electrode 2 is lowered, and the polycrystalline silicon film is easily peeled off from the lower electrode 2. The

Therefore, in the present embodiment, the semiconductor layer 3 formed at the time of manufacturing the electron source 10 is constituted by a laminated film of the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32, and the first The first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 have different crystal orientations, and the second grain 32a, which is a crystal grain of the second polycrystalline silicon film 32, is more The columnarity is made higher than that of the first grain which is a crystal grain (grain) of one polycrystalline semiconductor film 31. Specifically, regarding the process parameters at the time of forming each of the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32, the conditions other than the pressure are the same, and the first polycrystalline semiconductor film 31 has the same conditions. The first pressure that is the pressure at the time of film formation is different from the second pressure that is the pressure at the time of film formation of the second polycrystalline semiconductor film 32, and the second pressure is lower than the first pressure. It is. As an example, the first polycrystalline semiconductor film 31 is a non-doped polycrystalline silicon film having a thickness of 1.6 μm, the second polycrystalline semiconductor film 32 is a non-doped polycrystalline silicon film having a thickness of 0.4 μm, For process parameters other than the pressure during film formation, the flow rate of SiH ₄ gas is 2.5 sccm, the flow rate of H ₂ gas is 30 sccm under standard conditions, the RF power is 1.7 kW, the substrate temperature is 420 ° C., and the first pressure Is 1.3 Pa and the second pressure is 1.0 Pa, but these values are not particularly limited.

  Further, regarding the anodic oxidation process after forming the semiconductor layer 3 composed of the laminated film of the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 under the film forming conditions of this example, the anodic oxidation time is 6 seconds. The electron emission characteristics of the electron source 10 were measured for the electron source 10 of Example 1 manufactured as described above and the electron source 10 of Example 2 manufactured with an anodic oxidation time of 12 seconds. As a result, the electron emission efficiencies of the electron sources 10 of Examples 1 and 2 were 1.4% and 20.1%, respectively. Here, regarding Examples 1 and 2, the thicknesses of the second electron passage portions 6b are about 250 nm to 300 nm and 500 nm to 600 nm, respectively. Since the anodic oxidation reaction preferentially proceeds in the vicinity of the grain boundaries of the adjacent second grains 32a of the first polycrystalline semiconductor film 31, the second grains 32a in the thickness direction of the second electron passage portion 6b. The region 36 in which is formed and the first electron passage portion 6a are different in crystal orientation, and the second grain 32a is considered to have higher columnarity than the first grain. It is done. Further, it is considered that the film stress is lower in the first electron passage portion 6a than in the region 36 of the second electron passage portion 6b. FIG. 9C shows a cross-sectional TEM image of the semiconductor layer 3 formed under the same film formation conditions as the electron source 10 of Example 2. In Example 2, the lower electrode 2 is formed in a stripe shape.

  Further, the semiconductor layer 3 is a single-layer polycrystalline silicon film, the pressure at the time of film formation is 1.0 Pa, the film thickness is 2 μm, and the anodization time is 6 seconds. When the electron emission characteristics of each of the electron sources of Comparative Example 2 in seconds were measured, it was confirmed that the product was a short circuit defective product. Further, the semiconductor layer 3 is formed as a single-layer polycrystalline silicon film, the pressure at the time of film formation is 1.3 Pa, the film thickness is 2 μm, and the anodization time is 6 seconds. When the electron emission characteristics of each of the electron sources of Comparative Example 4 measured in seconds were measured, the electron emission efficiency of the electron source of Comparative Example 3 was 1.2%, and it was confirmed that Comparative Example 4 was a short-circuit defective product. It was.

  In short, in Examples 1 and 2, it was confirmed that the electron emission efficiency was improved as compared with other Comparative Examples 1 to 4.

  In the electron source 10 of the present embodiment described above, the region 36 where the second grain 32a is formed in the thickness direction of the second electron passage portion 6b and the first electron passage portion 6a have crystal orientation. In contrast, since the second grain 32a has higher columnarity than the first grain, the electron emission characteristics can be improved as compared with the prior art. In addition, the process resistance against the anodizing treatment is improved as compared with the prior art, and the electron emission characteristics can be further improved while ensuring the adhesion between the electron passage layer 6 and the lower electrode 2.

  Further, in the electron source 10 of the present embodiment, when each of the polycrystalline semiconductor films 31 and 32 is a polycrystalline silicon film, the region 36 of the second electron passage portion 6b is more than the first electron passage portion 6a. By setting the process parameters of the first polycrystalline semiconductor film 31 and the second polycrystalline semiconductor film 32 so that the value of [(111) orientation ratio] / [(220) orientation ratio] is increased, The second grain 32a has higher columnarity than the first grain, and the electron emission characteristics can be improved as compared with the conventional one.

  Further, in the electron source 10 of the present embodiment, the first electron passage portion 6a has a lower film stress than the region 36 of the second electron passage portion 6b, so that the adhesion between the electron passage layer 6 and the lower electrode 2 is improved. Can be improved.

  By the way, in this embodiment, each insulating film 34 and 35 in the 2nd electron passage part 6b is comprised by the silicon oxide film, However It is comprised by the silicon nitride film or the silicon oxynitride film instead of the silicon oxide film. In this case, nitriding treatment (nitriding process) or oxynitriding treatment (oxynitriding process) may be employed instead of the above-described oxidation treatment (oxidation process).

  In the electron source 10 of this embodiment, for example, the lower electrode 2, the surface electrode 7, the electron passage layer 6, and the like are appropriately patterned so that a number of electron source elements 10 a are arranged in a matrix on the one surface side of the substrate 11. An arrangement may be adopted.

2 Lower electrode 6 Electron passage layer 6a First electron passage portion 6b Second electron passage portion 7 Surface electrode 10 Electron source 10a Electron source element 11 Substrate 32a Second grain 33 Microcrystalline semiconductor 34 Second insulating film 35 Second 1 insulating film 36 region

Claims (3)

  An electron source that includes an electron passage layer through which electrons pass by an electric field that acts when a voltage is applied between the lower electrode and the surface electrode, with the surface electrode being a high potential side, and emits the electrons through the surface electrode. The electron passage layer is provided on the first electron passage portion and a first electron passage portion formed of a large number of first grain aggregates formed along the thickness direction of the lower electrode. A second electron passage portion, and the second electron passage portion includes at least a plurality of second grains formed along the thickness direction of the lower electrode and the second grains adjacent to each other. A plurality of nanometer-order microcrystalline semiconductors interposed therebetween, and an insulating film formed on the surface of each of the microcrystalline semiconductors and having a film thickness smaller than the crystal grain size of the microcrystalline semiconductor, Of electron passage The region in which the second grain is formed in the first direction and the first electron passage portion are different in crystal orientation, and the second grain has a columnar property as compared with the first grain. An electron source characterized by being expensive.   An electron source element composed of the lower electrode, the electron passage layer, and the surface electrode includes a glass substrate formed on one surface side, and the lower electrode is formed on the one surface of the glass substrate. It is made of a metal layer, and the region of the second electron passage portion has a value of [(111) orientation ratio] / [(220) orientation ratio] larger than that of the first electron passage portion. The electron source according to claim 1.   3. The electron source according to claim 1, wherein the first electron passage portion has a lower film stress than the region of the second electron passage portion. 4.