JP2011205812A - Fault detection circuit of thyristor series circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fault detection circuit that detects a fault even when a thyristor is short-circuited while holding a certain amount of impedance, in a thyristor series circuit in which a plurality of thyristors are connected in series.SOLUTION: A gate control device 2 detects a fault of a thyristor in a thyristor series circuit in which thyristors TH1-THN are connected in series. The device includes voltage detectors DV1-DVN for detecting each forward-voltage signal FV1-FVN of the thyristors TH1-THN. Three voltage detectors DV1-DV3 of the voltage detectors DV1-DVN detect reverse-voltage signals RV1-RV3, respectively, and determine a failure of the thyristor from which a forward-voltage signal is detected when the forward-voltage signals FV1-FVN are detected in a period when the reverse-voltage signals RV1-RV3 are detected.

Description

  The present invention relates to a failure detection circuit that detects a failure in a thyristor series circuit in which a plurality of thyristors are connected in series.

  In general, a thyristor series circuit in which a large number of thyristors are connected in series is known. An example of the thyristor series circuit is a thyristor valve for direct current power transmission. Each thyristor of the thyristor series circuit is provided with a snubber circuit in parallel. The thyristor is stably driven by providing a snubber circuit.

  Each thyristor of the thyristor series circuit has a light emitting diode for detecting that a voltage (hereinafter referred to as “forward voltage”) is applied in the forward direction of the thyristor (the direction in which current flows through the thyristor). May be provided. This light emitting diode emits light using a voltage generated by the impedance of the snubber circuit. The light emitted from the light emitting diode is input to the gate control device (for example, pulse generator) of the thyristor series circuit as an FV signal (forward voltage signal) through the optical fiber cable.

  In addition, a light emitting diode for detecting that a voltage (hereinafter referred to as “reverse voltage”) is applied to some thyristors of the thyristor series circuit in the reverse direction (opposite polarity in the forward direction) of the thyristor. May be provided. The light emitted from the light emitting diode is input to the thyristor gate control device as an RV signal (reverse voltage signal) through the optical fiber cable. The gate control device uses the FV signal, the RV signal, and the phase control on timing signal from the control panel to give a gate pulse to the thyristor, and controls the firing, and also detects a failure using the FV signal (for example, Patent Documents). Perform 1).

  The gate control device detects a commutation failure using the gate pulse and the phase control on timing signal, and sends it to the control panel as a commutation failure detection signal. The control panel uses the commutation failure detection signal. In some cases, control is performed to accelerate the ignition phase of the thyristor (hereinafter referred to as “β advance”) to recover from the commutation failure.

JP 2006-271084 A

  However, in the thyristor failure detection device disclosed in the prior art document, it is difficult to detect a thyristor failure when the thyristor is short-circuited (insufficiently short-circuited) with a resistance value of several tens of ohms or more.

  For this reason, in the gate control device using this detection method, the thyristor short-circuited in such a state cannot be determined as a failure, and the control of the thyristor series circuit is continued. In this case, the phase of the voltage applied to the failed thyristor is more advanced than the voltage applied to other normal thyristors. As a result, the gate control device detects the FV signal from the failed thyristor even though the thyristor series circuit as a whole is not in the period in which the forward voltage is applied. Since the gate control device generates a commutation failure due to such an FV signal, there is a case where the power conversion operation by the thyristor series circuit cannot be stabilized due to frequent beta advancement by the control panel.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a fault detection circuit for a thyristor series circuit that can detect a fault even when the thyristor is short-circuited while maintaining a certain level of impedance in a thyristor series circuit in which a plurality of thyristors are connected in series. Is to provide.

  A failure detection circuit for a thyristor series circuit according to an aspect of the present invention is a failure detection circuit for detecting a failure of the thyristor in a thyristor series circuit in which a plurality of thyristors are connected in series, and each of the plurality of thyristors A plurality of forward voltage detection means for detecting a forward voltage; a reverse voltage detection means for detecting a reverse voltage of the thyristor; and the reverse voltage is detected during a period in which the reverse voltage is detected by the reverse voltage detection means. When a forward voltage is detected by the forward voltage detection means in the thyristor different from the thyristor, the failure determination means determines that the thyristor that has detected the forward voltage is a failure.

  According to the present invention, in a thyristor series circuit in which a plurality of thyristors are connected in series, it is possible to provide a failure detection circuit that can detect a failure even when the thyristor is short-circuited while maintaining a certain level of impedance. .

The block diagram which shows the structure of the power converter device which concerns on the 1st Embodiment of this invention. The block diagram which shows the structure which mainly comprised the circuit of 1 arm among the power converter circuits of the power converter device which concerns on the 1st Embodiment of this invention. The block diagram which shows the structure of the voltage detector which detects the forward voltage and reverse voltage which concern on 1st Embodiment. The lineblock diagram showing the composition of the voltage detector which detects the forward voltage concerning a 1st embodiment. The lineblock diagram showing the composition of the gate control device concerning a 1st embodiment. The block diagram which shows the structure of the thyristor element failure detection circuit which concerns on 1st Embodiment. 1 is a configuration diagram showing a configuration of a gate control circuit according to a first embodiment. FIG. The graph which shows the relationship between the resistance at the time of thyristor OFF under the predetermined condition which concerns on 1st Embodiment, and the phase advance of the forward voltage signal FV.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a configuration diagram showing a configuration of a power conversion device 10 according to the first embodiment of the present invention.

  The power conversion device 10 converts AC power supplied from the three-phase AC power supply AP into DC power and supplies it to the DC circuit DP, or converts DC power supplied from the DC circuit DP into AC power and converts it into three-phase. Supply to AC power supply AP.

  The power conversion device 10 includes a thyristor valve 1, a gate control device 2, and a control panel 3.

  FIG. 2 is a diagram showing a configuration of one arm circuit in the entire power conversion circuit of the power conversion device 10 in FIG. 1 and omitting the configuration of the other arms. In addition, the same code | symbol is attached | subjected to the same part in a figure, the detailed description is abbreviate | omitted, and a different part is mainly described. In the following embodiments, the same description is omitted.

  The thyristor valve 1 is connected to the gate control device 2 by an optical fiber cable or the like.

  The thyristor valve 1 includes N thyristors TH1, TH2, TH3,..., THN, N snubber circuits SN1, SN2, SN3,..., SNN, and N voltage dividing resistors RP1, RP2, RP3,. RPN and N voltage detectors DV1, DV2, DV3,..., DVN are provided.

  The N thyristors TH1 to THN are all connected in series. N snubber circuits SN1 to SNN are connected in parallel with N thyristors TH1 to THN, respectively. The N voltage dividing resistors RP1 to RPN are connected in series with the N voltage detectors DV1 to DVN, respectively. N circuits in which voltage dividing resistors RP1 to RPN and voltage detectors DV1 to DVN are connected in series are connected in parallel to N thyristors TH1 to THN, respectively.

  Thyristors TH1 to THN are switching elements for power conversion. The thyristors TH1 to THN are driven (ignited) according to the gate pulse GP output from the gate control device 2. When the thyristors TH1 to THN are driven, AC power and DC power are mutually converted.

  The voltage dividing resistors RP1 to RPN uniformly divide a DC voltage component applied between the electrodes of the thyristor valve and also serve to suppress the current flowing through the voltage detectors DV1 to DVN.

  The snubber circuits SN1 to SNN uniformly divide the AC voltage component applied between the thyristor valve poles, and protect against transient voltage nonuniformity and overvoltage applied when the thyristors TH1 to THN are turned on and off, respectively. Further, the snubber circuits SN1 to SNN are provided to reduce power loss and perform stable switching with respect to the thyristors TH1 to THN, respectively. Each of the snubber circuits SN1 to SNN has a configuration in which a resistor RS and a capacitor CS are connected in series.

  The voltage detectors DV1 to DVN output forward voltage signals FV1 to FVN to the gate control device 2, respectively, when a forward voltage (voltage in a direction in which current flows through the thyristors TH1 to THN) is applied to the thyristors TH1 to THN, respectively. . Thereby, the voltage detectors DV1 to DVN detect the forward voltage.

  Three of the N voltage detectors DV1 to DV3 receive reverse voltage signals RV1 to RV3 to the gate control device 2 when a reverse voltage (voltage opposite to the polarity of the forward voltage) is applied to the thyristors TH1 to TH3, respectively. Are output respectively. Thereby, the voltage detectors DV1 to DV3 detect the reverse voltage. That is, the three voltage detectors DV1 to DV3 detect both the forward voltage and the reverse voltage.

  The gate control device 2 generates a gate pulse GP based on various signals received from the control panel 3 and forward voltage signals FV1 to FVN or reverse voltage signals RV1 to RV3 received from the thyristor valve 1. The gate control device 2 outputs a gate pulse GP to each thyristor TH1 to THN of the thyristor valve 1 via an optical fiber cable to drive each thyristor TH1 to THN. Thereby, the thyristor valve 1 performs a power conversion operation. Based on various signals received from the thyristor valve 1, the gate control device 2 detects a commutation failure and a failure of each of the thyristors TH1 to THN.

  The control panel 3 transmits and receives various signals to and from the gate control device 2 to control and monitor power conversion by the thyristor valve 1.

  FIG. 3 is a configuration diagram showing the configuration of the voltage detector DV1 that detects the forward voltage and the reverse voltage according to the present embodiment. Note that the configurations of the voltage detectors DV2 and DV3 are the same as the configuration of the voltage detector DV1, and thus the description thereof is omitted.

  The voltage detector DV1 includes Zener diodes DZF and DZR, light emitting elements LF and LR, and a resistor RD.

  The Zener diode DZF is connected in series with the voltage dividing resistor RP1. The Zener diode DZF is attached in a direction that prevents a current flowing due to a forward voltage. The Zener diode DZF applies a voltage for causing the light emitting element LF to emit light when a forward voltage is applied to the voltage detector DV1. The Zener diode DZF conducts in the direction in which this current flows when the current due to the forward voltage becomes excessive (when the overcurrent flows). Thereby, the Zener diode DZF protects the light emitting element LF from an excessive current.

  The light emitting element LF emits light when a forward voltage is applied to the voltage detector DV1. When the light emitting element LF emits light, the forward voltage signal FV1 is output to the gate control device 2. The light emitting element LF is a light emitting diode (LED).

  The Zener diode DZR is connected in series with the Zener diode DZF in the opposite direction to the Zener diode DZF. That is, the Zener diode DZR is attached in a direction that prevents a current flowing due to a reverse voltage. The Zener diode DZR applies a voltage for causing the light emitting element LR to emit light when a reverse voltage is applied to the voltage detector DV1. The Zener diode DZR conducts in the direction in which this current flows when the current due to the reverse voltage becomes excessive (when the overcurrent flows). Thus, the Zener diode DZR protects the light emitting element LR from overcurrent.

  The light emitting element LR emits light when a reverse voltage is applied to the voltage detector DV1. When the light emitting element LR emits light, the light emitting element LR outputs a reverse voltage signal RV1 to the gate control device 2. The light emitting element LR is a light emitting diode.

  The resistor RD suppresses the current flowing through the light emitting elements LF and LR. As a result, the resistor RD causes a predetermined current to flow through the light emitting elements LF and LR.

  FIG. 4 is a configuration diagram showing the configuration of the voltage detector DVN that detects the forward voltage according to the present embodiment. FIG. 4 shows the configuration of the current detector DVN other than the three voltage detectors DV1 to DV3 out of N.

  The current detector DVN has a configuration in which the Zener diode DZR and the light emitting element LR are removed from the voltage detector DV1 shown in FIG.

  The Zener diode DZF prevents a voltage having a polarity opposite to that of the light emitting element LF from being applied. In other respects, the voltage detector DVN has the same configuration as the voltage detector DV1 shown in FIG.

  FIG. 5 is a configuration diagram showing the configuration of the gate control device 2 according to the present embodiment.

  The gate control device 2 includes a majority circuit 21, a thyristor element failure detection circuit 22, and a gate control circuit 23.

  The majority circuit 21 receives the reverse voltage signals RV1 to RV3 output from the three voltage detectors DV1 to DV3. The majority circuit 21 outputs the calculation result of the received reverse voltage signals RV1 to RV3 as the reverse voltage signal RV to the thyristor element failure detection circuit 22 and the gate control circuit 23. When the majority circuit 21 receives two or more reverse voltage signals RV1 to RV3, it sets the reverse voltage signal RV to “1” and outputs it. When the majority circuit 21 receives one or less reverse voltage signals RV1 to RV3, it sets the reverse voltage signal RV to “0” and outputs it. That is, when the reverse voltage signal is received from the majority (more than half) of the voltage detectors DV1 to DV3, the majority circuit 21 outputs the reverse voltage signal RV indicating “1”. Otherwise, the majority circuit 21 outputs a reverse voltage signal RV indicating “0”.

  The thyristor element failure detection circuit 22 receives the forward voltage signals FV1 to FVN output from the voltage detectors DV1 to DVN and the reverse voltage signal RV output from the majority circuit 21, respectively. The thyristor element failure detection circuit 22 detects the failures NG1 to NGN of the thyristors TH1 to THN of the thyristor valve 1 based on the forward voltage signals FV1 to FVN and the reverse voltage signal RV. The thyristor element failure detection circuit 22 outputs a forward voltage aggregate signal FV used to drive the thyristors TH1 to THN of the thyristor valve 1 to the gate control circuit 23 based on the forward voltage signals FV1 to FVN and the reverse voltage signal RV. .

  The gate control circuit 23 includes a phase control ON timing signal ON which is a signal for conducting the thyristors TH1 to THN, a gate block GB which suppresses the output of the gate pulse GP, a phase control ON timing signal TON for the other phase to be commutated, and a thyristor. The forward voltage aggregate signal FV output from the element failure detection circuit 22 and the reverse voltage signal RV output from the majority circuit 21 are input.

  The gate control circuit 23 generates a gate pulse GP based on the phase control on timing signal ON and the forward voltage aggregate signal FV. The gate control circuit 23 outputs the generated gate pulse GP to each thyristor TH1 to THN of the thyristor valve 1. As a result, the gate control circuit 23 fires the thyristors TH1 to THN. When the gate control circuit 23 detects a commutation failure of the thyristor valve 1 after outputting the gate pulse GP, it outputs a commutation failure signal CFD. The gate control circuit 23 stops the output of the gate pulse GP based on the gate block GB, the phase control on timing signal TON of the other phase to be commutated, and the reverse voltage signal RV.

  FIG. 6 is a configuration diagram showing the configuration of the thyristor element failure detection circuit 22 according to the present embodiment.

  The thyristor element failure detection circuit 22 includes N circuits CR1, CR2,..., CRN corresponding to the N thyristors TH1 to THN, and an OR circuit ORT.

  Here, in each logic circuit constituting the thyristor element failure detection circuit 22, it is determined that various signals are “1” when received and “0” when not received. For example, the forward voltage signal FV1 is determined to be “1” when received and “0” when not received. Similarly, the reverse voltage signal RV is determined to be “1” when received and “0” when not received.

  The circuit CR1 includes AND circuits AN11 and AN12, a logic NOT circuit NT11, on-delay circuits TM11 and TM12, flip-flops FF11 and FF12, and an OR circuit OR11. Note that the circuits CR2 to CRN are configured in the same manner as the circuit CR1, and thus the description thereof is omitted.

  A forward voltage signal FV1 and a reverse voltage signal RV corresponding to the thyristor TH1 are input to the AND circuit AN11. The AND circuit AN11 outputs an operation result obtained by performing a logical product of the forward voltage signal FV1 and the reverse voltage signal RV to the on-delay circuit TM11. Therefore, the AND circuit AN11 outputs a signal to the on-delay circuit TM11 while receiving both the forward voltage signal FV1 and the reverse voltage signal RV.

  The on-delay circuit TM11 outputs a signal to the set of flip-flops FF11 when the signal from the AND circuit AN11 continues for a predetermined time. Even if the thyristors TH1 to THN are normal, the forward voltage signals FV1 to FVN and the reverse voltage signal RV may be detected simultaneously due to the voltage sharing imbalance of the thyristors. Therefore, the time period of the on delays TM11 to TMN1 is set to about 100 μs to about 2 milliseconds when the frequency of the AC voltage is 50 Hz to 60 Hz.

  When the flip-flop FF11 is set by a signal from the on-delay circuit TM11, it outputs a signal to the OR circuit OR11 and the AND circuit AN12. The flip-flop FF11 is reset when a reset signal is input.

  A forward voltage signal FV1 is input to the logic negation circuit NT11. The logic negation circuit NT11 outputs a signal to the on-delay circuit TM12 when the forward voltage signal FV1 is not input.

  The on-delay circuit TM12 outputs a signal to the set of flip-flops FF12 when the signal from the logic negation circuit NT11 continues for a predetermined time.

  When the flip-flop FF12 is set by the signal from the on-delay circuit TM12, it outputs a signal to the OR circuit OR11. The flip-flop FF12 is reset when a reset signal is input.

  When the OR circuit OR11 receives a signal from at least one of the flip-flop FF11 and the flip-flop FF12, the OR circuit OR11 detects the failure NG1 of the thyristor TH1. Therefore, the OR circuit OR11 receives the thyristor TH1 when the forward voltage signal FV1 and the reverse voltage signal RV are simultaneously received continuously for a predetermined time or when the forward voltage signal FV1 is not continuously received for a predetermined time. Judge as a failure. Even during normal operation, the forward voltage signals FV1 to FVN cannot be received while the thyristor is turned on. Therefore, the set values of the on delays TM12 to TMN2 are set sufficiently longer than the cycle of the AC power supply.

  The AND circuit AN12 receives the signal from the flip-flop FF11 and the forward voltage signal FV1. The signal from the flip-flop FF11 is input after being inverted (logical negation). When the logical product circuit AN12 has not received the signal from the flip-flop FF11 and receives the forward voltage signal FV1, the logical product circuit AN12 outputs the signal to the logical sum circuit ORT. That is, when the AND circuit AN12 receives the forward voltage signal FV1 while it is not determined that the thyristor TH1 has failed due to the simultaneous reception of the forward voltage signal FV1 and the reverse voltage signal RV for a predetermined time, Output a signal.

  The OR circuit ORT receives signals from the N circuits CR1 to CRN corresponding to the N thyristors TH1 to THN, respectively. When the OR circuit ORT receives at least one signal from the N circuits CR1 to CRN, it outputs a common forward voltage aggregate signal FV for the N thyristors TH1 to THN.

  FIG. 7 is a configuration diagram showing the configuration of the gate control circuit 23 according to the present embodiment.

  The gate control circuit 23 includes an OR circuit OR61, flip-flops FF61 and FF62, an on-delay circuit TM61, AND circuits AN61 and AN62, a logic NOT circuit NT61, and a one-shot circuit OS61.

  A phase control ON timing signal ON is input to the set of flip-flops FF61. When receiving the phase control on timing signal ON, the flip-flop FF61 outputs a signal to the flip-flop FF62 and the logic negation circuit NT61. The flip-flop FF61 has reset priority. Therefore, the flip-flop FF61 does not output a signal while receiving a signal for reset.

  To the OR circuit OR61, the gate block GB and the phase control ON timing signal TON of the other phase to be commutated are input. The OR circuit OR61 outputs a signal to reset the flip-flop FF61 when receiving at least one signal from the phase control ON timing signal TON of the other phase to be commutated in the gate block GB. Thereby, the flip-flop FF61 is reset.

  When the flip-flop FF62 receives the signal output from the flip-flop FF61, the flip-flop FF62 outputs a signal to the AND circuit AN61. The reverse voltage signal RV is input to the flip-flop FF62 through the on-delay TM61. Accordingly, the flip-flop FF62 is reset when the reverse voltage signal RV is continuously output for a predetermined time. The flip-flop FF62 has set priority. Therefore, the flip-flop FF62 outputs a signal even while receiving a signal for reset.

  The AND circuit AN61 receives the signal output from the flip-flop FF62 and the forward voltage aggregate signal FV output from the thyristor element failure detection circuit 22. When the AND circuit AN61 receives both the signal output from the flip-flop FF62 and the forward voltage aggregate signal FV, the AND circuit AN61 outputs a signal to the one-shot circuit OS61.

  When the one-shot circuit OS61 receives a signal from the AND circuit AN61, it outputs a one-pulse waveform signal to the thyristor valve 1 and the AND circuit AN62 as a gate pulse GP.

  The AND circuit AN62 receives a signal from the gate pulse GP and the flip-flop FF61 via the logic negation circuit NT61. The signal output from the flip-flop FF61 is inverted (logical negation) and input to the AND circuit AN62. When the AND circuit AN62 receives the gate pulse GP while the signal is not output from the flip-flop FF61, the AND circuit AN62 outputs the commutation failure signal CFD. That is, when the gate pulse GP is output during a period when no signal is output from the flip-flop FF61, the AND circuit AN62 regards it as a strong point pulse and outputs the commutation failure signal CFD. When the commutation failure signal CFD is output to the control panel 3, beta advance or the like is performed.

  According to this embodiment, the following effects can be obtained.

  First, a phenomenon caused by an insufficient short circuit of the thyristor of the thyristor valve 1 will be described.

  Usually, the capacitor CS constituting the snubber circuits SN1 to SNN is several μF, and the resistor RS is several tens of Ω. Further, the resistors RP1 to RPN are several tens of kΩ, and the impedances of the voltage detectors DV1 to DVN are 1 to several KΩ. Therefore, if the normal thyristors TH1 to THN are in the off state, the impedance is sufficiently larger than that of the snubber circuits SN1 to SNN. Therefore, the combined impedance of one thyristor and snubber circuit is a capacitive impedance of several hundred to several thousand Ω, so that the thyristor valve 1 as a whole also has a capacitive impedance. Since the thyristor valve 1 as a whole is capacitive, when the thyristor valve is off, the phase of the current flowing through the thyristor valve 1 is advanced by about 90 ° el with respect to the voltage phase of the thyristor valve 1.

  For example, a description will be given in a state where the thyristor THN is short-circuited insufficiently while maintaining a resistance value of several tens of Ω to several tens of kΩ. Even if the thyristor TH1 is short-circuited insufficiently, the thyristor valve 1 as a whole is capacitive. Therefore, when the thyristor valve 1 is in the OFF state, the current flowing through the thyristor valve 1 is advanced by about 90 ° el compared to the voltage phase of the thyristor valve 1. It is a phase.

  If this faulty thyristor THN is short-circuited insufficiently with a resistance value of several tens of Ω to several tens of kΩ, its impedance is resistive and cannot be ignored compared to the impedance of the snubber circuit SNN.

  As the impedance of the failed thyristor THN becomes lower, the combined impedance of the thyristor THYN, the snubber circuit SNN, the resistor RPN, and the voltage detector DVN shifts from capacitive to resistive.

  When the impedance is capacitive, the current phase precedes the commutation phase, but with resistance, the current phase and the voltage phase are the same phase.

  Therefore, as the resistance value of the failed thyristor THYN decreases, the voltage phase applied to the thyristor THYN approaches the current phase. That is, the voltage phase of the thyristor THYN advances in comparison with the voltage phase of the thyristor valve 1. Therefore, the forward voltage signal FVN detected from the thyristor THYN also advances from the phase of the entire thyristor valve.

  FIG. 8 shows an example in which the relationship between the resistance when the thyristor is off and the phase advance of the forward voltage signal FV is calculated under certain conditions. In FIG. 8, the lead phase amount of the FV signal decreases as the resistance value decreases in a region where the resistance value when the thyristor is off is 100Ω or less. This is because the voltage phase of the actual thyristor advances, but as the resistance value when the thyristor is off decreases, the shared voltage applied to the thyristor decreases, so only the vicinity of the peak value of the shared voltage is related to the detection sensitivity of the voltage detector. This is because the voltage cannot be detected. Similarly, when the resistance value when the thyristor is off is 100 kΩ or more, the phase advance amount shows a negative value. Similarly, when the state is healthy due to the detection level, the phase is detected slightly later than the phase of the entire thyristor valve.

  Thus, the phase of the voltage applied to the failed thyristor is more advanced than the other thyristors. As a result, as a whole, the forward voltage is applied from the failed thyristor to the thyristor valve 1 as a whole even though the reverse voltage is applied.

  Even in the case of such a failure, in the gate control device 2, in the thyristor series circuit in which a plurality of thyristors TH1 to THN are connected in series, even if some of the thyristors are short-circuited insufficiently, the reverse voltage signal RV1 By using ~ RV3, this insufficient short circuit can be detected as a failure. Thereby, the thyristor short-circuited insufficiently can be specified. In addition, the gate control device 2 generates the gate pulse GP by excluding the forward voltage signal detected from the failed thyristor. For this reason, the gate control device 2 does not operate the strong point circuit by the thyristor having such a failure. Therefore, a stable power conversion operation is not hindered by outputting a CFD signal from the gate control device to the control panel and causing frequent beta advancement.

  The thyristor element failure detection circuit 22 excludes the forward voltage signal of the failed thyristor and outputs the forward voltage aggregate signal FV. Thereby, even if some thyristors fail, the gate control apparatus 2 can control the thyristor valve 1 continuously by the normal forward voltage aggregate signal FV.

  As a result, in a thyristor series circuit in which a plurality of thyristors are connected in series, even if the thyristor is short-circuited while maintaining a certain level of impedance, it can be detected as a failure and can detect a failure continuously. A circuit can be provided. Further, by using this failure detection circuit, it is possible to provide a control device and a power conversion device for a series thyristor in which unnecessary gate pulses are not generated.

  In the present embodiment, in order to detect a failure of the thyristors TH1 to TH3, the reverse voltage signals RV1 to RV3 are detected from the three thyristors TH1 to TH3 out of N. However, the present invention is not limited to this. When a failure of a thyristor is detected, the failure can be detected by detecting at least one reverse voltage signal of another normal (reliable) thyristor different from the self thyristor. Moreover, you may detect a reverse voltage signal from all the thyristors TH1-THN. By applying the reverse voltage signals detected by all the thyristors TH1 to THN to the majority circuit, the more accurate reverse voltage signal RV can be used for detecting the failure of the thyristors TH1 to THN. In addition to the majority circuit, any circuit or device may be used as long as it can be determined that the reverse voltage signal is detected from a normal (reliable) thyristor.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 1 ... Thyristor valve, 2 ... Gate control apparatus, 3 ... Control panel, 10 ... Power converter, AP ... AC power supply, CS ... Capacitor, FV1-FVN ... Forward voltage signal, DV1-DVN ... Voltage detector, GP ... Gate Pulse, RP1 to RPN ... voltage dividing resistor, RS ... resistor, RV ... reverse voltage signal, SN1-SNN ... snubber circuit, TH1-THN ... thyristor.

Claims (9)

A failure detection circuit for detecting a failure of the thyristor in a thyristor series circuit in which a plurality of thyristors are connected in series,
A plurality of forward voltage detection means for detecting the respective forward voltages of the plurality of thyristors;
Reverse voltage detection means for detecting the reverse voltage of the thyristor;
When the forward voltage is detected by the forward voltage detection means in the thyristor different from the thyristor detecting the reverse voltage during the period in which the reverse voltage is detected by the reverse voltage detection means, the forward voltage is detected. A failure detection circuit for a thyristor series circuit, comprising: failure determination means for determining a failure of the thyristor. A failure detection circuit for detecting a failure of the thyristor in a thyristor series circuit in which a plurality of thyristors are connected in series,
A plurality of forward voltage detection means for detecting the respective forward voltages of the plurality of thyristors;
A plurality of reverse voltage detection means for respectively detecting reverse voltages of at least three thyristors among the plurality of thyristors;
When a forward voltage is detected by the forward voltage detection means during a period in which reverse voltages are detected from more than half of the plurality of reverse voltage detection means, the forward voltage A failure detection circuit for a thyristor series circuit, comprising: failure determination means for determining that the thyristor detecting the failure is a failure. A control device for a thyristor series circuit comprising a failure detection circuit that controls a thyristor series circuit in which a plurality of thyristors are connected in series, and detects a failure of the thyristor,
A plurality of forward voltage detection means for detecting the respective forward voltages of the plurality of thyristors;
Reverse voltage detection means for detecting the reverse voltage of the thyristor;
When the forward voltage is detected by the forward voltage detection means in the thyristor different from the thyristor detecting the reverse voltage during the period in which the reverse voltage is detected by the reverse voltage detection means, the forward voltage is detected. A failure judging means for judging that the thyristor is faulty,
Gate signal generating means for generating a gate signal for driving the thyristor series circuit, excluding the forward voltage detected from the forward voltage detecting means of the thyristor determined as a failure by the failure determining means. A control device for a thyristor series circuit. A control device for a thyristor series circuit comprising a failure detection circuit that controls a thyristor series circuit in which a plurality of thyristors are connected in series, and detects a failure of the thyristor,
A plurality of forward voltage detection means for detecting the respective forward voltages of the plurality of thyristors;
A plurality of reverse voltage detection means for respectively detecting reverse voltages of at least three thyristors among the plurality of thyristors;
When a forward voltage is detected by the forward voltage detection means during a period in which reverse voltages are detected from more than half of the plurality of reverse voltage detection means, the forward voltage A failure determination means for determining that the thyristor detecting the failure is a failure,
Gate signal generating means for generating a gate signal for driving the thyristor series circuit, excluding the forward voltage detected from the forward voltage detecting means of the thyristor determined as a failure by the failure determining means. A control device for a thyristor series circuit. The commutation failure detection means for detecting a commutation failure in the thyristor series circuit based on the gate signal generated by the gate signal generation means. Control device for thyristor series circuit. A plurality of thyristors connected in series forming a thyristor series circuit for power conversion;
A plurality of forward voltage detection means for detecting the respective forward voltages of the plurality of thyristors;
Reverse voltage detection means for detecting the reverse voltage of the thyristor;
When the forward voltage is detected by the forward voltage detection means in the thyristor different from the thyristor detecting the reverse voltage during the period in which the reverse voltage is detected by the reverse voltage detection means, the forward voltage is detected. A power conversion device comprising failure determination means for determining a failure of the thyristor. A plurality of thyristors connected in series forming a thyristor series circuit for power conversion;
A plurality of forward voltage detection means for detecting the respective forward voltages of the plurality of thyristors;
A plurality of reverse voltage detection means for respectively detecting reverse voltages of at least three thyristors among the plurality of thyristors;
When a forward voltage is detected by the forward voltage detection means during a period in which reverse voltages are detected from more than half of the plurality of reverse voltage detection means, the forward voltage A power conversion device comprising: failure determination means for determining that the thyristor detecting the failure is a failure. Gate signal generation means for generating a gate signal for driving the thyristor series circuit, excluding the forward voltage detected from the forward voltage detection means of the thyristor determined as a failure by the failure determination means. The power converter according to claim 6 or 7, wherein The power conversion device according to claim 8, further comprising a commutation failure detection unit that detects a commutation failure of the thyristor series circuit based on the gate signal generated by the gate signal generation unit.

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