JP2011199375A - Semiconductor switch integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor switch integrated circuit which suppresses an increase in the size and cost of a chip and a package and can achieves a stable operation.SOLUTION: A resistive element is connected between a control voltage application terminal and a connection point between a FET of an on state and the FET of an off state. Further, the resistive element is connected between a source terminal and a drain terminal of the FET of an off state. As a result, voltage can stably be fed to the drain terminal and the source terminal of the FET constituting the semiconductor switch integrated circuit, and the potentials of the source terminal and the drain terminal of the FET of an off state can be set to a prescribed potential, even if DC voltage including GND potential other than control voltage is not added from an outside.

Description

  The present invention relates to a semiconductor switch integrated circuit that switches a high-frequency signal, and more particularly to a semiconductor switch integrated circuit that can perform a switching operation stably without increasing a control voltage application terminal.

  In mobile communication terminals and small electronic devices that handle high-frequency signals, MESFETs (Metal-Semiconductor Field Effect Transistors), which are field-effect transistors made of compound semiconductors such as GaAs, are used to switch the input / output paths of high-frequency signals. Many semiconductor switch integrated circuits using HJFETs (Hetero Junction Field Effect Transistors) are used. In such mobile communication terminals and electronic devices, the size of the semiconductor switch integrated circuit, which is a built-in component, is strongly reduced in order to significantly reduce the size and to mount a plurality of types of wireless devices in the same device. It is requested. In addition, with the price reduction of mobile communication terminals and small electronic devices, there is a strong demand for lower prices of semiconductor switch integrated circuits.

FIG. 7 shows an example of a conventional semiconductor switch integrated circuit. The semiconductor switch integrated circuit shown in FIG. 7 has a SPDT (Single
Pole Double Through) switch. 7, terminals 11 to 13 are high-frequency signal input / output terminals, terminals 21 and 22 are control voltage application terminals, Q11 and Q12 are field effect transistors (hereinafter referred to as FETs) that perform a switching operation, and R21 and R22 are FETs Q11 and Q12. Resistors connecting the respective drain terminals and source terminals, and R31 and R32 are gate resistors connected to the gate terminals of the FETs Q11 and Q12.

  In order to operate the semiconductor switch integrated circuit, it is necessary to determine the potential of the gate terminal, the drain terminal, and the source terminal of each FET constituting the semiconductor switch integrated circuit, and to turn the FET into a conductive state or a cut-off state. Usually, to make the FET conductive, the gate potential may be set equal to or higher than the drain potential and source potential of the FET. On the other hand, in order to turn off the FET, the gate potential may be set lower than the pinch-off voltage Vp of the FET with respect to the drain potential and source potential of the FET.

  For example, in FIG. 7, a high voltage (hereinafter referred to as a high level control voltage) is applied to the control voltage application terminal 21 and a low voltage (hereinafter referred to as a low level control pressure) is applied to the control voltage application terminal 22. The difference between the high level control voltage and the low level control voltage is set to a value sufficiently larger than the absolute value of the pinch-off voltage of the FETs Q11 and Q12.

  When the control voltage is applied to the control voltage application terminals 21 and 22 as described above, a current flows from the control voltage application terminal 21 to the control voltage application terminal 22 through the gate resistance R31, FET Q11, FET Q12, and gate resistance R32. An equivalent circuit focusing on the current path at this time is shown in FIG. As shown in FIG. 8, the potential of the high-frequency signal input / output terminal 11 that is the drain potential and the source potential of the FETs Q11 and Q12 shown in FIG. 7 is a value represented by the following equation.

V _term = V _CTL (H) −R31 · I _CTL −Vbi (Formula 1)
V _term : potential of the high-frequency signal input / output terminal 11;
V _CTL (H): High level control voltage (V) applied to the control voltage application terminal 21
R31: resistance value of the gate resistor R31 (Ω)
I _CTL : Current (A) flowing from the control voltage application terminal 21 to the control voltage application terminal 22
Vbi: Built-in potential (V) of the diode D11 existing at the gate terminal of the FET Q11

At this time, the drain potential and the source potential of the FET Q11 are the values shown in Equation 1, and the gate potential is higher than V _term obtained from Equation 1 by Vbi. That is, the FET Q11 becomes conductive. On the other hand, regarding the FET Q12, when the low level control voltage V _CTL (L) applied to the control voltage application terminal 22 is sufficiently low and the following relationship is satisfied, the FET Q12 is cut off.

V _CTL (L) + R32 · I _CTL + | Vp | <V _term (Formula 2)
V _CTL (L): Low level control voltage (V) applied to the control voltage application terminal 22
VP: pinch-off voltage (V) of FETQ12
R32: resistance value of the gate resistance R32 (Ω)

  When a high frequency signal is input to the high frequency input terminal 11 in such a state, the input high frequency signal passes through the conducting FET Q11 and is output to the high frequency signal input / output terminal 12. On the other hand, the high frequency signal is not output to the high frequency signal input / output terminal 13 because the high frequency signal is blocked by the FET Q12 in the cut-off state. Conversely, when a low-level control voltage is applied to the control voltage application terminal 21 and a high-level control voltage is applied to the control voltage application terminal 22, the states of the FET Q11 and the FET Q12 are switched from the above description, and the high-frequency signal is changed to the high-frequency signal. When input to the input / output terminal 11, the high frequency signal passes through the conducting FET Q12 and is output to the high frequency signal input / output terminal 13. On the other hand, the high-frequency signal is not output to the high-frequency signal input / output terminal 12 because the high-frequency signal is blocked by the FET Q11 in the cut-off state.

  Based on the above operation principle, the semiconductor switch integrated circuit switches the passage path by applying a voltage to the control voltage application terminal. That is, in a semiconductor switch integrated circuit, a desired potential is applied to each of the gate terminal, drain terminal, and source terminal of the FET constituting the circuit, and the conduction state and cutoff state of the switch are determined to switch the input / output of the high-frequency signal. It will be.

  By the way, since the current flows between the control voltage application terminals, the voltage of the high-frequency signal input / output terminal, that is, the drain potential and the source potential of the FET performing the switching operation is determined, so that the gate reverse leakage current of the FET almost flows. In the absence of the FET, for example, when the FET whose gate reverse leakage current is reduced to the limit is used or when the FET is operated at a low temperature, the drain potential and the source potential of the FET become unstable. This is based on the precondition that the current flows between the control voltage application terminals 21 and 22 in order to satisfy Equation 1, and when the current does not flow, the gate forward current of the FET that should be in a conductive state flows. Otherwise, the anode portion and the cathode portion of the diode are in an open state, and the high level control voltage applied to the control voltage application terminal does not appear at the high frequency signal input / output terminal.

  If this happens, the potential between the drain terminal or source terminal of the FET constituting the semiconductor switch integrated circuit cannot be determined, so that the conduction state or cutoff state of the FET becomes unstable, making it impossible to perform desired path switching. End up. Actually, the gate reverse leakage current never disappears, so the voltage at the drain terminal and the source terminal of the FET is determined by a minute current. However, in the case of performing high-speed switching, the switching time is delayed. This causes signal degradation such as dullness at the rising edge of the high frequency signal.

  In order to prevent such a problem, a voltage may be applied from the outside to the high-frequency signal input / output terminal corresponding to the drain terminal and the source terminal of the FET. In other words, if a voltage is forcibly applied from the outside, the potentials of the gate, drain, and source can be determined without depending on the leakage current of the FET constituting the semiconductor switch integrated circuit, and the semiconductor switch integrated circuit operates stably. It becomes possible.

  FIG. 9 shows a conventional semiconductor switch integrated circuit in which such measures are taken. In the circuit shown in FIG. 9, an external resistor R1 is connected between the high-frequency signal input / output terminal and GND. With this configuration, even when there is no reverse gate leakage current of the FET in the cut-off state, a current is allowed to flow from the control voltage application terminal to which the high-level control voltage is applied to the GND by the external resistor R1. The voltage is determined and stable operation of the semiconductor switch integrated circuit is achieved. The same effect can be obtained by connecting an inductor that blocks high-frequency signals instead of an external resistor. In FIG. 9, reference numerals 1, 2, and 3 denote high-frequency signals that are input and output to the high-frequency signal input / output terminals 11, 12, and 13 of the semiconductor switch integrated circuit 30 through external capacitors C1, C2, and C3, respectively. Signal input / output terminal.

  Furthermore, as shown in FIG. 10, the same effect can be obtained with a configuration in which a resistance element is provided in the semiconductor switch integrated circuit 30. In the circuit shown in FIG. 10, one end of the resistor R41 is connected to the connection point of the high-frequency signal input / output terminal 11, the FET Q11, and the FET Q12, and the other end is connected to the outside as the external connection terminal 23. By connecting a constant voltage source or GND to the external connection terminal 23, it is possible to operate stably. Note that Patent Literature 1 and Patent Literature 2 describe a circuit similar to the circuit shown in FIG.

JP 2002-135095 A Japanese Patent Laid-Open No. 9-023101

  In order to stabilize the operation of the semiconductor switch integrated circuit, the semiconductor switch integrated circuit shown in FIG. 9 requires a resistor or an inductor for blocking a high-frequency signal instead of the resistor, resulting in an increase in the number of external elements. It was. Further, as shown in FIG. 10, it is possible to form a resistor in the semiconductor switch integrated circuit, but it is necessary to provide a pad connected to the resistor element in the integrated circuit, resulting in an increase in chip size and cost. There was a problem. In addition, the external connection terminals used in the examples shown in FIGS. 7 and 9 are 5 terminals. However, 6 terminals are required, and the number of terminals is increased, so that a package having a rank larger than that must be selected. appear. In general, when the number of terminals is increased, the package cost is increased, resulting in an increase in the package cost.

  An object of the present invention is to provide a semiconductor switch integrated circuit that solves the above problems, suppresses an increase in the size and cost of a chip and a package, and can realize a stable operation.

  In order to achieve the above object, according to the first aspect of the present invention, a field effect transistor is connected between at least two high-frequency signal input / output terminals, and a control voltage is applied to the gate terminal of the field effect transistor. In the semiconductor switch integrated circuit in which a high-frequency signal is allowed to pass between or cut off between the two high-frequency signal input / output terminals, a drain terminal or a source terminal is connected to the first high-frequency signal input / output terminal, and a second high-frequency signal input / output terminal is connected. A first field effect transistor having a source terminal or drain terminal connected to the terminal; a source terminal or drain terminal connected to the first high frequency signal input / output terminal; and a drain terminal or source terminal connected to the third high frequency signal input / output terminal. The connected second field effect transistor and the gate terminal of the first field effect transistor are controlled. A first control terminal for applying a voltage; a second control voltage application terminal for applying a control voltage to the gate terminal of the second field effect transistor; and one end connected to the first control voltage application terminal; A first resistance element having the other end connected to the drain terminal or the source terminal of the first field effect transistor, one end connected to the second control voltage application terminal, and the other end to the second field effect transistor The second resistance element connected to the source terminal or the drain terminal of the first and second control elements are connected to the first control voltage application terminal and the second control voltage application terminal via the first and second resistance elements. It is characterized by that.

  According to a second aspect of the present invention, in the semiconductor switch integrated circuit according to the first aspect, a third resistance element that connects a drain terminal and a source terminal of the first field effect transistor and the second field effect transistor; The first control voltage application terminal and the second control voltage application terminal are connected via the first to third resistance elements.

  According to the present invention, a voltage can be stably supplied to the drain terminal and the source terminal of the FET constituting the semiconductor switch integrated circuit without applying a DC voltage including the GND potential from the outside in addition to the control voltage. There is an advantage that stable operation can be realized while downsizing.

  Further, it is possible to adjust the resistance value, adjust the power handling and insertion loss for each path, and there is an advantage that the circuit design according to the application of the semiconductor switch integrated circuit is possible.

1 is a diagram for explaining a semiconductor switch integrated circuit according to a first embodiment of the present invention; FIG. FIG. 2 is a linearity characteristic diagram of the semiconductor switch integrated circuit shown in FIG. 1. It is a figure explaining the semiconductor switch integrated circuit of the 2nd Example of this invention. It is a figure explaining the semiconductor switch integrated circuit of the 3rd Example of this invention. It is a figure explaining the semiconductor switch integrated circuit of the 4th Example of this invention. It is a figure explaining the semiconductor switch integrated circuit of the 5th Example of this invention. It is a figure which shows an example of the conventional semiconductor switch integrated circuit. FIG. 8 is an equivalent circuit diagram of the semiconductor switch integrated circuit shown in FIG. 7. It is a figure which shows another example of the conventional semiconductor switch integrated circuit. It is a figure which shows another example of the conventional semiconductor switch integrated circuit.

  Embodiments of the present invention will be described with reference to the drawings. The members, arrangements, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.

  FIG. 1 is an explanatory diagram of a first embodiment of the present invention, and shows an example in which an SPDT switch is configured. In FIG. 1, 11 is a high frequency signal input / output terminal (corresponding to a first high frequency signal input / output terminal), 12 is a high frequency signal input / output terminal (corresponding to a second high frequency signal input / output terminal), and 13 is a high frequency signal input / output terminal. Terminal (corresponding to the third high-frequency signal input / output terminal), 21 is a control voltage application terminal (corresponding to the first control voltage application terminal), 22 is a control voltage application terminal (corresponding to the second control voltage application terminal), Q11 is an FET (corresponding to the first FET), Q12 is an FET (corresponding to the second FET), R11 is a resistance element (corresponding to the first resistance element) added according to the present invention, and R12 is added according to the present invention. The other resistance elements (corresponding to the second resistance element), R31 and R32, are gate resistors connected to the gate terminals of the FETs Q11 and Q12, respectively, and usually have a large resistance value of several kΩ to several hundred kΩ. Resistance element A.

  In the semiconductor switch integrated circuit shown in FIG. 1, the path switching operation of the semiconductor switch integrated circuit is performed by changing the conduction state of the FET Q11 and the FET Q12 by the voltages applied to the control voltage application terminal 21 and the control voltage application terminal 22. Although a single gate FET is used in FIG. 1, in order to increase power handling, a stacked FET or a multi-gate FET in which a plurality of FETs are connected in series can be used.

  Next, the operation of the semiconductor switch integrated circuit will be described. In the SPDT switch shown in FIG. 1, when a high level control voltage is applied to the control voltage application terminal 21 and a low level control voltage is applied to the control voltage application terminal 22, the current flows from the control voltage application terminal 21 to the resistance elements R 31 and FET Q 11. A current is supplied to the high-frequency signal input / output terminal 11 which is the drain terminal or the source terminal of the FET constituting the semiconductor switch integrated circuit 30 by two paths, a current path flowing through the gate electrode and a current path flowing through the resistance element R11. Flowing. Thereafter, a current flows toward the control voltage application terminal 22 having a low potential, and this current path also includes a path between the drain terminal or the source terminal and the gate terminal of the FET Q12, a path passing through the resistance element R32, and a path passing through the resistance element R12. There are two paths. Of these two paths, the current flowing between the drain terminal or the source terminal of the FET Q12 and the gate terminal is a leakage current applied in the reverse direction of the diode described above, which is extremely small, which has caused unstable operation of the semiconductor switch integrated circuit. .

  In the present invention, by providing the resistance element R12, even when the reverse leakage current of the gate portion of the FET Q12 becomes zero, the control applied with the low level control voltage from the control voltage application terminal 21 to which the high level control voltage is applied. A current flows to the voltage application terminal 22, the potential of the high-frequency signal input / output terminal 11 which is also a connection point between the resistance element R11 and the resistance element R12 and which is the drain terminal or the source terminal of the FETs Q11 and Q12 is determined to be a predetermined value. . As a result, the FET Q11 is turned on and the FET Q12 is turned off, so that the operation as a semiconductor switch integrated circuit can be performed reliably.

  If the resistance elements R11 and R12 are equal to each other, a low-level control voltage is applied to the control voltage application terminal 21, a high-level control voltage is applied to the control voltage application terminal 22, and the states of the FET Q11 and the FET Q12 are switched. Even when the path is switched, the potential of the high-frequency signal input / output terminal 11 becomes the same value as before the path switching, and there is no difference in characteristics depending on the path. On the other hand, the RF terminal voltage at the time of path switching can be changed by adjusting the values of the resistance element R11 and the resistance element R22, and the characteristic difference can be set according to the passage path.

  For example, FIG. 2 shows a graph showing the input power dependence of the insertion loss of the semiconductor switch integrated circuit when the resistance element R12 is made larger than the resistance element R11 in FIG. The resistance value of the resistance element R11 is 100 kΩ, the resistance value of the resistance element R12 is 900 kΩ, and the high level switching voltage and the low level switching voltage are the same before and after the line switching.

  In the semiconductor switch circuit shown in FIG. 1, a high-level control voltage is applied to the control voltage application terminal 21 from the relationship between the resistance value of the resistance element R11 and the resistance value of the resistance element (resistance value of R11 << resistance value of R21). When a low level control voltage is applied to the terminal 22, switching the FET Q11 to the passing state and switching the FET Q12 to the cutoff state causes the control voltage application terminal 21 to switch the low level switching voltage and the control voltage application terminal 22 to switch the high level. The potential of the high-frequency signal input / output terminal 11 becomes higher than when a voltage is applied to turn off the FET Q11 and pass the FET Q12. When the potential of the high-frequency signal input / output terminal is higher, the reverse voltage applied to the gate terminal of the FET in the cut-off state increases, so that power handling increases. That is, when the high-frequency signal input / output terminal 11 and the high-frequency signal input / output terminal 12 are in a passing state, it is possible to pass high power.

  On the other hand, when a low-level control voltage is applied to the control voltage application terminal 21 and a high-level control voltage is applied to the control voltage application terminal 22, the high-frequency signal input / output terminal 11 and the high-frequency signal input / output terminal 13 are placed in a passing state. The potential of the signal input / output terminal 11 is lower than before switching the path. For this reason, although power handling is reduced, the forward voltage applied to the gate terminal of the passing FET is increased, so that the on-resistance of the FET is reduced. That is, the passage loss is improved when the high-frequency signal input / output terminal 11 and the high-frequency signal input / output terminal 13 are in a passing state.

  In the example shown in FIG. 2, the insertion loss is 0.4 dB when the high-frequency signal input / output terminal 12 and the high-frequency signal input / output terminal 11 are conductive, and the input power at 1 dB compression, which is an index indicating linearity, is 28.4 dBm. It has become. On the other hand, when the passage path is switched to bring the high-frequency signal input / output terminal 13 and the high-frequency signal input / output terminal 11 into a conductive state, the insertion loss is 0.34 dB, and the input power at the time of 1 dB compression is 22.8 dBm. Can be confirmed.

  When the resistance value of the resistance element is changed in this way, in addition to the stable operation of the semiconductor switch integrated circuit which is the original purpose, characterization for each path is also possible.

  FIG. 3 is a diagram for explaining a second embodiment of the present invention, which is an example in which an SP3T (Single Pole 3 Through) switch is configured. In FIG. 3, 11 is a high frequency signal input / output terminal (corresponding to a first high frequency signal input / output terminal), 12 is a high frequency signal input / output terminal (corresponding to a second high frequency signal input / output terminal), and 13 is a high frequency signal input / output. Terminal (corresponding to a third high-frequency signal input / output terminal), 14 is a high-frequency signal input / output terminal, 21 is a control voltage application terminal (corresponding to a first control voltage application terminal), 22 is a control voltage application terminal (second Control voltage application terminal), 23 is a control voltage application terminal, Q11 is an FET (corresponding to the first FET), Q12 is an FET (corresponding to the second FET), Q13 is an FET, R11 is a resistance element (first element) R12 is another resistance element (corresponding to the second resistance element), R13 is another resistance element, R31, R32, and R33 are gate resistors connected to the gate terminals of the FETs Q11, Q12, and Q13, respectively. so That.

  Also in the circuit configuration shown in FIG. 3, both control voltage application terminals are connected via resistance elements R <b> 11 and R <b> 12 </ b> R <b> 13, and the connection point is connected to a common high-frequency signal input / output terminal 11. When operating the SP3T switch configured as described above, a high level is applied to the control voltage application terminal connected to the gate terminal of one FET that is to be turned on, and a low level is applied to the gate terminals of two FETs that are to be turned off. Apply. In any state, a current flows from a control voltage application terminal to which a high level is applied to a control voltage application terminal to which a low level is applied, and the potential of the high-frequency signal input / output terminal 11 depends on the gate reverse leakage current of the FET in the cutoff state. Without being decided. In the semiconductor switch integrated circuit shown in FIG. 3, since all FETs are connected to the high frequency signal input / output terminal 11, if the potential of the high frequency signal input / output terminal 11 is determined, the drain voltage of all FETs is determined. And the state of all FETs is determined. As a result, the switch operation can be performed stably.

  As described in the first embodiment, the three resistance elements R11, R12, and R13 can be characterized by different resistance values by making the resistance values different from each other.

  In the above description, the point connected from the control voltage application terminal via the resistor is the same connection point, but the point connected from each control voltage application terminal via the resistor differs depending on the circuit configuration and layout. There are cases where it is better to make a point, or a different point. A third embodiment is shown as an embodiment in such a case.

  FIG. 4 is an explanatory diagram of the third embodiment of the present invention. Unlike the first embodiment described above, the resistor element R11 connected to the first control voltage application terminal 21 is connected to the high frequency signal input / output terminal 12, and the resistor element R12 connected to the second control voltage application terminal 22 is connected to the high frequency signal. Each is connected to the input / output terminal 13. Further, a resistance element 13 (corresponding to a third resistance element) is added, and a resistance element is connected between the drain terminal or source terminal of the FET Q11 and the source terminal or drain terminal of the FET Q12, that is, the first control voltage application terminal 21. The high-frequency signal input / output terminal 12 connected via R11 and the high-frequency signal input / output terminal 13 connected to the second control voltage application terminal 22 via the resistor element R12 are connected. .

  With this configuration, the control voltage application terminal 21 and the control voltage application terminal 22 are connected by three resistance elements R11, R13, and R12, and the connection point between the resistance element R11 and the resistance element R13 is a high-frequency signal input. A connection point between the resistance element R13 and the resistance element R12 is connected to the output terminal 12 to the high-frequency signal input / output terminal 13.

  Here, when a high level voltage and a low level voltage are applied to the control voltage application terminals 21 and 22, current flows between the control voltage terminals via the resistance elements, and even if the gate reverse current of the FET is 0, the high frequency The potential of the signal input / output terminal 12 and the high-frequency signal input / output terminal 13, that is, the potential of the connection point of the resistance elements R11, R12, and R13 is determined by the resistance value of the resistance element and the gate forward current of the FET to which a high level voltage is applied. Will be.

  As a result, the potential of the drain or source of the FET Q11 connected to the high-frequency signal input / output terminal 12 and the FET Q12 connected to the high-frequency signal input / output terminal 13 is determined, so that stable operation is possible.

  As described in the first embodiment, the three resistance elements R11, R12, and R13 can be characterized by different resistance values by making the resistance values different from each other.

  Next, a fourth embodiment will be described. FIG. 5 is an explanatory diagram of the fourth embodiment of the present invention. Unlike the above-described third embodiment, the resistance element 13 (corresponding to the third resistance element) is connected between the drain terminal and the source terminal of the FET Q11, that is, to the first control voltage application terminal 21 via the resistance R11. The high-frequency signal input / output terminal 12 and the high-frequency signal input / output terminal 11 are connected to each other. Further, in this embodiment, a resistance element R14 (corresponding to a third resistance element) is provided, and is connected between the drain terminal and the source terminal of the FET Q12, that is, via the second control voltage application terminal 22 and the resistance element R21. The high-frequency signal input / output terminal 13 and the high-frequency signal input / output terminal 11 are connected.

  With this configuration, when a high-level voltage and a low-level voltage are applied to the control voltage application terminals 21 and 22, current flows between the control voltage terminals via the resistance elements, and the gate reverse current of the FET is zero. However, the potentials of the high-frequency signal input / output terminal 12 and the high-frequency signal input / output terminal 13, that is, the potential at the connection point of the resistance elements R11 and R13, and the potential at the connection point of R12 and R14 are the resistance value of the resistance element and the high level. It is determined by the gate forward current of the FET to which the voltage is applied.

  As a result, the potential of the drain or source of the FET Q11 connected to the high-frequency signal input / output terminal 12 and the FET Q12 connected to the high-frequency signal input / output terminal 13 is determined, so that stable operation is possible.

  As described in the first embodiment, the three resistance elements R11, R12, R13, and R14 can be characterized by different resistance values by making the resistance values different from each other.

  Next, a fifth embodiment will be described. The present invention is not limited to SPDT switches and SP3T switches, and can also be applied to DPDT (Dual Pole Double Through) switches having a more complicated configuration. FIG. 6 is an explanatory diagram of the fifth embodiment of the present invention.

  In FIG. 6, 11 is a high frequency signal input / output terminal (corresponding to a first high frequency signal input / output terminal), 12 is a high frequency signal input / output terminal (corresponding to a second high frequency signal input / output terminal), and 13 is a high frequency signal input / output. Terminal (corresponding to a third high-frequency signal input / output terminal), 14 is a high-frequency signal input / output terminal, 21 is a control voltage application terminal (corresponding to a first control voltage application terminal), 22 is a control voltage application terminal (second Q11 is an FET (corresponding to the first FET), Q12 is an FET (corresponding to the second FET), Q13 is an FET, Q14 is an FET, and R11 is a resistance element (first resistance element). R12 is another resistance element (corresponding to the second resistance element), R21 is a resistance element (corresponding to the third resistance element) connecting the drain terminal and the source terminal of the FET Q11, and R22 is the resistance of the FET Q12. Source A resistor element (corresponding to the third resistor element) connecting both ends of the child and drain terminals, R23 is a resistor element (corresponding to the third resistor element) connecting both ends of the source terminal and drain terminal of the FET Q13, and R24 is FET Q14 , R31, R32, R33, R34 are gate resistors connected to the gate terminals of the FETs Q11, Q12, Q13, Q14, respectively.

  Here, when a high level switching voltage is applied to the control voltage application terminal 21 and a low level switching voltage is applied to the control voltage application terminal 22, the resistance element R 11, between the control voltage application terminal 21 and the control voltage application terminal 22, R21, R24, R12 or R11, R22, R23, R12 are connected, and the current flows even if the gate reverse leakage current of the FET becomes zero.

  As a result, the potentials of the high-frequency signal input / output terminal 11, the high-frequency signal input / output terminal 12, the high-frequency signal input / output terminal 13, and the high-frequency signal input / output terminal 14 that are connection points of the resistors are determined and connected to these terminals. The drain and source potentials of the FETQ11, FETQ12, FETQ13, and FETQ14 are determined by the resistance value of each resistance element and the gate forward current of the FET to which a high level switching voltage is applied.

  In the semiconductor switch integrated circuit shown in FIG. 6, since the potentials of the drain terminals and source terminals of all the FETs constituting the FET are determined, the conduction state or the cutoff state of all the FETs is clearly determined, and a stable switching operation is possible. It becomes.

  In addition, it is possible to characterize each passing path by adjusting the resistance values of the resistance elements R11, R12 and R21, R22, R23, R24 that determine the potential of the high frequency input / output terminal. As explained in.

  In terms of operation principle, for example, when the resistor element R11 connected to the control voltage application terminal 21 is connected to the high frequency signal input / output terminal 11, R12 connected to the control voltage application terminal 22 is not connected to the high frequency signal input / output terminal 14. Even if it is connected to the high-frequency signal input / output terminal 12 or the high-frequency signal input / output terminal 13, the same effect can be obtained.

11, 12, 13: High-frequency signal input / output terminals, 21, 22: Control voltage application terminals, 30: Semiconductor switch integrated circuit chips, Q11, Q12, Q13, Q14: Field effect transistors, R11, R12, R13: Resistors, R21 , R22, R23, R24: drain terminal, resistance between source terminals, R31, R32, R33, R34: gate resistance

Claims (2)

A field effect transistor is connected between at least two high frequency signal input / output terminals, and a high frequency signal is passed between the two high frequency signal input / output terminals by applying a control voltage to the gate terminal of the field effect transistor. In a semiconductor switch integrated circuit that allows or shuts off,
A first field effect transistor having a drain terminal or a source terminal connected to the first high-frequency signal input / output terminal, and a source terminal or a drain terminal connected to the second high-frequency signal input / output terminal;
A second field effect transistor having a source terminal or drain terminal connected to the first high-frequency signal input / output terminal, and a drain terminal or source terminal connected to the third high-frequency signal input / output terminal;
A first control terminal that applies a control voltage to the gate terminal of the first field effect transistor; a second control voltage application terminal that applies a control voltage to the gate terminal of the second field effect transistor;
A first resistance element having one end connected to the first control voltage application terminal and the other end connected to a drain terminal or a source terminal of the first field effect transistor;
A second resistance element having one end connected to the second control voltage application terminal and the other end connected to a source terminal or a drain terminal of the second field effect transistor;
A semiconductor switch integrated circuit, wherein the first control voltage application terminal and the second control voltage application terminal are connected via the first and second resistance elements. The semiconductor switch integrated circuit according to claim 1,
A third resistance element connecting a drain terminal and a source terminal of the first field effect transistor and the second field effect transistor;
A semiconductor switch integrated circuit, wherein the first control voltage application terminal and the second control voltage application terminal are connected via the first to third resistance elements.

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