JP2011198829A - Light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light emitting device which has a large degree of freedom of layout.SOLUTION: The light emitting device 10 includes a light emitting element 21 which has a first electrode 34, a second electrode 40, and at least one or more carrier transport layers 38 disposed between the first electrode 34 and second electrode 40, a light emission drive transistor Tr13 connected to the light emitting element 21, a capacitor Cs having a capacitor electrode Cs1, and a select transistor Tr11 connected to the light emission drive transistor Tr13 through the capacitor electrode Cs1.

Description

  The present invention relates to a light emitting device using an organic EL (electroluminescence) element.

  In recent years, as a next-generation display device following a liquid crystal display (LCD), a light-emitting element type display panel in which self-light-emitting elements such as organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) are two-dimensionally arranged. Research and development for full-scale practical application and dissemination of display devices are actively underway.

  The organic EL element includes an anode electrode, a cathode electrode, and an electron injection layer, a light emitting layer, a hole injection layer, and the like formed between these electrodes. In the organic EL element, light is emitted by energy generated by recombination of holes supplied from the hole injection layer and electrons supplied from the electron injection layer in the light emitting layer. Such an organic EL element is used as a display device as disclosed in Patent Document 1, and is driven by, for example, a transistor provided in each pixel.

JP 2008-83529 A

  By the way, such a display device has a problem that the layout of the organic EL element is limited by a plurality of transistors arranged in each pixel including the organic EL element and wiring connected to the transistor.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a light-emitting device having a high degree of freedom in layout of organic EL elements.

The light emitting device of the present invention is
A light-emitting element having a first electrode, a second electrode, and at least one carrier transport layer disposed between the first electrode and the second electrode;
A light emission driving transistor connected to the light emitting element;
A capacitor having a capacitor electrode;
A selection transistor connected to the light emission drive transistor via the capacitor electrode;
It is characterized by having.
One of the source and drain electrodes of the selection transistor is preferably connected to the gate electrode of the light emission driving transistor via the capacitor electrode, and the other is connected to the anode line.
Preferably, the one of the source and drain electrodes of the selection transistor is connected to one side of the capacitor electrode, and the gate electrode of the light emission driving transistor is connected to the other side of the capacitor electrode facing the one side. .

  According to the present invention, the degree of freedom of the layout of the organic EL element can be increased.

It is an equivalent circuit diagram showing a pixel drive circuit. It is a top view of a pixel. It is the III-III sectional view taken on the line shown in FIG. It is the IV-IV sectional view taken on the line shown in FIG. It is the VV sectional view taken on the line shown in FIG. 2 is an equivalent circuit diagram showing a circuit configuration and a driving principle of a pixel. FIG. 4A shows a current flow during a scanning period _TSC , and FIG. 4B shows a current flow during a group emission voltage period. The flow is shown. It is a timing chart figure in which operation was shown. 5 is a diagram illustrating a method for manufacturing the light emitting device according to Embodiment 1. FIG. 5 is a diagram illustrating a method for manufacturing the light emitting device according to Embodiment 1. FIG. 5 is a diagram illustrating a method for manufacturing the light emitting device according to Embodiment 1. FIG.

  A light-emitting device and a method for manufacturing the light-emitting device according to each embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an active driving type light emitting device using a bottom emission type organic EL (electroluminescence) element that emits light of an organic EL element to the outside through a substrate on which the organic EL element is formed is taken as an example. explain.

(Embodiment 1)
A light-emitting device and a method for manufacturing the light-emitting device according to Embodiment 1 will be described with reference to the drawings.

  FIG. 1 is an equivalent circuit of a pixel driving circuit of a light emitting device. FIG. 2 is a plan view of the pixel, and FIG. 3 is a cross-sectional view taken along the line III-III shown in FIG. 4 is a sectional view taken along line IV-IV shown in FIG. 2, and FIG. 5 is a sectional view taken along line VV shown in FIG. FIG. 6 is a diagram showing pixel writing and light emission operations, and FIG. 7 is a timing chart.

  In the light emitting device 10, three pixels 30 that emit three colors of red (R), green (G), and blue (B) are set on the pixel substrate 31 shown in FIG. A plurality of, for example, m pixels are repeatedly arranged in the left and right direction (1), and a plurality of, for example, n pixels of the same color are arranged in the column direction (up and down direction in FIG. 1). In this manner, m × n pixels that emit RGB colors are arranged in a matrix. Each pixel 30 includes an organic EL element (light emitting element) 21 that emits RGB light and a pixel circuit DS that actively operates the organic EL element 21. The three pixels 30 of red (R), green (G), and blue (B) may be in a delta arrangement.

  As illustrated in FIG. 1, the pixel circuit DS includes a first selection transistor Tr11, a second selection transistor Tr12, a light emission drive transistor Tr13, a capacitor Cs, and an organic EL element 21. The first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 are inverted staggered n-channel TFTs (Thin Film Transistors) each including a semiconductor layer having amorphous silicon.

In the light emitting device 10, as shown in FIGS. 1 and 2, a plurality of current supply lines (anode lines) La connected to a plurality of pixel circuits DS arranged in a predetermined row, and a voltage Vss such as a ground potential are provided. A data line Ld connected to the counter electrode (second electrode) 40, which is a cathode formed by a single electrode layer for all the pixels, and a plurality of pixel circuits DS arranged in a predetermined column. A plurality of gate lines Lg for selecting the first selection transistor Tr11 and the second selection transistor Tr12 of the plurality of pixel circuits DS arranged in a predetermined row and a plurality of current supply lines La are electrically connected to each other between the pixels. Are connected to each other in the column direction connection line Lc. The current supply line La is connected to a power supply or current supply driver (not shown), and the power supply or current supply driver scans a plurality of groups of current supply lines La for each unit, as will be described in detail in FIG. The applied voltage is modulated to a low level L and a high level H during the period T _{SC and} during the light emission period _TEM , respectively. Further, as will be described in detail later, the current supply line La and the column-direction connecting wiring Lc are formed together with the source electrode and the drain electrode using source-drain conductive layers that become the source and drain electrodes of the transistors Tr11 to Tr13. Is done. The data line Ld is formed together with these gate electrodes by a gate conductive layer that becomes the gate electrode of each of the transistors Tr11 to Tr13, and the gate line Lg is formed using a third metal layer provided above the source-drain conductive layer. Is done. The wirings provided in these different layers and the respective electrodes of the transistor are connected via contact portions 41 to 44 provided in the insulating film 32.

  As shown in FIGS. 1 to 5, the gate electrode 11 g of the first selection transistor Tr <b> 11 is gated through the contact portion 42 that is a contact hole provided in the insulating film 32 and the gate electrode 12 g of the second selection transistor Tr <b> 12. The current supply line La is connected to the line Lg, and is connected to the drain electrode 11d by being stacked on the drain electrode 11d of the first selection transistor Tr11. Further, the source electrode 11s of the first selection transistor Tr11 is connected to the capacitor electrode Cs1 through a contact portion 43 that is a contact hole provided in the insulating film 32.

  The drain electrode 12d of the second selection transistor Tr12 is connected to the source electrode 13s of the light emission drive transistor Tr13 via the pixel electrode (first electrode) 34, and the source electrode 12s is provided on the insulating film 32. It is connected to the data line Ld through a contact portion 41 which is a contact hole. The gate electrode 12g of the second selection transistor Tr12 is connected to the gate line Lg through the contact portion. In this manner, the pixel electrode 34 connects the drain electrode 12d and the source electrode 13s without being connected to each other by a dedicated wiring, so that the number of wirings and the wiring location are reduced. The area can be improved, and the flexibility of layout is also improved.

  The drain electrode 13d of the light emission drive transistor Tr13 is connected to the current supply line La, the gate electrode 13g of the light emission drive transistor Tr13 is connected to the capacitor electrode Cs1 via the contact portion 44, and further via the capacitor electrode Cs1. Are connected to the source electrode 11s of the first selection transistor Tr11. Further, the source electrode 13s of the light emission drive transistor Tr13 is connected by partially overlapping the pixel electrode 34 in the contact portion 45. As described above, since the capacitor electrode Cs1 is connected to the source electrode 11s and the gate electrode 13g, the number of wirings and the location of the wiring are reduced, so that the area of the capacitor electrode Cs1 can be improved and the flexibility of layout is also improved. To do.

  The capacitor Cs includes a capacitor electrode Cs1, a transparent pixel electrode 34 that functions as the other capacitor electrode, and an insulating film 32 such as silicon nitride that is a derivative interposed between the capacitor electrode Cs1 and the pixel electrode 34. The drain electrode 12d and the source electrode 13s are both connected and arranged behind the opposing left and right sides of the pixel electrode 34 shown in FIG. 2, and the source electrode 11s and the gate electrode 13g are both connected to the pixel electrode 34 shown in FIG. Are connected to the front side of the opposite left and right sides. That is, the line connecting the drain electrode 12d and the source electrode 13s does not intersect the line connecting the source electrode 11s and the gate electrode 13g. Therefore, the current flowing between the drain electrode 12d and the source electrode 13s is not easily interfered with the current flowing through the source electrode 11s and the gate electrode 13g.

  In the present embodiment, as shown in FIG. 1, column-direction connecting lines Lc that electrically connect a plurality of current supply lines La are formed in the column direction of each pixel orthogonal to the arrangement direction of the current supply lines La. Is done. In the present embodiment, for example, one column-direction connecting line Lc is formed in each column for every four current supply line La units. For example, in the case of the light-emitting device 10 in which m × n pixels are arranged, m column-direction connection lines Lc are formed for four current supply lines La, and the column-direction connection provided in the light-emitting device 10. The total number of wirings Lc is m × n / 4 (n is an integer multiple of 4). In this way, the current supply lines La adjacent to each other are electrically connected to each other in the unit of the predetermined number of current supply lines La by the column-direction connection wiring Lc, so that the wiring resistance is lowered as a whole. Suppresses the voltage drop caused by a single resistor. Therefore, each pixel 30 is connected to each unit from the current supply line La without largely depending on the resistance of the current supply line La between the power supply or the current supply driver (not shown), that is, the position in the light emitting device 10. A uniform voltage is applied every time, and a current corresponding to the display signal can be passed through the organic EL element 21. If the voltage drop of the current supply line La can be suppressed to a desired degree, the number of the plurality of current supply lines La connected to each other is not limited to four as long as it is an integer of 2 or more. Further, the number of column-direction connecting lines Lc provided for a plurality of current supply lines La connected to each other is arbitrary, and may be one or more, for example, every two or six. A connection wiring Lc may be provided.

  Further, in the present embodiment, as shown in FIG. 2, a conductive layer 48 is provided on the upper surface of the current supply line La of each row and the upper surface of each of the light emitting drive transistors Tr13 of the light emitting drive transistors Tr13 of the plurality of pixels 30 of that row. ing. The conductive layer 48 is formed wider on the upper surface of the current supply line La than the current supply line La. The conductive layer 48 is made of a conductive material. By providing the conductive layer 48, the resistance of the current supply line La can be further reduced, and the voltage drop can be suppressed. In particular, in this embodiment, as will be described in detail later, by forming the conductive layer 48 simultaneously with the formation of the gate line Lg using the third metal layer, the current can be increased without increasing the number of manufacturing steps. The resistance of the supply line La can be reduced.

  Next, the organic EL element 21 includes a pixel electrode 34, a hole injection layer 36, an interlayer 37, a light emitting layer 38, and a counter electrode 40. The hole injection layer 36, the interlayer 37, and the light emitting layer 38 are carrier transport layers in which electrons and holes are transported as carriers. The carrier transport layer is disposed between the interlayer insulating film 33, the insulating layer 35, and the partition wall 39 arranged in the column direction.

  On the pixel substrate 31 of each pixel, gate electrodes 11g, 12g, and 13g of a first selection transistor Tr11, a second selection transistor Tr12, and a light emission driving transistor Tr13 formed by patterning a gate conductive layer are formed. Further, one electrode Cs1 of the capacitor Cs is formed on the pixel substrate 31 of each pixel, and a gate conductive layer is patterned on the pixel substrate 31 adjacent to each pixel and extends along the column direction. A data line Ld is formed, and an insulating film 32 functioning as a dielectric of the gate insulating film and the capacitor Cs is further formed so as to cover them.

  When the organic EL element 21 is a bottom emission type that emits display light from the pixel substrate 31 side, the capacitor electrode Cs1 and the pixel electrode 34 are doped with indium oxide (ITO) doped with tin oxide or zinc oxide. In addition, a transparent electrode such as indium oxide (Indium Zinc Oxide) is formed, and the gate electrode 13g of the light emission drive transistor Tr13 is formed so as to overlap the capacitor electrode Cs1 in the contact portion 44. If the gate conductive layer contains aluminum and the capacitor electrode Cs1 is made of ITO, the cell electrode can be prevented from being induced by patterning the gate conductive layer after the capacitor electrode Cs1 is first patterned. When the organic EL element 21 is a top emission type that emits display light from the counter electrode 40 side, the counter electrode 40 is a transparent electrode such as ITO, but the capacitor electrode Cs1 does not need to be transparent. Cs1 can be formed together and integrally with the gate electrode 13g of the light emission drive transistor Tr13 by patterning the gate conductive layer. Since the gate conductive layer can be patterned at once by photolithography, if it is a top emission type, the manufacturing process of these members can be simplified.

  The insulating film 32 is formed of an insulating material such as a silicon oxide film or a silicon nitride film, and is formed on the pixel substrate 31 so as to cover the data line Ld, the gate electrodes 12g and 13g, and the capacitor electrode Cs1. The A contact portion as a contact hole is formed in the insulating film 32 to contact the gate conductive layer and the source / drain layer.

Each of the first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 is an n-channel thin film transistor (TFT). Each transistor is formed on the pixel substrate 31.
As shown in FIG. 3, the second selection transistor Tr12 includes a semiconductor layer 111 having a-Si or microcrystalline silicon, a protective insulating film 112, a drain electrode 11d, a source electrode 11s, and an a containing n-type impurities. -Ohmic contact layers 114 and 115 having microcrystalline silicon containing Si or n-type impurities, and a gate electrode 11g. As shown in FIG. 4, the second selection transistor Tr12 includes a semiconductor layer 121 having a-Si or microcrystalline silicon, a protective insulating film 122, a drain electrode 12d, a source electrode 12s, and an a containing n-type impurities. -Ohmic contact layers 124 and 125 having microcrystalline silicon containing Si or n-type impurities, and a gate electrode 12g. The light-emitting drive transistor Tr13 includes a semiconductor layer 131 including a-Si or microcrystalline silicon, a protective insulating film 132, a drain electrode 13d, a source electrode 13s, and a-Si or n-type impurities including n-type impurities. And ohmic contact layers 134 and 135 having microcrystalline silicon, and a gate electrode 13g.
The light emission drive transistor Tr13 is larger in size than the first selection transistor Tr11 and larger in size than the second selection transistor Tr12 in order to supply current to the organic EL element 21 to emit light. That is, in the light emission drive transistor Tr13, the channel width of the semiconductor layer 131 is longer than the channel width of the semiconductor layer of the first selection transistor Tr11 and longer than the channel width of the semiconductor layer 121 of the second selection transistor Tr12. Therefore, the source and drain electrodes 13s and 13d of the light emission drive transistor Tr13 are longer than the source and drain electrodes 11s and 11d of the first selection transistor Tr11 and longer than the source and drain electrodes 12s and 12d of the second selection transistor Tr12. . The channel widths of the source and drain electrodes 13s and 13d and the semiconductor layer 131 of the light emitting drive transistor Tr13 extend along the column direction.

  In each of the transistors Tr11, Tr12, and Tr13, the gate electrode is selected from at least one of, for example, a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, a MoNb alloy film, and the like. It is formed from an opaque gate conductive layer. Since the first selection transistor Tr11, the second selection transistor Tr12, and the gate electrodes 11g, 12g, and 13g of the light emission drive transistor Tr13 formed by the gate conductive layer are opaque to the light emitted from the organic EL element 21, Light entering from the lower side of the selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 toward each semiconductor layer can be shielded. The drain electrode and the source electrode are each formed of a source-drain conductive layer such as aluminum-titanium (AlTi) / Cr, AlNdTi / Cr, or Cr. In addition, an ohmic contact layer is formed between the drain electrode and the source electrode and the semiconductor layer for low resistance contact.

  In this embodiment, as shown in FIGS. 1 and 2, in the light emission drive transistor Tr13, the drain electrode 13d is connected to each column, and the drain electrode 13d also functions as a part of the column-direction connecting line Lc. . As a result, the four current supply lines La and the column-direction connecting lines Lc arranged in the row direction are connected in a mesh shape in the row direction and the column direction, thereby reducing the overall resistance and suppressing the voltage drop. it can. Since the drain electrode 13d also serves as a wiring for connecting the current supply line La in this way, there is no need to separately provide a region for forming a wiring for connecting the current supply line La on the pixel substrate. The voltage drop of the current supply line La can be suppressed without reducing the aperture ratio (the ratio of the area of the light emitting layer 38 interposed between the pixel electrode 34 and the counter electrode 40). Note that the gate line Lg running in the same direction as the current supply line La is formed using a third metal layer different from the source-drain conductive layer forming the source electrode and the drain electrode of the transistor. Since the gate line Lg extending in the row direction intersects the column-direction connecting line Lc (drain electrode 13d) via the interlayer insulating film 33 positioned below the gate line Lg, the gate line Lg is a current supply line. It is electrically insulated from La and the column direction connection wiring Lc. Further, a contact portion 49 that is a contact hole is provided in the interlayer insulating film 33 on the drain electrode 13d and the current supply line La, and the conductive layer 48 is placed on the drain electrode 13d and the current supply line La via the contact portion 49. Since they are connected to each other by being deposited, the current supply line La, the column-direction connecting line Lc, and the conductive layer 48 are connected to each other, so that the resistance of the entire line can be further lowered and the voltage drop is suppressed. Can do. Note that since the conductive layer 48 is formed using the third metal layer that is the same layer as the gate line Lg, the conductive layer 48 can be formed without increasing the number of steps for forming the conductive layer 48.

  The pixel electrode (anode electrode) 34 is made of a light-transmitting conductive material, for example, indium thin oxide (ITO) doped with tin oxide, indium oxide doped with zinc oxide (Indium Zinc Oxide), or the like. The Each pixel electrode 34 is separated from the pixel electrode 34 of another adjacent pixel 30.

  The interlayer insulating film 33 is formed of an insulating material, for example, a silicon nitride film, has a substantially rectangular opening 33 a that opens the center of each pixel electrode 34, and is adjacent to the pixel electrode 34 so as to surround the periphery of the pixel electrode 34. 34. The interlayer insulating film 33 is formed so as to cover the transistors Tr11, Tr12, Tr13, the current supply line La, and the like. As shown in FIG. 5, a gate line Lg and a conductive layer 48 are formed on the interlayer insulating film 33. Further, an insulating layer having an insulating material, for example, a silicon nitride film so as to cover the gate line Lg and the conductive layer 48 is formed. 35 is formed. The insulating layer 35 is formed with an opening 35a whose shape substantially coincides with the opening 33a, and the opening 33a and the light emitting layer 38 interposed between the pixel electrode 34 and the counter electrode 40 by the opening 35a, that is, A light emitting area of the pixel 30 is drawn. Further, a groove-shaped opening 39 b extending in the column direction (vertical direction in FIG. 2) is formed in the partition wall 39 across the plurality of pixels 30.

  The partition 39 is formed by curing an insulating material, for example, a photosensitive resin such as polyimide, and is formed on the interlayer insulating film 33 and the insulating layer 35. The partition 39 is formed in a stripe shape as shown in FIG. 2 and includes an opening 39b. The partition wall 39 is a liquid containing a material that becomes the light emitting layer 38 of the R (red) pixel 30 formed on the pixel electrode 34 during the manufacturing process, and a material that becomes the light emitting layer 38 of the G (green) pixel 30. And a liquid containing a material that will become the light emitting layer 38 of the B (blue) pixel 30, when applied to the pixel electrode 34, it flows out to the pixels 30 emitting different colors adjacent to each other in the row direction. The light-emitting layer 38 is prevented from being mixed. The planar shape of the partition wall 39 is not limited to this and may be a lattice shape.

  The hole injection layer 36 is formed on the pixel electrode 34 and has a function of supplying holes to the light emitting layer 38. The hole injection layer 36 includes an organic polymer material, a low molecular material, or an inorganic compound that can inject and transport holes. As an organic compound-containing liquid containing an organic polymer hole injection / transport material, for example, polyethylenedioxythiophene (PEDOT) which is a conductive polymer and polystyrene sulfonic acid (PSS) which is a dopant are dispersed in an aqueous solvent. The hole injection layer 36 is formed by applying and drying the PEDOT / PSS aqueous solution that is the dispersion. As the inorganic compound, the hole injection layer 36 is formed by continuously forming a high-resistance molybdenum oxide on the pixel electrode 34 and the surface of the partition wall 39.

  The interlayer 37 is formed on the hole injection layer 36. The interlayer 37 has a function of suppressing the hole injection property of the hole injection layer 36 to facilitate recombination of electrons and holes in the light emitting layer 38, in order to increase the light emission efficiency of the light emitting layer 38. It is an organic compound layer provided.

  The light emitting layer 38 is formed on the interlayer 37. The light emitting layer 38 has a function of generating light by applying a voltage between the anode electrode and the cathode electrode. The light emitting layer 38 is a known polymer light emitting material capable of emitting fluorescence or phosphorescence, for example, red (R) or green (G) containing a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene. And a blue (B) light emitting material. In addition, these luminescent materials are suitably used in a nozzle coating method in which a solution (dispersion) dissolved (or dispersed) in an aqueous solvent or an organic solvent such as tetralin, tetramethylbenzene, mesitylene, and xylene is discharged as a continuous liquid flow. It forms by apply | coating by the inkjet method etc. which are discharged as a separated several droplet, and volatilizing a solvent.

  Further, in the case of the bottom emission type, the counter electrode (cathode electrode) 40 is provided on the light emitting layer 38 side, and a layer having a conductive material, for example, a material having a low work function such as Li, Mg, Ca, Ba, and the like. A laminated structure having a light-reflective conductive layer such as Al laminated thereon. In the case of the top emission type, it is provided on the light emitting layer 38 side and is extremely thin with a thickness of about 10 nm, for example, Li, Mg, Ca, Ba A transparent laminated structure having a light transmissive low work function layer having a low work function material such as ITO and a light transmissive conductive layer such as ITO having a thickness of about 100 nm to 200 nm. In the present embodiment, the counter electrode 40 is composed of a single electrode layer formed across a plurality of pixels 30, and for example, a common voltage Vss that is a ground potential is applied.

Next, the operation of the light emitting device 10 and the operation of the pixel 30 according to the present embodiment will be described with reference to FIGS. When the current supply lines La are connected to each other in units of d rows (d is an integer of 2 or more), the first row gate line Lg to the nth row (n = c × d is satisfied; however, c is 2 or more) Of the gate lines Lg in the scanning period T _SC of the gate lines Lg connected to each other in the d-th scanning period, that is, a group of the i-th row to (i + d−1) -th row (where i = d × k− (d−1) = d (k−1) +1, where k is a natural number and is equal to or less than n / d). The group write voltage period T _WR (= d × T _SC ) of each group is assumed. In each group of d rows, groups emission voltage period T _EM as a group writing voltage period T _WR after the light emission period is followed, then the group writing voltage period T _WR, Groups emission voltage period T _EM is repeated again.

  In accordance with the control signal group output from the control circuit, the gate driver sequentially outputs high level (on level ON) pulses from the first row gate line Lg to the n th gate line Lg. In the present embodiment, since the current supply lines La are connected to each other by the column-direction connecting wiring Lc in units of four, the power supply or the current supply driver is set to “d = 4” according to the control signal group output from the control circuit. ", A low level L pulse is sequentially output every four rows from the current supply line La of the first row.

Here, as shown in FIG. 7, in each gate line Lg of the group of i to (i + d−1) rows, one scanning period T _{SC in} which the ON level ON pulse of the gate line Lg is output is shifted from each other. However, each one scanning period T _SC is set within the group write voltage period T _WR in which a low level L pulse is output to the current supply line La of i to (i + d−1) rows. In the present embodiment, since the current supply lines La of i to (i + d−1) rows are connected to each other by the column-direction connecting wiring Lc, the low level to the current supply lines La of i to (i + d−1) rows is low. The time length of the pulse of L is the sum of one scanning period T _SC for sequentially outputting on-level ON pulses from the i-th to (i + d−1) -th gate lines Lg, that is, the group write voltage period T _WR Become. In other words, the i-th (i + d−1) -th group current supply lines La are output to the i-th gate line Lg from the off-level OFF to on-level ON pulse, and then the (i + d−1) -th row. A low level L pulse is output until a pulse for switching from the ON level ON to the OFF level OFF is output to the gate line Lg. In addition, during the period when the ON level ON pulse is output to the gate line Lg of each row, the data driver syncs the data lines Ld in all columns according to the emission luminance gradation according to the control signal group output from the control circuit. A display signal that is a current (ie, a current toward the data driver) is generated. Here, the data driver applies a current driver that passes a gray-scale current that has a current value according to the image data received by the control circuit, or a gray-scale voltage that flows a current having a current value according to the image data. The display driver outputs a display signal to the data line Ld of each column and causes a sink current to flow.

The current flow and voltage application of each pixel 30 will be described in detail.
At the start time t _{i of the i-th} scanning period T _SC , a high level (on-level ON) pulse is output from the scanning driver to the i-th gate line Lg, and from time t _i to time t _{(i + 1).} During the scanning period T _SC until immediately before, the i-th gate line Lg has an on-level ON scanning signal voltage that turns on the first selection transistor Tr11 and the second selection transistor Tr12. Applied to line Lg. Subsequently, at the start time t _{(i + 1)} of the scanning period T _{SC in} the (i + 1) th row, a high level (on level ON) pulse is output from the scanning driver to the gate line Lg in the (i + 1) th row, On-level ON scanning signal voltage that turns on the first selection transistor Tr11 and the second selection transistor Tr12 on the gate line Lg of the (i + 1) th row from t _{(i + 1)} to immediately before time t _{(i + 2).} Is applied to the gate line Lg of the (i + 1) th row. Similarly, from time t _{(i + 2),} which is the scanning period T _SC of the (i + 2) th row, to immediately before time t _{(i + 3)} , the gate line Lg of the (i + 2) th row has the first selection transistor Tr11 and the second selection transistor Tr11. An on-level ON scanning signal voltage that turns on the selection transistor Tr12 is applied to the gate line Lg of the (i + 2) -th row, and the time from the time t _{(i + 3)} that is the scanning period T _SC of the (i + 3) -th row. Until just before t _{(i + 4)} , the (i + 3) -th row gate line Lg has an on-level ON scanning signal voltage that turns on the first selection transistor Tr11 and the second selection transistor Tr12. Applied to the gate line Lg of the eye.

Furthermore, at the start time t _i of the group write voltage period T _{WR for} the d-th group of the i- (i + d−1) th row, the current of the i- (i + d−1) -th group from the power supply or current supply driver. A low level L pulse signal is output to the supply line La. The low level L is equal to or lower than the reference potential Vss. Furthermore, each row of the scanning period T _SC, the data driver in accordance with image data received by the control circuit, supplying a sink current of a predetermined current value.

First, in the scanning period T _SC of the i-th gate line Lg, the first selection transistor Tr11 and the second selection transistor Tr12 are turned on, and the data driver performs a sink current for current control whose voltage value is equal to or lower than the reference voltage Vss. To the data line Ld of each column. Therefore, a voltage corresponding to the current value of the sink current is applied to one end of the gate and source of the light emission drive transistor Tr13, and as shown in FIG. 6A, the data line Ld and the second selection transistor Tr12 are used. A sink current flows through the light emission drive transistor Tr13.

Since the potential of the gate electrode 13g of the light emission drive transistor Tr13 is equal to the potential of the drain electrode 13d, a potential difference is generated between the gate and the source of the light emission drive transistor Tr13, and the data line Ld follows the voltage specified by the data driver. The sink current I having the current value (that is, the current value according to the image data) flows in the direction indicated by the arrow K shown in FIG. In the scanning period T _SC , since the power supply signal voltage of the current supply line La is equal to or lower than the reference voltage H, the anode potential of the organic EL element 21 is lower than the cathode potential, and the reverse bias voltage is applied to the organic EL element 21. Is applied. Therefore, no current from the current supply line La flows through the organic EL element 21.

  At this time, both ends of the capacitor 13 of each pixel 30 become a voltage according to the current value of the current flowing through the drain electrode 13d-source electrode 13s of the light emission drive transistor Tr13 based on the display signal controlled by the data driver. That is, the capacitor 13 of each pixel 30 has a charge that causes a potential difference between the gate and the source of each light emission drive transistor Tr13 that causes the current I according to the display signal to flow through the light emission drive transistor Tr13 of each pixel 30. Charged.

Such an operation is performed for each scanning period T _SC for i to (i + d−1) rows. At the end time t _{(i + d)} of the group write voltage period T _WR, the pulse output from the scan driver to the (i + d−1) -th gate line Lg is switched from the on level ON to the off level OFF, and the power source or current A signal output from the supply driver to the i to (i + d−1) rows of current supply lines La is switched from the low level L to the high level H. Accordingly, in the group of i to (i + d−1) rows, _{i to (i + d)} during the group light emission voltage period T _EM from the end time t _{(i + d)} to the start time t _i of the next group write voltage period T _WR. -1) An off level OFF (low level) scanning signal voltage is applied to the gate of the first selection transistor Tr11 and the gate of the second selection transistor Tr12 to the gate line Lg of the row, and also applied to the current supply line La. The power supply signal voltage is a high-level power supply voltage H that is sufficiently higher than the potential low level L output during the reference potential Vss and the group write voltage period _TWR .

Therefore, as shown in FIG. 6B, in the group light emission voltage period _TEM , the second selection transistor Tr12 in the non-selected row is turned off, and no current flows through the second selection transistor Tr12. Furthermore, the group emission voltage period T _EM, the first selection transistor Tr11 is turned off, capacitor 13, continues to hold the electric charge stored by the first and second ends, the light emission drive transistor Tr13 is maintained in the on state Keep doing. That is, the gate-source voltage value V _GS of the light emission drive transistor Tr13 is equal in the group light emission voltage period T _EM and the group write voltage period T _WR immediately before the group light emission voltage period T _EM . Therefore, even a group emission voltage period T _EM, since the light emission drive transistor Tr13 continues flowing a current having a current value according to the image data, the current value of the current I of the group emission voltage period T _EM is the group emission voltage period T _EM It is equal to the current value of the current K in the previous group write voltage period _TWR . During the group emission voltage period T _EM, current K flowing through the light emission drive transistor Tr13 is flow through the organic EL element 21 emits light at a luminance according to the current value of the current I in which the organic EL element 21 flows. In this way, the organic EL element 21 emits light at a luminance gradation according to the display signal.

Further, when i~ (i + d-1) a group writing voltage period T _WR of th gate line Lg is completed, continue (i + d) th ~ (i + 2d-1) gate line Lg of row groups are sequentially selected at a group writing voltage period T _WR that, during this time, the signal output from the power source or current supply driver (i + d) ~ (i + 2d-1) row of the current supply line La is switched from the low level L to high level H. As described above, when the writing of all the rows is completed by switching the voltage of the current supply line La so that the writing is performed in a group of d rows connected to each other, the current supply line La is completed. One scanning period T _SC starts from Lg, and writing is repeated.

  Next, a manufacturing method of the bottom emission type light emitting device according to the present embodiment will be described with reference to FIGS. The first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 have the same basic structure except for the channel width, and the first selection transistor Tr11 is the same as the second selection transistor Tr12. Since it is formed by the same process, the description thereof is omitted below.

  First, a pixel substrate 31 having a glass substrate or the like is prepared. A transparent conductive film such as ITO is deposited on the pixel substrate 31 by sputtering, vacuum evaporation, or the like, and then a capacitor electrode Cs1 is patterned by photolithography.

  Next, on the pixel substrate 31, for example, at least one of a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, and a MoNb alloy film is formed by sputtering, vacuum deposition, or the like. A gate conductive film is formed and patterned into the shapes of the gate electrodes 12g and 13g of the transistors Tr12 and Tr13 and the data line Ld as shown in FIG. At this time, the gate electrode 13g of the light emission drive transistor Tr13 is formed so as to overlap with a part of the capacitor electrode Cs1 in the contact portion 44, but the transparent metal oxide such as ITO which becomes the capacitor electrode Cs1 has a contact resistance with Al. Therefore, the gate conductive film is preferably a Mo film or MoNb alloy film having a relatively low contact resistance with a transparent metal oxide such as ITO. In the case of the top emission type, the capacitor electrode Cs1 does not need to be transparent, so that the gate conductive film is patterned to integrally form the gate electrode 13g of the light emission drive transistor Tr13 and the source electrode 11s of the first selection transistor Tr11. Since it is formed, there is no restriction on the material of the transparent conductive film described above.

  Subsequently, an insulating film 32, an amorphous silicon film, and a silicon nitride film are successively deposited on the gate electrodes 12g and 13g, the capacitor electrode Cs1, and the data line Ld by a CVD (Chemical Vapor Deposition) method or the like, and a silicon nitride film is formed. The protective insulating films 122 and 132 are formed by patterning.

  Next, after depositing an amorphous silicon film containing an n-type impurity by a CVD method or the like, patterning is performed to form ohmic contact layers 124, 125, 134, 135 as shown in FIG. The semiconductor layers 121 and 131 of the transistors Tr12 and Tr13 are formed by patterning.

  Next, a transparent conductive film such as ITO is used on the insulating film 32 by sputtering, vacuum deposition, or the like in the case of the bottom emission type, and a light reflective conductive film and a transparent conductive film such as ITO in the case of the top emission type. After coating, the pixel electrode 34 is formed by patterning by photolithography.

  Subsequently, after forming contact portions 41 and 43 which are through holes in the insulating film 32, for example, Mo film, Cr film, Al film, Cr / Al laminated film, AlTi alloy film, AlNdTi alloy film, MoNb alloy film A source-drain conductive film containing at least one of the above is coated by sputtering, vacuum deposition or the like, and patterned by photolithography to form drain electrodes 12d, 13d and a source as shown in FIGS. The electrodes 12s and 13s, the current supply line La, and the column direction connection wiring Lc are formed. At this time, the source electrode 13s of the light emission drive transistor Tr13 and the drain electrode 12d of the second selection transistor Tr12 are formed so as to overlap with part of the pixel electrode 34, respectively. Thus, since the source electrode 13s of the light emission drive transistor Tr13 and the drain electrode 12d of the second selection transistor Tr12 are connected via the pixel electrode 34, the second selection transistor Tr12 and the light emission drive transistor Tr13 are mutually connected. A lead-out wiring for connection becomes unnecessary, and the aperture ratio of the pixel can be increased. The contact holes 41 and 43 together with the contact holes exposing the connection terminal portions of the gate lines Lg for connection to the gate driver and the connection terminal portions of the data lines Ld for connection to the data driver are respectively formed in the insulating film 32. You may form in. If the conductive film to be the pixel electrode 34 is deposited after forming the contact holes and the contact portions 41 and 43 and then patterned by photolithography, the pixel electrode 34 is formed and the contact portions 41 and 43 are formed. A connection portion having a three-layer structure in which a conductive film to be the pixel electrode 34 is interposed between the gate conductive film and the source-drain conductive film can be formed.

  Subsequently, as shown in FIG. 8C, an interlayer insulating film 33 having a silicon nitride film is formed by CVD or the like so as to cover the transistors Tr12, Tr13 and the like.

  In the interlayer insulating film 33, openings that become the contact portion 49 and the contact portion 42 are formed by photolithography or the like. Subsequently, for example, a metal film including a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, a MoNb alloy film, or the like is formed by a vacuum evaporation method or a sputtering method. Next, by patterning by photolithography, as shown in FIGS. 2 and 9A, the conductive layer 48 connected to the column-direction connecting wiring Lc and the current supply line La via the contact portion 49, and the contact portion 42 are formed. Thus, the gate electrode 12g of the second selection transistor Tr12 and the gate line Lg connected to the gate electrode 11g of the first selection transistor Tr11 are formed. Subsequently, an insulating layer 35 having a silicon nitride film or the like is formed so as to cover the conductive layer 48 and the gate line Lg. Next, as shown in FIG. 9B, an opening 35 a that exposes the pixel electrode 34 is formed in the insulating layer 35 and the interlayer insulating film 33.

  Next, photosensitive polyimide is applied so as to cover the interlayer insulating film 33 and the insulating layer 35, and is patterned by exposure, development, and baking through a mask corresponding to the shape of the partition wall 39, as shown in FIG. As shown in FIG.

  Subsequently, the organic compound-containing liquid containing the hole injection material was surrounded by the opening 35a by a nozzle printing apparatus that continuously flows, an inkjet apparatus that discharges the liquid as a plurality of individual droplets, or a roll-type printing apparatus. It is selectively applied onto the pixel electrode 34. Subsequently, the pixel substrate 31 is heated in an air atmosphere to volatilize the solvent of the organic compound-containing liquid, thereby forming the hole injection layer 36. The organic compound-containing liquid may be applied in a heated atmosphere. In addition to the wet film formation, the hole injection layer 36 may be formed by vapor deposition.

  Subsequently, an organic compound-containing liquid containing a material that becomes the interlayer 37 is applied onto the hole injection layer 36 using a nozzle printing apparatus, an inkjet apparatus, or a roll printing apparatus. The interlayer 37 is formed by performing heat drying in a nitrogen atmosphere or heat drying in a vacuum to remove the residual solvent. The organic compound-containing liquid may be applied in a heated atmosphere.

  Next, an organic compound-containing liquid containing the light emitting polymer material (R, G, B) is similarly applied by a nozzle printing apparatus, an ink jet apparatus, or a roll type printing apparatus and heated in a nitrogen atmosphere to remove residual solvent. Removal is performed to form the light emitting layer 38. The organic compound-containing liquid may be applied in a heated atmosphere.

  In the case of the bottom emission type, a layer having a low work function material such as Li, Mg, Ca, Ba and a light reflective conductive layer such as Al are formed on the pixel substrate 31 formed up to the light emitting layer 38 by vacuum deposition or sputtering. A counter electrode 40 having a two-layer structure is formed. In the case of the top emission type, the counter electrode 40 is formed on a light transmissive low work function layer having an extremely thin material having a low work function such as Li, Mg, Ca, Ba, and the like having a thickness of about 10 nm. In addition, a transparent laminated structure having a light-reflective conductive layer such as ITO having a thickness of about 100 nm to 200 nm is obtained.

Next, outside the display area where the plurality of pixels 30 are formed, a sealing resin having an ultraviolet curable resin or a thermosetting resin is applied onto the pixel substrate 31, and the pixel substrate 31 and the sealing substrate are bonded together. . Next, the sealing resin is cured by ultraviolet rays or heat to bond the pixel substrate 31 and the sealing substrate.
Through the above steps, the light emitting device 10 is manufactured as shown in FIG.

  In the present embodiment, a plurality of current supply lines La formed in the row direction are formed by forming the column-direction connecting lines Lc so that the drain electrodes 13d of the light emission drive transistors Tr13 are connected to each other in units of a plurality of rows. Are tied in a mesh. Accordingly, it is possible to suppress a drop due to the wiring resistance of the voltage applied to the current supply line La, and it is possible to cause a plurality of organic EL elements to emit light satisfactorily. In particular, in the present embodiment, since the drain electrode 13d is extended in the column direction of the pixel to form the column direction connection wiring Lc, a wiring for connecting the current supply line La is formed separately from the drain electrode 13d. There is no need to provide a region to be formed on the pixel substrate 31. Thereby, the voltage drop of the current supply line La can be suppressed without reducing the aperture ratio of the pixel 30.

In the present embodiment, since the drain electrode 13d is extended, the gate line Lg intersecting the drain electrode 13d is formed of a third metal layer different from the gate conductive layer and the source-drain conductive layer. is doing. When forming the gate line Lg, the thickness of the current supply line La can be increased without particularly increasing the number of steps by forming the third metal layer on the current supply line La and the drain electrode 13d. Thus, the resistance of the current supply line La can be reduced.
The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in the above-described embodiment, the conductive layer 48 is formed so as to cover the current supply line La and is formed on the drain electrode 13d of the light emission drive transistor Tr13. However, the present invention is not limited thereto. Instead, the conductive layer 48 may be formed so as to be separated for each pixel on the current supply line La. Further, it may be formed so as to cover only the drain electrode 13d.

  In the above-described embodiment, the bottom emission type organic EL element has been mainly described. However, the present invention is not limited thereto, and the top emission type organic EL element that emits display light of the organic EL element 21 to the outside through the counter electrode 40 is not limited thereto. It can also be used.

  In the embodiment described above, the light emitting device is a display device. However, the light emitting device can also be applied to a printer head that emits light to a photosensitive drum of a printer.

In the above-described embodiment, the organic EL element includes the hole injection layer 36, the interlayer 37, and the light emitting layer 38. However, the combination of the carrier transport layers is not limited to this, and for example, the hole injection layer 36 The light emitting layer 38 may be a two-layer structure, the light emitting layer may be a single layer structure also serving as a hole injection layer, or the carrier transport layer including the light emitting layer may be a layer structure of four or more layers.
In the above-described embodiment, the organic EL element 21 is applied, but other light emitting elements such as LEDs may be applied.

  In the above-described embodiments, the configurations of the embodiments may be arbitrarily combined as long as there is consistency.

  DESCRIPTION OF SYMBOLS 10 ... Light-emitting device, 30 ... Pixel, 21 ... Organic EL element, 31 ... Pixel substrate, 32 ... Insulating film, 33 ... Interlayer insulating film, 34 ... Pixel electrode, 35 ... Insulating layer, 36 ... Hole injection layer, 37 ... Interlayer, 38 ... Light emitting layer, 39 ... Partition, 40 ... Counter electrode, 41, 42, 43, 44 , 49 ... contact part, 48 ... conductive layer, Cs ... capacitor, Cs1 ... capacitor electrode, La ... current supply line, Lc ... column direction connection wiring, Ld ... data Line, Lg ... Gate line, Tr11 ... First selection transistor, Tr12 ... Second selection transistor, Tr13 ... Light emission drive transistor

Claims (3)

A light-emitting element having a first electrode, a second electrode, and at least one carrier transport layer disposed between the first electrode and the second electrode;
A light emission driving transistor connected to the light emitting element;
A capacitor having a capacitor electrode;
A selection transistor connected to the light emission drive transistor via the capacitor electrode;
A light emitting device comprising:   2. The light emitting device according to claim 1, wherein one of the source and drain electrodes of the selection transistor is connected to the gate electrode of the light emission driving transistor through the capacitor electrode, and the other is connected to the anode line. .   The one of the source and drain electrodes of the selection transistor is connected to one side of the capacitor electrode, and the gate electrode of the light emission driving transistor is connected to the other side of the capacitor electrode facing the one side. The light emitting device according to claim 2.

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