JP2011193179A - Radiowave receiver and radiowave clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a radiowave receiver including a small offset voltage-removing circuit with a simple configuration in the radiowave receiver for performing signal amplification processing of a plurality of stages. <P>SOLUTION: The radiowave receiver for demodulating a received signal includes: a plurality of IF amplifiers 101 arranged in series; a phase delay circuit 112 for generating a delay signal obtained by performing prescribed phase delay of a received input signal at least at one place between the stages of the plurality of IF amplifiers 101; and an offset-removing circuit 102 having a subtractor 42 for outputting a difference between the delay signal and the input signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a radio wave receiving apparatus including an amplifying unit for a received radio wave signal, and a radio timepiece including the radio wave receiving apparatus.

  Radio wave receivers capable of obtaining a high signal amplification factor have been developed. In this radio wave receiving apparatus, after the received carrier frequency input signal is converted to a frequency lower than the carrier frequency, the signal converted to the lower frequency is amplified using a plurality of signal amplifiers.

  However, it is known that an offset voltage is generated when an input signal is amplified by a signal amplifier. Therefore, in the signal amplification processing over a plurality of stages, the offset voltage generated by the amplification up to the previous stage is also amplified during the amplification after the second stage. The amplified offset voltage causes a part or the whole of the signal waveform to be out of the operating voltage range of the radio wave receiver, resulting in a problem that the signal is distorted or cannot be read at all. .

  In order to solve such a problem, a technique for removing an offset voltage by arranging a capacitor between the respective signal amplifiers is known. However, in order to remove the DC offset voltage from the low frequency signal below the intermediate frequency, a capacitor having a large capacity is required. It has been difficult to arrange such a large capacitor on a small LSI chip. Therefore, conventionally, the amplified signal is integrated for a predetermined time, the offset voltage is calculated from the average of the integrated values, fed back to the circuit portion before signal amplification, and subtracted from the input voltage to remove the offset voltage. Have been disclosed (for example, Patent Document 1 and Patent Document 2).

JP 2002-111864 A International Publication No. 2007/020845

  However, when a feedback circuit is added to the receiving circuit to remove the offset voltage, the scale of the integrating circuit for accurately obtaining the offset voltage is increased, and the stability of the circuit is likely to be impaired by the feedback processing. was there. In addition, there is a problem in that the response performance of the receiving circuit is deteriorated by requiring a predetermined integration time when obtaining the offset voltage.

  An object of the present invention is to provide a radio wave receiving apparatus that performs a plurality of stages of signal amplification processing and includes a small offset voltage removing unit with a simple configuration.

In order to achieve the above object, the present invention described in claim 1
In the radio wave receiver that demodulates the received signal,
Comprising a plurality of signal amplifying means arranged in series;
At least one of the stages of the plurality of signal amplification means is
A delay signal generating means for generating a delayed signal obtained by delaying a received input signal by a predetermined phase; a signal combining means for outputting a difference between the delayed signal and the input signal;
It is characterized by having.

The invention described in claim 2 is the radio wave receiver according to claim 1,
The delayed signal generating means includes
Data holding means is provided for outputting the input signal after holding the input signal for a predetermined time.

The invention according to claim 3 is the radio wave receiving apparatus according to claim 2,
The input signal is discretely input to the delay signal generation unit and the signal synthesis unit at a frequency equal to or higher than the frequency of the input signal.

The invention according to claim 4 is the radio wave receiving apparatus according to any one of claims 1 to 3,
The delayed signal generating means includes
Analog-to-digital conversion means for digitally converting the analog voltage data of the input signal at a predetermined sampling frequency;
Digital-analog conversion means for converting a digital signal into analog voltage data,
The data holding means is
The digital-converted input signal is held for a predetermined time and then output to the digital-analog conversion means.

The invention according to claim 5 is the radio wave receiver according to any one of claims 1 to 4,
The output signal of the said signal synthetic | combination means is input, The band filter which selectively outputs the signal of the same frequency as the said input signal is provided.

The invention according to claim 6 is the radio wave receiver according to any one of claims 1 to 5,
Frequency conversion means for converting the received signal into a signal of a predetermined intermediate frequency;
The input signal is the converted intermediate frequency signal.

Invention of Claim 7 is equipped with the electromagnetic wave receiver as described in any one of Claims 1-6,
A radio timepiece that receives standard radio waves from the radio wave receiver.

  According to the present invention, there is an effect that the offset voltage can be removed with a small and simple configuration in the radio wave receiving apparatus that performs signal amplification processing in a plurality of stages.

It is a block diagram which shows the internal structure of the radio timepiece of embodiment of this invention. It is a figure which shows the circuit structure of the intermediate | middle frequency amplification part and offset removal circuit which are contained in the radio wave reception process part of a radio timepiece. It is a figure which shows the signal waveform in each part of the intermediate | middle frequency amplification part and offset removal circuit contained in the radio wave reception process part of a radio timepiece.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an internal configuration of a radio timepiece including a radio wave receiver according to an embodiment of the present invention.

  The radio timepiece 1 in this embodiment is a timepiece having a function of receiving a standard radio wave and correcting the current time. The standard radio wave is, for example, a 40 kHz and 60 kHz amplitude modulated wave called JJY in Japan. In this standard radio wave, 60 codes are arranged and transmitted per second according to a predetermined format per second. JJY has three types of transmission codes. These codes indicate the ratio of the duration of a high level period output at a predetermined amplitude and a low level period that is 10% of the amplitude of the high level period. Each is a different rectangular wave. Then, by decoding these three types of code arrays (time codes), time and date data can be acquired.

  As shown in FIG. 1, the radio timepiece 1 includes a radio wave reception processing unit 10 that receives a standard radio wave and outputs a time code signal, an oscillation circuit 11 that generates a pulse signal (clock signal) of a predetermined frequency, A clock circuit 12 that counts time based on a pulse signal input from the oscillation circuit 11, a CPU 13 that performs overall control processing of the radio timepiece 1, and a display that displays information such as time based on a control signal from the CPU 13. Part 14 and the like.

  The display unit 14 is, for example, an LCD (liquid crystal display). Alternatively, in the case of a pointer type timepiece, for example, a plurality of hands, a step motor that rotates the hands by a predetermined angle, and a drive circuit that outputs a pulse for driving the step motor are included.

  The radio wave reception processing unit 10 includes an antenna 22 that receives a standard radio wave, an RF amplifier 23 that amplifies the received signal, a mixer 25 that converts the received signal into a signal in a predetermined intermediate frequency band, and a mixer 25. A local oscillator 24 that oscillates and outputs a signal for frequency conversion, a BPF (band pass filter) 26 that extracts only a signal in a predetermined intermediate frequency band from the signals output from the mixer 25, and a BPF 26 An intermediate frequency amplification unit 101 that amplifies the received signal, and an offset removal circuit 102 (offset voltage removal means) that is disposed in the middle of the signal amplification processing in the intermediate frequency amplification unit 101 and removes the offset voltage generated in the intermediate frequency amplification unit 101 ), A detector 28 for demodulating the time code signal from the amplified intermediate frequency signal, and the demodulated signal as a reference voltage By comparison, a like determining comparator 29 the signal level.

  The antenna 22 is, for example, a bar antenna configured by providing a winding around a ferrite core. By combining this antenna 22 and a capacitor (not shown) with an appropriate capacity, it is possible to receive radio waves in the standard frequency band to be received. In addition, when selecting and receiving one standard radio wave from a plurality of standard radio stations in different frequency bands, the tuning frequency may be changed by changing the capacitance of the combined capacitor. it can.

  When receiving the standard radio wave of 40 kHz, the local oscillator 24 oscillates, for example, a 39.9 kHz signal and outputs it to the mixer 25. The input radio wave signal is converted into an intermediate frequency signal of 100 Hz in the mixer 25. The local oscillator 24 uses, for example, a VCO (Voltage Controlled Oscillator). When a single standard radio wave is selected from a plurality of standard radio stations in different frequency bands and received, the oscillation frequency is set. It is possible to change so that an intermediate frequency signal having the same frequency can be output.

  The BPF 26 passes only a signal in a predetermined intermediate frequency band out of the signals output from the mixer 25 and outputs the signal to the intermediate frequency amplification unit 101. The BPF 26 removes an image frequency signal, an offset voltage leaked from the local oscillator 24, noise at other frequencies, and the like.

  The intermediate frequency amplifying unit 101 is configured with three IF amplifiers A1, A2, and A3 (signal amplifying means), although not particularly limited thereto. In the present embodiment, the intermediate frequency signal is amplified in two stages by the IF amplifiers A1 and A2, and then input to the offset removal circuit 102, which is generated by the IF amplifiers A1 and A2, and the amplified offset voltage is removed. . The intermediate frequency signal from which the offset voltage has been removed is further amplified by the third-stage IF amplifier A3.

  FIG. 2 is a diagram illustrating a circuit configuration of the offset removal circuit 102.

  The offset removal circuit 102 is provided between the IF amplifier A2 and the IF amplifier A3. The offset removal circuit 102 includes a switch 41 that outputs the output signal of the IF amplifier A2 to the node 47 in a pulsed manner at a predetermined interval, and a phase delay circuit 112 (delayed signal generation) that delays the input signal from the node 47 by a predetermined phase. Means), a subtractor 42 (signal synthesis means) that calculates and outputs a difference between the input signal of the node 47 and the output signal of the phase delay circuit 112, and outputs only a frequency equal to or lower than the intermediate frequency from the output signal of the subtractor 42. An LPF (low-pass filter) 43 to be passed is provided.

  The phase delay circuit 112, for example, an ADC 46 (analog / digital converter) that quantizes the voltage value of the input intermediate frequency signal at a predetermined sampling frequency and converts the digital value, and a shift register 45 (data) that holds the converted digital data. Holding means) and a DAC 44 (digital / analog converter) that converts the digital output data of the shift register 45 into analog again.

  The subtractor 42 is, for example, a subtraction circuit using an operational amplifier. The subtractor 42 inputs the input signal from the node 47 to the non-inverting terminal (plus terminal) side, and outputs the output signal of the phase delay circuit 112 to the inverting terminal (minus terminal). To the side.

  The LPF 43 is a bandpass filter that selectively extracts and restores an intermediate frequency signal from a signal on which a signal generated by switching the switch 41 is superimposed. Therefore, it is good also as using BPF which can also exclude a low frequency band.

  The components of the electronic timepiece 1 shown in FIGS. 1 and 2 can be arranged on a single LSI substrate stored inside the electronic timepiece 1 except for the antenna 22 and the display unit 14. Alternatively, the oscillation circuit 11, the clock circuit 12, and the CPU 13 may be formed on a watch LSI substrate, and the radio wave reception processing unit 10 excluding the antenna 22 may be formed on a different LSI substrate.

  Next, the offset voltage removal method and the signal flow in the offset removal circuit 102 will be described.

The standard radio wave is an amplitude-modulated wave in which either a high-level signal or a low-level signal is alternately transmitted in the range of a duration of 200 ms to 800 ms. Therefore, the standard radio wave is intermediate between 100 Hz amplified by the IF amplifiers A1 and A2. In the frequency signal V1, a sine wave having substantially the same amplitude A and the same frequency ω / (2π) repeatedly appears with the offset voltage V0, as represented by the equation (1).
V1 (t) = Asin (ωt) + V0 (1)

Here, a delay signal V2 (formula (2)) obtained by delaying the signal of formula (1) by a predetermined phase φ is generated.
V2 (t) = Asin (ωt + φ) + V0 (2)
Then, subtracting the signal of formula (2) from the signal of formula (1),
Vr (t) = V1 (t) −V2 (t)
= A√ (2 (1-cosφ)) sin (ωt + θ) (3)
However,
θ = atan (− (1−cos φ) / sin φ) (4)
Thus, a combined signal Vr expressed by the mathematical formulas (3) and (4) is obtained. That is, the output signal Vr is delayed from the original signal V1 by the phase θ, the amplitude is amplified by √ (2 (1-cosφ)) times, and the offset voltage V0 is removed.

  Therefore, when the phase delay φ of the delay signal Vr is set to 60 degrees, for example, the amplification factor of the amplitude is 1, and the phase delay θ of the synthesized signal Vr with respect to the input intermediate frequency signal V1 is −30 degrees. . The offset voltage V0 is removed from the combined signal.

  FIG. 3 is a diagram showing signal waveforms in each part of the intermediate frequency amplifying unit 101 and the offset removing circuit 102.

  First, as shown in FIG. 3A, the input signal to the IF amplifier A1 is a sine wave having a substantially constant amplitude converted into a signal having an intermediate frequency (for example, 100 Hz) by the mixer 25 and the BPF 26.

  Next, when this input signal passes through the IF amplifiers A1 and A2, an offset voltage V0 represented by a broken line is added to the amplified signal output from the IF amplifier A2 as shown in FIG. The This offset voltage V0 is the sum of the offset voltage generated by IF amplifier A1 multiplied by the amplification factor of IF amplifier A2 and the offset voltage generated by IF amplifier A2. Here, in FIG. 3, the signal amplification factors of the IF amplifiers A1, A2, and A3 are all shown as 1.

  Subsequently, the output signal of the IF amplifier A 2 is input to the offset removal circuit 102. This output signal is sent to the node 47 only during the period when the switch 41 is on. The operation of switching the switch 41 on and off is performed based on a clock signal input from the oscillation circuit 11. Alternatively, an appropriate frequency signal can be input by dividing the clock signal from the oscillation circuit 11. The frequency of the clock signal is set to a value that is equal to or higher than the intermediate frequency and that can be easily separated by the LPF 43 later. Here, for example, it is 5 times the intermediate frequency, that is, 500 Hz (FIG. 3G).

The switch 41 is turned on for a predetermined time in synchronization with the rising of the clock signal from the low level to the high level. As shown by the signal voltage waveform at the node 47 (FIG. 3C), for example, by setting the period during which the switch 41 is turned on to be shorter than the period of the intermediate frequency signal or the clock signal, the IF amplifier A2 The output signal voltage is input in the form of a pulse, and the voltage of the signal voltage at the node 47 is 0 because the switch 41 is turned off except during this input period.

  The signal voltage at the node 47 is branched to the subtractor 42 and the phase delay circuit 112 and input simultaneously. The voltage value of the signal input to the phase delay circuit 112 is converted to a digital value by the ADC 46 at a predetermined sampling frequency, and sequentially input to the shift register 45 having the number of bits corresponding to the number of bits of the converted digital value. . The digital signal output from the shift register 45 after a predetermined period is returned to an analog signal by the DAC 44 and output from the phase delay circuit 112.

  The phase delay amount of the signal output from the phase delay circuit 112 is appropriately set according to the number of shift register stages and the frequency at which each shift register is operated. In the present embodiment, for example, a three-stage shift register is provided, and data input to the first shift register in synchronization with the rising edge of the clock signal is sent to the next shift register every half cycle, and the clock signal Is output from the third-stage shift register in synchronization with the fall after one and a half cycles. Then, the voltage signal analog-converted by the ADC 46 is sent to the subtractor 42. As a result, the delayed signal is delayed in phase by 3π / 5 from the amplified input signal of FIG. 3C, as shown in FIG.

  In the subtracter 42, the voltage value of the signal input via the phase delay circuit 112 is subtracted from the voltage value of the node 47 that is directly input, and is output to the LPF 43. In this embodiment, since the input signal to the subtractor 42 is pulsed, the output signal from the subtractor 42 is a broken line equal to the dotted line shown in FIG. 3C, as shown in FIG. The discrete signal on e1 and the discrete signal on the broken line e2 obtained by inverting the dotted line shown in FIG.

  The signal output from the subtractor 42 to the LPF 43 is input to the IF amplifier A3 after high frequency fluctuation components equal to or higher than the intermediate frequency are removed, further amplified, and output from the intermediate frequency amplifier 101. As shown in FIG. 3E, a signal obtained by synthesizing the waveform of the broken line e1 and the waveform of the broken line e2 becomes a waveform obtained by advancing the output signal of the IF amplifier A2 by 3π / 10, as indicated by a dotted line e3. On the other hand, the phase of the discrete signal output from the subtractor 42 is delayed by the LPF 43, and in this embodiment, the signal finally output from the IF amplifier A3 is intermediate as shown in FIG. The frequency signal is reproduced and the phase is close to that of the output signal of the IF amplifier A2.

  In this way, the intermediate frequency signal is greatly amplified within the operating voltage range of the radio wave reception processing unit 10 by the three IF amplifiers A1, A2, and A3, and is output to the detector 28.

  As described above, according to the radio wave receiver provided in the radio timepiece 1 of the embodiment of the present invention, a signal obtained by delaying the input signal by a predetermined phase is generated by the phase delay circuit 112 and the subtractor 42 is used. Since the delayed signal is subtracted from the original input signal, even if the intermediate frequency amplifier 101 uses a plurality of IF amplifiers A1 to A3, the signal is not distorted by the amplified offset voltage and is a high signal. An amplification factor can be obtained.

  In addition, since the influence of the offset voltage is removed in almost real time, it is difficult to be affected by temporary signal distortion, and the output signal can be prevented from being greatly delayed.

  In addition, by holding the input voltage value using a simple configuration without using a feedback circuit or an integration circuit, the input voltage value can be delayed by a predetermined phase, and the offset voltage can be removed. It can be placed on an LSI chip and can be stably amplified.

  In addition, since only a necessary amount of signals are intermittently output using the switch 41, the configuration of the delay signal generation circuit 112 is simplified and the size can be reduced.

  In addition, data can be easily processed by digitizing the input voltage of the intermediate frequency signal to the delay circuit.

  Further, by digitizing the data only in the delay signal generation circuit 112 and delaying it using the shift register 45, it is possible to easily delay the signal based on the input of the clock signal without requiring arithmetic processing by a CPU or the like. it can.

  In addition, since the intermediate frequency band signal is restored by the LPF 43 after the offset is removed using discrete data, the signal can be amplified while removing the offset without degrading the signal quality.

  In particular, after the conversion to the intermediate frequency is performed using the local oscillator 24 and the mixer 25, the intermediate frequency signal is amplified using a plurality of amplifiers and an offset removal circuit, so that noise is not increased. A high signal amplification factor can be obtained without degrading the signal quality.

  In addition, by using the radio wave reception processing unit 10 including the offset removal circuit 102 for the radio timepiece 1, the standard radio wave reception apparatus can reduce the offset removal circuit in the low frequency band and can perform amplification processing with a high signal amplification factor. It can be performed.

  Furthermore, in the case of amplification of a signal in which a signal of a predetermined frequency lasts for a sufficiently long period of time compared to the intermediate frequency, such as a standard radio wave received by a radio clock, the waveform between the normal input signal waveform and the delayed signal waveform Since it is not necessary to consider the time change, it is possible to reliably synthesize the same signals that differ only in phase.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the present embodiment, a standard radio wave receiver mounted on a radio timepiece is taken as an example. However, the radio wave receiver of the present invention can receive other radio waves that receive radio waves whose waveforms of adjacent periods of an intermediate frequency signal do not change significantly. It can also be used in a receiving device, for example, a radio receiver.

  In the above embodiment, a set of pulsed input signal data is output to the subtractor 42 per cycle of the clock signal sent to the switch 41. However, the operating frequency of the shift register 45 is changed or the shift register 45 By providing a plurality of stages 45 to increase the number of samplings, predetermined continuous time data is directly input from the switch 41 to the subtractor 42, or offset voltage removal processing is performed without using the switch 41. It is also possible.

  Further, in the offset removal circuit 102 of the above embodiment, the offset removal processing is performed without performing additional control calculation processing by a combination of the analog circuit and the digital circuit, but the output of the IF amplifier A2 is converted into a digital signal, It is also possible to perform offset removal by digital processing using a CPU (Central Processing Unit) or a RAM (Random Access Memory) by DSP (Digital Signal Processing). Alternatively, on the contrary, it is also possible to delay by setting the output timing of the signal voltage held in the sample hold circuit appropriately by a latch or the like, and to perform offset removal by analog processing. In addition, the details shown in the embodiment, such as the switching frequency of the switch and the number of IF amplifiers, can be changed as appropriate without departing from the spirit of the invention.

DESCRIPTION OF SYMBOLS 1 Radio time signal 10 Radio wave reception process part 11 Oscillation circuit 12 Timing circuit 13 CPU
14 Display unit 22 Antenna 23 RF amplifier 24 Local oscillator 25 Mixer 26 BPF
28 Detector 29 Comparator 41 Switch 42 Subtractor 43 LPF
44 DAC
45 Shift register 46 ADC
47 node 101 intermediate frequency amplifier 102 offset removing circuit 112 phase delay circuit A1, A2, A3 IF amplifier

Claims (7)

In the radio wave receiver that demodulates the received signal,
Comprising a plurality of signal amplifying means arranged in series;
At least one of the stages of the plurality of signal amplification means is
A delay signal generating means for generating a delayed signal obtained by delaying a received input signal by a predetermined phase; a signal combining means for outputting a difference between the delayed signal and the input signal;
A radio wave receiving apparatus comprising: The delayed signal generating means includes
The radio wave receiver according to claim 1, further comprising a data holding unit that outputs the input signal after holding the input signal for a predetermined time. The radio wave receiver according to claim 2, wherein the input signal is discretely input to the delay signal generation unit and the signal synthesis unit at a frequency equal to or higher than the frequency of the input signal. The delayed signal generating means includes
Analog-to-digital conversion means for digitally converting the analog voltage data of the input signal at a predetermined sampling frequency;
Digital-analog conversion means for converting a digital signal into analog voltage data,
The data holding means is
The radio wave receiving apparatus according to any one of claims 1 to 3, wherein the digital-converted input signal is held for a predetermined time and then output to the digital-analog converting means. The radio wave receiving apparatus according to any one of claims 1 to 4, further comprising a bandpass filter that receives an output signal of the signal synthesizing unit and selectively outputs a signal having the same frequency as the input signal. . Frequency conversion means for converting the received signal into a signal of a predetermined intermediate frequency;
The radio wave receiving device according to any one of claims 1 to 5, wherein the input signal is the converted intermediate frequency signal. The radio wave receiving apparatus according to any one of claims 1 to 6,
A radio timepiece that receives standard radio waves from the radio wave receiver.

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