JP2011193027A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve light shielding of a floating diffusion portion of a MOS-type solid-state imaging apparatus. <P>SOLUTION: The solid-state imaging apparatus includes a plurality of pixels. Each pixel includes: a photodiode 1 which generates an electric charge in accordance with the quantity of incident light; the floating diffusion portion 3 which temporarily holds the electric charge; a gate electrode 304 which controls transfer of the electric charge between the photodiode and floating diffusion portion; and readout circuits 5 to 8 which read the electric charge temporarily held in a semiconductor region, to the outside. The imaging apparatus also includes light shielding members 427a and 427b arranged to cover a side wall of the gate electrode on the side of a photoelectric conversion portion. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more specifically to a MOS solid-state imaging device.

  In recent years, the demand for solid-state imaging devices has been rapidly increasing as imaging devices for image input, mainly digital still cameras and video cameras.

  As these solid-state imaging devices, CCD and MOS type sensors are widely used. Since the former has higher sensitivity and lower noise than the latter, it is popular as a high-quality imaging device. However, on the other hand, the power consumption is high, the driving voltage is high, and the manufacturing cost cannot be increased by a general-purpose semiconductor manufacturing process. Furthermore, there is a problem that it is difficult to integrate peripheral circuits such as a drive circuit. On the other hand, the MOS type sensor has a feature that it can cover the above weak points.

  A CMOS solid-state image pickup device has been put to practical use as a representative of MOS type solid-state image pickup devices. A circuit diagram of one pixel of the CMOS solid-state imaging device is shown in FIG. 11, a plan layout diagram is shown in FIG. 12, and a sectional structure is shown in FIG.

  In FIG. 11, 1 is a photodiode (PD), 2 is a transfer MOS transistor for transferring the charge of the photodiode, 3 is a floating diffusion (FD) section for temporarily storing the transferred charge, and 4 is an FD section 3. And a reset MOS transistor for resetting PD1, 5 is a selection MOS transistor for selecting any one row in the pixel array of the solid-state imaging device, and 6 is a source follower by converting the charge accumulated in FD3 into a voltage. A source follower MOS transistor to be amplified by the type amplifier, 7 is a readout line that is shared by one column and reads out a pixel voltage signal, and 8 is a constant current source for making the readout line 7 a constant current.

  Next, the operation of the CMOS solid-state imaging device shown in FIG. 11 will be briefly described. Incident light is converted into charges by the PD 1, and the converted charges are transferred to the FD unit 3 by the transfer MOS transistor 2 and stored. Since the FD unit 3 and the PD 1 are previously reset to a constant potential by turning on the reset MOS transistor 4 and the transfer MOS transistor 2, the potential of the FD unit 3 changes according to the charge generated by the incident light. The potential of the FD unit 3 is amplified by the source follower MOS transistor 6 and output to the read line 7. The pixel is selected by turning on the selection MOS transistor 5. In an output circuit (not shown), the difference between the reset potential of the FD unit 3 and the potential after storing the optical signal is calculated to detect the optical signal.

  FIG. 12 is a diagram showing an example of the layout of the pixel circuit shown in FIG. Reference numeral 10 denotes an active region in which the PD 1 is formed, and 11 denotes an active region in which the selection MOS transistor 5 and the source follower MOS transistor 6 are formed. Reference numeral 20 denotes a region of the transfer MOS transistor 2, 21 denotes a region surrounded by a broken line indicating the gate line of the transfer MOS transistor 2, and 30 denotes a portion of the FD portion 3 formed by a semiconductor PN junction. . Reference numeral 31 denotes a contact for extracting an electrode from the diffusion region 30 of the FD portion 3, and 32 denotes a metal electrode for extracting the FD portion 3. Reference numeral 34 denotes polysilicon which becomes an electrode of the FD portion 3 and also becomes a gate electrode of the amplification MOS transistor 6, and 33 is a contact for connecting the metal electrode 32 to the polysilicon electrode 34.

  Reference numeral 40 denotes a region of the reset MOS transistor 4 and reference numeral 41 denotes a contact for connection to a reset power source. Reference numeral 50 denotes a gate region of the selection MOS transistor 5, 51 denotes a contact for connection to the VDD power source, and 60 denotes a region of the source follower MOS transistor 6, and the polysilicon electrode 34 electrically connected to the FD portion 3. Is used as a gate electrode. Reference numeral 70 denotes a signal output line including a first layer wiring, which is formed of a metal electrode. Reference numeral 71 denotes a contact connecting the signal output line 70 and the source electrode of the region 60 of the source follower MOS transistor 6.

  FIG. 13 shows a cross-sectional view of CC ′ in the layout shown in FIG. Reference numeral 301 denotes an n-type silicon substrate, 302a denotes a P-type well, 302b denotes a P-type buried layer, 303a denotes a gate oxide film of the transfer MOS transistor 2, and 303b denotes a thin oxide film on the light receiving portion. Reference numeral 304 denotes a gate electrode of the transfer MOS transistor 2, reference numeral 305 denotes an N-type cathode of PD1, and reference numeral 306 denotes a surface P-type region for embedding PD1. Reference numeral 307a denotes a LOCOS oxide film for element isolation, 307b denotes a P-type channel stop layer, and 308 denotes an N-type high concentration region that forms the FD portion 3 and also serves as the drain region of the transfer MOS transistor 2. Reference numeral 309 denotes an interlayer insulating film that insulates the gate electrode 304 and the metal first layer 321; 320, a contact plug; and 321, a metal first layer that serves as an extraction electrode of the FD portion 3. 322 is an interlayer insulation film that insulates the metal first layer 321 and the metal second layer 323, 323 is a metal second layer, 324 is an interlayer insulation film that insulates the metal second layer 323 and the metal third layer 325, and 325 is a metal The third layer 326 is a passivation film. In the color photoelectric conversion device, a color filter layer (not shown) is further formed on the passivation film 326 and a microlens for improving sensitivity is formed.

  Light incident from the surface enters the PD 1 through an opening without the metal third layer 325. The light is absorbed in the N-type cathode 305 or the P-type well 302a of PD1, and an electron / hole pair is generated. Among these, electrons are accumulated in the N-type cathode region.

  However, the conventional CMOS solid-state imaging device has a problem in that signal electrons generated by incident light are mixed into the FD unit 3 to change the output voltage. As shown in FIG. 13, among the electron-hole pairs 330b generated under the gate electrode 304 of the transfer MOS transistor 2 by the obliquely incident light beam 330a, electrons are transferred from the N-type cathode 305 of the PD1 to the FD section 3. Is attracted to the N-type high concentration layer 308 constituting.

  Further, the light 331a incident on the gate electrode 304 of the transfer MOS transistor 2 is repeatedly reflected as shown in FIG. 13, and electron / hole pairs 331b are generated immediately below the N-type high concentration layer 308. Among these, electrons are attracted to the N-type high concentration layer 308. In order to prevent this, if the metal first layer 321 is extended to the opening side to improve the light shielding property, the capacitance of the FD portion 3 increases and the charge conversion coefficient decreases, thereby deteriorating the S / N. Was produced.

  As described above, electrons directly captured by the FD unit 3 without passing through the PD 1 become pseudo signals, which increase the noise of the solid-state imaging device, reduce the dynamic range, increase the dark output, and shading in the dark. Cause problems such as an increase in In particular, when a so-called electronic shutter operation is performed in which charges are transferred simultaneously from the PD 1 to all the FD units 3 and the charges are sequentially read out to the signal lines, the longer the time that the charges are held in the FD unit 3, the more suspicious signals are generated. Superimposed. Therefore, the phenomenon of shading and in-plane distribution of S / N is caused. For this reason, improving the light shielding property of the FD unit 3 has been a problem of the conventional CMOS type solid-state imaging device.

  Even in a CCD solid-state imaging device, a source follower type amplifier circuit using a floating diffusion at the final stage of a readout circuit is generally used. Patent Document 1 shows an example in which polysilicon is used to lead an electrode to a source follower amplifier. However, the invention of Patent Document 1 does not mention improvement of the light shielding property, and does not consider the fact that electrons generated inside silicon flow into the floating diffusion as shown in the prior art. Furthermore, in the CCD type solid-state imaging device, since there is only one floating diffusion amplifier circuit in the subsequent stage of the horizontal CCD, it is possible to lay out far from the pixel portion without being restricted by the pixel area, so that little ingenuity is required. .

  On the other hand, in the MOS type solid-state imaging device, since the floating diffusion portion exists for each pixel, the photodiode and the floating diffusion portion are close to each other. In addition, since the metal electrode that plays the role of shading is also used as the circuit wiring, it is necessary to create a gap. there were.

  Patent Document 2 discloses a measure for enhancing the light shielding of the floating diffusion portion in the MOS type solid-state imaging device. FIG. 14 shows a cross-sectional structure according to the present invention. As shown in FIG. 14, the light shielding member 1009 is arranged on the photodiode so as to cover the opening in a cylindrical shape.

Japanese Patent Laid-Open No. 03-116840 JP 2000-124438 A

  In the configuration of Patent Document 2, light shielding properties can be expected, but the process of leaving only the side surface of the light shielding member in a fine pixel is extremely difficult, and the light shielding member is insulated from the first layer wiring 1006 and the second layer wiring 1007. In order to achieve this, a margin in the horizontal direction is also required, the actual opening becomes extremely narrow, and the sensitivity is lowered, which is not a practical measure.

  The present invention has been made in view of the above problems, and an object thereof is to improve the light shielding property of the floating diffusion portion of the MOS type solid-state imaging device.

In order to achieve the above object, a solid-state imaging device of the present invention includes a photoelectric conversion unit that generates a charge according to the amount of incident light, a semiconductor region that temporarily stores charge, the photoelectric conversion unit, and the semiconductor region. A solid-state imaging device having a plurality of pixels each including a gate electrode that controls transfer of electric charge between the gate electrode and a readout circuit that reads out the electric charge temporarily stored in the semiconductor region. And a light shielding member disposed so as to cover the side wall on the photoelectric conversion portion side.

  According to the present invention, the light shielding property of the floating diffusion portion of the MOS type solid-state imaging device can be improved.

It is a block diagram which shows the structure of the camera system using the MOS type solid-state imaging device in embodiment of this invention. It is an example of the partial circuit diagram of the MOS type solid-state imaging device in the embodiment of the present invention. FIG. 5 is a timing chart of the all-pixel simultaneous accumulation operation control in the MOS type solid-state imaging device according to the embodiment of the present invention. It is a figure which shows the pixel layout of the MOS type solid-state imaging device in the 1st Embodiment of this invention. It is a figure which shows an example of the pixel cross section of the MOS type solid-state imaging device in the 1st Embodiment of this invention. It is a figure which shows an example of the pixel cross section of the MOS type solid-state imaging device in the 2nd Embodiment of this invention. It is a figure which shows an example of the pixel cross section of the MOS type solid-state imaging device in the 3rd Embodiment of this invention. It is a figure which shows an example of the pixel cross section of the MOS type solid-state imaging device in the 4th Embodiment of this invention. It is a figure which shows an example of the pixel layout of the MOS type solid-state imaging device in the 4th Embodiment of this invention. It is a figure which shows an example of the pixel cross section of the MOS type solid-state imaging device in the 5th Embodiment of this invention. It is a figure which shows the pixel circuit of the conventional MOS type solid-state imaging device. It is a figure which shows an example of the pixel layout of the conventional MOS type solid-state imaging device. It is a figure which shows an example of the pixel cross section of the conventional MOS type solid-state imaging device. It is a figure which shows another example of the pixel cross section of the conventional MOS type solid-state imaging device.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components exemplified in this embodiment should be changed as appropriate according to the configuration of the apparatus to which the present invention is applied and various conditions. However, the present invention is not limited to these examples.

  FIG. 1 is a block diagram illustrating a configuration of a digital camera using a solid-state imaging device in the present embodiment. In FIG. 1, 101 is a shutter and 102 is a photographing lens. The shutter 101 is disposed in front of the photographing lens 102 to control exposure. The light that has passed through the shutter 101 and the photographing lens 102 is imaged on the solid-state imaging device 104 while the amount of light is controlled by the diaphragm 103 as necessary. The electrical signal output according to the amount of light incident from the solid-state imaging device 104 is processed by the analog signal processing circuit 105 and then converted from an analog signal to a digital signal by the A / D converter 106. The converted digital signal is further processed by the digital signal processing unit 107 and stored in the memory 110 or sent to an external device through the external I / F 113.

  The processing timing of the solid-state imaging device 104, the analog signal processing circuit 105, the A / D converter 106, and the digital signal processing unit 107 is controlled by the timing generation unit 108, and the entire system is controlled by the overall control / calculation unit 109. . When the digital signal output from the A / D converter 106 is recorded on the recording medium 112, the digital signal is recorded through the recording medium control I / F unit 111 controlled by the overall control / calculation unit 109.

  Next, a schematic configuration of the solid-state imaging device 104 of FIG. 1 will be described with reference to FIG. FIG. 2 is a diagram showing a part of an imaging device in which an NMOS transistor is used as a transistor constituting a pixel as the solid-state imaging device 104. As shown in FIG. 2, pixels having the same configuration as that described with reference to FIG. 11 in the conventional example are two-dimensionally arranged. In FIG. 2, only 2 × 2 pixels are shown for easy understanding of the configuration, but in reality hundreds of thousands to millions of pixels are two-dimensionally arranged. It is also possible to use a PMOS transistor.

  Each pixel 100 includes a PD 1, a transfer MOS transistor 2, an FD unit 3, a reset MOS transistor 4, a selection MOS transistor 5, and a source follower MOS transistor 6. The gate of the selection MOS transistor 5 in the same row is on the selection line SEL (i), the gate of the reset MOS transistor 4 is on the reset line RES (i), and the gate of the transfer MOS transistor 5 is on the transfer line TX (i). It is connected. Then, scanning / selection is performed by the vertical scanning circuit 120. A current source 8 is connected to the output line 7 in the same column, and the potential of the output line 7 can be read out by a source follower operation.

  123 is an optical signal transfer MOS transistor. The gate is connected to the optical signal readout line TS. When an optical signal appears on the output line 7, the gate is turned on via the optical signal readout line TS. Is transferred to the charge storage unit 128. Reference numeral 124 denotes a noise signal transfer MOS transistor, the gate of which is connected to the noise signal readout line TN. After the pixel 100 is reset, the signal (noise) on the output line 7 is charged before an optical signal appears on the output line 121. Transfer to the storage unit 128. The optical signal and the noise signal stored in the charge storage unit 128 are sequentially scanned and read out by the horizontal scanning circuit 127, and output by taking the difference between the optical signal and the noise signal by a differential amplifier circuit (not shown). .

  In the circuit shown in FIG. 2, in addition to PD1, transfer MOS transistor 2, and source follower MOS transistor 6, select MOS transistor 5, reset MOS transistor 4 and the like are described. Among these, the reset MOS transistor 4 and the selection MOS transistor 5 may be configured by one transistor. Alternatively, at least one of the source follower MOS transistor 6, the selection MOS transistor 5, and the reset MOS transistor 4 may be shared by a plurality of pixels.

  Next, the all-pixel simultaneous accumulation operation control in the solid-state imaging device 104 having the configuration shown in FIG. 2 will be described with reference to the timing chart of FIG. In FIG. 3, a signal given to the signal line shown in FIG. 2 is shown using “Φ”. First, in order to reset PD1 of all pixels, the reset pulse ΦRES of all rows and the transfer pulse ΦTX of all rows are simultaneously turned ON. From the moment when these two pulses are turned off, photoelectric conversion by PD1 is simultaneously performed on the entire screen, and the accumulation operation starts. After accumulation for a desired time, the transfer pulse ΦTX of all rows is turned on and then turned off again, so that the signal charges of each pixel are transferred to the FD section 3 of each pixel all at once. Next, by turning ON / OFF the selection pulse for each row, the charges transferred to the FD unit 3 are sequentially read for each row. The signal read here is an “S + N” signal composed of an optical signal and a noise signal, stored in the charge storage unit 128 of FIG. 2, and sequentially read in accordance with an operation by the horizontal scanning circuit 127. When the charges stored in the pixels in all rows are read, the signal accumulation / readout period ends.

  Next, the FD sections 3 of all the pixels are simultaneously reset by turning ON the reset pulse for all the rows. After the reset pulse is turned OFF, the potentials of the FD units 3 in each row are sequentially read out. The read signal is a noise signal, and is stored as a “N” signal in a capacitor unit that is provided in the charge storage unit 128 along with a capacitor unit for “S + N” signal. The stored “S + N” signal and “N” signal are input to a differential amplifier (not shown) to extract the “S” signal.

  In this operation, the time for which charges are held in the FD section 3 differs for each row. Therefore, in the conventional structure, a row having a long holding time (this row is compared to a row having a short holding time (in this case, the first row)) In the case of the last line), the output potential is shaded by a false signal entering the FD section 3. In the present invention, since it flows into the FD section 3 is suppressed, such shading does not occur or does not cause a problem.

<First Embodiment>
Next, a detailed configuration of each pixel of the solid-state imaging device according to the first embodiment used in the imaging device having the above-described configuration will be described.

  FIG. 4 shows a layout of the pixel circuit in the first embodiment. In addition, the same reference number is attached | subjected to the structure similar to FIG. 12 mentioned above, and description is abbreviate | omitted.

  In FIG. 4, reference numeral 73 denotes a light shielding member for the gate electrode of the transfer MOS transistor 2. The light shielding member 73 lays out the polysilicon of the gate electrode of the transfer MOS transistor 2 so as to cover the polysilicon 21 in the channel length direction, and prevents incident light from entering directly under the FD portion 3 in the channel width direction. The layout is slightly larger than the channel width. Here, the length of the light shielding film extending from the gate electrode in the channel length direction and the length extending in the channel width direction will be described.

In the channel length direction, the PD part and the FD part are arranged, and when the amount of the light shielding film extending to the PD part side is large, the aperture ratio of the PD is lowered. It becomes difficult to form a contact. In contrast, the channel width direction is more flexible than the channel length direction. Therefore, the extending length is preferably larger in the channel width direction than in the channel length direction.
FIG. 5 is a view showing an AA ′ cross section of FIG. 4. In addition, the same reference number is attached | subjected to the structure similar to FIG. 13 mentioned above, and description is abbreviate | omitted here.

  The present embodiment is characterized in that light shielding members 327a and 327b are arranged through a thin silicon oxide film 328a and a silicon oxide film side wall 328b so as to cover the gate electrode 304. The light shielding members 327a and 327b are desirably thinner than the polysilicon constituting the gate electrode 304, and need to be able to sufficiently shield light even with a thin film thickness. Furthermore, it is preferable that the material does not reflect light. Suitable materials include tungsten, tungsten alloy, titanium, titanium alloy, tantalum, tantalum alloy, molybdenum, molybdenum alloy, and the like. Among them, tungsten is excellent in light shielding properties, material stability, and workability. Silicides between these materials and polysilicon forming a gate electrode can also be used as a light shielding material.

  Of the light incident from the surface, the light incident near the gate electrode 304 of the transfer MOS transistor 2 is blocked by the light shielding members 327a and 327b, so that no charge is generated near the FD portion 3 (N-type high concentration region 308). .

  As described above, according to the present embodiment, by providing the light shielding members 327a and 327b on the gate electrode 304 of the transfer MOS transistor 2, the light shielding property of the FD unit 3 can be improved, and the influence of the false signal is eliminated. be able to. In addition, since there is no shading in the dark and the dynamic range and S / N can be increased, a high-quality image can be obtained even when image reading is performed by electronic shutter control of all-pixel simultaneous storage type. .

  Next, a manufacturing method from the formation of the gate electrode 304 to the formation of the silicon oxide film 309 will be described.

  After the gate electrode 304 is formed, the gate electrode 304 is oxidized in an oxidizing gas atmosphere and the surface is covered with a thin insulating film. Thereafter, a light shielding member is deposited on the entire surface by a CVD method or a sputtering method, and then the light shielding member is left only at a desired portion by patterning. In the case of tungsten, the film thickness is preferably 50 nm to 250 nm. If it is too thin, the light shielding property is impaired, and if it is too thick, the amount of light incident on the photodiode is reduced, and the sensitivity is lowered. Further, as shown in FIG. 5, the CVD method is more preferable than the sputtering method in order to improve the coverage of the side wall portion. Thereafter, a silicon oxide film 309 is deposited by a CVD method. After depositing a sufficient film thickness, the surface is planarized by CMP (Chemical Mechanical Polishing). For the silicon oxide film 309, BPSG (Boron-Phosphorus-Silicate-Glass) having thermal reflow property may be used. In this case, after CVD, heat of 850 ° C. or higher is applied to reflow the BPSG film, and then the surface is polished by CMP. When the reflow is performed, it is easier to planarize the surface of the silicon insulating film by CMP.

  Needless to say, the present invention can also be applied to a case where a hole accumulation type pixel is configured by inverting all the conductivity types of each configuration.

<Second Embodiment>
FIG. 6 is a diagram showing an example of a pixel cross section of a MOS type solid-state imaging device according to the second embodiment of the present invention. In FIG. 6, the same components as those in FIG. 5 described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 6, the shape of the light shielding members 427a and 427b in the present embodiment is different from the shape of the light shielding members 327a and 327b shown in FIG. 5 in the first embodiment. Also in this embodiment, the light shielding members 427a and 427b are disposed through the thin silicon oxide films 328a and 328b so as to cover the gate electrode 304. However, of the gate electrode 304, the side facing the PD1 and the top surface are covered with the light shielding members 427a and 427b, and the side surface and top surface facing the FD portion 3 are not covered with the light shielding member. This is because the light shielding member is required on the PD1 side where the light is incident, and the FD portion 3 is conveniently not covered by the light shielding member in order to draw out the electrode.

  Thus, by providing the light shielding member asymmetrically with respect to the channel length direction of the transfer MOS transistor 2, a light shielding structure suitable for a smaller pixel can be provided.

  In the present embodiment, among the gate electrode 304, the side surface and the upper surface facing the PD1 are covered with a light shielding member. However, even when only the side surface facing the PD1 is covered, a considerable amount of light shielding is achieved. An effect can be obtained.

<Third Embodiment>
FIG. 7 is a diagram illustrating an example of a pixel cross section of a MOS type solid-state imaging device according to the third embodiment of the present invention. In FIG. 7, the same components as those in FIG. 5 described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the present embodiment, the shape of the asymmetric light shielding members 427a and 427b shown in the second embodiment does not include the thin silicon oxide film 328a covering the gate electrode 304 as shown in FIG. In the example, the light shielding members 527a and 527b are in direct contact with the side surfaces and the upper surface.

  In this embodiment, as shown in FIG. 7, the light shielding members 527 a and 527 b are made of two layers of metal, and the metal atoms of the other layer 527 a diffuse into the polysilicon of the gate electrode 304 in the layer 527 b in direct contact with the gate electrode 304. Barrier metal that can be prevented is used. When tungsten is used as an example of the light shielding member 527a, titanium silicide or a laminate of titanium silicide and titanium is suitable as the barrier metal 527b.

  In addition, the resistance of the polysilicon can be significantly reduced by “lining” the polysilicon with metal in this way. As the number of pixels per row increases or the gate line width decreases as the pixel size decreases, the gate delay of the transfer MOS transistor 2 becomes a factor that increases the signal readout time from each pixel. Due to the resistance, it is possible to provide a solid-state imaging device that operates at a high speed even on finer pixels.

  Further, the barrier metal can prevent the heavy metal used as the light shielding member 527a from diffusing into the polysilicon gate electrode 304 by heat treatment. Therefore, even if the resistance is lowered, it is possible to prevent an increase in point defects due to the influence of the work function of the transfer transistor and the diffusion of heavy metal through the gate insulating film into the silicon.

<Fourth Embodiment>
FIG. 8 is a diagram showing an example of a pixel cross section of a MOS type solid-state imaging device according to the fourth embodiment of the present invention. In FIG. 8, the same components as those in FIG. 5 described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In this embodiment, a silicon oxide film 328 is provided between the light shielding members 627 a and 627 b made of two layers of metal and the gate electrode 304, and a contact hole 629 is formed in the silicon oxide film 328, and the contact hole 629 is interposed therebetween. Thus, the configuration in which the light shielding members 627a and 627b are connected to the gate electrode 304 is different from the above-described third embodiment.

  A planar layout at this time is shown in FIG. 9, the same reference numerals are assigned to the same components as those in FIG. In FIG. 9, contact hole 774 is opened on the field oxide film.

  By not connecting the gate electrode 304 made of polysilicon and the light shielding member 627a on the active region as in this embodiment, the threshold value change of the transfer MOS transistor 2 due to diffusion of heavy metal can be achieved even when there is no barrier metal. It can be minimized. However, because of the fine pixels, when the distance between the contact hole 774 and the active region cannot be taken, it is desirable to lay a barrier metal under the light shielding member 627a as in this embodiment.

  Thus, according to the present embodiment, in addition to the same effects as those of the third embodiment, the diffusion of the heavy metal of the light shielding member into the semiconductor substrate can be minimized.

<Fifth Embodiment>
FIG. 10 is a diagram illustrating an example of a pixel cross section of a MOS type solid-state imaging device according to the fifth embodiment of the present invention. In FIG. 10, the same components as those in FIG. 5 described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In this embodiment, the gate electrode of the transfer MOS transistor 2 is shielded by the light shielding member 827, and a potential barrier is provided in the silicon to prevent the charge generated near the transfer MOS transistor 2 from diffusing into the FD portion 3. . At the same time, since the electrode lead-out from the FD part 3 is a direct lead-out from the polysilicon, the light directly above the FD part 3 is shielded by the metal first layer, so that the light shielding property of the FD part 3 is improved overall. It is possible to provide a new structure.

  In FIG. 10, 802 is a buried P-type high concentration layer, 803a is an N-type epitaxial layer, 804a, 804b and 804c are P-type isolation layers, and 805a, 805b and 805c are P-type well layers. Reference numerals 806a and 806b denote channel stop P-type layers below the field oxide film. A field transfer layer 814 defines a charge transfer path from the PD 1 to the FD section 3 and forms a potential barrier immediately below the transfer MOS transistor 2. A polysilicon lead 812 is in direct contact with the N-type high concentration region. An electrode 827 is a light shielding member.

  In the present embodiment, among the gate electrode 304 of the transfer MOS transistor 2, the PD1 side wall and a part of the surface of PD1 are shielded, and at the same time, a P-type isolation layer 804b, a P-type well layer 805b, and a field stop layer 814 are provided. ing. As a result, of the electron / hole pairs 831b generated at the PD1 end by the oblique incident light 831a, the electrons are not diffused to the FD section 3 side but are collected at the N-type cathode 305 of the PD1.

  Thus, in the present embodiment, diffusion from the silicon inside to the FD portion 3 can be suppressed. Thus, in this embodiment, a false signal can be more effectively eliminated by a combination of a light shielding member and a potential barrier.

1: Photodiode, 2: Transfer MOS transistor, 3: Floating diffusion part, 4: Reset MOS transistor, 5: Select MOS transistor, 6: Source follower MOS transistor, 7: Read line, 8: Constant current source, 100: Pixel , 101: shutter, 102: photographic lens, 103: aperture, 104: solid-state imaging device, 105: analog signal processing circuit, 106: A / D converter, 107: digital signal processing unit, 108: timing generation unit, 109: Overall control / arithmetic unit, 110: memory, 111: recording medium control I / F unit, 112: recording medium, 113: external I / F unit, 120: vertical scanning circuit, 123: optical signal transfer MOS transistor, 124: noise Signal transfer MOS transistor, 127: horizontal scanning circuit, 128: charge storage , 301: n-type silicon substrate, 302a: P-type well, 302b: P-type buried layer, 303a: gate oxide film of MOS transistor, 303b: thin oxide film on the light receiving portion, 304: gate electrode of transfer MOS transistor, 305 : N-type cathode of photodiode, 306: Surface P-type region, 307a: LOCOS oxide film for element isolation, 307b: P-type channel stop layer, 308: N-type high concentration region, 309: Silicon oxide film, 320: Contact plug, 321: Metal first layer, 322: Interlayer insulating film, 323: Metal second layer, 324: Interlayer insulating film, 325: Metal third layer, 326: Passivation film, 327a, 427a: Light shielding member, 327b, 427b: light shielding member, 328a: insulating film, 328b: gate electrode side wall oxide film, 330a, 31a: oblique incident light, 330b, 331b: electron-hole pair, 527a, 627a: barrier metal, 527b, 627b: light shielding member, 628a: insulating film, 628b: sidewall oxide film, 629: contact hole, 774: gate electrode Contact hole for connecting the light shielding member, 803: N-type epitaxial layer, 804a, 804b, 804c: P-type isolation layer, 805a, 805b, 805c: P-type well layer, 806a, 806b: Channel stop P-type layer, 812: Poly Silicon lead electrode, 814: field stop layer, 827: light shielding member, 828: insulating film covering gate electrode, 831a: oblique incident light, 831b: electron / hole pair

Claims (15)

  A photoelectric conversion unit that generates electric charge according to the amount of incident light;
  A semiconductor region for temporarily holding charge; and
  A gate electrode for controlling transfer of electric charge between the photoelectric conversion portion and the semiconductor region;
  A readout circuit for reading out the electric charge temporarily held in the semiconductor region;
  A solid-state imaging device having a plurality of pixels,
  A light shielding member disposed to cover a side wall of the gate electrode on the photoelectric conversion unit side;
  A solid-state imaging device.   A photoelectric conversion unit that generates electric charge according to the amount of incident light;
  A semiconductor region to which the charge is transferred;
  A gate electrode for controlling transfer of electric charge between the photoelectric conversion portion and the semiconductor region;
  An electrode connected to the semiconductor region;
  A readout circuit for reading out the charge of the semiconductor region to the outside;
  A solid-state imaging device having a plurality of pixels,
  A light shielding member disposed to cover a side wall of the gate electrode on the photoelectric conversion unit side;
  A solid-state imaging device.   3. The solid-state imaging device according to claim 1, wherein the light shielding member extends from a side wall of the gate electrode onto the photoelectric conversion unit.   The solid-state imaging device according to claim 1, wherein the light shielding member includes a plurality of metal layers.   5. The solid-state imaging device according to claim 4, wherein a metal layer disposed on the gate electrode side among the plurality of metal layers is formed of a barrier metal.   The solid-state imaging device according to claim 1, wherein the light shielding member and the gate electrode are electrically connected.   The solid-state imaging device according to claim 3, further comprising an insulating film between the light shielding member and the gate electrode.   The solid-state imaging device according to claim 7, wherein a contact hole that electrically connects the light shielding member and the gate electrode is provided in the insulating film.   The solid-state imaging device according to claim 8, wherein the contact hole is opened above the active region of the gate electrode.   The solid-state imaging device according to claim 1, further comprising a polysilicon electrode that is in direct contact with the semiconductor region.   A plurality of wiring layers each including a wiring are provided above the polysilicon electrode, and the wiring of the wiring layer closest to the photoelectric conversion unit among the plurality of wiring layers is disposed above the semiconductor region. The solid-state imaging device according to claim 10.   The region under the gate electrode, which is a potential barrier against the charge, is disposed between the photoelectric conversion portion and the semiconductor region. The solid-state imaging device according to item 1.   The solid-state imaging device according to claim 1, wherein a region serving as a potential barrier with respect to the electric charge is disposed below the semiconductor region.   An insulating film covering the photoelectric conversion unit;
  The solid-state imaging device according to claim 1, wherein the light shielding member extends so as to be in contact with an insulating film covering the photoelectric conversion unit.   The plurality of pixels are arranged to form a plurality of rows,
  The solid-state imaging device according to claim 1, wherein transfer pulses are simultaneously turned on in all of the plurality of rows.

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