JP2007157912A - Solid imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid imaging apparatus in which each pixel has a charge storage unit to enable simultaneous electronic shutter operation at all pixels, and which reduces light incident on the charge storage unit to suppress the generation of a false signal due to the light incidence. <P>SOLUTION: The pixel on a board 21 includes the charge storage unit 3 which accumulates charges transferred from a photodiode 1, an amplifying transistor which puts out a signal corresponding to the charge volume of a floating diffusion 4, a first transfer gate 11 which transfers a charge from the photodiode 1 to the charge storage unit 3, and a second transfer unit 5 which transfers a charge from the charge storage unit 3 to the floating diffusion 4. A gap 40 is formed across inter-layer films 32 and 33 formed on the board 21, in such a way that the gap 40 virtually encircles the charge storage unit 3 in a plan view in a direction almost normal to the board 21. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device that captures a subject image.

  In recent years, video cameras, electronic still cameras, and the like have been widely used. For these cameras, CCD type or amplification type solid-state imaging devices are used. In an amplification type solid-state imaging device, signal charges generated and accumulated in a photoelectric conversion unit of a light receiving pixel are guided to an amplification unit provided in the pixel, and a signal amplified by the amplification unit is output from the pixel. In an amplification type solid-state imaging device, a plurality of such pixels are arranged in a matrix. As the amplification type solid-state imaging device, for example, a solid-state imaging device using a junction field effect transistor (JFET) in the amplification unit (Patent Documents 1 and 2 below), or a CMOS type solid-state imaging using a CMOS transistor in the amplification unit. There is a device (the following Patent Document 3).

  Conventionally, in an amplification type solid-state imaging device, in order to prevent image distortion caused by the exposure accumulation time of each pixel being shifted for each row when performing an electronic shutter operation (so-called rolling shutter), There has been proposed a configuration that realizes an electronic shutter operation simultaneously for all pixels in which the exposure time of pixels is constant (Patent Documents 1 to 3 below).

In the conventional solid-state imaging device disclosed in Patent Documents 1 to 3, each pixel has a photoelectric conversion unit and an amplification unit, and a charge storage unit (storage unit) that temporarily stores charges between them. is doing. In such a conventional solid-state imaging device, after all the pixels are exposed simultaneously, the signal charges generated in each photoelectric conversion unit are transferred to each charge storage unit at the same time, and accumulated once. The signal charges are sequentially converted into pixel signals at a predetermined readout timing.
JP-A-11-177076 JP 2004-335882 A JP 2004-111590 A

  However, as a result of the inventor's research, in the conventional solid-state imaging device, light that has not been assumed in the past is incident on the charge storage unit that temporarily accumulates signal charges, which is false. It has been found that the image quality is degraded due to the generation of the signal.

  An example of the state of light incidence on such a charge storage portion is shown in FIG. FIG. 14 is a diagram illustrating a state of light incidence of the solid-state imaging device disclosed in Patent Document 1, and a part of light rays 301 to 305 of incident light are entered in the pixel cross-sectional view of FIG. It is a thing.

In FIG. 14, reference numeral 101 denotes a buried photodiode (BPD) as a photoelectric conversion unit that generates and accumulates charges according to incident light, and 102 denotes a junction-type field effect that outputs a signal according to the received charge to the control region. Transistor (JFET) 103 is a charge storage unit that temporarily stores the charge generated and stored by the BPD 101 before it is transferred to the JFET, 104 is polysilicon that controls the transfer of the charge from the BPD 101 to the charge storage unit 103, etc. A first transfer gate electrode 105, 105 a second transfer gate electrode made of polysilicon or the like for controlling the transfer of charge from the charge storage unit 103 to the JFET 102, 107 discharges the charge transferred to the control region of the JFET 102 Reset gate made of polysilicon or the like for controlling a reset drain (not shown) It is the RG). 201 is a P-type silicon substrate, 202 is an N-type well, 205 is a surface N-type layer of the BPD 101, and 206 is a P-type charge storage layer of the BPD 101. Reference numeral 204 denotes a P-type gate region (P gate), 207 denotes an N ⁺ type source region, 208 denotes an N ⁺ type drain region, and 209 denotes an N type channel region (N channel). . Further, reference numeral 210 denotes a first amylium layer as a wiring, and 211 denotes a light shielding film made of a second aluminum layer also serving as a wiring.

  As shown in FIG. 14, for example, a part of the light beam 301 passes through the transfer gate electrode 104 and enters the charge storage unit 103, and the other part of the light beam 301 enters the transfer gate electrode 104, the light shielding film 211, and one layer. The light is sequentially reflected from the side of the eye amylnium layer 210 and then passes through the transfer gate electrode 105 toward the charge storage portion 103. The light beam 302 is sequentially reflected by the transfer gate electrode 107, the light shielding film 211, the first amylnium layer 210, and the light shielding film 211, and then passes through the transfer gate electrode 105 and enters the charge storage unit 103. The light ray 303 is reflected by the N-type well 202 in the vicinity of the end of the transfer gate electrode 104, and further reflected between the lower surface of the transfer gate electrode 104 and the N-type well 202, and then enters the charge storage portion 103. To do.

  The present invention has been made in view of the above-described circumstances, and in a solid-state imaging device capable of performing an electronic shutter operation simultaneously for all pixels by having a charge storage unit, the light to the charge storage unit is provided. An object of the present invention is to provide a solid-state imaging device capable of reducing incidence and suppressing generation of a false signal due to light incidence.

  In order to solve the above problems, the solid-state imaging device according to the first aspect of the present invention includes a photoelectric conversion unit that generates and accumulates charges according to incident light, and a charge storage that accumulates charges transferred from the photoelectric conversion unit. An amplifier that outputs a signal corresponding to the amount of charge at a predetermined portion, a first transfer gate that transfers charge from the photoelectric conversion portion to the charge storage portion, and a charge from the charge storage portion to the predetermined portion. A solid-state imaging device having a plurality of pixels provided with a second transfer gate portion for transferring the substrate, wherein a gap is seen in a substantially normal direction of the substrate in an interlayer film formed on the substrate. It is formed so as to substantially surround the charge storage portion in plan view.

  A solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein a part of the gap is disposed on the photoelectric conversion unit.

  A solid-state imaging device according to a third aspect of the present invention is the solid-state imaging device according to the first or second aspect, further comprising a light-shielding film formed to cover the charge storage portion, and an upper edge of the gap is the light-shielding film It has reached the lower surface of.

  Note that the upper end edge of the gap means an end edge of the gap opposite to the substrate side. The lower surface of the light shielding film refers to the surface of the light shielding film on the substrate side. These points are the same also about the 5th aspect mentioned later.

  A solid-state imaging device according to a fourth aspect of the present invention includes a photoelectric conversion unit that generates and accumulates charges according to incident light, a charge storage unit that accumulates charges transferred from the photoelectric conversion unit, and a charge amount of a predetermined part An amplifying unit that outputs a signal corresponding to the first transfer gate unit, a first transfer gate unit that transfers charge from the photoelectric conversion unit to the charge storage unit, and a second transfer that transfers charge from the charge storage unit to the predetermined part A solid-state imaging device having a plurality of pixels provided with a gate portion on a substrate, wherein an inter-layer film formed on the substrate has a gap in a plan view when viewed from a substantially normal direction of the substrate. Are formed so as to substantially surround the effective light receiving region.

  A solid-state imaging device according to a fifth aspect of the present invention includes, in the fourth aspect, a light-shielding film formed to cover the pixel region other than the region corresponding to the effective light receiving region of the photoelectric conversion unit, The upper edge of the gap reaches the lower surface of the light shielding film.

  In the solid-state imaging device according to the sixth aspect of the present invention, in the third or fifth aspect, the light shielding film also serves as a wiring.

  According to the present invention, in a solid-state imaging device capable of performing an electronic shutter operation simultaneously for all pixels by having a charge storage unit in a pixel, light incidence to the charge storage unit is reduced, and a false signal due to the light incidence It is possible to provide a solid-state imaging device capable of suppressing the occurrence of the above.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is an electric circuit diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment of the present invention.

  In FIG. 1, the solid-state imaging device according to the present embodiment is illustrated as having 2 columns × 2 rows = 4 pixels 10 arranged in a two-dimensional matrix. The number of pixels is not particularly limited, but actually, for example, tens to thousands of pixels are arranged in each row and each column, and resolution is increased by increasing the number of pixels. The present invention can be applied not only to a two-dimensional image sensor but also to a one-dimensional image sensor.

  As shown in FIG. 1, each pixel 10 includes a photodiode 1 as a photoelectric conversion unit that generates and accumulates charges according to incident light, and a charge storage unit 3 that accumulates charges transferred from the photodiode 1. Floating diffusion (FD) 4 as a predetermined part, MOS transistor (amplifying transistor) 7 as an amplifying part for outputting a signal corresponding to the charge amount of the predetermined part (in this embodiment, FD4), Reset gate section 6 for discharging charge, first transfer gate section 11 for transferring charge from photodiode 1 to charge storage section 3, gate electrode constituting first transfer gate section 11 and charge storage section 3 An electrode 2 that functions as both gate electrodes of the first gate electrode, a second transfer gate portion 5 that transfers charges from the charge storage portion 3 to the FD 4, and a photodiode 1 A MOS transistor (unnecessary charge discharging transistor) 8 as an unnecessary charge discharging gate portion for discharging unnecessary charges that do not contribute to image formation generated from the photodiode 1, and a vertical selection switch 9 made of a MOS transistor; It has.

  FIG. 2 is a schematic plan view schematically showing a main part of one pixel (unit pixel) 10 in FIG. FIG. 3 is a schematic cross-sectional view along the line A-A ′ in FIG. 2. FIG. 4 is a schematic cross-sectional view taken along line B-B ′ in FIG. 2. FIG. 5 is a schematic plan view showing the second amylium layers 36 to 38 in FIGS. 3 and 4. FIG. 6 is a schematic plan view showing the third amylnium layer 39 in FIGS. 3 and 4. 5 and 6 also show the same A-A 'line and B-B' line as in FIG.

As shown in FIGS. 3 and 4, a P-type well 22 is formed on an N-type silicon substrate 21. The photodiode 1 is configured by forming the N-type layer (N ⁺ ) 23 in the P-type well 22. This photodiode 1 has a structure in which a high-concentration P-type layer (P ⁺⁺ ) 24 is added to the substrate surface side.

  As shown in FIG. 3, the charge storage unit 3 includes an N-type layer formed in the P-type well 22. A portion 2a corresponding to the gate electrode for the charge storage portion 3 of the electrode 2 made of polysilicon or the like is formed on the charge storage portion 3, and the charge storage portion 3 is effectively a MOS diode having a gate. It is configured as.

  As shown in FIGS. 2 and 3, the electrode 2 has a portion 2 b formed between the charge storage portion 3 and the photodiode 1 in addition to the portion 2 a. The first transfer gate portion 11 is configured as a MOS transistor having the portion 2b of the electrode 2 as a gate and the charge storage portion 3 and the N-type layer 23 of the photodiode 1 as a source or a drain.

The P-well 22, as shown in FIGS. 2 to 4, consisting of the N-type layer ^{(N +)} FD4, and, N-type layer ^(N +) 25 to 27 is formed. The N-type layer 25 is connected to the power supply VDD by a wiring (not shown).

  A gate electrode 5a made of polysilicon or the like is formed between the charge storage unit 3 and the FD 4, and the second transfer gate unit 5 uses the gate electrode 5a as a gate and the charge storage unit 3 and FD 4 as a source or It is configured as a MOS transistor as a drain.

  As shown in FIGS. 2 and 4, a gate electrode 6 a is formed between the FD 4 and the N-type layer 25, and the reset gate unit 6 uses the gate electrode 6 a as a gate and the FD 4 and the N-type layer 25. The MOS transistor is configured as a source or drain.

  As shown in FIGS. 2 and 4, a gate electrode 7a is formed between the N-type layers 25 and 26, and the amplifying transistor 7 uses the gate electrode 7a as a gate and the N-type layers 25 and 26 as sources or It is configured as a MOS transistor as a drain. As shown in FIGS. 2 to 4, the gate electrode 7a is connected to the FD 4 by a first amylium layer 28 serving as a wiring.

  As shown in FIGS. 2 and 4, a gate electrode 9a is formed between the N-type layers 26 and 27. The vertical selection switch 9 uses the gate electrode 9a as a gate and the N-type layers 26 and 27 as sources or It is configured as a MOS transistor as a drain.

  As shown in FIG. 2, a gate electrode 8a is formed between the N-type layer 25 and the photodiode 1, and the unnecessary charge discharging transistor 8 has the gate electrode 8a as a gate and the N-type layer 25 and the photo diode. This is configured as a MOS transistor using the N-type layer 23 of the diode 1 as a source or drain.

  As shown in FIGS. 3 and 4, on the substrate 21, a silicon oxide film 31 that becomes a gate insulating film and the like, and interlayer films 32 to 34 made of, for example, a silicon oxide film are provided from the lower side (substrate 21 side). It is formed in order. First amylium layers 28, 30, and 35 are formed immediately above the interlayer film 32, second amylium layers 36 to 38 are formed immediately above the interlayer film 33, and a third layer is formed immediately above the interlayer film 34. An amylnium layer 39 is formed. The first amylnium layer 35 is a relay wiring that electrically relays the electrode 2 to the second amylium layer 36. The amylnium layer 39 also serves as a predetermined wiring.

  In the present embodiment, as shown in FIGS. 2 and 3, the gaps 40 are substantially formed in the interlayer films 32 and 33 in the plan view as viewed from the substantially normal direction of the substrate 21. It is formed to surround. In the present embodiment, the gap 40 is preferable because it completely surrounds the charge storage portion 3. However, in the present invention, the gap 40 may surround most of the charge storage portion 3 even if it is not partially connected and does not completely surround the charge storage portion 3. In the present embodiment, as shown in FIGS. 2 and 3, the left portion of the gap 40 in these drawings is formed on the photodiode 1. However, the left portion of the gap 40 may be disposed between the photodiode 1 and the portion 2a of the electrode 2, for example.

  Further, in the present embodiment, as shown in FIG. 3 (see also FIG. 8 described later), the lower end of the portion on the silicon oxide film 31 in the gap 40 (near D in FIGS. 3 and 8) is The silicon oxide film 31 bites into the silicon oxide film 31, and the thickness of the lower side of the gap 40 is smaller than the thickness of other portions.

  Furthermore, in the present embodiment, as shown in FIGS. 3 and 5, the second amylnium layer 36 is formed not only to be used as a wiring, but also to cover the charge storage portion 3, It has become. As shown in FIG. 3, the upper edge of the gap 40 (the edge opposite to the substrate 21) reaches the lower surface of the second amylnium layer 36 as a light shielding film. It is not always necessary that the upper edge of the gap 40 reaches the lower surface of the amylium layer 36. However, in order to make the light shielding to the charge storage unit 3 more complete, the upper edge of the gap 40 is not as in the present embodiment. It is preferable to reach the lower surface of the amylnium layer 36.

  The third amylnium layer 39 is a light-shielding film that also serves as a wiring, and has an opening 39a through which incident light directed to the photodiode 1 passes, as shown in FIGS.

  In the present embodiment, a color filter or incident light is collected toward the photodiode 1 on the photodiode 1 at a position above the third amylium layer 39 as in the known solid-state imaging device. An on-chip microlens or the like for providing light is provided, but illustration thereof is omitted.

  As shown in FIG. 1, the solid-state imaging device according to the present embodiment includes a drive control unit provided outside the imaging unit, a CDS (Correlated Double Sampling; correlation 2), in addition to the imaging unit including a plurality of pixels 10. Double sampling) circuit 51. The drive control unit includes a horizontal scanning circuit 52, a vertical scanning circuit 53, a horizontal selection switch 54 composed of MOS transistors, an output buffer amplifier 55, and the like.

  As shown in FIG. 1, one end (the N-type layer 27) of the vertical selection switch 9 is connected to a vertical signal line 50 for each column, and further connected to a CDS circuit 51 provided for each column. The signal processed by the CDS circuit 51 is input to the output buffer 55 via the horizontal selection switch 54, and is supplied from an output terminal Vout to an external circuit (not shown) as an imaging signal. The horizontal selection switch 54 is controlled by the horizontal scanning circuit 52.

  As shown in FIG. 1, the gate electrodes 8 a of the unnecessary charge discharging transistors 8 of all the pixels 10 are connected in common and receive a driving pulse φPDRST from the vertical scanning circuit 33. The electrodes 2 of all the pixels 10 (the electrode serving as the gate electrode of the first transfer gate unit 11 and the gate electrode for the charge storage unit 3) are connected in common and receive the drive pulse φSTG from the vertical scanning circuit 33.

  As shown in FIG. 1, the gate electrode 5a of the second transfer gate section 5 is connected for each row, and receives drive pulses φTX (1) and φTX (2) from the vertical scanning circuit 33 for each row. . The gate electrode 9a of the vertical selection switch 9 is connected to each row and receives drive pulses φSEL (1) and φSEL (2) from the vertical scanning circuit 33 for each row. The gate electrode 6a of the reset gate 6 is connected to each row and receives drive pulses φRST (1) and φRST (2) from the vertical scanning circuit 33 for each row.

  The solid-state imaging device according to the present embodiment can basically be manufactured by using a semiconductor manufacturing process in the same manner as a conventional solid-state imaging device. As for the gap 40, for example, after the interlayer film 33 is fabricated, a resist is formed on the entire surface of the interlayer film 33, and only a portion corresponding to the gap 40 in the resist is removed by photolithography, and this resist is used as a mask. After forming the gap 40 by dry etching, the resist is removed, and then the second amylnium layers 36 to 38 may be formed by a normal method. At this time, even if a part of aluminum enters a part of the gap 40, the amylnium enhances the light reflection function at the wall part of the gap 40, so that there is no influence on the light shielding function for the charge storage unit 3. Absent. Needless to say, the method of forming the gap 40 is not limited to dry etching as described above.

  Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 7 is a timing chart showing the operation of the solid-state imaging device according to this embodiment. In FIG. 7, it is assumed that the corresponding transistor is turned on when each drive pulse is high.

  First, φPDRST is set to high to turn on the unnecessary charge discharging transistors 8 of all the pixels 10 at the same time, and the charges stored in the photodiodes 1 of all the pixels 10 are discarded to the power supply VDD.

  Next, φPDRST is set to low to turn off unnecessary charge discharging transistors 8 of all the pixels 10 at the same time, and charge accumulation in the photodiodes 1 of all the pixels 10 is started. At this time, the charges stored in the charge storage unit 3 are sequentially read at the time of the previous reading and the charge storage unit 3 is empty. However, a separate timing for resetting the charge storage unit 3 may be provided. .

  Next, before the predetermined accumulation time has elapsed since φPDRST was set to low, φSTG was set to high to turn on the first transfer gates 11 of all the pixels 10 at the same time, and the charge stored in the photodiodes 1 was stored as a charge. The data is transferred to the unit 3, and φSTG is set to low to turn off the first transfer gate unit 11 of all the pixels 10. As shown in FIG. 7, the time from when φPDRST is made low to when φSTG is made low again is the accumulated exposure time (electronic shutter time). When the charge is transferred from the photodiode 1 to the first transfer gate section 2 with φSTG being high, the potential of φSTG is set to a potential at which the charge from the photodiode 1 can be completely transferred.

  Next, φPDRST is set to high to turn on the unnecessary charge discharging transistors 8 of all the pixels 10 to reset the photodiodes 1. This prevents the charge from being overflowed into the charge storage unit 3 when it is stored in the photodiode 1 and exceeds the maximum accumulated charge of the photodiode 1 while reading out the charge stored in the charge storage unit 3. Alternatively, the photodiode 1 is reset to the power supply VDD in preparation for the next charge accumulation. While the charge is stored in the charge storage unit 3, a potential that forms an inversion layer on the surface of the charge storage unit 3 may be applied as the potential of φSTG, thereby generating dark current during storage. You can prevent it.

  Thereafter, φSEL (1) is set high to turn on the vertical selection switch 9 in the first row, and the pixel 10 in the first row is selected. In this selected state, φRST (1) is set high and the reset gate unit 6 is turned on to reset the FD 4 connected to the gate electrode 7a of the amplifying transistor 7. The reset output from the amplifying transistor 7 at this time is stored in the CDS circuit 51 via the vertical signal line 50. Next, φTX (1) is set high to turn on the second transfer gate portion 5 of the pixel 10 in the first row, and charges in the charge storage portion 3 of the pixel 10 in the first row are transferred to the FD 4. At this time, the potential of φSTG is set to a potential at which charges can be completely transferred from the charge storage unit 3 to the FD 4. An amplified potential corresponding to the charge amount of the FD 4 is sent to the CDS circuit 51 through the vertical output line 50. In the CDS circuit 51, the difference from the reset output stored earlier is output as a pixel signal of the pixels 10 in the first row. The pixel signals of the pixels 10 in the first row are serially output from the output terminal Vout via the output buffer amplifier 55 by sequentially turning on the horizontal selection switch 54 by the horizontal scanning circuit 52.

  Thereafter, φSEL (1) is set to low, then φSEL (2) is set to high, and the vertical selection switch 9 in the second row is turned on to select the pixel 10 in the second row. In this selected state, as shown in FIG. 7, the states of the drive pulses φTX (2) and φRST (2) are the same as the states of the drive pulses φTX (1) and φRST (1) when φSEL (1) is high. And the same state. Thereby, the same readout operation as the pixel 10 in the first row described above is performed on the pixels 10 in the second row.

  As can be seen from the above description, an electronic shutter operation simultaneously for all pixels is realized.

  Here, FIG. 8 shows a state of light incidence toward the charge storage unit 3 and the like of the solid-state imaging device according to the present embodiment. FIG. 8 is an enlarged view of FIG. 3 in which some rays of incident light are written.

  FIG. 9 shows a solid-state imaging device according to a comparative example compared with the solid-state imaging device according to the present embodiment. FIG. 9 corresponds to FIG. 3 and FIG. 8. In FIG. 9, the same or corresponding elements as those in FIG. 3 and FIG. This comparative example is different from the present embodiment only in that the gap 40 is not formed in the interlayer films 32 and 33.

  According to the present embodiment, air exists in the gap 40 or is in a state close to a vacuum, but in any case, the refractive index in the gap 40 is approximately 1.0. On the other hand, since the interlayer films 32 and 33 are, for example, silicon oxide films, the refractive index is relatively large. For this reason, the critical angle at the wall portion of the gap 40 becomes small. Therefore, the wall portion of the gap 40 acts as a total reflection surface for most of the light entering the gap 40 from the interlayer films 32 and 33. Therefore, in the present embodiment, since the gap 40 surrounds the charge storage portion 3, as shown in FIG. 8, the light coming obliquely from the side is totally reflected by the wall portion of the gap 40, and the light is charged. The storage unit 3 is shielded from light. Further, since the charge storage portion 3 is covered with the second amylnium layer 36 as a light shielding film, light coming from above is shielded by the amylnium layer 36. In the present embodiment, since the upper edge of the gap 40 reaches the lower surface of the amylium layer 36, light that enters through the gap between the upper edge amylium layer 36 of the gap 40 also enters the wall portion of the gap 40. Therefore, the light shielding property for the charge storage unit 3 is further improved.

  Furthermore, according to the present embodiment, the left side portion of the gap 40 in FIGS. 2, 3, and 8 is formed on the photodiode 1, so the left side portion of the gap 40 is the portion of the photodiode 1 and the electrode 2. Compared with the case where it is arranged between 2 a and 2 a, the left side portion in the gap 40 is arranged at a position farther from the charge storage unit 3. For this reason, light such as a light beam 312 in FIG. 9 to be described later can be shielded more effectively, and the light shielding property to the charge storage unit 3 is further enhanced.

  Furthermore, according to the present embodiment, the lower end of the gap 40 on the silicon oxide film 31 (near D in FIGS. 3 and 8) bites into the silicon oxide film 31, and the silicon oxide film 31. Since the thickness of the lower side of the gap 40 is thinner than the thickness of other portions, the light such as the light beam 312 in FIG. The light shielding property for the charge storage unit 3 is further increased. However, in the present invention, the lower end of the portion on the silicon oxide film 31 in the gap 40 does not necessarily have to bite into the silicon oxide film 31.

  The light shielding property of the charge storage unit 3 described above can be understood more easily by comparing FIG. 8 with FIG. In FIG. 9, light rays 311, 312, and 313 a that enter the charge storage unit 3 are reflected by the wall portion of the gap 40 and do not enter the charge storage unit 3 in FIG. The light beam 313a is a light beam reflected by the gate electrode 5a among the light beams 313.

  As described above, according to the present embodiment, in the solid-state imaging device that can perform the electronic shutter operation simultaneously for all the pixels because the pixel 10 has the charge storage unit 3, the light incident on the charge storage unit 3 can be performed. Therefore, the false signal due to the incident light can be suppressed.

  In this embodiment, the CDS circuit 51 is provided in the chip. However, the CDS process may be performed outside without providing the CDS circuit 51 in the chip.

  In this embodiment, the unnecessary charge discharging transistor 8 is provided. However, in the present invention, the unnecessary charge discharging transistor 8 is not necessarily provided.

  Further, in the present embodiment, the electrode 2 has the portion 2a as the gate electrode for the charge storage portion 3, but the charge can be completely transferred from the photodiode 1 to the charge storage portion 3 and from the charge storage portion 3 to the FD 4. If the charge storage portion 3 is produced as described above, the electrode 2 may not have the portion 2 a as the gate electrode 4 for the charge storage portion 3.

  [Second Embodiment]

  FIG. 10 is a schematic plan view schematically showing the main part of the unit pixel of the solid-state imaging device according to the second embodiment of the present invention. FIG. 11 is a schematic cross-sectional view taken along the line D-D ′ in FIG. 10. FIG. 12 is a schematic plan view showing second amylium layers 36 to 38 in FIG. FIG. 13 is a schematic plan view showing the third amylnium layer 39 in FIG. 10 to 13 correspond to FIGS. 2, 3, 5, and 6, respectively. FIG. 11 also shows the state of incident light. 10 to 13, elements that are the same as or correspond to those in FIGS. 2 to 6 are given the same reference numerals, and redundant descriptions thereof are omitted.

  This embodiment is different from the first embodiment only in the points described below. In the first embodiment, the gap 40 that substantially surrounds the charge storage portion 3 is formed in the interlayer films 32 and 33, whereas in the present embodiment, the gap 40 is not formed, but instead. In addition, a gap 60 is formed in the interlayer films 32 to 34 so as to substantially surround the effective light receiving region of the photodiode 1 in a plan view as viewed from the substantially normal direction of the substrate 21.

  In the present embodiment, the second amylnium layer 36 covers only a small part of the charge storage portion 3.

  Further, in the present embodiment, the light shielding film formed so that the upper edge (edge opposite to the substrate 21) of the gap 60 covers the pixel region other than the region corresponding to the effective light receiving region of the photodiode 1. And reaches the lower surface of the third amylnium layer 39. It is not always necessary that the upper edge of the gap 60 reaches the lower surface of the amylnium layer 39. However, in order to make the light shielding to the charge storage unit 3 more complete, the upper edge of the gap 60 is not as in the present embodiment. It is preferable to reach the lower surface of the amylnium layer 36. In this embodiment, the amylnium layer 39 also serves as a predetermined wiring.

  In the present embodiment, as shown in FIG. 11, the lower end of the portion on the silicon oxide film 31 in the gap 60 bites into the silicon oxide film 31, and the silicon oxide film 31 is located below the gap 60. Is thinner than other parts.

  According to the present embodiment, light that is about to enter the charge storage unit 3 is reflected by the amylnium layer 39 serving as a light shielding film and the wall surface of the gap 60, and is not incident on the charge storage unit 3. Therefore, according to the present embodiment, as in the first embodiment, in the solid-state imaging device capable of performing the electronic shutter operation for all the pixels simultaneously by the pixel 10 having the charge storage unit 3, Light incidence to the charge storage unit 3 can be reduced, and consequently, false signals due to the light incidence can be suppressed.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

  For example, the present invention can also be applied to a solid-state imaging device using a junction field effect transistor in an amplification unit as disclosed in Patent Documents 1 and 2.

1 is an electric circuit diagram showing a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic plan view which shows typically the principal part of the unit pixel in FIG. FIG. 3 is a schematic cross-sectional view along the line A-A ′ in FIG. 2. FIG. 3 is a schematic sectional view taken along line B-B ′ in FIG. 2. FIG. 5 is a schematic plan view showing a second amylium layer in FIGS. 3 and 4. FIG. 5 is a schematic plan view showing a third amylium layer in FIGS. 3 and 4. 2 is a timing chart illustrating an operation of the solid-state imaging device illustrated in FIG. 1. It is a figure which shows the mode of the incident light of the solid-state imaging device shown in FIG. It is a figure which shows the solid-state imaging device by a comparative example. It is a schematic plan view which shows typically the principal part of the unit pixel of the solid-state imaging device by the 2nd Embodiment of this invention. It is a schematic sectional drawing in alignment with the D-D 'line in FIG. FIG. 12 is a schematic plan view showing a second amylnium layer in FIG. 11. FIG. 12 is a schematic plan view showing a third amylium layer in FIG. 11. It is a figure which shows the mode of the light incidence of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode 3 Charge storage part 4 Floating diffusion 5 2nd transfer gate part 7 Amplifying transistor 11 1st transfer gate part 21 Substrate 32-34 Interlayer film 40,60 Gap

Claims (6)

A photoelectric conversion unit that generates and accumulates charges according to incident light, a charge storage unit that accumulates charges transferred from the photoelectric conversion unit, an amplification unit that outputs a signal according to a charge amount of a predetermined portion, and the photoelectric conversion A solid-state substrate having a plurality of pixels each including a first transfer gate portion that transfers charges from the charge storage portion to the charge storage portion and a second transfer gate portion that transfers charges from the charge storage portion to the predetermined portion An imaging device,
A solid-state imaging device, wherein a gap is formed in an interlayer film formed on the substrate so as to substantially surround the charge storage portion in a plan view viewed from a substantially normal direction of the substrate.   The solid-state imaging device according to claim 1, wherein a part of the gap is disposed on the photoelectric conversion unit.   3. The solid-state imaging device according to claim 1, further comprising: a light shielding film formed to cover the charge storage portion, wherein an upper end edge of the gap reaches a lower surface of the light shielding film. A photoelectric conversion unit that generates and accumulates charges according to incident light, a charge storage unit that accumulates charges transferred from the photoelectric conversion unit, an amplification unit that outputs a signal according to a charge amount of a predetermined portion, and the photoelectric conversion A solid-state substrate having a plurality of pixels each including a first transfer gate portion that transfers charges from the charge storage portion to the charge storage portion and a second transfer gate portion that transfers charges from the charge storage portion to the predetermined portion An imaging device,
In the interlayer film formed on the substrate, a gap is formed so as to substantially surround the effective light receiving region of the photoelectric conversion unit in a plan view viewed from a substantially normal direction of the substrate. Solid-state imaging device.   A light-shielding film formed so as to cover the pixel region other than the region corresponding to the effective light-receiving region of the photoelectric conversion unit, and an upper end edge of the gap reaches a lower surface of the light-shielding film. The solid-state imaging device according to claim 4.   The solid-state imaging device according to claim 3, wherein the light shielding film also serves as a wiring.

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