JP2011192941A - Thin film transistor substrate, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce defects, such as an electric conduction failure, in a thin film transistor. <P>SOLUTION: A thin film transistor substrate includes: a substrate 10; a gate electrode 5a formed on the substrate 10; a source electrode 5i and a drain electrode 5h that are disposed separately with each other at locations sandwiching the gate electrode 5a on the gate electrode 5a; and a semiconductor layer 50 that is integrally formed to cover at least a part of the source electrode 5i, at least a part of the drain electrode 5h and a region between the source electrode 5i and the drain electrode 5h and contains crystalline silicon. The semiconductor layer 50 has a pair of impurity semiconductor film sections 5f, 5g containing a dopant and a semiconductor film section 5b formed between the pair of impurity semiconductor film sections 5f, 5g, wherein the pair of impurity semiconductor film sections 5f, 5g are formed at a portion covering at least a part of the source electrode 5i on one end side of the semiconductor layer and a portion covering at least a part of the drain electrode 5h on the another end side. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film transistor substrate and a method for manufacturing the thin film transistor substrate.

In a conventional thin film transistor, amorphous silicon is generally used for a semiconductor layer in which a channel region is formed.
In addition, for the purpose of improving the on-current of the thin film transistor, an attempt to use crystalline silicon, particularly microcrystalline silicon (microcrystalline silicon: crystalline (polycrystalline) silicon having a crystal grain size of approximately 50 to 100 nm) for the semiconductor layer. However, when crystalline silicon is used for the semiconductor layer of a transistor having an inverted staggered structure, there is a problem that defects such as conduction failure may be caused.
This is because the surface of the semiconductor layer containing crystalline silicon has many irregularities, so that the etching gas passes through the crystalline silicon recess during dry etching when forming a channel protective film on the channel formation region of the semiconductor layer. May reach the gate insulating film and part of the gate insulating film may be scraped off. In addition, the impurity semiconductor film and the source / drain electrodes formed on the semiconductor layer having a part of the gate insulating film and having a large number of crystalline silicon unevenness are not stacked with a normal structure. This is because a current path between the two is not normally formed, which causes a defect such as a conduction failure.
In order to reduce defects such as poor conduction, a technique is known in which a semiconductor layer in which an amorphous silicon layer is stacked on a crystalline silicon layer is applied to a thin film transistor (see, for example, Patent Document 1).

JP 2004-304140 A

However, in the case of Patent Document 1, if the surface of the crystalline silicon layer is too large, the amorphous silicon layer may not be able to alleviate the unevenness. Further, when the amorphous silicon layer is formed thick in order to reduce the unevenness, the resistance in the film thickness direction of the semiconductor layer is increased, and the on-current is hardly increased.
In addition, when the interface between the crystalline silicon layer and the amorphous silicon layer becomes a current path, the disturbance of the interface due to the unevenness leads to an increase in resistance value, and it is difficult to obtain an increase in on-current. was there.

  Accordingly, an object of the present invention is to reduce defects such as conduction failure of thin film transistors.

In order to solve the above problems, one aspect of the present invention is a thin film transistor substrate,
A substrate, a gate electrode formed on the substrate, a source electrode and a drain electrode provided on the gate electrode so as to be sandwiched between the gate electrode, at least a part of the source electrode, A semiconductor layer including crystalline silicon, which is integrally formed so as to cover at least a part of the drain electrode and a region between the source electrode and the drain electrode, and the semiconductor layer includes the source on one end side. A portion covering at least a portion of the electrode and a portion covering at least a portion of the drain electrode on the other end side, and formed between a pair of impurity semiconductor film portions including a dopant and the pair of impurity semiconductor film portions. And a semiconductor film portion.
Preferably, the impurity semiconductor film portion on one end side and the impurity semiconductor film portion on the other end side face each other with the semiconductor film portion above the gate electrode interposed therebetween.
Preferably, a cap layer is formed so as to cover the upper surface of the semiconductor layer.
Preferably, the light emitting device further includes a first electrode, a second electrode, and a light emitting element provided between the first electrode and the second electrode.

Another aspect of the present invention is a method of manufacturing a thin film transistor substrate,
A source / drain electrode forming step in which a source electrode and a drain electrode are separately formed on a gate electrode formed on a substrate so as to sandwich the gate electrode; and a semiconductor layer containing crystallized silicon is formed on the source electrode Forming a semiconductor layer integrally so as to cover at least a part of the electrode, at least a part of the drain electrode, and a region between the source electrode and the drain electrode; and ion doping on both ends of the semiconductor layer One impurity semiconductor film part covering at least part of the source electrode on one end side of the semiconductor layer and including a dopant, and covering at least part of the drain electrode on the other end side of the semiconductor layer and including a dopant The other impurity semiconductor film part is formed, and the semiconductor film part sandwiched between the pair of impurity semiconductor film parts is formed. An ion doping process that, characterized in that it comprises a.
Preferably, in the ion doping step, ion doping is performed in a state where the semiconductor layer portion corresponding to the upper side of the gate electrode is shielded by a resist film, and the semiconductor film portion is opposed to the semiconductor film portion therebetween. A pair of impurity semiconductor film portions is formed.
Preferably, after the semiconductor layer forming step, a step of forming a cap layer covering the semiconductor layer is provided, and the resist film is formed on the cap layer.

  The present invention can reduce defects such as poor conduction of thin film transistors.

It is a top view which shows the arrangement configuration of the pixel of an EL panel. It is a top view which shows schematic structure of EL panel. It is a circuit diagram showing a circuit corresponding to one pixel of an EL panel. It is the top view which showed 1 pixel of EL panel. It is arrow sectional drawing of the surface along the VV line of FIG. It is arrow sectional drawing of the surface along the VI-VI line of FIG. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is explanatory drawing which shows the manufacturing process of a thin-film transistor. It is a front view which shows an example of the mobile telephone by which EL panel was applied to the display panel. They are the front side perspective view (a) which shows an example of the digital camera with which the EL panel was applied to the display panel, and a rear side perspective view (b). It is a perspective view which shows an example of the personal computer by which EL panel was applied to the display panel. It is a figure for demonstrating the measuring method of the crystallinity degree of the semiconductor by a Raman spectroscopy.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a plan view showing an arrangement configuration of a plurality of pixels P in an EL panel 1 that is a light emitting device, and FIG. 2 is a plan view showing a schematic configuration of the EL panel 1.

As shown in FIGS. 1 and 2, in the EL panel 1, a plurality of pixels P that respectively emit R (red), G (green), and B (blue) are arranged in a matrix with a predetermined pattern. .
In the EL panel 1, a plurality of scanning lines 2 are arranged so as to be substantially parallel to each other along the row direction, and the plurality of signal lines 3 are arranged along the column direction so as to be substantially orthogonal to the scanning lines 2 in plan view. They are arranged so as to be substantially parallel to each other. A voltage supply line 4 is provided along the scanning line 2 between the adjacent scanning lines 2. A range surrounded by the two signal lines 3 adjacent to the scanning lines 2 and the voltage supply lines 4 corresponds to the pixel P.
Further, the EL panel 1 is provided with a bank 13 that is a grid-like partition wall so as to cover the scanning line 2, the signal line 3, and the voltage supply line 4. A plurality of substantially rectangular openings 13a surrounded by the banks 13 are formed for each pixel P, and predetermined carrier transport layers (a hole injection layer 8b and a light emitting layer 8c described later) are formed in the openings 13a. ) Are provided and become a light emitting region of the pixel P. The carrier transport layer is a layer that transports holes or electrons when a voltage is applied.
In FIG. 1, the banks 13 are provided in a lattice shape, but the present invention is not limited to this, and for example, the banks 13 may be provided only in one direction along the signal line 3. .

  FIG. 3 is a circuit diagram showing a circuit corresponding to one pixel of the EL panel 1 operating in the active matrix driving method.

  As shown in FIG. 3, the EL panel 1 is provided with a scanning line 2, a signal line 3 intersecting with the scanning line 2, and a voltage supply line 4 along the scanning line 2. For each pixel P, a switch transistor 5 which is a thin film transistor, a driving transistor 6 which is a thin film transistor, a capacitor 7 and an EL element (light emitting element) 8 are provided.

  In each pixel P, the gate of the switch transistor 5 is connected to the scanning line 2, one of the drain and source of the switch transistor 5 is connected to the signal line 3, and the other of the drain and source of the switch transistor 5 is It is connected to one electrode of the capacitor 7 and the gate of the driving transistor 6. One of the source and drain of the drive transistor 6 is connected to the voltage supply line 4, and the other of the source and drain of the drive transistor 6 is connected to the other electrode of the capacitor 7 and the anode (first electrode) of the EL element 8. Has been. Note that the cathodes (second electrodes) of the EL elements 8 of all the pixels P are kept at a constant voltage Vcom (for example, ground potential).

  Further, in the periphery of the EL panel 1, each scanning line 2 is connected to a scanning driver, each voltage supply line 4 is connected to a constant voltage source or a driver that outputs an appropriate voltage signal, and each signal line 3 is connected to a data driver. The EL panel 1 is driven by these drivers by an active matrix driving method. The voltage supply line 4 is supplied with predetermined power by a constant voltage source or a driver.

  Next, the circuit structure of the EL panel 1 and the pixel P will be described with reference to FIGS. Here, FIG. 4 is a plan view corresponding to one pixel P of the EL panel 1, FIG. 5 is a cross-sectional view taken along the line V-V in FIG. 4, and FIG. It is arrow sectional drawing of the surface along the VI-VI line. In FIG. 4, electrodes and wiring are mainly shown.

  As shown in FIG. 4, the switch transistor 5 and the drive transistor 6 are arranged along the signal line 3, the capacitor 7 is disposed in the vicinity of the switch transistor 5, and the EL element 8 is disposed in the vicinity of the drive transistor 6. ing. Further, a switch transistor 5, a drive transistor 6, a capacitor 7, and an EL element 8 are disposed between the scanning line 2 and the voltage supply line 4.

  As shown in FIGS. 4 to 6, a first insulating film 11 serving as a gate insulating film is formed on one surface of the substrate 10, and a second insulating film 12 is formed on the first insulating film 11. Has been. The signal line 3 is formed between the first insulating film 11 and the substrate 10, and the scanning line 2 and the voltage supply line 4 are formed between the first insulating film 11 and the second insulating film 12.

  4 and 6, the switch transistor 5 is a thin film transistor having a coplanar bottom gate structure. The switch transistor 5 includes a gate electrode 5a, a drain electrode 5h, a source electrode 5i, a semiconductor film portion 5b of the semiconductor layer 50, impurity semiconductor film portions 5f and 5g of the semiconductor layer 50, and the like.

The gate electrode 5 a is formed on the upper surface of the substrate 10. The gate electrode 5a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film. An insulating first insulating film 11 is formed on the substrate 10 on which the gate electrode 5a is formed, and the gate electrode 5a is covered with the first insulating film 11. The first insulating film 11 has, for example, optical transparency and is made of silicon nitride or silicon oxide.
On the first insulating film 11, a source electrode 5i and a drain electrode 5h are formed so as to be spaced apart in one direction (channel length direction) and sandwich the gate electrode 5a. The source electrode 5i and the drain electrode 5h are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
A semiconductor layer 50 is formed on the first insulating film 11 so as to cover the source electrode 5 i and the drain electrode 5 h and to be integrally connected on the first insulating film 11. The semiconductor layer 50 is made of crystalline silicon and contains microcrystalline silicon.
The semiconductor layer 50 has an impurity semiconductor film portion 5g that covers one end side along one direction and covers the source electrode 5i, an impurity semiconductor film portion 5f that covers the drain electrode 5h on the other end side along one direction, And a semiconductor film part 5b located between the pair of impurity semiconductor film parts 5g and 5f. The impurity semiconductor film part 5g and the impurity semiconductor film part 5f are semiconductor layers containing a dopant, and the semiconductor film part 5b is an intrinsic semiconductor layer containing no dopant. The pair of impurity semiconductor film portions 5g and 5f are opposed to one direction (channel length direction) with the semiconductor film portion 5b interposed therebetween. A semiconductor film portion 5b is disposed on the first insulating film 11 at a position corresponding to the gate electrode 5a. The semiconductor film portion 5b is opposed to the gate electrode 5a with the first insulating film 11 interposed therebetween. Yes. Then, a channel is formed on the interface side with the first insulating film 11 on the lower surface side of the semiconductor film portion 5b of the semiconductor layer 50.
The impurity semiconductor films 5g and 5f are n-type semiconductors, but are not limited to this and may be p-type semiconductors.
Further, an insulating cap layer 14 is formed on the semiconductor layer 50 (semiconductor film portion 5b, impurity semiconductor films 5g, 5f), and the semiconductor film portion 5b and impurity semiconductor films 5g, 5f are formed by the cap layer 14. It is covered. An insulating second insulating film 12 is further formed on the cap layer 14. The switch transistor 5 is covered with the cap layer 14 and the second insulating film 12.
The cap layer 14 and the second insulating film 12 are made of, for example, silicon nitride or silicon oxide.

  4 and 5, the driving transistor 6 is a thin film transistor having a coplanar type bottom gate structure. The driving transistor 6 includes a gate electrode 6a, a drain electrode 6h, a source electrode 6i, a semiconductor film portion 6b of the semiconductor layer 60, impurity semiconductor film portions 6f and 6g of the semiconductor layer 60, and the like.

The gate electrode 6a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film, and is formed between the substrate 10 and the first insulating film 11 similarly to the gate electrode 5a. . The gate electrode 6a is covered with a first insulating film 11 made of, for example, silicon nitride or silicon oxide.
On the first insulating film 11, a source electrode 6i and a drain electrode 6h are formed so as to be spaced apart in one direction (channel length direction) and sandwich the gate electrode 6a. The source electrode 6i and the drain electrode 6h are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
Further, on the first insulating film 11, a semiconductor layer 60 is formed which covers the source electrode 6 i and the drain electrode 6 h and is integrally connected on the first insulating film 11. The semiconductor layer 60 is made of crystalline silicon and contains microcrystalline silicon.
The semiconductor layer 60 has an impurity semiconductor film portion 6g that covers one end side along one direction and covers the source electrode 6i, an impurity semiconductor film portion 6f that covers the other end side along one direction and covers the drain electrode 6h, A semiconductor film portion 6b positioned between the pair of impurity semiconductor film portions 6g and 6f. The impurity semiconductor film part 6g and the impurity semiconductor film part 6f are semiconductor layers containing a dopant, and the semiconductor film part 6b is an intrinsic semiconductor layer containing no dopant. The pair of impurity semiconductor film portions 6g and 6f are opposed to one direction (channel length direction) with the semiconductor film portion 6b interposed therebetween. A semiconductor film portion 6b is disposed on the first insulating film 11 at a position corresponding to the gate electrode 6a, and the semiconductor film portion 6b is opposed to the gate electrode 6a with the first insulating film 11 interposed therebetween. Yes. Then, a channel is formed on the interface side with the first insulating film 11 on the lower surface side of the semiconductor film portion 6 b of the semiconductor layer 60.
The impurity semiconductor films 6g and 6f are n-type semiconductors, but are not limited thereto, and may be p-type semiconductors.
Further, an insulating cap layer 14 is formed on the semiconductor layer 60 (semiconductor film portion 6b, impurity semiconductor films 6g, 6f), and the semiconductor film portion 6b and impurity semiconductor films 6g, 6f are formed by the cap layer 14. It is covered. An insulating second insulating film 12 is further formed on the cap layer 14. The driving transistor 6 is covered with the cap layer 14 and the second insulating film 12.

  The capacitor 7 is connected between the gate electrode 6a and the source electrode 6i of the driving transistor 6, and as shown in FIGS. 4 and 6, one electrode 7a is interposed between the substrate 10 and the first insulating film 11. The other electrode 7b is formed between the first insulating film 11 and the cap layer 14, and the electrode 7a and the electrode 7b are opposed to each other with the first insulating film 11 that is a dielectric interposed therebetween.

The signal line 3, the electrode 7a of the capacitor 7, the gate electrode 5a of the switch transistor 5, and the gate electrode 6a of the driving transistor 6 are formed by forming a conductive metal film on the entire surface of the substrate 10 by a photolithography method and an etching method. It is formed in a lump by processing the shape by means of, for example.
In addition, the scanning line 2, the voltage supply line 4, the electrode 7 b of the capacitor 7, the drain electrode 5 h and source electrode 5 i of the switch transistor 5, and the drain electrode 6 h and source electrode 6 i of the driving transistor 6 are on the first insulating film 11. The conductive metal film is formed by shape processing by a photolithography method, an etching method, or the like.

In the first insulating film 11, a contact hole 11a is formed in a region where the gate electrode 5a and the scanning line 2 overlap, and a contact hole 11b is formed in a region where the drain electrode 5h and the signal line 3 overlap. A contact hole 11c is formed in a region where 6a and the source electrode 5i overlap, and contact plugs 20a to 20c are buried in the contact holes 11a to 11c, respectively. The contact plug 20a electrically connects the gate electrode 5a of the switch transistor 5 and the scanning line 2, the contact plug 20b electrically connects the drain electrode 5h of the switch transistor 5 and the signal line 3, and the contact plug 20c electrically connects the switch transistor. 5 source electrode 5i and capacitor 7 electrode 7a are electrically connected, and source electrode 5i of switch transistor 5 and gate electrode 6a of drive transistor 6 are electrically connected. The scanning line 2 may be in direct contact with the gate electrode 5a, the drain electrode 5h may be in contact with the signal line 3, and the source electrode 5i may be in contact with the gate electrode 6a without using the contact plugs 20a to 20c.
Further, the gate electrode 6a of the driving transistor 6 is integrally connected to the electrode 7a of the capacitor 7, the drain electrode 6h of the driving transistor 6 is integrally connected to the voltage supply line 4, and the source electrode 6i of the driving transistor 6 is connected to the capacitor. 7 is integrally connected to the electrode 7b.

The pixel electrode 8 a is provided on the substrate 10 via the first insulating film 11 and is formed independently for each pixel P. The pixel electrode 8a is a transparent electrode, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium − It consists of tin oxide (CTO). Note that the source electrode 6i of the driving transistor 6 partially overlaps the pixel electrode 8a, and the pixel electrode 8a and the source electrode 6i are connected.
As shown in FIGS. 4 and 5, the cap layer 14 and the second insulating film 12 include the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, and the peripheral portion of the pixel electrode 8a. The electrode 7b of the capacitor 7 and the first insulating film 11 are formed so as to cover. Openings 14a and 12a are formed in the cap layer 14 and the second insulating film 12 so that the center of each pixel electrode 8a is exposed. Therefore, the second insulating film 12 is formed in a lattice shape in plan view.

  A panel in which the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, the capacitor 7, the pixel electrode 8a, the cap layer 14, and the second insulating film 12 are formed on the surface of the substrate 10. Is a transistor array panel.

  As shown in FIGS. 4 and 5, the EL element 8 includes a pixel electrode 8a as a first electrode serving as an anode, a hole injection layer 8b that is a compound film formed on the pixel electrode 8a, and a hole. A light emitting layer 8c, which is a compound film formed on the injection layer 8b, and a counter electrode 8d as a second electrode formed on the light emitting layer 8c are provided. The counter electrode 8d is a single electrode common to all the pixels P, and is continuously formed in all the pixels P.

The hole injection layer 8b is a functional layer made of, for example, PEDOT (poly (ethylenedioxy) thiophene) that is a conductive polymer and PSS (polystyrene sulfonate) that is a dopant. This is a carrier injection layer that injects holes from the electrode 8a toward the light emitting layer 8c.
The light emitting layer 8c includes a material that emits any one of R (red), G (green), and B (blue) for each pixel P. For example, the light emitting layer 8c is made of a polyfluorene light emitting material or a polyphenylene vinylene light emitting material. This is a layer that emits light upon recombination of electrons supplied from the electrode 8d and holes injected from the hole injection layer 8b. For this reason, the pixel P that emits R (red), the pixel P that emits G (green), and the pixel P that emits B (blue) have different light emitting materials for the light emitting layer 8c. The R (red), G (green), and B (blue) pattern of the pixel P may be a delta arrangement or a stripe pattern in which the same color pixels are arranged in the vertical direction.

The counter electrode 8d is made of a material having a work function lower than that of the pixel electrode 8a. For example, the counter electrode 8d is made of a simple substance or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal.
The counter electrode 8d is an electrode common to all the pixels P, and covers a bank 13 described later together with a compound film such as the light emitting layer 8c.

As described above, the light emitting layer 8 c serving as a light emitting portion is partitioned for each pixel P by the second insulating film 12 and the bank 13.
And in the opening part 13a, the positive hole injection layer 8b and the light emitting layer 8c as a carrier transport layer are laminated | stacked on the pixel electrode 8a.

Specifically, when the hole injection layer 8b and the light emitting layer 8c are formed by a wet method, the bank 13 is adjacent to a liquid material in which a material for forming the hole injection layer 8b or the light emitting layer 8c is dissolved or dispersed in a solvent. It functions as a partition wall that prevents the pixel P from bleeding.
For example, as shown in FIG. 5, an opening 13 a is formed in the bank 13 provided on the second insulating film 12 inside the opening 12 a of the second insulating film 12.
Then, a liquid containing a material to be the hole injection layer 8b is applied on each pixel electrode 8a surrounded by each opening 13a, and the substrate 10 is heated to dry the liquid to form a film. The resulting compound film becomes the hole injection layer 8b which is the first carrier transport layer.
Further, a liquid material containing a material to be the light emitting layer 8c is applied on each hole injection layer 8b surrounded by each opening 13a, and the whole substrate 10 is heated to dry the liquid material to form a film. The compound film becomes the light emitting layer 8c which is the second carrier transport layer.
A counter electrode 8 d is provided so as to cover the light emitting layer 8 c and the bank 13.

In the EL panel 1, the pixel electrode 8a, the substrate 10 and the first insulating film 11 are transparent, and light emitted from the light emitting layer 8c is transmitted through the pixel electrode 8a, the first insulating film 11 and the substrate 10. Exit. Therefore, the back surface (lower surface) of the substrate 10 becomes a display surface.
The display surface may be the opposite side instead of the substrate 10 side. In this case, the counter electrode 8d is a transparent electrode, the pixel electrode 8a is a reflective electrode, and light emitted from the light emitting layer 8c is transmitted through the counter electrode 8d and emitted.

The EL panel 1 is driven as follows to emit light.
In a state where a predetermined level of voltage is applied to all the voltage supply lines 4, the scanning driver sequentially applies voltages to the scanning lines 2, thereby sequentially selecting the scanning lines 2.
When each scanning line 2 is selected, if a voltage of a level corresponding to the gradation is applied to all the signal lines 3 by the data driver, the switch transistor 5 corresponding to the selected scanning line 2 is turned on. Therefore, a voltage of a level corresponding to the gradation is applied to the gate electrode 6a of the drive transistor 6.
The potential difference between the gate electrode 6a and the source electrode 6i of the drive transistor 6 is determined according to the voltage applied to the gate electrode 6a of the drive transistor 6, and the magnitude of the drain-source current in the drive transistor 6 is determined. The EL element 8 emits light with brightness according to the drain-source current.
Thereafter, when the selection of the scanning line 2 is released, the switch transistor 5 is turned off, so that the charge according to the voltage applied to the gate electrode 6a of the driving transistor 6 is stored in the capacitor 7 and the driving transistor 6 The potential difference between the gate electrode 6a and the source electrode 6i is maintained.
For this reason, the drive transistor 6 keeps flowing the drain-source current having the same current value as that at the time of selection, and maintains the luminance of the EL element 8.

  Next, in the EL panel 1 according to the present invention, the merit of forming the semiconductor layers 50 and 60 in the switch transistor 5 and the drive transistor 6 used as drive elements on the upper surface of the first insulating film 11 from crystalline silicon. explain.

  Until now, the semiconductor layer in which a channel is formed in a thin film transistor is formed of crystalline silicon having a higher degree of crystallinity than amorphous silicon, thereby increasing the on-current and improving transistor characteristics. . However, due to the occurrence of leakage current due to many irregularities generated on the surface of the semiconductor layer containing crystalline silicon and the increase in resistance due to the disturbance of the interface due to the irregularities, the on-current is as originally expected. May not increase.

On the other hand, as shown in FIGS. 5 and 6, in the thin film transistor (switch transistor 5 and drive transistor 6) of this embodiment, the semiconductor layers 50 and 60 having the semiconductor film portions 5b and 6b in which the channels are formed are gated. By forming on the first insulating film 11 covering the substrate 10 on which the electrodes 5a and 6a are formed, the semiconductor layers 50 and 60 are uneven, but the semiconductor facing the first insulating film 11 is formed. The lower surfaces of the layers 50 and 60 can be made relatively flat, and the interface between the first insulating film 11 and the semiconductor layers 50 and 60 can be made relatively smooth.
The semiconductor layers 50 and 60 cover the source electrodes 5i and 6i and the drain electrodes 5h and 6h that are formed on the first insulating film 11 so as to be separated from each other. The impurity semiconductor film portions 5g and 6g, and the portions covering the drain electrodes 5h and 6h are the other impurity semiconductor film portions 5f and 6f. Further, the portion sandwiched between one impurity semiconductor film portion 5g, 6g and the other impurity semiconductor film portion 5f, 6f is the semiconductor film portion 5b, 6b, which is on the first insulating film 11 and of the gate electrode 5a. It is arranged at a position corresponding to the upper side. Then, one of the impurity semiconductor film portions 5g and 6g, the semiconductor film portions 5b and 6b, and the other impurity semiconductor film portion 5f in the semiconductor layers 50 and 60 that electrically connect the source electrodes 5i and 6i and the drain electrodes 5h and 6h. , 6f are integrally connected on the first insulating film 11, and the current path between the source electrodes 5i, 6i and the drain electrodes 5h, 6h is that of the semiconductor layers 50, 60 along the interface on the first insulating film 11. It becomes the bottom side. In particular, since the semiconductor film portions 5b and 6b on the first insulating film 11 are opposed to the gate electrodes 5a and 6a via the first insulating film 11, the first insulating film 11 side in the semiconductor film portions 5b and 6b. A channel is formed on a certain lower surface side.

In this way, the current path between the source electrodes 5i, 6i and the drain electrodes 5h, 6h in the thin film transistors 5, 6 is on the lower surface side of the semiconductor layers 50, 60 facing the interface with the relatively flat first insulating film 11. Thus, the current path is not affected by the surface irregularities of the semiconductor layers 50 and 60. In particular, since the channel regions in the semiconductor film portions 5b and 6b of the semiconductor layers 50 and 60 are not affected by the surface irregularities of the semiconductor layers 50 and 60, the semiconductor layers 50 and 60 containing crystalline silicon in the thin film transistors 5 and 6 are formed. Since the corresponding on-current can be obtained, the on-current of the thin film transistors 5 and 6 can be increased and the transistor characteristics can be improved.
That is, in the thin film transistors 5 and 6, the semiconductor layers 50 and 60 having the semiconductor film portions 5b and 6b in which the channels are formed are formed on the first insulating film 11 covering the substrate 10 on which the gate electrodes 5a and 6a are formed. By doing so, the source electrodes 5i, 6i on the first insulating film 11 and the drain electrodes 5h, 6h are electrically connected by the semiconductor layers 50, 60 containing crystalline silicon, and the on-current of the thin film transistors 5, 6 is reached. Can be improved.

  Next, a method for manufacturing thin film transistors such as the switch transistor 5 and the drive transistor 6 used as drive elements in the EL panel 1 will be described with reference to process diagrams shown in FIGS. The thin film transistors shown in the process diagrams (FIGS. 7 to 15) are partially different in shape from the switch transistor 5 and the drive transistor 6, but will be described as a conceptual thin film transistor common to the switch transistor 5 and the drive transistor 6. .

First, a gate metal layer is deposited on the substrate 10 by sputtering and patterned by a photolithography method, an etching method, or the like to form a gate electrode 5a (6a) as shown in FIG. The signal line 3 and the electrode 7a of the capacitor 7 are formed on the substrate 10 together with the gate electrode 5a (6a) (see FIGS. 5 and 6).
Further, as shown in FIG. 7, a first insulating film 11 such as silicon nitride is formed on the substrate 10 by plasma CVD so as to cover the gate electrode 5a (6a).

Next, as shown in FIG. 8, an electrode metal layer 9h to be the source electrode 5i (6i) and the drain electrode 5h (6h) is formed on the first insulating film 11 by sputtering or the like.
Next, the electrode metal layer 9h is patterned by photolithography or the like to form the source electrode 5i (6i) and the drain electrode 5h (6h) on the first insulating film 11, as shown in FIG.
Note that the pixel electrode 8a is formed on the first insulating film 11 in advance so that the pixel electrode 8a is sandwiched between the source electrode 6i of the driving transistor 6 (see FIG. 5). In addition to the source electrode and the drain electrode, the scanning line 2, the voltage supply line 4, and the electrode 7b of the capacitor 7 are formed (see FIGS. 4 to 6).

Next, as shown in FIG. 10, a semiconductor film 9c made of crystalline silicon, and particularly containing microcrystalline silicon (microcrystalline silicon) is formed on the first insulating film 11 by plasma CVD. The semiconductor film 9c becomes the semiconductor layer 50 (60) covering the source electrode 5i (6i) and the drain electrode 5h (6h) on the first insulating film 11.
The microcrystalline silicon semiconductor film 9c is formed after plasma decomposition of SiH ₄ gas and H ₂ gas, but the ratio of H ₂ gas to SiH ₄ gas is overwhelmingly increased, and the degree of crystallinity is increased. Therefore, by increasing the plasma power and pressure, the semiconductor film 9c which is a microcrystalline silicon thin film can be formed. In the present embodiment, argon is used as the carrier gas, the gas flow rate is SiH ₄ / H ₂ = 50/10500 [SCCM], the semiconductor is used under the conditions of a power density of 0.134 [W / cm ² ] and a pressure of 300 [Pa]. A film 9c was formed.
In particular, in order to increase the crystallinity of the microcrystalline silicon formed by changing the surface state of the base film (for example, the first insulating film 11), the first insulating film 11 and the like are formed before the semiconductor film 9c is formed. Plasma treatment is performed on the surface. The plasma treatment was performed using N ₂ O gas under the conditions of a gas flow rate of 2000 [SCCM], a power density of 0.356 [W / cm ² ], and a pressure of 80 [Pa]. Although N ₂ O gas is used in this embodiment, oxygen gas or hydrogen gas can be used under appropriate conditions instead of N ₂ O gas.
Whether or not the semiconductor film 9c is microcrystallized can be determined based on the crystallinity calculated by Raman spectroscopic measurement. For example, amorphous silicon gives a spectrum with a broad peak around 480 cm ⁻¹ . Grain boundary or very small crystalline silicon having a crystal diameter of 5 nm or less gives a spectrum having a broad peak around 500 cm ⁻¹ . Crystallized silicon gives a spectrum with a relatively sharp peak near 520 cm ⁻¹ . For example, as shown in FIG. 19, the spectrum of the microcrystalline silicon film to be measured is each component spectrum, that is, each spectrum of amorphous silicon, grain boundary, or very fine crystalline silicon having a crystal diameter of 5 nm or less, crystallized silicon. Can be expressed as being superimposed at a certain ratio. The crystallinity d (%) can be calculated by obtaining this ratio by a known analysis method. The intensity of the component spectrum of amorphous silicon included in the spectrum of the predetermined microcrystalline silicon film is I _a-Si , the intensity of the component spectrum of very fine crystalline silicon having a grain boundary or a crystal diameter of 5 nm or less is I _uc-Si , When the intensity of the component spectrum of crystallized silicon is I _c-Si , the crystallinity d (%) is calculated by the following formula (1).
d (%) = (Ic _-Si + _Iuc-Si ) / (Ic _-Si + _Iuc-Si + _Ia-Si ) × 100 (1)
The higher the crystallinity d (%), the more crystallized silicon is contained in the semiconductor film 9c. A crystallinity of 20% or more is defined as a microcrystalline silicon layer. The microcrystalline silicon crystallized preferably has a crystallinity of 80% or more, but the surface of such a semiconductor film 9c tends to be uneven as shown in FIG. On the other hand, the lower surface side of the semiconductor film 9c facing the first insulating film 11 forms a relatively flat and smooth interface.
Further, when a silicon film is formed on a metal, if the adhesion between silicon and the metal is poor, the silicon film (semiconductor film 9c) may be peeled off. Therefore, the source electrode 5i (6i) and the drain electrode 5h (6h) It is desirable to use Cr or Cr alloy having good adhesion to silicon on the surface of

Next, as shown in FIG. 11, a semiconductor layer 50 (60) is formed from the semiconductor film 9c by performing dry etching in a state where the area corresponding to the channel layer in the semiconductor film 9c is protected by the photoresist 15.
Next, as shown in FIG. 12, after removing the photoresist 15, the cap layer 14 covering the semiconductor layer 50 (60) is formed on the first insulating film 11. Although the cap layer 14 is not necessarily required, it has an effect of preventing the impurity semiconductor film portion from being exposed to the atmosphere and oxidized during ion doping in a later step. 14 is desirable.

Next, as shown in FIG. 13, a resist film 16 is formed on the cap layer 14 corresponding to the upper side of the gate electrode 5a (6a). For example, the resist film 16 is made of a photosensitive resin and can be formed by backside exposure using the gate electrode 5a (6a) as a mask.
Next, as shown in FIG. 14, the resist film 16 is used as a mask, ion doping is performed on both ends of the semiconductor layer 50 (60), the source electrode 5i (6i) is covered on one end, and the impurity semiconductor film containing the dopant A portion 5g (6g) and an impurity semiconductor film portion 5f (6f) containing a dopant covering the drain electrode 5h (6h) on the other end side are formed. Further, a semiconductor film portion 5b (6b) not containing a dopant is formed between the pair of impurity semiconductor film portions 5g (6g) and 5f (6f).
When the n-type impurity semiconductor film portion is formed by ion doping, phosphine (PH ₃ ) gas or arsine (AsH ₃ ) is generally used as a gas containing phosphorus (P) and arsenic (As) as dopants. By mixing the dopant gas with H ₂ gas and performing an electric discharge decomposition treatment, an ion species containing a dopant of P ⁺ , PH ⁺ or As ⁺ , AsH ⁺ , and an ion species containing only hydrogen such as H ⁺ and H ₂ ⁺ Occurs. By irradiating a target substrate as a large-diameter ion beam without mass separation of these ion species, a dopant is implanted into the semiconductor layer 50 (60) through the cap layer 14 to form an impurity semiconductor film portion. . The dopant irradiated to the portion masked by the resist film 16 does not penetrate the resist film 16 and does not reach the semiconductor layer 50 (60), so that the semiconductor which is the semiconductor layer 50 (60) portion in the masked range is used. The film part 5b (6b) is not doped. In the ion doping, the thickness of the cap layer 14 of the silicon nitride film is 2000 mm, the dose is 1 to 5 × 10 ¹⁶ [atom / cm ² ], the ion energy is 80 to 100 [100 keV], and the dopant gas is 5% with H ₂ gas. Perform in diluted conditions. After the ion doping, an annealing process is performed at 350 ° C. for 1 hour to activate the impurity semiconductor film part and repair defects generated in the impurity semiconductor film part by the ion doping. Note that in the case of forming a p-type impurity semiconductor film portion, ion doping may be performed by appropriately adjusting a dose amount and ion energy using a mixed gas of diborane (B ₂ H ₆ ) gas or the like and H ₂ gas. .

Next, as shown in FIG. 15, after the resist film 16 is peeled off, the second insulating film 12 is formed on the cap layer 14.
In this way, a thin film transistor (a driving transistor 6 and a switch transistor 5) is formed, and a thin film transistor substrate including the driving transistor 6 and the switch transistor 5 is manufactured.

Further, the second insulating film 12 and the cap layer 14 are patterned by photolithography to form an opening 12a in which the central portion of the pixel electrode 8a is exposed (see FIG. 5).
Next, after depositing a photosensitive resin such as polyimide, exposure is performed to form, for example, a lattice-shaped bank 13 having openings 13a through which the pixel electrodes 8a are exposed (see FIG. 5).
Next, a liquid material in which a material for forming the hole injection layer 8b and the light emitting layer 8c is dissolved or dispersed in a solvent is applied to the opening 13a of the bank 13, and the liquid material is dried to form a carrier transport layer. A hole injection layer 8b and a light emitting layer 8c are sequentially formed (see FIG. 5).
Next, the EL device 8 is manufactured by forming the counter electrode 8d on the bank 13 and the light emitting layer 8c over the entire surface (see FIG. 5), and the EL panel 1 is manufactured.

As described above, the semiconductor layers 50 and 60 in the thin film transistor (the driving transistor 6 and the switch transistor 5) are formed on the upper surface of the first insulating film 11 on which the source electrodes 5i and 6i and the drain electrodes 5h and 6h are formed. In the semiconductor layer 50, the current path between the source electrodes 5i, 6i and the drain electrodes 5h, 6h in the thin film transistors 5, 6 faces the interface with the relatively flat first insulating film 11, It is normally formed on the lower surface side of 60. In particular, the laminated structure of the first insulating film 11, the source electrodes 5i and 6i, the drain electrodes 5h and 6h, and the impurity semiconductor films 5f, 6f, 5g, and 6g is not affected by the surface unevenness of the semiconductor layers 50 and 60. The current path is normally formed. Therefore, defects such as conduction failure can be reduced.
As described above, the semiconductor layers 50 and 60 having the semiconductor film portions 5b and 6b in which the channels are formed in the thin film transistors 5 and 6 are formed on the first insulating film 11 covering the substrate 10 on which the gate electrodes 5a and 6a are formed. According to the formation, since the current path is not formed in the film thickness direction but is formed in a straight line in the channel direction, the source electrodes 5i and 6i and the drain electrodes 5h and 6h on the first insulating film 11 are made crystalline. The semiconductor layers 50 and 60 containing conductive silicon can be electrically connected, and the on-current of the thin film transistors 5 and 6 can be improved.

Thus, the EL element 8 including the switch transistor 5 and the drive transistor 6 in which the on-current (Id) of the thin film transistor is stabilized at a suitable value preferably emits light, and the EL panel 1 using the switch transistor 5 and the drive transistor 6 as the drive element. Can display a good image and improve display performance.
The EL panel 1 formed and manufactured as described above is used as a display panel for various electronic devices.
For example, the display panel 1a of the mobile phone 200 shown in FIG. 16, the display panel 1b of the digital camera 300 shown in FIGS. 17A and 17B, or the display panel 1c of the personal computer 400 shown in FIG. The EL panel 1 can be applied.

The application of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.
For example, according to the above-described embodiment, the semiconductor layer 50 covers the source electrode 5i and the drain electrode 5h. However, the semiconductor layer 50 only needs to cover at least a part of the source electrode 5i and at least a part of the drain electrode 5h.

1 EL panel 5 Switch transistor (thin film transistor)
6 Drive transistor (thin film transistor)
5a, 6a Gate electrode 50, 60 Semiconductor layer 5b, 6b Semiconductor film part 5f, 6f Impurity semiconductor film part 5g, 6g Impurity semiconductor film part 5h, 6h Drain electrode 5i, 6i Source electrode 8 EL element 9c Semiconductor film 9h Electrode metal layer DESCRIPTION OF SYMBOLS 10 Substrate 11 First insulating film 12 Second insulating film 13 Bank 14 Cap layer 15 Photoresist 16 Resist film

Claims (7)

A substrate,
A gate electrode formed on the substrate;
On the gate electrode, a source electrode and a drain electrode, which are provided separately from each other so as to sandwich the gate electrode,
A semiconductor layer integrally formed to cover at least a part of the source electrode, at least a part of the drain electrode, and a region between the source electrode and the drain electrode, and containing crystalline silicon;
With
The semiconductor layer has a portion covering at least a part of the source electrode on one end side and a portion covering at least a part of the drain electrode on the other end side, and a pair of impurity semiconductor film portions including a dopant and the pair And a semiconductor film portion formed between the impurity semiconductor film portions.   2. The thin film transistor according to claim 1, wherein the impurity semiconductor film portion on the one end side and the impurity semiconductor film portion on the other end side face each other with the semiconductor film portion above the gate electrode interposed therebetween. substrate.   The thin film transistor substrate according to claim 1, wherein a cap layer is formed so as to cover an upper surface of the semiconductor layer.   The thin film transistor substrate according to any one of claims 1 to 3, further comprising a first electrode, a second electrode, and a light emitting element provided between the first electrode and the second electrode. A source / drain electrode forming step in which a source electrode and a drain electrode are separately formed on a gate electrode formed on a substrate in an arrangement sandwiching the gate electrode;
A semiconductor layer forming step of integrally forming a semiconductor layer containing crystallized silicon so as to cover at least a part of the source electrode, at least a part of the drain electrode, and a region between the source electrode and the drain electrode. When,
Ion doping is performed on both ends of the semiconductor layer, one impurity semiconductor film portion including a dopant covering at least a part of the source electrode on one end side of the semiconductor layer, and the drain on the other end side of the semiconductor layer An ion doping step of forming at least a part of the electrode and forming the other impurity semiconductor film part containing the dopant and forming a semiconductor film part sandwiched between the pair of impurity semiconductor film parts;
A method of manufacturing a thin film transistor substrate, comprising:   In the ion doping step, ion doping is performed in a state where the semiconductor layer portion corresponding to the upper side of the gate electrode is shielded by a resist film, and the semiconductor film portion and a pair of impurities facing each other with the semiconductor film portion interposed therebetween 6. The method of manufacturing a thin film transistor substrate according to claim 5, wherein a semiconductor film portion is formed. After the semiconductor layer forming step, comprising a step of forming a cap layer covering the semiconductor layer,
The method of manufacturing a thin film transistor substrate according to claim 6, wherein the resist film is formed on the cap layer.

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