JP2011014347A - Light-emitting device and method for manufacturing light-emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting device for attaining reduction of leak current and a method for manufacturing the light-emitting device.SOLUTION: The light-emitting device has a carrier transport layer (8b, 8c, 8d) of an EL element 8 in an EL panel 1 and a treatment to irradiate ultraviolet rays on an end part S of the carrier transport layer covering the sidewall 13a of a bank 13 in the EL element 8 is applied to carry out reforming for making the end part S to have high resistance, thereby, the end part S of the carrier transport layer is made to have a higher resistance than the light-emitting region part C of the carrier transport layer and leak current at the end part S of the carrier transport layer is reduced. Further, the light-emitting region part C of the carrier transport layer is made a current passage so that it may flow the current contributing to light emission to the EL element 8.

Description

  The present invention relates to a light emitting device and a method for manufacturing the light emitting device.

Conventionally, in the manufacturing process of an EL element used for an EL (Electro Luminescence) panel, as a step of forming a carrier transport layer, a partition between barrier ribs formed so as to surround a pixel electrode (anode) provided on a glass substrate. A nozzle printing technique is known in which a liquid EL material liquid is poured into a groove through a nozzle and applied (for example, see Patent Document 1).
An EL element is manufactured by providing a counter electrode (cathode) on a carrier transport layer formed by drying the applied EL material liquid and forming a film, and a coating area where the EL material is applied becomes a light emitting area of the EL panel. .

JP 2002-75640 A

However, the EL material liquid applied on the pixel electrodes between the barrier ribs may crawl up the slopes of the barrier ribs due to surface tension or the like, and such “scoop” portions are carriers in the light emitting region on the pixel electrodes. The film may be formed thinner than the transport layer.
When the carrier transport layer portion formed thinner than the light emitting region becomes a low resistance region and becomes a leakage current path between the pixel electrode and the counter electrode, a predetermined current is applied to the light emitting region of the EL element. to not flow, the emission brightness of the EL element may be decreased.

  Thus, an object of the present invention is to reduce the leakage current.

In order to solve the above problems, one aspect of the present invention provides:
Production of a light emitting device comprising: a first electrode formed on an upper surface side of a substrate; a carrier transport layer formed on the first electrode; a second electrode formed on the carrier transport layer; and a partition. In the method
The partition wall is sandwiched between side walls so as to expose the first electrode,
An application step of applying a liquid material in which a material for the carrier transport layer is dissolved or dispersed in a solvent between the side walls of the partition walls;
The carrier formed so as to cover the side wall of the partition wall rather than the carrier transport layer portion formed so as to cover the first electrode with the liquid material applied in the application step. A high resistance treatment process for increasing the resistance of the end of the transport layer;
It is characterized by having.
Preferably, in the high resistance treatment step, at least the carrier transport layer that covers the first electrode is covered with a mask portion, and an end of the carrier transport layer that covers the side wall is irradiated with predetermined light. The resistance of the end is increased.
Preferably, in the high resistance treatment step, the resistance of the end portion of the carrier transport layer formed on the side wall of the partition is increased from the first electrode side.
Then, the light emitting device is manufactured by the method for manufacturing the light emitting device.

Another aspect of the present invention is as follows:
In a light emitting device comprising: a first electrode formed on an upper surface side of a substrate; a carrier transport layer formed on the first electrode; a second electrode formed on the carrier transport layer; and a partition wall.
The partition has side walls sandwiching the first electrode so as to expose the first electrode,
The carrier transport layer is formed by applying a liquid material in which a material to be the carrier transport layer is dissolved or dispersed in a solvent between the sidewalls of the partition wall,
The carrier transport layer that covers the side wall of the partition wall has a higher resistance than the carrier transport layer portion that covers the first electrode.
Preferably, the end portion of the carrier transport layer that climbs on the side wall of the partition wall from the first electrode side and is formed thinner than the first electrode side has a high resistance.
Preferably, the end portion of the carrier transport layer is increased in resistance by being irradiated with ultraviolet rays.

  According to the present invention, leakage current can be reduced.

It is a top view which shows the arrangement configuration of the pixel of an EL panel. It is a top view which shows schematic structure of EL panel. It is a circuit diagram showing a circuit corresponding to one pixel of an EL panel. It is the top view which showed 1 pixel of EL panel. It is arrow sectional drawing of the surface along the VV line of FIG. It is sectional drawing which shows the pixel electrode exposed between the banks of EL panel. It is sectional drawing which shows the carrier transport layer formed into a film on the pixel electrode between the banks of EL panel. It is sectional drawing which shows the process of irradiating predetermined light to the edge part of a carrier transport layer using a mask, and performing a high resistance process. It is a perspective view which shows the mask distribute | arranged on the board | substrate. It is explanatory drawing which shows a box type mask (a), a stripe type mask and (b), and a modification (c) of the stripe type mask. It is the top view (a) which shows EL element for a test, and sectional drawing (b) in the bb line. It is a graph which shows the current density-voltage characteristic which is the verification result in a test EL element. It is a front view which shows an example of the mobile telephone by which EL panel was applied to the display panel. They are the front side perspective view (a) which shows an example of the digital camera with which the EL panel was applied to the display panel, and a rear side perspective view (b). It is a perspective view which shows an example of the personal computer by which EL panel was applied to the display panel.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a plan view showing an arrangement configuration of a plurality of pixels P in an EL panel 1 that is a light emitting device, and FIG. 2 is a plan view showing a schematic configuration of the EL panel 1.

As shown in FIGS. 1 and 2, in the EL panel 1, a plurality of pixels P that respectively emit R (red), G (green), and B (blue) are arranged in a matrix with a predetermined pattern. .
In the EL panel 1, a plurality of scanning lines 2 are arranged so as to be substantially parallel to each other along the row direction, and the plurality of signal lines 3 are arranged along the column direction so as to be substantially orthogonal to the scanning lines 2 in plan view. They are arranged so as to be substantially parallel to each other. A voltage supply line 4 is provided along the scanning line 2 between the adjacent scanning lines 2. A range surrounded by the two signal lines 3 adjacent to the scanning lines 2 and the voltage supply lines 4 corresponds to the pixel P. Here, a plurality of pixels P that emit R (red), a plurality of pixels P that emit G (green), and a plurality of pixels P that emit B (blue), respectively, along the arrangement direction of the signal lines 3. The pixels P are arranged side by side, and are arranged in the order of the pixels P that emit R (red), the pixels P that emit G (green), and the pixels P that emit B (blue) along the arrangement direction of the scanning lines 2. .
Further, the EL panel 1 is provided with a plurality of banks 13 which are partition walls extending in a direction along the signal line 3. Predetermined carrier transport layers (a hole injection layer 8b, an interlayer 8c, and a light emitting layer 8d, which will be described later) are provided in a range sandwiched between the banks 13 and become a light emitting region of the pixel P. That is, the bank 13 partitions the pixel P for each color of R (red), G (green), and B (blue). The carrier transport layer is a layer that transports holes or electrons when a voltage is applied.

  FIG. 3 is a circuit diagram showing a circuit corresponding to one pixel of the EL panel 1 operating in the active matrix driving method.

  As shown in FIG. 3, the EL panel 1 is provided with a scanning line 2, a signal line 3 intersecting with the scanning line 2, and a voltage supply line 4 along the scanning line 2. For each pixel P, a switch transistor 5 that is a thin film transistor, a drive transistor 6 that is a thin film transistor, a capacitor 7, and an EL element 8 are provided.

  In each pixel P, the gate of the switch transistor 5 is connected to the scanning line 2, one of the drain and source of the switch transistor 5 is connected to the signal line 3, and the other of the drain and source of the switch transistor 5 is It is connected to one electrode of the capacitor 7 and the gate of the driving transistor 6. One of the source and drain of the driving transistor 6 is connected to the voltage supply line 4, and the other of the source and drain of the driving transistor 6 is connected to the other electrode of the capacitor 7 and the anode of the EL element 8. Note that the cathodes of the EL elements 8 of all the pixels P are kept at a constant voltage Vcom (for example, grounded).

  Further, in the periphery of the EL panel 1, each scanning line 2 is connected to a scanning driver, each voltage supply line 4 is connected to a constant voltage source or a driver that outputs an appropriate voltage signal, and each signal line 3 is connected to a data driver. The EL panel 1 is driven by these drivers by an active matrix driving method. The voltage supply line 4 is supplied with predetermined power by a constant voltage source or a driver.

  Next, the circuit structure of the EL panel 1 and the pixel P will be described with reference to FIGS. Here, FIG. 4 is a plan view corresponding to one pixel P of the EL panel 1, and FIG. 5 is a cross-sectional view taken along the line VV of FIG. In FIG. 4, electrodes and wiring are mainly shown.

  As shown in FIG. 4, the switch transistor 5 and the drive transistor 6 are arranged along the signal line 3, the capacitor 7 is disposed in the vicinity of the switch transistor 5, and the EL element 8 is disposed in the vicinity of the drive transistor 6. ing. Further, a switch transistor 5, a drive transistor 6, a capacitor 7, and an EL element 8 are disposed between the scanning line 2 and the voltage supply line 4.

As shown in FIG. 5, the drive transistor 6 includes a gate electrode 6a, a semiconductor film 6b, a channel protective film 6d, impurity semiconductor films 6f and 6g, a drain electrode 6h, a source electrode 6i, and the like.
The switch transistor 5 is a thin film transistor similar to the drive transistor 6 described in detail below, and includes a gate electrode 5a, a semiconductor film, a channel protective film, an impurity semiconductor film, a drain electrode 5h, a source electrode 5i, and the like. Details are omitted here.
As shown in FIGS. 4 and 5, an interlayer insulating film 11 serving as a gate insulating film is formed on one surface of the substrate 10, and an interlayer insulating film 12 is formed on the interlayer insulating film 11. ing. The signal line 3 is formed between the interlayer insulating film 11 and the substrate 10, and the scanning line 2 and the voltage supply line 4 are formed between the interlayer insulating film 11 and the interlayer insulating film 12.

The gate electrode 6 a is formed between the substrate 10 and the interlayer insulating film 11. The gate electrode 6a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film. In addition, an insulating interlayer insulating film 11 is formed on the gate electrode 6a, and the gate electrode 6a is covered with the interlayer insulating film 11.
Interlayer insulating film 11 is, for example, made of silicon nitride or silicon oxide. An intrinsic semiconductor film 6b is formed on the interlayer insulating film 11 at a position corresponding to the gate electrode 6a, and the semiconductor film 6b is opposed to the gate electrode 6a with the interlayer insulating film 11 interposed therebetween.
The semiconductor film 6b is made of, for example, amorphous silicon or polycrystalline silicon, and a channel is formed in the semiconductor film 6b. An insulating channel protective film 6d is formed on the central portion of the semiconductor film 6b. The channel protection film 6d, for example, made of silicon nitride or silicon oxide.
An impurity semiconductor film 6f is formed on one end portion of the semiconductor film 6b so as to partially overlap the channel protective film 6d, and the impurity semiconductor film 6g is formed on the other end portion of the semiconductor film 6b. There has been formed so as to overlap a portion the channel protection film 6d. The impurity semiconductor films 6f and 6g are formed on both ends of the semiconductor film 6b so as to be separated from each other. The impurity semiconductor films 6f and 6g are n-type semiconductors, but are not limited thereto, and may be p-type semiconductors.
On the impurity semiconductor film 6f, the drain electrode 6h is formed. A source electrode 6i is formed on the impurity semiconductor film 6g. The drain electrode 6h and the source electrode 6i are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
An insulating interlayer insulating film 12 serving as a protective film is formed on the channel protective film 6d, the drain electrode 6h, and the source electrode 6i, and the channel protective film 6d, the drain electrode 6h, and the source electrode 6i are formed on the interlayer insulating film 12. It is covered by. The drive transistor 6 is covered with an interlayer insulating film 12. The interlayer insulating film 12 is made of, for example, silicon nitride or silicon oxide having a thickness of 100 nm to 200 nm.

  The capacitor 7 is connected between the gate electrode 6a and the source electrode 6i of the drive transistor 6, and as shown in FIG. 4, one electrode 7a is formed between the substrate 10 and the interlayer insulating film 11, The other electrode 7b is formed between the interlayer insulating film 11 and the interlayer insulating film 12, and the electrodes 7a and 7b are opposed to each other with the interlayer insulating film 11 as a dielectric interposed therebetween.

Note that the signal line 3, the electrode 7a of the capacitor 7, the gate electrode 5a of the switch transistor 5, and the gate electrode 6a of the drive transistor 6 are formed by forming a conductive film formed over the substrate 10 by a photolithography method, an etching method, or the like. It is formed at a time by processing.
The scanning line 2, the voltage supply line 4, the electrode 7 b of the capacitor 7, the drain electrode 5 h and source electrode 5 i of the switch transistor 5, and the drain electrode 6 h and source electrode 6 i of the driving transistor 6 are formed on the interlayer insulating film 11. The formed conductive film is formed by shape processing by a photolithography method, an etching method, or the like.

In the interlayer insulating film 11, a contact hole 11a is formed in a region where the gate electrode 5a and the scanning line 2 overlap, and a contact hole 11b is formed in a region where the drain electrode 5h and the signal line 3 overlap, and the gate electrode 6a. A contact hole 11c is formed in a region where the source electrode 5i overlaps, and contact plugs 20a to 20c are embedded in the contact holes 11a to 11c, respectively. The contact plug 20a electrically connects the gate electrode 5a of the switch transistor 5 and the scanning line 2, the contact plug 20b electrically connects the drain electrode 5h of the switch transistor 5 and the signal line 3, and the contact plug 20c electrically connects the switch transistor. 5 source electrode 5i and capacitor 7 electrode 7a are electrically connected, and source electrode 5i of switch transistor 5 and gate electrode 6a of drive transistor 6 are electrically connected. The scanning line 2 may be in direct contact with the gate electrode 5a, the drain electrode 5h may be in contact with the signal line 3, and the source electrode 5i may be in contact with the gate electrode 6a without using the contact plugs 20a to 20c.
The gate electrode 6a of the driving transistor 6 is integrally connected to the electrode 7a of the capacitor 7, the drain electrode 6h of the driving transistor 6 is integrally connected to the voltage supply line 4, and the source electrode 6i of the driving transistor 6 is connected to the capacitor. 7 is integrally connected to the electrode 7b.

The pixel electrode 8 a is provided on the substrate 10 via the interlayer insulating film 11 and is formed independently for each pixel P. The pixel electrode 8a is a transparent electrode, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium − It consists of tin oxide (CTO). The pixel electrode 8a partially overlaps the source electrode 6i of the driving transistor 6, and the pixel electrode 8a and the source electrode 6i are connected.
4 and 5, the interlayer insulating film 12 includes the scanning line 2, the signal line 3, the voltage supply line 4, the switch transistor 5, the driving transistor 6, the peripheral portion of the pixel electrode 8a, and the electrode of the capacitor 7. It is formed to cover the 7b and the interlayer insulating film 11.
An opening 12a is formed in the interlayer insulating film 12 so that the central portion of each pixel electrode 8a is exposed. The interlayer insulating film 12 is formed in a lattice shape in plan view.

As shown in FIGS. 4 and 5, the bank 13 extends in one direction along the signal line 3, and is parallel to the position covering the switch transistor 5 and the drive transistor 6 via the interlayer insulating film 12. It is formed in stripes as viewed.
The side wall 13a of the bank 13 is located inside the opening 12a of the interlayer insulating film 12, and the center side of the pixel electrode 8a is exposed between the opposing side walls 13a.
Then, when the hole 13 forms the hole injection layer 8b, the interlayer 8c, and the light emitting layer 8d, which will be described later, by the wet method, the material for forming the hole injection layer 8b, the interlayer 8c, and the light emitting layer 8d is dissolved in a solvent. It functions as a partition that prevents the dispersed liquid from bleeding into the adjacent pixels P. In addition, between the side walls 13a facing each other in the banks 13 arranged in parallel, a recess 13b is formed, and a liquid material is applied on the pixel electrode 8a in the recess 13b. The recess 13b, similar to the banks 13 extending in one direction.

  As shown in FIGS. 4 and 5, the EL element 8 includes a pixel electrode 8a as a first electrode serving as an anode, a hole injection layer 8b that is a compound film formed on the pixel electrode 8a, and a hole. An interlayer 8c, which is a compound film formed on the injection layer 8b, a light emitting layer 8d, which is a compound film formed on the interlayer 8c, and a second electrode formed on the light emitting layer 8d Counter electrode 8e. The counter electrode 8e is a single electrode common to all the pixels P, and is continuously formed in all the pixels P.

The hole injection layer 8b is a carrier transport layer made of, for example, PEDOT (poly (ethylenedioxy) thiophene) which is a conductive polymer and PSS (polystyrene sulfonate) which is a dopant, This is a layer for injecting holes from the pixel electrode 8a toward the light emitting layer 8c.
The hole injection layer 8b is formed, for example, by applying a liquid material mainly composed of water in which PEDOT and PSS are dispersed and applying it by a wet printing method such as a nozzle printing method, followed by drying. Layer.

The interlayer 8c is an electron transport suppression layer made of, for example, a polyfluorene-based material, and has a function of suppressing movement of electrons from the light emitting layer 8d to the hole injection layer 8b when a forward bias is applied. It is a layer having.
The interlayer 8c is, for example, dried after a liquid material obtained by dissolving an interlayer material in an organic solvent such as tetralin, tetramethylbenzene, and mesitylene is applied by a wet printing method such as a nozzle printing method. This is a layer formed.

The light emitting layer 8d includes a material that emits one of R (red), G (green), and B (blue) for each pixel P, and includes, for example, a carrier transport made of a polyfluorene light emitting material or a polyphenylene vinylene light emitting material. It is a layer that emits light due to recombination of electrons supplied from the counter electrode 8e and holes injected from the hole injection layer 8b side. For this reason, the pixel P that emits R (red), the pixel P that emits G (green), and the pixel P that emits B (blue) have different light emitting materials for the light emitting layer 8d. The R (red), G (green), and B (blue) pattern of the pixel P may be a stripe pattern in which the same color pixels are arranged in the vertical direction, or may be a delta arrangement.
The light emitting layer 8d is formed by, for example, applying a liquid material obtained by dissolving light emitting materials of respective colors in an organic solvent such as tetralin, tetramethylbenzene, and mesitylene by a wet printing method such as a nozzle printing method. It is a layer formed by drying.

The counter electrode 8e is formed of a material having a work function lower than that of the pixel electrode 8a. For example, the counter electrode 8e is formed of a simple substance or an alloy containing at least one of indium, magnesium, calcium, lithium, barium, and a rare earth metal.
The counter electrode 8e is an electrode common to all the pixels P and covers a bank 13 described later together with a compound film such as the light emitting layer 8d.

As described above, the light emitting layer 8 d that is a light emitting portion is partitioned for each pixel P by the interlayer insulating film 12 and the bank 13. In the recess 13b between the side walls 13a of the bank 13 in the opening 12a of the interlayer insulating film 12, a hole injection layer 8b, an interlayer 8c, and a light emitting layer 8d as a carrier transport layer are stacked on the pixel electrode 8a. (See FIG. 5).
Specifically, the sidewall 13 a of the bank 13 provided on the interlayer insulating film 12 is formed inside the opening 12 a of the interlayer insulating film 12.
Then, a liquid material containing a material to be the hole injection layer 8b is applied on the pixel electrode 8a surrounded by the opening 12a and sandwiched between the side walls 13a, and the substrate 10 is heated to dry the liquid material. The compound film thus formed becomes the hole injection layer 8b which is a carrier transport layer.
Further, a liquid material containing a material to be the interlayer 8c is applied onto the hole injection layer 8b surrounded by the opening 12a and sandwiched between the side walls 13a, and the substrate 10 is heated to dry the liquid material. The compound film thus formed serves as an interlayer 8c which is a carrier transport layer.
Further, a liquid material containing a material to be the light emitting layer 8d is applied to the interlayer 8c surrounded by the opening 12a and sandwiched between the side walls 13a, and the substrate 10 is heated to dry the liquid material. The formed compound film becomes the light emitting layer 8d which is a carrier transport layer.
A counter electrode 8e is provided so as to cover the light emitting layer 8d and the bank 13 (see FIG. 5).

In this EL panel 1, the pixel electrode 8a, the substrate 10 and the interlayer insulating film 11 are transparent, and light emitted from the light emitting layer 8d is transmitted through the pixel electrode 8a, the interlayer insulating film 11 and the substrate 10 and emitted. . Therefore, the back surface of the substrate 10 becomes a display surface.
Instead of the substrate 10 side may be a side opposite to the display surface. In this case, the counter electrode 8e is a transparent electrode, the pixel electrode 8a is a reflective electrode, and light emitted from the light emitting layer 8d is transmitted through the counter electrode 8e and emitted.

The EL panel 1 is driven as follows to emit light.
In a state where a predetermined level of voltage is applied to all the voltage supply lines 4, the scanning driver sequentially applies voltages to the scanning lines 2, thereby sequentially selecting the scanning lines 2.
When each scanning line 2 is selected, if a voltage of a level corresponding to the gradation is applied to all the signal lines 3 by the data driver, the switch transistor 5 corresponding to the selected scanning line 2 is turned on. Therefore, a voltage of a level corresponding to the gradation is applied to the gate electrode 6a of the drive transistor 6.
The potential difference between the gate electrode 6a and the source electrode 6i of the drive transistor 6 is determined according to the voltage applied to the gate electrode 6a of the drive transistor 6, and the magnitude of the drain-source current in the drive transistor 6 is determined. , EL element 8 is the drain - emits light with brightness corresponding to source current.
Thereafter, when the selection of the scanning line 2 is released, the switch transistor 5 is turned off, so that the charge according to the voltage applied to the gate electrode 6a of the driving transistor 6 is stored in the capacitor 7 and the driving transistor 6 the potential difference between the gate electrode 6a and the source electrode 6i is maintained.
For this reason, the drive transistor 6 keeps flowing the drain-source current having the same current value as that at the time of selection, and maintains the luminance of the EL element 8.

  Next, a method for manufacturing the EL panel 1 will be described.

A gate metal layer is deposited on the substrate 10 by sputtering and patterned by photolithography to form the signal line 3, the electrode 7a of the capacitor 7, the gate electrode 5a of the switch transistor 5, and the gate electrode 6a of the driving transistor 6. Next, an interlayer insulating film 11 to be a gate insulating film such as silicon nitride is deposited by plasma CVD. A contact hole (not shown) is formed in the interlayer insulating film 11 to open an external connection terminal of each scanning line 2 for connection to a scanning driver located on one side of the EL panel 1.
Next, a semiconductor layer such as amorphous silicon that becomes the semiconductor film 6b (5b) and an insulating layer such as silicon nitride that becomes the channel protective film 6d (5d) are successively deposited, and then the channel protective film 6d (5d) is formed by photolithography. After pattern formation and an impurity layer to be the impurity semiconductor films 6f and 6g (5f and 5g) are deposited, the impurity layer and the semiconductor layer are successively patterned by photolithography to form the impurity semiconductor films 6f and 6g (5f and 5g). Then, the semiconductor film 6b (5b) is formed.
Then, contact holes 11a to 11c are formed by photolithography, and contact plugs 20a to 20c are formed in the contact holes 11a to 11c. This step may be omitted.
Next, the drain electrode 5h and the source electrode 5i of the switch transistor 5 and the source and drain metal layers to be the drain electrode 6h and the source electrode 6i of the driving transistor 6 are deposited and appropriately patterned to obtain the scanning line 2, the voltage supply line 4, An electrode 7b of the capacitor 7, a drain electrode 5h and a source electrode 5i of the switch transistor 5, and a drain electrode 6h and a source electrode 6i of the driving transistor 6 are formed. Thus, the switch transistor 5 and the drive transistor 6 are formed. Thereafter, an ITO film is deposited and then patterned to form the pixel electrode 8a.
Next, an insulating film is formed by vapor deposition so as to cover the switch transistor 5, the driving transistor 6, and the like, and the insulating film is patterned by photolithography, whereby the opening 12a from which the central portion of the pixel electrode 8a is exposed. An interlayer insulating film 12 having the following is formed. Together with the opening 12a, an external connection terminal of the scanning line 2 (not shown), an external connection terminal of each signal line 3 for connecting to a data driver located on one side of the EL panel 1, and an external connection terminal of the voltage supply line 4 are respectively provided. A plurality of contact holes to be opened are formed.
Next, a photosensitive resin such as polyimide is deposited and exposed to form a striped bank 13 on which the side wall 13a is located on the pixel electrode 8a. The bank 13 exposes a contact hole (not shown) that opens the external connection terminal.

Then, as shown in FIG. 6 (FIG. 4), a lattice-shaped interlayer insulating film 12 that opens the plurality of pixel electrodes 8a for each pixel P and a striped bank 13 that sandwiches the pixel electrodes 8a are formed. The electrode 8 a is exposed from the recess 13 b between the side walls 13 a of the striped bank 13 in the opening 12 a of the lattice-like interlayer insulating film 12.
The substrate 10 on which the pixel electrode 8a, the interlayer insulating film 12, the bank 13 and the like are formed is preferably subjected to pure water ultrasonic cleaning. Furthermore, it is preferable to clean the entire substrate surface by O ₂ plasma treatment or UV ozone treatment after the pure water ultrasonic cleaning.

Next, between the banks 13 extending in one direction along the signal line 3, a material that becomes the hole injection layer 8 b, the interlayer 8 c, or the light emitting layer 8 d is used as a solvent in the recess 13 b between the side walls 13 a of the bank 13. By applying a dissolved or dispersed liquid material and drying the liquid material, a hole injection layer 8b, an interlayer 8c, and a light emitting layer 8d, which are carrier transport layers, are formed.
Specifically, application by a nozzle printing method in which a predetermined liquid material is poured out from a nozzle (not shown) that moves relative to a recess 13b that is sandwiched between side walls 13a of the bank 13 and extends in one direction. By performing the process and drying the liquid material to form a compound film, the hole injection layer 8b, the interlayer 8c, and the light emitting layer are formed on the pixel electrode 8a in the recess 13b as shown in FIG. 8d are formed in order.
In addition, after applying the liquid substance used as the positive hole injection layer 8b on the pixel electrode 8a pinched | interposed between the side walls 13a of the bank 13, and drying, the liquid substance used as the interlayer 8c is further applied between the side walls 13a. After being dried, a liquid material that becomes the light emitting layer 8d is further applied between the side walls 13a and dried to form the hole injection layer 8b, the interlayer 8c, and the light emitting layer 8d, as shown in FIG. it is possible to form a carrier transport layer of the three layers comprising the film.

Since each carrier transport layer (hole injection layer 8b, interlayer 8c, light emitting layer 8d) is a layer formed through a step of applying a liquid material to the recess 13b between the side walls 13a of the bank 13, A part of the liquid material applied to 13b scoops up the surface of the side wall 13b of the bank 13 by its surface tension, so that the end S of the carrier transport layer (8b, 8c, 8d) is formed as shown in FIG. The film is formed on the side wall 13a.
In particular, the edge portion S of the carrier transport layer formed on the side wall 13a so as to cover the side wall 13a is an emission region portion C of the carrier transport layer formed so as to cover the pixel electrode 8a. is formed thin than extremely thin portion is also formed.

If the end S of the carrier transport layer (8b, 8c, 8d) thinly formed so as to cover the side wall 13a is interposed between the pixel electrode 8a and the counter electrode 8e, for example, electric field concentration As a result, a leakage current from the pixel electrode 8a toward the counter electrode 8e through the end S of the carrier transport layer may occur. If the end portion S of the carrier transport layer becomes a path for leakage current, a predetermined current will not flow in the light emitting region portion C on the center side of the carrier transport layer, so that the EL element 8 (light emitting layer 8d) This causes a problem that the luminance of light emission is lowered and the image quality of the EL panel 1 is lowered.
For this reason, in the subsequent process of the carrier transport layer deposition process (coating process), a process is performed to make the end S of the carrier transport layer less likely to be a leakage current path. If the end portion S of the carrier transport layer does not serve as a leakage current path, the light emitting region C of the carrier transport layer serves as a current path, and the EL element 8 (light emitting layer 8d) emits light suitably.

Therefore, after the coating process, as shown in FIGS. 8 and 9, a carrier transport layer that covers at least the pixel electrode 8a using a mask 30 in which a plurality of mask portions 32 are provided on a light-transmitting mask plate 31 is used. In the state where the light emitting region portion C is covered with the mask portion 32 and shielded from light, predetermined light is applied to the end S of the carrier transport layer not covered with the mask portion 32 by irradiating predetermined light from the upper surface side of the substrate 10. A high resistance treatment process for increasing the resistance of the end S by applying light is performed to reduce the leakage current.
Specifically, as shown in FIGS. 8 and 9, the mask 30 is within the opening 12 a of the interlayer insulating film 12 in the substrate 10 and between the side walls 13 a of the bank 13. A plurality of mask portions 32 corresponding to the arrangement and size of the pixel electrodes 8a exposed from the surface are provided.
The mask 30 is arranged on the upper surface side of the substrate 10 so that each mask portion 32 corresponds to the light emitting region portion C of the carrier transport layer covering each pixel electrode 8a, and the light emitting region of the carrier transport layer is formed by the mask portion 32. Cover part C.
Then, the end portion S of the carrier transport layer is selected by irradiating the substrate 10 with ultraviolet light, which is predetermined light, through the mask 30 in a state where the light emitting region portion C of the carrier transport layer is covered with the mask portion 32. In particular, the end S of the carrier transport layer is modified by irradiating ultraviolet rays so that the resistance of the end S of the carrier transport layer is higher than that of the light emitting region C of the carrier transport layer.

  In this manner, the light emitting region portion C of the carrier transport layer covering the pixel electrode 8a is covered with the mask portion 32 of the mask 30, and the end portion S of the carrier transport layer covering the side wall 13a of the bank 13 is irradiated with ultraviolet rays. By selectively increasing the resistance of the end portion S of the carrier transport layer, the leakage current at the end portion S of the carrier transport layer can be reduced.

The mask 30 shown in FIG. 9 and FIG. 10A is exposed in the opening 12a of the interlayer insulating film 12 in the substrate 10 and between the side walls 13a of the bank 13, and is arranged in a matrix. Although the box-type mask 30 is provided with a plurality of mask portions 32 corresponding to the pixel electrodes 8a, the shape of the mask is not limited thereto.
For example, a mask 30a shown in FIG. 10B has a shape corresponding to the recess 13b between the side walls 13a of the bank 13, and can cover a plurality of pixel electrodes 8a exposed in the recess 13b. It may be a stripe type mask 30a provided with a plurality of mask portions 32a. Even in this mask 30a, the light emitting region portion C of the carrier transport layer covering each pixel electrode 8a is covered with the mask portion 32a, and ultraviolet rays are applied to the end portion S of the carrier transport layer that rides on the side wall 13a of the bank 13. , it is possible to selectively high resistance to the ends S.
Further, as in the mask 30b shown in FIG. 10C, a plurality of slits 33 corresponding to the boundary portion between the pixel electrode 8a and the side wall 13a are provided along the side wall 13a of the bank 13 on the light-shielding mask plate. The mask 30b may be used. Even in this mask 30b, the light-shielding mask plate is used as a mask portion to cover the light-emitting region portion C of the carrier transport layer that covers each pixel electrode 8a, and the end of the carrier transport layer that rides on the side wall 13a of the bank 13 It is possible to selectively increase the resistance of the end portion S by applying ultraviolet rays to the portion S.

Then, after removing the mask 30 from the upper surface side of the substrate 10, the counter electrode 8e is formed on the entire surface of the bank 13 and the light emitting layer 8d.
By forming the counter electrode 8e in this way, the EL element 8 and the EL panel 1 are manufactured as shown in FIG.

  Next, verification that the resistance of the carrier transport layer is increased by irradiation with ultraviolet rays will be described.

As shown in FIGS. 11A and 11B, the test EL element 80 used in the verification test has a pixel electrode 8a formed on the upper surface of the glass substrate 10, and a 2 mm square on the pixel electrode 8a. bank 13 pixel electrode 8a is exposed from the opening of the are formed.
A carrier transport layer in which a hole injection layer 8b, an interlayer 8c, and a light emitting layer 8d are sequentially formed is formed on the upper surfaces of the pixel electrode 8a and the bank 13, and a counter electrode 8e is formed on the carrier transport layer. A film is formed.
In addition, after forming the bank 13 having an opening on the pixel electrode 8a, the glass substrate 10 is subjected to O ₂ plasma treatment to perform surface cleaning.
Further, the hole injection layer 8b is made of H.264. C. A “BAYTRON (registered trademark) P CH8000” manufactured by Starck was formed by spin coating. The resistivity of the hole injection layer 8b is 100 to 300 [kΩ · cm].
The interlayer 8c and the light emitting layer 8d were formed by applying a liquid material in which each material was dissolved in xylene by a spin coating method. A red light emitting material was used for the light emitting layer 8d.

Then, three kinds of test EL elements 80 having different ultraviolet irradiation treatment conditions applied to the carrier transport layer after applying the light emitting layer 8d are prepared, and the current density-voltage characteristics in the light emitting region of each test EL element 80 are shown. Measured and verified changes in resistance.
In the case of the comparative example in which the ultraviolet irradiation treatment was not performed, after applying the light emitting layer 8d, drying was performed in a nitrogen atmosphere at 140 ° C. for 40 minutes.
In the case of Example 1 in which the ultraviolet irradiation treatment was performed, after the light emitting layer 8d was applied, the carrier transport layer was irradiated with ultraviolet rays for 10 seconds, and then dried at 140 ° C. for 40 minutes in a nitrogen atmosphere.
In the case of Example 2 in which the ultraviolet irradiation treatment was performed, after the light emitting layer 8d was applied, the carrier transport layer was irradiated with ultraviolet rays for 60 seconds and then dried in a nitrogen atmosphere at 140 ° C. for 40 minutes.
In addition, the ultraviolet irradiation (ultraviolet wavelength 365nm) was irradiated from the position 100 mm away with respect to the light emission area | region of the board | substrate 10 using the "handy UV lamp LUV-4" by ASONE Co., Ltd. for the ultraviolet irradiation process. When the intensity of the irradiated ultraviolet rays (integrated irradiation illuminance) was measured, it was 2.25 [mj / cm ² ] in the case of Example 1 (irradiation for 10 seconds), and in the case of Example 2 (irradiation for 60 seconds), 13. It was 47 [mj / cm ² ].

As is clear from the graph of current density-voltage characteristics shown in FIG. 12, the current density in the test EL element 80 is that in which the ultraviolet irradiation process was performed in Example 1, compared with the comparative example in which the ultraviolet irradiation process was not performed. It can be seen that Example 2 is smaller, further, the longer the time of irradiation with ultraviolet rays, the smaller the intensity of the irradiated ultraviolet rays (integrated irradiation illuminance), the smaller, and the higher the resistance.
That is, the end S of the EL element 8 in the EL panel 1 is subjected to a process of irradiating ultraviolet rays so that the end S can be improved in resistance. Then, by increasing the resistance of the end portion S of the carrier transport layer rather than the light emitting region portion C of the carrier transport layer, the leakage current at the end portion S of the carrier transport layer is reduced, and the light emission of the carrier transport layer By using the region portion C as a current path, a current contributing to light emission can be passed through the EL element 8.

As described above, the edge S of the carrier transport layer of the EL element 8 in the EL panel 1, and the end of the carrier transport layer covering the side wall 13 a of the bank 13 so as to ride on the bank 13 of the EL element 8. By performing the process of irradiating the portion S with ultraviolet rays, the end portion S can be increased in resistance.
By increasing the resistance of the end S of the carrier transport layer, the current flowing through the end S can be limited, and the leakage current at the end S of the carrier transport layer can be reduced.
And, by increasing the resistance of the end portion S of the carrier transport layer, it becomes easier for current to flow relatively to the light emitting region C of the carrier transport layer, so that the leakage current at the end portion S of the carrier transport layer can be reduced. In addition, since the light emitting region C of the carrier transport layer can be used as a current path, a current that contributes to light emission can be supplied to the EL element 8.
Therefore, the light emission luminance of the EL element 8 can be improved, and the image quality of the EL panel 1 can be improved.

The EL panel 1 formed and manufactured as described above is used as a display panel for various electronic devices.
For example, the display panel 1a of the mobile phone 200 shown in FIG. 13, the display panel 1b of the digital camera 300 shown in FIGS. 14A and 14B, or the display panel 1c of the personal computer 400 shown in FIG. The EL panel 1 can be applied.

  In the embodiment described above, the ultraviolet light that is the predetermined light is irradiated to improve the resistance of the carrier transport layer. However, the present invention is not limited to this, and the irradiation is performed. As long as the light can be processed to increase the resistance of the carrier transport layer, light having other wavelengths such as visible light may be used.

  In addition, it is needless to say that other specific detailed structures can be appropriately changed.

1 EL panel (light emitting device)
8 EL element 8a Pixel electrode (first electrode)
8b Hole injection layer (carrier transport layer)
8c Interlayer (carrier transport layer)
8d Light emitting layer (carrier transport layer)
8e Counter electrode (second electrode)
10 substrates 13 banks
13a Side wall 13b Recessed part 30, 30a, 30b Mask 31 Mask plate 32, 32a Mask part 33 Slit C Light emitting area part S End part P Pixel

Claims (7)

Production of a light emitting device comprising: a first electrode formed on an upper surface side of a substrate; a carrier transport layer formed on the first electrode; a second electrode formed on the carrier transport layer; and a partition. In the method
The partition wall is sandwiched between side walls so as to expose the first electrode,
An application step of applying a liquid material in which a material for the carrier transport layer is dissolved or dispersed in a solvent between the side walls of the partition walls;
The carrier formed so as to cover the side wall of the partition wall rather than the carrier transport layer portion formed so as to cover the first electrode with the liquid material applied in the application step. A high resistance treatment process for increasing the resistance of the end of the transport layer;
A method for manufacturing a light-emitting device.   The resistance increasing treatment step includes covering at least the carrier transport layer covering the first electrode with a mask portion, and irradiating an end portion of the carrier transport layer covering the side wall with predetermined light, thereby The method of manufacturing a light emitting device according to claim 1, wherein the resistance of the portion is increased.   3. The light emitting device according to claim 1, wherein the resistance increasing treatment step increases resistance of an end portion of the carrier transport layer formed on the side wall of the partition from the first electrode side. 4. Device manufacturing method.   A light-emitting device manufactured by the method for manufacturing a light-emitting device according to claim 1. In a light emitting device comprising: a first electrode formed on an upper surface side of a substrate; a carrier transport layer formed on the first electrode; a second electrode formed on the carrier transport layer; and a partition wall.
The partition has side walls sandwiching the first electrode so as to expose the first electrode,
The carrier transport layer is formed by applying a liquid material in which a material to be the carrier transport layer is dissolved or dispersed in a solvent between the sidewalls of the partition wall,
The light emitting device is characterized in that the resistance of the end portion of the carrier transport layer covering the side wall of the partition wall is higher than that of the carrier transport layer portion covering the first electrode.   6. The end of the carrier transport layer, which climbs on the side wall of the partition wall from the first electrode side and is thinner than the first electrode side, has a high resistance. The light-emitting device of description.   7. The light emitting device according to claim 5, wherein an end portion of the carrier transporting layer has a high resistance by being irradiated with ultraviolet rays.

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