JP2011192920A - Method for manufacturing semiconductor light-emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor light-emitting device in which neither a top-surface platinum layer nor a reverse-surface platinum layer are peeled from a support substrate. <P>SOLUTION: In the method for manufacturing the semiconductor light-emitting device by bonding a light-emitting body formed by laminating a plurality of semiconductor layers on a substrate for growth and a support part including a support substrate made of silicon together through a bonding material such as solder, the top-surface platinum layer and back-surface platinum layer are entirely made into silicides through a heat treatment on the top surface and back surface of the support substrate, respectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device, and more particularly, to a method for manufacturing a semiconductor light emitting device using a technique for bonding a growth substrate and a support substrate using a solder layer.

  Conventionally, a technique of bonding (bonding) a stacked structure in which a plurality of semiconductor layers are stacked on a growth substrate and a support substrate made of a material different from the growth substrate via a bonding material such as solder. A method of manufacturing a semiconductor light emitting device using the same is known. A method for manufacturing a semiconductor light emitting device using a technique for bonding such a laminated structure and a support substrate is disclosed in, for example, Patent Document 1.

  Below, the manufacturing method of the conventional semiconductor light-emitting device is demonstrated. First, a front surface metal layer and a back surface metal layer are formed on the front surface and the back surface of a support substrate made of n-type silicon (Si), respectively. Furthermore, a gold tin (AuSn) layer is laminated on the surface metal layer, and the formation of the support portion is completed. Next, a plurality of semiconductor layers are stacked on the surface of the growth substrate made of gallium arsenide (GaAs). Further, the reflective electrode layer, the diffusion prevention layer, and gold (Au) are sequentially stacked on the stacked semiconductor layers, and the heat treatment is performed, thereby completing the formation of the light emitter. In addition, the heating temperature at the time of formation of a support body part and a light-emitting body part is about 500 degree centigrade (500 degreeC), for example.

  Next, the AuSn layer and the Au layer are brought into close contact with each other, and the support body portion and the light emitting body portion are subjected to heat treatment, whereby the support body portion and the light emitting body portion are joined to form a joined body. Subsequently, the support substrate is removed from the joined body by etching. A metal is formed on the semiconductor layer exposed by the removal, and the surface electrode is formed by performing heat treatment on the metal. In addition, the heating temperature of the process of joining a support body part and a light-emitting body part is about 340 degreeC, for example, and the heating temperature of the process of forming a surface electrode is about 400 degreeC, for example.

  However, the above-described manufacturing method has a problem in that the front surface metal layer and the back surface metal layer are peeled off from the support substrate during the growth substrate removal step and the element extraction step after the processing step into the chip.

JP 2004-270079 A

  The present invention has been made in view of the circumstances as described above, and provides a manufacturing method capable of manufacturing a semiconductor light emitting device in which a front surface metal layer and a back surface metal layer are not peeled off from a support substrate.

  In order to solve the above-described problems, a method for manufacturing a semiconductor light emitting device according to the present invention includes a surface having a surface orientation (111) orientation ratio of 0.98 or more on each of a front surface and a back surface of a support substrate made of silicon. A step of forming a platinum layer and a backside platinum layer, a step of laminating a first bonding metal layer on the front surface platinum layer to form a support portion, and a light emitting operation layer and an electrode layer on the growth substrate And a step of sequentially laminating a second bonding metal layer to form a light emitter portion, and pressing and heating the first bonding metal layer and the second bonding metal layer, and heating the first bonding metal A step of melting the layer and the second bonding metal layer to bond the support body and the light emitting body to form a bonded body, and heating for silicidizing the entire front surface platinum layer and the back surface platinum layer. And a processing step.

  A semiconductor light emitting device is manufactured by bonding a light emitter formed by laminating a plurality of semiconductor layers on a growth substrate and a support including a support substrate made of silicon via a bonding material such as solder. In the manufacturing method to be formed, the entire surface platinum layer and the back surface platinum layer are silicided by heat treatment on the front surface and the back surface of the support substrate, respectively.

  By siliciding the entire front surface platinum layer and back surface platinum layer, there is no easily peeled interface formed between the silicified layer and the platinum-only layer on the front and back surfaces of the support substrate. Peeling of the front surface platinum layer and the rear surface platinum layer on the front surface and the back surface of the support substrate can be prevented.

  In the present invention, since the orientation ratio of the surface orientation (111) of the front surface platinum layer and the back surface platinum layer formed on the front and back surfaces of the support substrate is 0.98 or more, the front surface platinum layer and the back surface are subjected to heat treatment. The platinum layer can be fully silicided.

It is sectional drawing in each manufacturing process of the semiconductor light-emitting device based on the Example of this invention. It is sectional drawing in each manufacturing process of the semiconductor light-emitting device based on the Example of this invention. FIG. 3 is a partially enlarged view of a region 3 surrounded by a broken line in FIG. 2. It is sectional drawing in the manufacturing process of the semiconductor light-emitting device based on the Example of this invention. It is sectional drawing in the manufacturing process of the semiconductor light-emitting device based on the Example of this invention. It is sectional drawing in the manufacturing process of the semiconductor light-emitting device based on the Example of this invention. It is sectional drawing of the semiconductor light-emitting device based on the Example of this invention. 1 is a top view of a semiconductor light emitting device according to an embodiment of the present invention. It is a figure explaining the conditions about the peeling test of a Pt layer. It is a figure explaining the evaluation method of the peeling test of a Pt layer. It is the figure which showed the test result of the peeling test of Pt layer. It is an XRD spectrum obtained by X-ray diffraction in a support substrate and a Pt layer. It is an XRD spectrum obtained by X-ray diffraction in a support substrate and a Pt layer. It is an XRD spectrum obtained by X-ray diffraction in a support substrate and a Pt layer. It is an XRD spectrum obtained by X-ray diffraction in a support substrate and a Pt layer. It is an XRD spectrum obtained by X-ray diffraction in a support substrate and a Pt layer. It is an XRD spectrum obtained by X-ray diffraction in a support substrate and a Pt layer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Manufacturing method and structure of semiconductor light emitting device)
First, the structure of a semiconductor light emitting device that is an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.

  A support substrate 11 made of silicon (Si) to which boron (B) is added is prepared (FIG. 1A). Next, a first platinum (Pt) layer (front surface platinum layer) 12 and a second Pt layer (back surface platinum layer) 13 as metal layers are formed on both surfaces of the support substrate 11 by a vacuum deposition method or a sputtering method under predetermined conditions. Are formed respectively (FIG. 1B). The film thickness of the first and second Pt layers is about 200 nanometers (nm). The predetermined condition will be described later.

  Next, a titanium (Ti) layer 14 is formed on the second Pt layer 13 by electron beam heating vapor deposition. Further, a first Ni layer 15 is formed on the Ti layer 14 by electron beam heating vapor deposition (FIG. 1C). The thickness of the Ti layer 14 is, for example, about 150 nm. The film thickness of the first Ni layer 15 is, for example, about 100 nm. In the present embodiment, the first Ni layer 15 having high wettability with respect to a gold tin (AuSn) solder layer, which will be described later, is formed on the Ti layer 14. For example, a layer made of palladium (Pd) is used. May be formed on the Ti layer 14.

  Next, an AuSn solder layer 16 is formed on the first Ni layer 15 by electron beam heating vapor deposition (FIG. 1D). The composition ratio of Au and Sn in the AuSn solder layer 16 is about 8: 2 by weight and about 7: 3 by atomic ratio. The film thickness of the AuSn solder layer 16 is, for example, about 300 nm. In the present embodiment, a first bonding metal layer is formed from the first Ni layer 15 and the AuSn solder layer 16. By the completion of this step, the formation of the support body 20 is completed.

  The Ti layer 14, the first Ni layer 15, and the AuSn solder layer 16 may be formed by a vapor deposition method such as sputtering, resistance heating vapor deposition, or electron beam vapor deposition.

Next, an n-type gallium arsenide (GaAs) substrate 21 is prepared as a growth substrate (FIG. 2A). Subsequently, it is made of an AlGaInP-based compound semiconductor on the GaAs substrate 21 by MOCVD (Metal Organic Chemical Vapor Deposition), and functions as a light emitting operation layer by laminating a plurality of semiconductor layers. A light emitting operation layer 22 is formed (FIG. 2B). The growth conditions are, for example, a growth temperature of about 700 degrees Celsius (700 ° C.) and a growth pressure of about 10 kilopascals (kPa). Moreover, as a raw material for the organic metal (MO) gas, for example, trimethylgallium (TMGa), trimethylaluminum (TMAl), or trimethylindium (TMI) is used. For example, arsine (AsH ₃ ) and phosphine (PH ₃ ) are used as the group V gas. For example, silane (SiH ₄ ) is used as an n-type impurity and dimethyl zinc (DMZn) is used as a p-type impurity.

  As shown in FIG. 3, a specific structure of the light emitting operation layer 22 includes an n-type cladding layer 22a, an active layer 22b, and a p-type cladding layer 22c. The specific manufacturing process is as follows.

First, an n-type having a composition of (Al _x Ga _1-x ) _y In _1-y P (0 ≦ x ≦ 1, 0 <y ≦ 1) and a Si concentration of about 3.0 × 10 ¹⁷ cm ⁻³ . The clad layer 22 a is formed on the GaAs substrate 21. For example, the composition of the n-type cladding layer 22a is _{(Al 0.7 Ga 0.3) 0.5 In} 0.5 P. Note that the film thickness of the n-type cladding layer 22a is, for example, about 1000 nm.

Next, composition of the active layer 22b of _{(Al x Ga 1-x)} y In 1-y P (0 ≦ x ≦ 1,0 <y <1), is formed on the n-type cladding layer 22a. Here, the values of x and y are set so that the band gap of the active layer 22b is smaller than the band gaps of the n-type cladding layer 22a and the p-type cladding layer 22c. For example, the active layer 22b is the well layer _{(Al 0.15 Ga 0.85) 0.5 In} 0.5 P or _{(Al 0.1 Ga 0.9) 0.5 In} 0.5 P, the barrier layer is _{(Al 0.5 Ga 0.5) 0.5 In} 0.5 P quantum It is a structure having a well. The active layer 22b may have a single structure (bulk structure). Moreover, the film thickness of the active layer 22b is about 200-500 nm, for example. The active layer 22b is not limited to the composition of the present embodiment, and may be, for example, a layer made of InGaP-based crystals not containing aluminum (that is, x = 0). For example, an active layer made of an InGaP-based crystal is In _0.5 Ga _0.5 P.

Next, the composition is (Al _x Ga _1-x ) _y In _1-y P (0 ≦ x ≦ 1, 0 <y ≦ 1), and the concentration of zinc (Zn) is about 5.0 × 10 ¹⁷ cm ^{−. The third} p-type cladding layer 22c is formed on the active layer 22b. For example, the composition of the p-type cladding layer 22c is _{(Al 0.7 Ga 0.3) 0.5 In} 0.5 P. The film thickness of the p-type cladding layer 22c is, for example, about 1000 nm. Through this process, the formation of the light emitting operation layer 22 is completed. The light emitting operation layer 22 may be a simple pn junction layer, a single hetero structure, or a double hetero structure.

  Further, an n-type GaAs buffer layer (not shown) may be formed as a base between the GaAs substrate 21 and the n-type cladding layer 22a. The film thickness of the n-type GaAs buffer layer is, for example, about 200 nm.

  Next, a gold-zinc (AuZn) layer 23 is deposited on the light emitting operation layer 22 as a reflective electrode layer by sputtering (FIG. 2C). The AuZn layer 23 reflects the light generated in the light emitting operation layer 22 to the light extraction surface side. Thereby, the light extraction efficiency of the semiconductor light emitting device can be improved.

  Next, a first tantalum nitride (TaN) layer 24 is formed on the AuZn layer 23 by reactive sputtering. Subsequently, a titanium-tungsten (TiW) layer 25 is formed on the first TaN layer 24 by reactive sputtering. Further, a second TaN layer 26 is formed on the TiW layer 25 by reactive sputtering (FIG. 2D). For example, the thickness of the first TaN layer 24 is about 200 nm, the thickness of the TiW layer 25 is about 100 nm, and the thickness of the second TaN layer 26 is about 100 nm. The first TaN layer 24, the TiW layer 25, and the second TaN layer 26 prevent a bonding member (eutectic material) described later from entering the AuZn layer 23 by diffusion. After the formation of the second TaN layer 26, in order to obtain an ohmic junction between the light emitting operation layer 22 and the AuZn layer 23, a heat treatment is performed at about 500 ° C. in a nitrogen atmosphere.

  Next, a second Ni layer 27 is formed on the second TaN layer 26 by electron beam heating vapor deposition. Further, an Au layer 28 is formed on the second Ni layer 27 by electron beam heating vapor deposition (FIG. 2E). For example, the thickness of the second Ni layer 27 is about 100 nm, and the thickness of the Au layer 28 is about 30 nm. Note that the second Ni layer 27 and the Au layer 28 may be formed by an evaporation method such as sputtering, resistance heating evaporation, or electron beam evaporation. In the present embodiment, a second bonding metal layer is formed from the second Ni layer 27 and the Au layer 28. By the end of this step, the formation of the light emitter 30 is completed.

  Next, with the AuSn solder layer 16 of the support member 20 and the Au layer 28 of the light emitter 30 facing each other, the support member 20 and the light emitter 30 are brought into close contact with each other. Then, the support body 20 and the light emitter 30 that are in close contact are thermocompression-bonded in a nitrogen atmosphere (FIG. 4). The thermocompression bonding conditions are, for example, a pressure of about 1 megapascal (MPa), a temperature of about 320 ° C., and a pressure bonding time of about 10 minutes. By this thermocompression bonding, the AuSn solder layer 16 is melted, and the second Ni layer 27 and the Au layer 28 are dissolved in the melted AuSn solder layer 16. Further, Au and Sn in the AuSn solder layer 16 and Au in the Au layer 28 are diffused and absorbed in the first Ni layer 15 and the second Ni layer 27. Further, the molten AuSn solder layer 16 is solidified to form a bonding layer 51 made of AuSnNi. Thereby, the support body part 20 and the light-emitting body part 30 are joined, and the joined body 60 is formed (FIG. 5). Note that the bonding material (first Ni layer 15, AuSn layer 16, second Ni layer 27, and Au layer 28), bonding atmosphere, bonding temperature, and bonding time are not limited to the above-described conditions. As long as the bonding strength is not deteriorated by oxidation or the like, other conditions that allow the support 20 and the light emitter 30 to be bonded may be used. For example, as the bonding temperature, a temperature at which the AuSn solder layer 16 melts (280 ° C. or more) can be selected as appropriate.

  Next, the GaAs substrate 21 is removed from the joined body 60 by wet etching using a mixed solution of ammonia water and hydrogen peroxide water. By removing the GaAs substrate 21, the surface of the light emitting operation layer 22 is exposed (FIG. 6). The removal of the GaAs substrate 21 may be performed by dry etching, chemical mechanical polishing (CMP), mechanical grinding, or a combination thereof.

  Next, a resist is applied on the light emitting operation layer 22. Patterning is performed so that the applied resist has a desired electrode pattern. Gold / germanium / nickel (AuGeNi) is deposited on the patterned opening of the resist by electron beam heating deposition. Thereafter, AuGeNi having a desired shape is formed by removing the resist (lift-off method). Further, the heat treatment at about 400 ° C. is performed on the AuGeNi and the bonded body 60 in a nitrogen atmosphere. As a result, the AuGeNi and the light emitting operation layer 22 are alloyed, and the external connection electrode 71 in good ohmic contact with the light emitting operation layer 22 is formed. Further, through this step, the entire first Pt layer 12 and the second Pt layer 13 are silicided (alloyed) with the support substrate 11, and the first alloy layer (back alloy layer) 72 and the second Pt layer 13 are formed. Two alloy layers (surface alloy layers) 73 are formed. That is, the first Pt layer 12 and the second Pt layer 13 are completely silicided in the film thickness direction, and the surface alloy layer 73 and the back alloy layer 72 are formed. By completing this process, the semiconductor light emitting device 100 is completed (FIG. 7). The semiconductor light emitting device 100 includes a bonding layer 51 formed above a support substrate 11 made of silicon, an AuZn layer 23 formed on the bonding layer 51, and a light emitting operation layer 22 formed on the AuZn layer 23. And an external connection electrode 71 formed on the light emitting operation layer 22. Further, the semiconductor light emitting device 100 includes a surface platinum silicide layer (surface alloy layer 73) and a back surface platinum silicide layer (back surface) made of an alloy of platinum and silicon formed on the front surface and the back surface of the support substrate 11, respectively. An alloy layer 72) is provided, and there is no layer composed only of platinum adjacent to the front surface alloy layer 73 and the back surface alloy layer 72.

  The shape of the external connection electrode 71 includes, for example, a grid-like linear electrode 71a as shown in FIG. 8 and a circular bonding pad 71b located at the center of the linear electrode. Note that the material of the external connection electrode 71 deposited by the electron beam heating deposition method is not limited to AuGeNi, and may be, for example, AuSnNi, AuSn, AuGe, or the like.

  The above-described manufacturing method is merely an example. For example, after the first Pt layer 12 and the second Pt layer 13 are formed, the entire first Pt layer 12 and the second Pt layer 13 are supported on the support substrate. Heat treatment for alloying (silicidation) may be performed. The bonding process is performed at 280 to 350 ° C. for 5 to 15 minutes, and the electrode alloying process is performed at 360 to 450 ° C. for 1 to 5 minutes. This increases the manufacturing time and damages the semiconductor light emitting device (particularly In view of avoiding damage to the bonding layer).

Hereinafter, it will be described that the first Pt layer 12 and the second Pt layer 13 as a whole are alloyed with the support substrate to prevent peeling on the front and back surfaces of the support substrate. Further, the reason why the entire Pt layer can be silicided with the support substrate by the subsequent heat treatment in manufacturing without performing the heat treatment only for siliciding the Pt layer with the support substrate will be described.
(Evaluation of film thickness of Pt layer by peeling)
Next, referring to FIGS. 9 to 17, good adhesion is obtained between the first and second Pt layers of the semiconductor light emitting device 100 formed by the manufacturing method described above and the support substrate 11, It will be described that the first and second Pt layers are not peeled off from the support substrate 11.

  In order to confirm the peeling of the Pt layer from the support substrate (Si substrate doped with B), a Pt layer having a thickness of 200 nm was formed on the surface of the support substrate under six types of film formation conditions, The substrate is subjected to heat treatment at 320 ° C. for 10 minutes (first heat treatment), and all the support substrates are heated at 400 ° C. for 180 seconds each (second heat treatment) (second heat treatment) (See FIG. 9).

  Here, the six types of film forming conditions include an electron beam evaporation method (hereinafter referred to as EB evaporation method) in a state where the temperature of the support substrate (hereinafter simply referred to as substrate temperature) is 25 ° C., and a substrate temperature of 100. EB deposition method at a temperature of 30 ° C., sputtering method at a substrate temperature of 30 ° C., sputtering method at a substrate temperature of 50 ° C., sputtering method at a substrate temperature of 70 ° C., substrate temperature of 300 ° C. It is a sputtering method in the state made into.

  EB vapor deposition is a method of forming a film by applying an electron beam to a vapor deposition material and heating it to evaporate the material. For this reason, unless the stage holding the support substrate is cooled, the temperature of the support substrate rises to about 100 ° C. due to radiant heat. From the above, EB deposition was performed at a substrate temperature of 25 ° C. by cooling the stage, and EB deposition was performed at a substrate temperature of 100 ° C. by not cooling the stage.

  On the other hand, the sputtering method is a method in which a deposited material is knocked out to form a film by applying Ar particles having energy by plasma discharge to a target (deposited material). For this reason, since the Pt atoms have kinetic energy, there is a slight increase in temperature due to the Ar particles entering the support substrate. However, if the support substrate is not exposed to plasma, a significant increase in the substrate temperature occurs. Absent. That is, in the sputtering method, the temperature of the support substrate is about 30 ° C. without cooling the stage. From the above, sputtering was performed at a substrate temperature of 30 ° C. by not cooling and heating the stage, and sputtering was performed at a substrate temperature of 50 ° C., 70 ° C. or 300 ° C. by heating the stage.

  Further, in the first heat treatment, the heating conditions of the step of bonding the support portion 20 and the light emitter portion 30 in the manufacturing method described above (FIG. 4) are assumed. Furthermore, in the second heat treatment, heating conditions for the ohmic junction between the external connection electrode 71 and the light emitting operation layer 22 in the manufacturing method described above are assumed. Note that the surface of the support substrate on which the Pt layer is formed is mirror-polished. Moreover, the Si substrate whose plane orientation is (100) was used as the support substrate.

  Next, a specific evaluation procedure will be described in detail with reference to FIG. First, six support substrates having a size obtained by dividing a 3 inch wafer into 1/4 were prepared. Subsequently, the natural oxide film of the prepared support substrate was removed. Thereafter, a Pt layer was formed on each of the six support substrates using the film formation conditions described above. That is, six evaluation samples having Pt layers formed according to each film forming condition are formed. In the following, a sample formed by EB vapor deposition with a substrate temperature of 25 ° C. is sample A, a sample formed by EB vapor deposition with a substrate temperature of 100 ° C. is sample B, and formed by a sputtering method with a substrate temperature of 30 ° C. Sample C, sample D formed by sputtering with a substrate temperature of 50 ° C. sample D, sample formed by sputtering with a substrate temperature of 70 ° C. sample E, formed by sputtering with a substrate temperature of 300 ° C. The sample to be processed is designated as sample F.

  After the Pt layer was formed, each sample was subjected to a first heat treatment (320 ° C., 10 minutes) and a second heat treatment (400 ° C., 180 seconds). Then, each sample was affixed on the adhesive sheet so that Pt layer might contact | connect an adhesive sheet. That is, the surface where the Pt layer is not formed is located on the upper side. After each sample was attached to the adhesive sheet, each sample was danced at 0.35 mm square.

  After the dicing, each sample was transferred to another pressure-sensitive adhesive sheet so that the Pt layer was positioned on the upper surface (that is, the other pressure-sensitive adhesive sheet and the surface on which the Pt layer was not formed were bonded). Here, the Pt layer with insufficient silicidation remains on the pressure-sensitive adhesive sheet by the transfer, and the Pt layer with sufficient silicidation is transferred to another pressure-sensitive adhesive sheet together with the support substrate. That is, peeling evaluation of the Pt layer was performed by the transfer.

  FIG. 11 is a table showing the results of the Pt layer peeling evaluation described above. As can be seen from FIG. 11, when the substrate temperature was 70 ° C. or lower, the Pt layer was not peeled off from the support substrate. This indicates that the Pt layer is fully silicided with the support substrate, and good adhesion is obtained between the Pt layer and the support substrate. When the substrate temperature was 100 ° C. or higher, the Pt layer was peeled off from the support substrate. This is probably because the Pt layer was not fully silicided and good adhesion was not obtained between the Pt layer and the support substrate. In FIG. 11, “with peeling (×)” means that a Pt layer (including a layer having a changed Pt layer) peels even in one of 0.35 mm square elements within a quarter-sized support substrate. It is a state of being.

  Next, with reference to FIGS. 12 to 17, the evaluation results of the Pt layer before and after the first and second heat treatments by the X-ray diffraction (XRD) method will be described. 12 shows the sample A, FIG. 13 shows the sample B, FIG. 14 shows the sample C, FIG. 15 shows the sample D, FIG. 16 shows the sample E, and FIG. In each figure, (a) shows the XRD spectrum before the heat treatment, and (b) shows the XRD spectrum after the heat treatment. The vertical axis of each graph is the number of X-ray photons per unit time (cps: counts per second), which is the intensity of X-rays, and the horizontal axis is the diffraction angle of X-rays (2θ degrees). In addition, only the vertical axis | shaft of FIG. 13 is a linear scale, and the vertical axis | shaft of another figure is a log scale.

In sample A, as shown in FIG. 12A, in the state before the heat treatment, the Pt peaks of (111), (200), (220) and the plane orientation are (400) in the state before the heat treatment. ) Si peak was detected. Here, the plane orientation (Si plane orientation) of the support substrate used for the sample is (100), but since the diffraction phenomenon is measured, the surface orientation is observed as a peak of (400) in the XRD spectrum. It was done. This also applies to FIGS. 13 to 17. After the heat treatment, as shown in FIG. 12B, the peak of Pt alone disappeared, and a plurality of peaks of PtSi and Pt ₂ Si were detected instead. From this, it was found that in Sample A, the entire Pt layer formed on the support substrate was silicided by the heat treatment. That is, in sample A, it was shown that the silicide layer on the support substrate does not have an adjacent layer made of only Pt.

In sample B, as shown in FIG. 13 (a), in the state before the heat treatment, the Pt peaks of (111), (200), (220) and the plane orientation are (400) in the state before the heat treatment. ) Si peak was detected. After the heat treatment, as shown in FIG. 13B, the Pt peaks of (200) and (220) disappear, the Pt peak of (111) becomes smaller, and new PtSi and Pt _{A 2} Si peak was detected. However, unlike FIG. 12B, the Pt peak of (111) did not disappear completely. From this, it was found that in Sample B, silicidation of the Pt layer formed on the support substrate proceeded by the heat treatment, but did not progress completely enough to silicidize the entire Pt layer. That is, in sample B, it was shown that a layer made of only Pt is adjacent to the silicide layer on the support substrate.

In sample C, as shown in FIG. 14 (a), in the state before the heat treatment, a peak of Pt having a plane orientation of (111) and a peak of Si having a plane orientation of (400) were detected. It was. After the heat treatment, as shown in FIG. 14B, the Pt peak with the plane orientation of (111) disappeared, and a plurality of PtSi and Pt ₂ Si peaks were detected instead. From this, it was found that also in Sample C, the entire Pt layer formed on the support substrate was silicided by the heat treatment as in Sample A.

In sample D, as shown in FIG. 15 (a), in the state before the heat treatment, a peak of Pt having a plane orientation of (111) and a peak of Si having a plane orientation of (400) were detected. It was. After the heat treatment, as shown in FIG. 15B, the Pt peak with the (111) plane orientation disappeared, and a plurality of PtSi and Pt ₂ Si peaks were detected instead. From this, it was found that also in Sample D, the entire Pt layer formed on the support substrate was silicided by the heat treatment as in Sample A.

In the sample E, as shown in FIG. 16A, in the state before the heat treatment, the peak of Pt with the plane orientation of (111), the peak of Si with the plane orientation of (400), and the PtSi A peak was detected. By detecting the peak of PtSi, it was found that in sample E, a silicide layer was already formed at the interface between the Pt layer and the support substrate at the time of film formation. After the heat treatment, as shown in FIG. 16 (b), the Pt peak with the plane orientation of (111) disappeared, and a plurality of PtSi and Pt ₂ Si peaks were detected instead. From this, it was found that, similarly to the sample A, the entire region of the Pt layer formed on the support substrate was also silicided in the sample E by the heat treatment.

In the sample F, as shown in FIG. 17A, in the state before the heat treatment, the Pt peaks and the plane orientations of (111), (200), and (220) are (400) in the state before the heat treatment. A Si peak and a PtSi peak were detected. Since the peak of PtSi was detected, it was found that a silicide layer was already formed at the interface between the Pt layer and the support substrate in Sample F as in Sample E. After the heat treatment, as shown in FIG. 17B, the Pt peaks with the plane orientations of (200) and (220) become smaller, and new peaks of PtSi and Pt ₂ Si are detected. However, the Pt peak with (111) plane orientation hardly changed. From this, it was found that in sample F, silicidation of the Pt layer formed on the support substrate hardly progressed by the heat treatment.

  From the results of FIG. 11 and the XRD spectra of FIGS. 12 to 17, it was found that the samples P, A, C, D, and E without peeling were silicided with the support substrate as a whole. Furthermore, in the samples B and F where peeling occurred, it was found that the portion peeled from the support substrate was a layer made of only Pt. In view of the above, it is considered that peeling occurring on the front and back surfaces of the support substrate can be prevented by siliciding the entire Pt layer formed on the front and back surfaces of the support substrate with the support substrate.

  Here, the difference between the sample without peeling and the sample with peeling was the substrate temperature when the Pt layer was formed, as shown in FIG. More specifically, it has been found that if a Pt layer is formed by EB vapor deposition or sputtering while the substrate temperature is maintained at 70 ° C. or lower, a Pt layer that is completely silicided by heat treatment can be formed.

  Furthermore, by evaluating the orientation of the Pt layer using the XRD spectrum before the heat treatment, it was possible to derive conditions for the Pt layer to be fully silicided after the heat treatment. This will be described below.

First, in order to evaluate the orientation of the Pt layer, the ratio of the peak intensity of Pt whose plane orientation is (111) to the total X-ray diffraction intensity from each plane orientation (that is, the orientation ratio of Pt (111)) Was calculated. That is, when the orientation ratio of _{Pt (111)} is Or _{Pt (111)} , the definition is as follows.

In this embodiment, since only the Pt peaks with the plane orientations of (111), (200), and (220) are detected, the formula (1) becomes the following formula (2).

By using Equation (2), the orientation ratio of Pt (111) of each sample is 0.98 in sample A, 0.76 in sample B, 1.00 in samples C, D, and E, and 0 in sample F. It was found to be .78. That is, it was found that Samples B and F that were not completely silicided after the heat treatment were shifted in orientation of the Pt layer from the (111) plane to another plane orientation immediately after film formation.

  From the above-described relationship between the substrate temperature during film formation and the orientation of the Pt layer, it was found that the Pt layer can be oriented in the (111) plane by setting the substrate temperature during film formation to 70 ° C. or lower. . This is presumably because when the substrate temperature during film formation is higher than 70 ° C., Pt reacts on the surface of the support substrate, and the orientation of Pt deviates from the (111) plane. Furthermore, it is considered that when the Pt layer is oriented in the (111) plane, Si constituting the support substrate is easily diffused, and the Pt layer is silicided over the entire area.

  From the above, in order to prevent delamination that occurs on the front and back surfaces of the support substrate, it is important to control the substrate temperature during film formation and to control the orientation of the Pt layer before heat treatment. It is done. In this embodiment, in particular, the Pt layer is oriented to the (111) plane by setting the substrate temperature at the time of film formation to 70 ° C. or less, thereby increasing the diffusion of Si during the heat treatment, thereby making the Pt layer completely It was found that the film can be silicided to prevent the peeling.

  From the above results, it can be said that if the first heat treatment and the second heat treatment are performed, the heat treatment for siliciding the entire Pt layer with the supporting substrate is not necessary. That is, if the substrate temperature at the time of film formation is set to 70 ° C. or less, the entire Pt layer can be silicided with the support substrate by the heat treatment at the time of bonding and the heat treatment at the time of forming the external connection electrode 71. . Accordingly, there is an advantage that the heat treatment only for siliciding the Pt layer with the supporting substrate becomes unnecessary, and the manufacturing time of the semiconductor light emitting device itself can be shortened.

  Further, as a result of setting the thickness of the Pt layer of this example to 200 nm, according to the present invention, it is possible to achieve complete silicidation of the Pt layer of at least 200 nm or less. In the semiconductor light emitting device manufactured by the manufacturing method of the present invention, it has been confirmed that no peeling occurs on the front and back surfaces of the support substrate even when the thickness of the Pt layer is 100 nm.

  The plane orientation of the support substrate (that is, the plane orientation of Si) may be other than (100), for example, (111).

  As described above, in the present invention, the light emitter portion 20 formed by laminating a plurality of semiconductor layers on the GaAs substrate 21 and the support portion 20 including the support substrate 11 made of silicon are made of solder or the like. A manufacturing method for forming a semiconductor light emitting device by bonding via a bonding material, wherein the entire first Pt layer 12 and the second Pt layer 13 are formed on the front surface and the back surface of the support substrate 11, respectively. Silicidation occurs by heat treatment.

  By siliciding the entire first Pt layer 12 and second Pt layer 13 as described above, a silicided layer and a layer made of only platinum are formed on the front surface and the back surface of the support substrate 11. The interface that is easy to peel off is eliminated, and peeling of the first Pt layer 12 and the second Pt layer 13 on the front and back surfaces of the support substrate 11 can be prevented.

  In the present invention, since the orientation ratio of the plane orientation (111) of the first Pt layer 12 and the second Pt layer 13 formed on the front and back surfaces of the support substrate is controlled to 0.98 or more, The first Pt layer 12 and the second Pt layer 13 can be completely silicided only by the heat treatment in the subsequent bonding body formation and external electrode formation steps. Furthermore, since the heat treatment performed only for silicidation of the entire first Pt layer 12 and the second Pt layer 13 can be reduced, the manufacturing time and the manufacturing cost of the semiconductor light emitting device can be easily reduced. It comes out.

11 Support substrate 12 First Pt layer (surface platinum layer)
13 Second Pt layer (backside platinum layer)
16 AuSn layer 20 Support portion 21 GaAs substrate 22 Light emitting operation layer 23 AuZn layer 28 Au layer 20 Light emitting portion 60 Joined body 71 External connection electrode 72 First alloy layer (back surface alloy layer)
73 Second alloy layer (surface alloy layer)
100 Semiconductor light emitting device

Claims (5)

Forming a front surface platinum layer and a back surface platinum layer having an orientation ratio of the plane orientation (111) of 0.98 or more on each of the front surface and the back surface of the support substrate made of silicon;
Laminating a first bonding metal layer on the surface platinum layer to form a support portion;
A step of sequentially laminating a light emitting operation layer, an electrode layer, and a second bonding metal layer on a growth substrate to form a light emitter portion;
The first bonding metal layer and the second bonding metal layer are pressure-bonded and heated to melt the first bonding metal layer and the second bonding metal layer, thereby the support body portion and the light emitting body. Joining the parts to form a joined body,
And a heat treatment step of siliciding the entire front surface platinum layer and the back surface platinum layer.   In the step of forming the front surface platinum layer and the back surface platinum layer, the front surface platinum layer and the back surface platinum layer are formed by vacuum evaporation or sputtering while maintaining the temperature of the support substrate at 70 ° C. or lower. The manufacturing method according to claim 1.   The step of removing the growth substrate from the bonded body, and further depositing a metal on the exposed surface of the light emitting operation layer exposed by the removing step and heating to form an external connection electrode, the heating The manufacturing method according to claim 1, wherein the processing step includes a heat treatment at the time of forming the joined body and a heat treatment at the time of forming the external connection electrode.   The manufacturing method according to claim 3, wherein a heating temperature at the time of forming the joined body is 280 to 350 degrees Celsius.   The manufacturing method according to claim 3 or 4, wherein a heating temperature at the time of forming the external connection electrode is 360 to 450 degrees Celsius.

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