JP2011192843A5 - - Google Patents

Claims (9)

An ESD protection N-type MOS transistor having a shallow trench isolation region for element isolation is provided between the external connection terminal and the internal circuit area to protect internal elements formed in the internal circuit area from destruction by ESD. A semiconductor device ,
The drain region and the gate electrode of the N-type MOS transistor overlap with each other only in a partial region in the channel width direction under the overlapping portion of the gate electrode through the gate insulating film, and in the other region in the channel width direction, the gate wherein a being spaced apart via an offset region the channel region under the electrode and said drain region.   2. The semiconductor device according to claim 1, wherein the overlapping portion is formed by overlapping a gate electrode protruding portion in which a part of the drain side of the gate electrode protrudes with the drain region through the gate insulating film.   2. The semiconductor device according to claim 1, wherein the overlapping portion is formed by overlapping a drain region protruding portion in which a part of the drain region on the gate side protrudes with the gate electrode through the gate insulating film. The superposition unit, a semiconductor device according to prior Symbol the shallow trench isolation claim are formed apart from the region 2 or 3 adjacent to the N-type MOS transistor for ESD protection. The gate electrode protrusion pre Symbol plurality installed claims 2 semiconductor device according to the N-type MOS inside transistor for ESD protection. The drain region protrusion front Symbol compared to other drain region of the N-type MOS transistor for ESD protection, thick N-type semiconductor device according to claim 3, wherein are formed by impurity concentration in the region of. The drain region protrusion before Symbol plurality installed claims 3 semiconductor device according to the N-type MOS inside transistor for ESD protection. A gate electrode disposed on the silicon substrate via a gate insulating film and having a gate electrode protrusion on the drain region side;
A source region disposed on the silicon substrate in contact with a channel region below the gate electrode;
A drain region disposed from the surface to the inside of the silicon substrate, which overlaps only through the gate insulating film only at the gate electrode protruding portion and constitutes the overlapping portion of the gate electrode;
An offset region that separates the channel region and the drain region except under the gate electrode protrusion,
A shallow trench isolation region disposed surrounding the source region, the drain region, the channel region and the offset region;
A semiconductor device having an N-type MOS transistor for ESD protection. A gate electrode disposed on a silicon substrate via a gate insulating film;
A source region disposed on the silicon substrate in contact with a channel region below the gate electrode;
A drain region protruding portion that overlaps with the gate electrode through the gate insulating film, and the drain region protruding portion protrudes below the gate electrode to form an overlapping portion on the gate electrode; A drain region disposed from the surface to the inside;
An offset region that separates the channel region and the drain region except under the drain region protrusion,
A shallow trench isolation region disposed surrounding the source region, the drain region, the channel region and the offset region;
A semiconductor device having an N-type MOS transistor for ESD protection.