JP2008103706A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008103706A5 JP2008103706A5 JP2007244092A JP2007244092A JP2008103706A5 JP 2008103706 A5 JP2008103706 A5 JP 2008103706A5 JP 2007244092 A JP2007244092 A JP 2007244092A JP 2007244092 A JP2007244092 A JP 2007244092A JP 2008103706 A5 JP2008103706 A5 JP 2008103706A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- interlayer insulating
- region
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (8)
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた絶縁膜と、
前記絶縁膜上に形成されたチャネル形成領域と、ソース領域又はドレイン領域として機能する不純物領域とを具備する半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の導電膜及び前記ゲート絶縁膜を覆って設けられた第１の層間絶縁膜と、
前記第１の層間絶縁膜上に、少なくとも前記不純物領域の一部と重なり、かつ、前記不純物領域と接しない第２の導電膜と、
前記第２の導電膜及び前記第１の層間絶縁膜の一部上に設けられた第２の層間絶縁膜と、
前記第２の層間絶縁膜上にソース電極又はドレイン電極として機能するとともに、前記第１の層間絶縁膜及び前記第２の層間絶縁膜に設けられた開口部を介して前記不純物領域と電気的に接続された第３の導電膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している前記第１の層間絶縁膜と、
前記第１の層間絶縁膜上に接している前記第２の層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
An insulating film provided on the substrate;
A semiconductor film comprising said insulating film channel forming region formed on, an impurity region functioning as a source region or a drain region,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
A first interlayer insulating film provided to cover the first conductive film and the gate insulating film ;
A second conductive film that overlaps at least a portion of the impurity region and does not contact the impurity region on the first interlayer insulating film;
A second interlayer insulating film provided on a part of the second conductive film and the first interlayer insulating film ;
It functions as a source electrode or a drain electrode on the second interlayer insulating film, and is electrically connected to the impurity region through an opening provided in the first interlayer insulating film and the second interlayer insulating film. A third conductive film connected;
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
The first interlayer insulating film in contact with the gate insulating film;
The second interlayer insulating film in contact with the first interlayer insulating film;
Consisting of
Wherein a is.
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた絶縁膜と、
前記絶縁膜上に形成されたチャネル形成領域と、ソース領域又はドレイン領域として機能する不純物領域とを具備する半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の導電膜及び前記ゲート絶縁膜を覆って設けられた第１の層間絶縁膜と、
前記第１の層間絶縁膜上に、少なくとも前記不純物領域の一部と重なり、かつ、前記不純物領域と接しない第２の導電膜と、
前記第２の導電膜及び前記第１の層間絶縁膜の一部上に設けられた第２の層間絶縁膜と、
前記第２の層間絶縁膜上にソース電極又はドレイン電極として機能するとともに、前記第１の層間絶縁膜、前記第２の層間絶縁膜、及び前記第２の導電膜に設けられた開口部を介して前記不純物領域と電気的に接続された第３の導電膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している前記第１の層間絶縁膜と、
前記第１の層間絶縁膜上に接している前記第２の層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
An insulating film provided on the substrate;
A semiconductor film comprising said insulating film channel forming region formed on, an impurity region functioning as a source region or a drain region,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
A first interlayer insulating film provided to cover the first conductive film and the gate insulating film ;
A second conductive film that overlaps at least a portion of the impurity region and does not contact the impurity region on the first interlayer insulating film;
A second interlayer insulating film provided on a part of the second conductive film and the first interlayer insulating film;
It functions as a source electrode or a drain electrode on the second interlayer insulating film , and through an opening provided in the first interlayer insulating film, the second interlayer insulating film , and the second conductive film. A third conductive film electrically connected to the impurity region;
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
The first interlayer insulating film in contact with the gate insulating film;
The second interlayer insulating film in contact with the first interlayer insulating film;
Consisting of
Wherein a is.
前記第２の導電膜は、少なくとも前記第１の層間絶縁膜を介して前記不純物領域の端部を覆っていることを特徴とする半導体装置。 In any one of Claim 1 or Claim 2 ,
The semiconductor device, wherein the second conductive film covers at least an end portion of the impurity region with the first interlayer insulating film interposed therebetween.
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた絶縁膜と、
前記絶縁膜上に形成されたチャネル形成領域と、ソース領域又はドレイン領域として機能する第１の不純物領域と、ＬＤＤ領域として機能する第２の不純物領域とを具備する半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の不純物領域の上方に前記ゲート絶縁膜と接して設けられているとともに、前記第１導電膜と同一材料で形成された第２の導電膜と、
前記第１の導電膜及び前記第２の導電膜を覆って設けられた層間絶縁膜と、
前記層間絶縁膜上にソース電極又はドレイン電極として機能するとともに、前記層間絶縁膜に設けられた開口部を介して前記第１の不純物領域と電気的に接続された第３の導電膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
An insulating film provided on the substrate;
A channel forming region formed on the insulating film, a first impurity region functioning as a source region or a drain region, a semiconductor film and a second impurity regions which function as LDD regions,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
A second conductive film provided above and in contact with the gate insulating film above the first impurity region and formed of the same material as the first conductive film;
An interlayer insulating film provided to cover the first conductive film and the second conductive film;
A third conductive film functioning as a source electrode or a drain electrode on the interlayer insulating film and electrically connected to the first impurity region through an opening provided in the interlayer insulating film;
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
An interlayer insulating film in contact with the gate insulating film;
Consisting of
Wherein a is.
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた絶縁膜と、
前記絶縁膜上に形成されたチャネル形成領域と、ソース領域又はドレイン領域として機能する第１の不純物領域と、ＬＤＤ領域として機能する第２の不純物領域とを具備する半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の不純物領域の上方に前記ゲート絶縁膜と接して設けられているとともに、前記第１の導電膜と同一材料で形成された第２の導電膜と、
前記第１の導電膜及び前記第２の導電膜を覆って設けられた層間絶縁膜と、
前記層間絶縁膜上にソース電極又はドレイン電極として機能するとともに、前記層間絶縁膜、第２の導電膜、および前記ゲート絶縁膜に設けられた開口部を介して前記第１の不純物領域と電気的に接続された第３の導電膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
An insulating film provided on the substrate;
A channel forming region formed on the insulating film, a first impurity region functioning as a source region or a drain region, a semiconductor film and a second impurity regions which function as LDD regions,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
Together is provided in contact with the gate insulating film above the first impurity region, a second conductive film formed by the same material as the first conductive film,
An interlayer insulating film provided to cover the first conductive film and the second conductive film;
It functions as a source electrode or a drain electrode on the interlayer insulating film, and is electrically connected to the first impurity region through an opening provided in the interlayer insulating film, the second conductive film, and the gate insulating film. A third conductive film connected to
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
An interlayer insulating film in contact with the gate insulating film;
Consisting of
Wherein a is.
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた島状の保護膜と、
前記保護膜と一部が重なるように絶縁膜を介して、チャネル形成領域と、ソース領域又はドレイン領域として機能する不純物領域とを具備する半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の導電膜及び前記ゲート絶縁膜を覆って設けられた第１の層間絶縁膜と、
前記第１の層間絶縁膜上に、少なくとも前記不純物領域の一部と重なり、かつ、前記不純物領域と接しない第２の導電膜と、
前記第２の導電膜及び前記第１の層間絶縁膜の一部上に設けられた第２の層間絶縁膜と、
前記第２の層間絶縁膜上にソース電極又はドレイン電極として機能するとともに、前記第１の層間絶縁膜、前記第２の層間絶縁膜、及び前記第２の導電膜に設けられた開口部を介して前記不純物領域と電気的に接続された第３の導電膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している前記第１の層間絶縁膜と、
前記第１の層間絶縁膜上に接している前記第２の層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
And island-shaped protective film provided on the substrate,
Via an insulating film so that the protective film to partially overlap, and a semiconductor film comprising a channel forming region and impurity regions serving as source and drain regions,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
A first interlayer insulating film provided to cover the first conductive film and the gate insulating film ;
A second conductive film that overlaps at least a portion of the impurity region and does not contact the impurity region on the first interlayer insulating film;
A second interlayer insulating film provided on a part of the second conductive film and the first interlayer insulating film;
It functions as a source electrode or a drain electrode on the second interlayer insulating film , and through an opening provided in the first interlayer insulating film, the second interlayer insulating film , and the second conductive film. A third conductive film electrically connected to the impurity region;
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
The first interlayer insulating film in contact with the gate insulating film;
The second interlayer insulating film in contact with the first interlayer insulating film;
Consisting of
Wherein a is.
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた島状の保護膜と、
前記基板及び保護膜上に形成された絶縁膜と、
前記絶縁膜上に、チャネル形成領域と、ソース領域又はドレイン領域として機能する不純物領域とを具備するとともに、前記保護膜によって囲まれている半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の導電膜及び前記ゲート絶縁膜を覆って設けられた第１の層間絶縁膜と、
前記第１の層間絶縁膜上に、ソース電極又はドレイン電極として機能するとともに、前記層間絶縁膜に設けられた開口部を介して前記不純物領域と電気的に接続する第２の導電膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している前記第１の層間絶縁膜と、
前記第１の層間絶縁膜上に接している前記第２の層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
And island-shaped protective film provided on the substrate,
An insulating film formed on the substrate and the protective film;
On the insulating film, a channel forming region, as well as and a impurity region functioning as a source region or a drain region, and a semiconductor film are surrounded by the protective film,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
A first interlayer insulating film provided to cover the first conductive film and the gate insulating film ;
A second conductive film which functions as a source electrode or a drain electrode on the first interlayer insulating film and is electrically connected to the impurity region through an opening provided in the interlayer insulating film ;
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
The first interlayer insulating film in contact with the gate insulating film;
The second interlayer insulating film in contact with the first interlayer insulating film;
Consisting of
Wherein a is.
前記第１の薄膜トランジスタと第２の薄膜トランジスタは、
前記基板上に設けられた絶縁膜と、
前記絶縁膜上に、チャネル形成領域と、ソース領域又はドレイン領域として機能する不純物領域とを具備する半導体膜と、
前記半導体膜上に形成されたゲート絶縁膜と、
前記チャネル形成領域の上方に前記ゲート絶縁膜を介してゲート電極として機能する第１の導電膜と、
前記第１の導電膜を覆って設けられた前記第１の導電膜及び前記ゲート絶縁膜を覆って設けられた第１の層間絶縁膜と、
前記第１の層間絶縁膜上に、少なくとも前記不純物領域の一部と重なり、かつ、前記不純物領域と接しない第２の導電膜と、
前記第２の導電膜及び前記第１の層間絶縁膜の一部上に設けられた第２の層間絶縁膜と、
前記第２の導電膜上に設けられた第２の層間絶縁膜上にソース電極又はドレイン電極として機能するとともに、前記第１の層間絶縁膜、前記第２の層間絶縁膜、及び前記第２の導電膜に設けられた開口部を介して前記不純物領域と電気的に接続された第３の導電膜と、
前記第３の導電膜を覆って設けられた第３の層間絶縁膜上に形成された島状の保護膜と、
からそれぞれ構成され、
前記第１の薄膜トランジスタと前記第２の薄膜トランジスタの間の領域は、
前記絶縁膜上に接している前記ゲート絶縁膜と、
前記ゲート絶縁膜上に接している前記第１の層間絶縁膜と、
前記第１の層間絶縁膜上に接している前記第２の層間絶縁膜と、
から構成され、
ていることを特徴とする半導体装置。 In a semiconductor device in which a first thin film transistor and a second thin film transistor are provided over a substrate ,
The first thin film transistor and the second thin film transistor are:
An insulating film provided on the substrate,
On the insulating film, a semiconductor film comprising a channel forming region and impurity regions serving as source and drain regions,
A gate insulating film formed on the semiconductor film;
A first conductive film serving as a gate electrode through the gate insulating film above the channel formation region,
A first interlayer insulating film provided to cover the first conductive film and the gate insulating film provided to cover the first conductive film;
A second conductive film that overlaps at least a portion of the impurity region and does not contact the impurity region on the first interlayer insulating film;
A second interlayer insulating film provided on a part of the second conductive film and the first interlayer insulating film;
The first interlayer insulating film, the second interlayer insulating film, and the second interlayer insulating film function as a source electrode or a drain electrode on the second interlayer insulating film provided on the second conductive film. A third conductive film electrically connected to the impurity region through an opening provided in the conductive film ;
An island-shaped protective film formed on a third interlayer insulating film provided to cover the third conductive film;
Each consists of
The region between the first thin film transistor and the second thin film transistor is:
The gate insulating film in contact with the insulating film;
The first interlayer insulating film in contact with the gate insulating film;
The second interlayer insulating film in contact with the first interlayer insulating film;
Consisting of
Wherein a is.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007244092A JP5350616B2 (en) | 2006-09-22 | 2007-09-20 | Semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006256902 | 2006-09-22 | ||
| JP2006256902 | 2006-09-22 | ||
| JP2007244092A JP5350616B2 (en) | 2006-09-22 | 2007-09-20 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008103706A JP2008103706A (en) | 2008-05-01 |
| JP2008103706A5 true JP2008103706A5 (en) | 2010-10-28 |
| JP5350616B2 JP5350616B2 (en) | 2013-11-27 |
Family
ID=39437761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007244092A Expired - Fee Related JP5350616B2 (en) | 2006-09-22 | 2007-09-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5350616B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010035627A1 (en) * | 2008-09-25 | 2010-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2011029610A (en) * | 2009-06-26 | 2011-02-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device, and method for manufacturing the same |
| US9287405B2 (en) * | 2011-10-13 | 2016-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising oxide semiconductor |
| CN107134496B (en) * | 2016-02-29 | 2019-05-31 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor (TFT) and its manufacturing method, display panel and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5019677B2 (en) * | 2001-06-25 | 2012-09-05 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| JP4233307B2 (en) * | 2002-11-05 | 2009-03-04 | シャープ株式会社 | Active matrix substrate and display device |
| JP5046529B2 (en) * | 2005-02-25 | 2012-10-10 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
2007
- 2007-09-20 JP JP2007244092A patent/JP5350616B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2020167423A5 (en) | ||
| JP2021114625A5 (en) | ||
| JP2022050650A5 (en) | ||
| JP2022160439A5 (en) | ||
| JP2020109866A5 (en) | ||
| JP2022043102A5 (en) | ||
| JP2017005277A5 (en) | ||
| JP2020194966A5 (en) | ||
| JP2009290189A5 (en) | ||
| JP2013042121A5 (en) | ||
| JP2017175129A5 (en) | Semiconductor device | |
| JP2010263195A5 (en) | ||
| JP2013214729A5 (en) | ||
| JP2013179295A5 (en) | ||
| JP2011049540A5 (en) | ||
| JP2011151383A5 (en) | ||
| JP2011071503A5 (en) | Semiconductor device | |
| JP2010251735A5 (en) | Semiconductor device | |
| JP2011181917A5 (en) | ||
| JP2010153828A5 (en) | Semiconductor device | |
| JP2009170900A5 (en) | Semiconductor device and display device having the same | |
| JP2011077503A5 (en) | ||
| JP2013165132A5 (en) | ||
| JP2006343755A5 (en) | ||
| JP2012080092A5 (en) |