JP2011192815A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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Abstract
Description
本発明は、半導体素子及びその製造方法に関し、特に、電極に半田バンプを形成する半導体素子及びその製造方法に関する。
The present invention relates to a semiconductor element and a manufacturing method thereof, and more particularly to a semiconductor element in which solder bumps are formed on electrodes and a manufacturing method thereof.
通常、半導体素子の実装において、半導体素子を裏返して回路基板に接合する実装方法であるフリップチップが使われている。これはシリコン基板からなるウエハの一方の平面に多数の電極を配設し、電極に半田バンプを形成する。その後、所定の素子寸法に切断（ダイシング）することで、フリップチップを得ることができる。
Usually, in the mounting of a semiconductor element, a flip chip, which is a mounting method in which the semiconductor element is turned over and bonded to a circuit board, is used. In this method, a large number of electrodes are arranged on one plane of a wafer made of a silicon substrate, and solder bumps are formed on the electrodes. Then, a flip chip can be obtained by cutting (dicing) into predetermined element dimensions.
半田バンプの製造方法は一般的に、図４に示すように（ａ）ウエハ１２に電極１３を形成する。（ｂ）フラックスマスク１６を使用し、電極３上にフラックス１８を塗布する。（ｃ）ボール搭載マスク１７を使って、フラックス１８が塗布された電極３上に半田ボール１９を搭載する。（ｄ）その後、リフロー加熱し半田を溶融させ、冷却することにより固体となり、球状から半球状に近い形状の半田バンプ１５が得られる。半田ボール搭載においては、多数の半田ボールを同時のせる装置がある。
In general, the solder bumps are manufactured by (a) forming electrodes 13 on the wafer 12 as shown in FIG. (B) A flux mask 16 is used and a flux 18 is applied on the electrode 3. (C) Using the ball mounting mask 17, the solder ball 19 is mounted on the electrode 3 to which the flux 18 is applied. (D) Thereafter, reflow heating is performed to melt the solder and cooling to obtain a solid, thereby obtaining the solder bump 15 having a shape close to a hemisphere from a spherical shape. In solder ball mounting, there is a device that allows a large number of solder balls to be placed simultaneously.
半田ボールと電極の接合において、クラック等を発生させない外部電極構造の半導体素子が従来技術として知られている（例えば、特許文献１参照）。これは、図３に示すカバー層１４と電極１３を工夫している。また、半田ボールの搭載には半田ボールを所定の配列に並べる配列用マスクと半田ボールを電極（パッド）上に供給する供給マスクを有する半田ボール搭載装置が従来技術として知られている（例えば、特許文献２参照）。
A semiconductor element having an external electrode structure that does not generate cracks or the like in joining of solder balls and electrodes is known as a conventional technique (see, for example, Patent Document 1). This devises the cover layer 14 and the electrode 13 shown in FIG. For mounting solder balls, a solder ball mounting apparatus having an arrangement mask for arranging solder balls in a predetermined arrangement and a supply mask for supplying the solder balls onto electrodes (pads) is known as a prior art (for example, Patent Document 2).
しかしながら、従来技術は、半田ボールを用いた半導体素子の半田バンプは、突出部分が大きいため外部衝撃に弱く、また、高さもあるため、実装時の半田バンプが溶融する際に、傾きずれてしまうという課題がある。また、半田ボール搭載装置の半田ボール整列では、電極と同じピッチの孔の空いた複数のマスク板を用意しなければならなく、ウエハタイプが変更になった場合にはそれぞれのマスク（治工具）を準備する必要があり、効率が悪いという課題がある。
However, according to the prior art, the solder bump of the semiconductor element using the solder ball is weak against external impact because of the large protruding portion, and also has a height, and therefore, when the solder bump at the time of mounting is melted, the solder bump is displaced. There is a problem. Also, in order to align the solder balls of the solder ball mounting device, it is necessary to prepare a plurality of mask plates with holes with the same pitch as the electrodes. If the wafer type is changed, each mask (tool) There is a problem that efficiency is poor.
従って、本発明は、電極に半田バンプを形成する半導体素子において、半田バンプの強度を向上させ、半田ボールを容易に搭載させる機能を有する半導体素子とその製造方法を提供することを目的とする。
Accordingly, an object of the present invention is to provide a semiconductor element having a function of improving the strength of a solder bump and easily mounting a solder ball in a semiconductor element in which a solder bump is formed on an electrode, and a manufacturing method thereof.
上記の課題を解決するために、本発明は、以下に掲げる構成とした。
本発明の半導体素子は、ウエハ上の電極に半田バンプを形成する半導体素子において、電子回路が形成されているウエハと、電子回路の入出力端子となる電極と、ウエハの表面を覆い保護する保護膜と、保護膜において電極上部に開孔された開孔部と、開孔部に半田が充填され、保護膜表面から突出部が形成されている半田バンプと、を備えることを特徴とする。
また、半田は、半田ボールであることを特徴とする。
また、保護膜層は、感光性ポリイミド樹脂であることを特徴とする。
また、本発明の製造方法は、ウエハに電極を形成する工程と、ウエハの表面に保護膜を形成する工程と、保護膜において電極上部を開孔する工程と、開孔部に半田を搭載する工程と、半田を溶融させ保護膜表面から突出部を形成する工程と、を備えることを特徴とする。
In order to solve the above-described problems, the present invention is configured as follows.
The semiconductor device of the present invention is a semiconductor device in which solder bumps are formed on electrodes on a wafer, a wafer on which an electronic circuit is formed, electrodes serving as input / output terminals of the electronic circuit, and protection for covering and protecting the surface of the wafer. And a solder bump in which a hole is opened in the upper part of the electrode in the protective film, and a solder bump is filled in the hole and a protrusion is formed from the surface of the protective film.
The solder is a solder ball.
The protective film layer is a photosensitive polyimide resin.
The manufacturing method of the present invention includes a step of forming an electrode on a wafer, a step of forming a protective film on the surface of the wafer, a step of opening an upper portion of the electrode in the protective film, and mounting solder in the opening portion. And a step of melting the solder and forming a protrusion from the surface of the protective film.
本発明は、電極に半田バンプを形成する半導体素子において、外部衝撃に強く、実装時に傾かない半田バンプである半導体素子を提供することができる効果を奏する。また、半田ボール整列において、マスクを準備する必要のない半導体素子の製造方法を提供することができる効果を奏する。
INDUSTRIAL APPLICABILITY The present invention provides an effect of providing a semiconductor element that is a solder bump that is resistant to external impact and does not tilt during mounting in a semiconductor element in which solder bumps are formed on electrodes. In addition, it is possible to provide a method for manufacturing a semiconductor device that does not require a mask in solder ball alignment.
以下、本発明の実施の形態について、詳細に説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号で表している。但し、図面は模式的なものであり、寸法関係の比率等は現実のものとは異なる。したがって、具体的な寸法等は以下の説明を照らし合わせて判断するべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。
Hereinafter, embodiments of the present invention will be described in detail. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the dimensional relationship ratios and the like are different from the actual ones. Therefore, specific dimensions and the like should be determined in light of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
図１に示すように、本発明の半導体素子１は、ウエハ２の一方の平面上に電極３と、保護膜４と、半田バンプ５を形成した構成になっている。
As shown in FIG. 1, the semiconductor element 1 of the present invention has a configuration in which an electrode 3, a protective film 4, and solder bumps 5 are formed on one plane of a wafer 2.
ウエハ２は、シリコン基板からなり、一方の面（図の上側）に回路配線された導電層（図示省略）があり、表面に外部出力として電極３が形成されている。電極３は電極パッドとも呼ばれ、ニッケル等の金属めっき法により製造できる。例えば、ウエハ２の厚さは０．１ｍｍ、電極３の厚さは０．１ｍｍ、サイズは０．２ｍｍ角である。
The wafer 2 is made of a silicon substrate, has a conductive layer (not shown) wired on one surface (upper side in the figure), and an electrode 3 is formed on the surface as an external output. The electrode 3 is also called an electrode pad and can be manufactured by a metal plating method such as nickel. For example, the thickness of the wafer 2 is 0.1 mm, the thickness of the electrode 3 is 0.1 mm, and the size is 0.2 mm square.
保護膜４は、ウエハ表面保護として、ウエハ２の一方の面（図面の上側）の全面を覆っており、電極３の上部に開孔を形成する。例えば、保護膜４は樹脂からなり、感光性ポリイミド樹脂を使用し、塗布法により製造することができる。厚さは０．１７ｍｍである。
The protective film 4 covers the entire surface of one surface (upper side of the drawing) of the wafer 2 as a wafer surface protection, and forms an opening above the electrode 3. For example, the protective film 4 is made of a resin and can be manufactured by a coating method using a photosensitive polyimide resin. The thickness is 0.17 mm.
開孔は保護膜４を露光除去し、電極３上面を露出させる。図２（ｃ）参照。
The opening exposes and removes the protective film 4 to expose the upper surface of the electrode 3. Refer to FIG.
半田バンプ５は、半田ボール搭載法によって製造され、電極３の上面と半田接合されており、保護膜４の厚さよりも上面（外側）に突出した半球形状である。例えば、突出高さは０．１ｍｍであり、半田ボールのサイズは０．２ｍｍ径を用いることができる。
The solder bumps 5 are manufactured by a solder ball mounting method, are soldered to the upper surface of the electrode 3, and have a hemispherical shape protruding to the upper surface (outside) than the thickness of the protective film 4. For example, the protrusion height is 0.1 mm, and the solder ball size can be 0.2 mm.
次に、図２に示すように、本発明の半導体素子１の製造方法を説明する。
（ａ）ウエハ２の一方の面に金属面を形成し、めっき開孔マスク（図示せず）を使って電極３をパターン形成する。ウエハ電極において一般的に行われる方法である。
Next, as shown in FIG. 2, a method for manufacturing the semiconductor element 1 of the present invention will be described.
(A) A metal surface is formed on one surface of the wafer 2, and the electrode 3 is patterned using a plating hole mask (not shown). This is a method generally performed in a wafer electrode.
（ｂ）ウエハ２の電極３が形成された面の全面に保護膜４を塗布し乾燥硬化させ形成する。例えば、保護膜４はポリイミド樹脂を塗布する。
(B) A protective film 4 is applied to the entire surface of the wafer 2 on which the electrodes 3 are formed, and is dried and cured. For example, the protective film 4 is applied with a polyimide resin.
（ｃ）ウエハ２に塗布された保護膜４の上面に電極３を形成したときに使用した開孔マスク６を用いて、露光をおこない、電極３の上部の保護膜４を除去し、電極３が露出する。この時、電極３と同じマスクであるので、電極３と同寸法の開孔部７となる。好ましくは、オーバー露光をさせ、開孔部７の底面は電極３面積より大きくする。
(C) Exposure is performed using the aperture mask 6 used when the electrode 3 is formed on the upper surface of the protective film 4 applied to the wafer 2, and the protective film 4 on the upper side of the electrode 3 is removed. Is exposed. At this time, since the mask is the same as the electrode 3, the opening portion 7 has the same dimensions as the electrode 3. Preferably, overexposure is performed, and the bottom surface of the opening 7 is larger than the area of the electrode 3.
（ｄ）電極３の上部において、保護膜４を除去し開孔した後、フラックス８を保護膜４と開孔され露出した電極３の全面に塗布をする。全面に塗布するので、マスクは必要ない。例えば、フラックス８は水溶性で、粘着性がないものを使用する。
(D) At the upper part of the electrode 3, the protective film 4 is removed and opened, and then the flux 8 is applied to the entire surface of the electrode 3 exposed through the protective film 4. Since it is applied to the entire surface, no mask is required. For example, the flux 8 is water-soluble and not sticky.
（ｅ）フラックス８が乾燥硬化された後、半田ボール９を開孔部７に振り込む。この時、ウエハ２上の特定位置に半田ボール９を載せ、外周を囲んだ治工具（図示なし）で、弧を描き転がすように振り込み動作させ、半田ボール９を開孔部７に入れる。開孔部７に直接振り込むので、マスクは必要ない。開孔深さは半田ボール９直径の１／３以上の深さがあり、開孔寸法は電極３と同寸法かやや大きくなるため、電極３と同寸法に半田ボール９を使用すれば、振り込みによって、半田ボール９をひとつだけ挿入することができる。また、フラックス８は粘着性がないので、保護膜４上や半田ボール９同士が接着することがない。開孔７に入らなかった余分な半田ボール９はウエハ２をやや傾け、はけで払えば良い。開孔部７に入った半田ボール９は十分な深さがあるので、飛び出す事はない。
(E) After the flux 8 is dried and hardened, the solder ball 9 is swung into the opening 7. At this time, the solder ball 9 is placed at a specific position on the wafer 2, and a soldering tool (not shown) surrounding the outer periphery is moved to draw an arc and roll, and the solder ball 9 is put into the opening 7. Since it is directly transferred to the opening 7, no mask is required. Since the opening depth is more than 1/3 of the diameter of the solder ball 9 and the opening size is the same as or slightly larger than that of the electrode 3, if the solder ball 9 is used to the same size as the electrode 3, transfer is performed. Thus, only one solder ball 9 can be inserted. Further, since the flux 8 is not sticky, the protective film 4 and the solder balls 9 do not adhere to each other. The extra solder balls 9 that have not entered the openings 7 may be removed by slightly tilting the wafer 2 and brushing. Since the solder ball 9 entering the opening 7 has a sufficient depth, it does not jump out.
（ｆ）開孔部７に半田ボール９が搭載された状態で、リフロー加熱装置等で半田を溶融させ、冷却後、溶融した半田が半田塊となり半田バンプ５が得られる。
(F) With the solder ball 9 mounted on the opening 7, the solder is melted by a reflow heating device or the like, and after cooling, the melted solder becomes a solder lump and the solder bump 5 is obtained.
溶融後、半田ボール９の体積から開孔部７を塞ぎ、残りの半田が半球状に保護膜表面から突出する。この時の突出高さは０．１ｍｍになる。保護膜厚さ及び半田ボール直径は電極寸法により決定すれば良い。
After melting, the opening 7 is closed from the volume of the solder ball 9, and the remaining solder protrudes from the surface of the protective film in a hemispherical shape. The protruding height at this time is 0.1 mm. The protective film thickness and the solder ball diameter may be determined by the electrode dimensions.
以上の工程により、図１に示した半導体素子１が完成する。
Through the above steps, the semiconductor element 1 shown in FIG. 1 is completed.
その後、半導体素子１を所定の素子寸法に切断（ダイシング）することで、フリップチップを得ることができる。
Thereafter, the semiconductor element 1 is cut (diced) into a predetermined element size, whereby a flip chip can be obtained.
本発明の半導体素子を用いることによって、半田バンプは保護膜に囲われており、突出部も半球形状になるため、外部衝撃に強くなる。さらに実装時には、保護膜が支柱の役目をして傾かない半田バンプとすることが可能である。
By using the semiconductor element of the present invention, the solder bump is surrounded by the protective film, and the protruding portion is also hemispherical, so that it is resistant to external impact. Further, when mounting, it is possible to form solder bumps in which the protective film serves as a support and does not tilt.
また、半田ボール整列において、開孔部に直接半田ボールを振り込むため、半田ボール整列用マスクを準備する必要のなく、効率のよい半導体素子の製造が可能となる。
Further, in solder ball alignment, the solder ball is directly transferred into the opening, so that it is not necessary to prepare a solder ball alignment mask, and an efficient semiconductor device can be manufactured.
上記のように、本発明の実施の形態を記載したが、この開示の一部をなす記述及び図面はこの発明を限定するものであると理解するべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかになるはずである。
Although the embodiment of the present invention has been described as described above, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques should be apparent to those skilled in the art.
例えば、電極寸法が大きく保護膜高さを高くしたい場合は、保護膜塗布から露光し開孔の工程を複数回繰り返しおこなってもよい。これにより、保護膜厚さが十分になり、深い開孔部が得られ、大口径の半田ボールを使用することができる。
For example, when the electrode dimensions are large and it is desired to increase the height of the protective film, exposure may be performed from the application of the protective film and the opening process may be repeated a plurality of times. Thereby, a protective film thickness becomes sufficient, a deep opening part is obtained, and a large-diameter solder ball can be used.
また、半導体素子はフリップチップの他、チップサイズパッケージに使用してもよい。
In addition to the flip chip, the semiconductor element may be used for a chip size package.
この様に、本発明はここでは記載していない様々な実施の形態等を包含するということを理解すべきである。したがって、本発明はこの開示から妥当な特許請求の範囲の発明特定事項によってのみ限定されるものである。
Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.
１、半導体素子
２、ウエハ
３、電極
４、保護膜
５、半田バンプ
６、開孔マスク
７、開孔部
８、フラックス
９、半田ボール
１１、半導体素子
１２、ウエハ
１３、電極
１４、カバー層
１５、半田バンプ
１６、フラックスマスク
１７、ボール搭載マスク
１８、フラックス
１９、半田ボール
1, semiconductor element 2, wafer 3, electrode 4, protective film
5, solder bump 6, aperture mask 7, aperture 8, flux 9, solder ball 11, semiconductor element 12, wafer 13, electrode 14, cover layer 15, solder bump 16, flux mask 17, ball mounting mask 18, Flux 19, solder balls
Claims (4)
In a semiconductor element that forms solder bumps on electrodes on a wafer, the wafer on which an electronic circuit is formed, the electrodes that serve as input / output terminals of the electronic circuit, a protective film that covers and protects the surface of the wafer, The protective film includes: an opening portion formed in the upper portion of the electrode; and a solder bump in which the opening portion is filled with solder and a protruding portion is formed from the surface of the protective film. Semiconductor element.
The semiconductor device according to claim 1, wherein the solder is a solder ball.
The semiconductor device according to claim 1, wherein the protective film layer is a photosensitive polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| JP2010057960A JP2011192815A (en) | 2010-03-15 | 2010-03-15 | Semiconductor device and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010057960A JP2011192815A (en) | 2010-03-15 | 2010-03-15 | Semiconductor device and method of manufacturing the same |
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| JP2011192815A true JP2011192815A (en) | 2011-09-29 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004179363A (en) * | 2002-11-27 | 2004-06-24 | Kyocera Corp | Manufacturing method of wiring board with solder bump |
| JP2005019813A (en) * | 2003-06-27 | 2005-01-20 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| JP2007115858A (en) * | 2005-10-20 | 2007-05-10 | Texas Instr Japan Ltd | Manufacturing method of electronic component |
| JP2008108908A (en) * | 2006-10-25 | 2008-05-08 | Shinko Electric Ind Co Ltd | Method of mounting solder ball and method of manufacturing solder ball-mounted substrate |
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2010
- 2010-03-15 JP JP2010057960A patent/JP2011192815A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004179363A (en) * | 2002-11-27 | 2004-06-24 | Kyocera Corp | Manufacturing method of wiring board with solder bump |
| JP2005019813A (en) * | 2003-06-27 | 2005-01-20 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| JP2007115858A (en) * | 2005-10-20 | 2007-05-10 | Texas Instr Japan Ltd | Manufacturing method of electronic component |
| JP2008108908A (en) * | 2006-10-25 | 2008-05-08 | Shinko Electric Ind Co Ltd | Method of mounting solder ball and method of manufacturing solder ball-mounted substrate |
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