JP2011192719A - Nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which improves in-plane uniformity of a threshold voltage by improving controllability of a gate recess amount of a device employing a GaN-based nitride semiconductor. <P>SOLUTION: The nitride semiconductor device includes a buffer layer 102 formed of a first GaN-based semiconductor, a carrier travelling layer 103 formed of a second GaN-based semiconductor, a carrier supply layer 104 formed of a third GaN-based semiconductor, on a substrate 101. A first insulation film 105, a second insulation film 106 containing aluminum, a third insulation film 107 with a thickness larger than the first insulation film 105 are formed on a carrier supply layer 104. A source electrode 108 and a drain electrode 109 are formed on the first insulation film 105. The gate electrode 110 is formed on the second insulation film 106 and third insulation film 107 including a recess structure. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device and a method for manufacturing the same, and more particularly to a nitride semiconductor device capable of improving in-plane uniformity of a threshold voltage.

  III-V nitride semiconductors are not only applied to short-wavelength optical elements by utilizing their physical characteristics, which are a wide band gap and a direct transition type band structure, but also have a high breakdown electric field and saturation electron velocity. Application to electronic devices is also being considered due to its features.

In particular, a two-dimensional electron gas (hereinafter referred to as 2DEG) that appears at the interface between an Al _x Ga _1-x N layer (where 0 <x ≦ 1) and a GaN layer epitaxially grown on a semi-insulating substrate sequentially. Hetero-junction field effect transistors (hereinafter referred to as “HFETs”) that use (referred to as “name”) are being actively researched and developed for practical use as high-power devices and high-frequency devices.

  For example, Nakayama et al. Have reported a field effect transistor having high gain, high breakdown voltage, and good in-plane uniformity (see Patent Document 1). FIG. 6 shows a cross-sectional view of an insulated gate HFET disclosed by Nakayama et al. As shown in FIG. 6, a buffer layer 1002, a carrier traveling layer 1003, a carrier supply layer 1004, an etching stopper layer 1005, and an ohmic contact layer 1006 are sequentially formed on a substrate 1001.

After that, a source electrode 1007 and a drain electrode 1008 are formed, and a first insulating film 1009 is further formed. A part of the insulating film 1009 and the ohmic contact layer 1006 between the source electrode 1007 and the drain electrode 1008 are removed to form a recess structure 1010. At this time, the ohmic contact layer 1006 is selectively etched by dry etching using a mixed gas of BCl ₃ and SF ₆ , and the etching is stopped at the etching stopper layer 1005 (see Non-Patent Document 1). Next, a gate insulating film 1009 is formed, and further, a recessed portion 1010 is embedded, and a gate electrode 1012 is formed in a region where the first insulating film remains. By doing so, the distance between the electrode and the carrier travel layer can be reduced by a recess in which the amount of digging is controlled only directly under the gate electrode, and a transistor having high gain and excellent in-plane uniformity can be obtained.

W02006 / 001369

D. Buttari, et al., “Selective dry etching of GaN over AlGaN in BCl3 / SF6 mixture” Proceedings of the 2004 IEEE Lester Eastman Conference on High Performance Devices, 2004, p. 132-137

However, the device having the structure described in Patent Document 1 improves the in-plane uniformity by controlling the recess amount by selective etching using an etching stopper layer 1005 and a mixed gas of BCl ₃ and SF _6. Since both the contact layer 1006 and the etching stopper layer 1005 are composed of AlGaN layers having different Al compositions, the selectivity of etching is small and the selectivity of the recess amount is poor. Further, from Non-Patent Document 1, even when the ohmic contact layer is made of GaN and the etching stopper layer is made of AlGaN, the etching selectivity is only about 20. Further, the ohmic contact layer 1006 is dry-etched in order to improve the gain, so that damage is formed at the interface between the nitride semiconductor and the insulating film, and collapse may be deteriorated. Further, since the formed recess structure has a recess, the coverage of the insulating film is deteriorated, which may cause an increase in gate leakage current and a decrease in breakdown voltage.

  Therefore, the present invention provides controllability of the gate recess amount of a device using a nitride semiconductor, particularly a GaN-based nitride semiconductor (for example, a mixed crystal or a laminate including GaN, AlGaN, InGaN, InAlGaN, or other GaN). An object of the present invention is to realize a nitride semiconductor device that can improve the in-plane uniformity of the threshold voltage and a method for manufacturing the same.

  In order to solve the above problems, a first nitride semiconductor device includes a substrate, a buffer layer made of a first GaN-based semiconductor formed on the substrate, and a second GaN formed on the buffer layer. Carrier traveling layer made of a semiconductor, a carrier supply layer made of a third GaN semiconductor formed on the carrier traveling layer, a silicon nitride film, a silicon oxide film, and silicon oxynitride formed on the carrier supply layer A first insulating film made of any one of the films, a second insulating film made of an insulating film containing aluminum formed on the first insulating film, and silicon formed on the second insulating film A third insulating film made of any one of a nitride film, a silicon oxide film, a silicon oxynitride film, SiOC, SiOB, and SiOF and thicker than the first insulating film; and a source electrode, a drain electrode, and a gate electrode It is equipped with a. The source electrode and the drain electrode are formed on the first insulating film, and the gate electrode has a recessed structure in which the third insulating film is removed using the second insulating film as an etch stopper layer, and includes the recessed structure. It is formed on the second and third insulating films.

  The first nitride semiconductor device may further include a spacer layer made of aluminum nitride formed between the carrier traveling layer and the carrier supply layer.

  Further, in the first nitride semiconductor device, the second insulating film may be present under the gate recess portion from which at least the third insulating film is removed.

  Further, in the first nitride semiconductor device, the first insulating film may be crystalline silicon nitride.

  By adopting such a configuration, the controllability of the recess amount can be improved, and a uniform threshold voltage can be realized in the plane. Furthermore, by not performing processing such as dry etching on the surface of the nitride semiconductor, damage to the surface can be eliminated, and the problem of poor coverage of the insulating film in the recessed portion can be avoided.

  The second nitride semiconductor device includes a substrate, a buffer layer made of the first GaN-based semiconductor formed on the substrate, and a carrier traveling layer made of the second GaN-based semiconductor formed on the buffer layer. A carrier supply layer made of a third GaN-based semiconductor formed on the carrier travel layer, and one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film formed on the carrier supply layer A first insulating film; a second insulating film made of an insulating film containing aluminum formed on the first insulating film; and a silicon nitride film, a silicon oxide film, and silicon formed on the second insulating film A third insulating film made of any one of an oxynitride film, SiOC, SiOB, and SiOF and having a thickness greater than that of the first insulating film, a source electrode, a drain electrode, and a gate electrode are provided. The source electrode and the drain electrode are formed on the carrier supply layer, and the gate electrode has a recess structure in which the third insulating film is removed using the second insulating film as an etch stopper layer, and includes a recess structure. And on the third insulating film.

  The second nitride semiconductor device may further include a spacer layer made of aluminum nitride formed between the carrier traveling layer and the carrier supply layer.

  Further, in the second nitride semiconductor device, the second insulating film may be present under the gate recess portion from which at least the third insulating film is removed.

  Further, in the second nitride semiconductor device, the first insulating film may be crystalline silicon nitride.

  By adopting such a configuration, the controllability of the recess amount can be improved, and a uniform threshold voltage can be realized in the plane. Furthermore, by not performing processing such as dry etching on the surface of the nitride semiconductor, damage to the surface can be eliminated, and the problem of poor coverage of the insulating film in the recessed portion can be avoided. In addition, since the insulating film in the ohmic electrode formation portion is removed, the annealing temperature at the time of contact formation can be lower than that in the structure of FIG.

  According to the nitride semiconductor device of the present invention, the in-plane uniformity of the threshold voltage can be improved, and the processing damage and insulating film coverage problems that occur during the process can be avoided. Can be realized.

It is a figure for demonstrating the structure of the nitride semiconductor device of 1st Embodiment. It is a figure for demonstrating an example of the manufacturing process of the nitride semiconductor device of 1st Embodiment. It is a figure for demonstrating the structure of the nitride semiconductor device regarding 1st Embodiment. It is a figure for demonstrating the structure of the nitride semiconductor device of 2nd Embodiment. It is a figure for demonstrating an example of the manufacturing process of the nitride semiconductor device of 2nd Embodiment. It is a figure which shows the structure of the semiconductor device in a prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The silicon nitride film (SiNx) is simply expressed as SiN, but this does not mean that the composition ratio of Si and N in the silicon nitride film is 1: 1. In addition, the constituent composition ratio of other substances is not meant.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing the structure of the nitride semiconductor device according to the first embodiment. As shown in FIG. 1, the nitride semiconductor device of the present embodiment includes, for example, a buffer layer 102 made of a first GaN-based semiconductor, a second GaN-based semiconductor on a high-resistance substrate 101 made of silicon (Si). And a carrier supply layer 104 made of a third GaN-based semiconductor, and a first insulating film 105, a second insulating film 106, and a third insulating film 107 are formed thereon. Has been. A source electrode 108 (hereinafter referred to as a source) and a drain electrode 109 (hereinafter referred to as a drain) for applying a bias are formed on the first insulating film 105, and a contact region 111 is formed by applying heat treatment. Then, in order to form a gate electrode 110 (hereinafter referred to as a gate) between the source electrode 108 and the drain electrode 109, a part of the third insulating film 107 is removed to form a recess structure. A gate electrode 110 is formed so as to cover the recess structure portion. Here, the “high resistance” is used to mean that no current flows during normal operation of the HFET, and a so-called semi-insulating layer is also called a high resistance layer.

  FIG. 2 is a diagram for explaining an example of a manufacturing process of the nitride semiconductor device of the present invention.

First, a buffer layer 102 made of a first GaN-based semiconductor having a thickness of 200 to 2000 nm made of high-resistance aluminum gallium nitride (Al _x Ga _1-x N (0 <x ≦ 1)) on the substrate 101, undoped the thickness consisting _{- (y N (0 <y} ≦ 1) Al y Ga 1) gallium nitride of the carrier transit layer 103 made of the second GaN-based semiconductor having a thickness of 1000nm consisting (GaN), N-type aluminum gallium nitride A laminated body in which a carrier supply layer 104 made of a third GaN-based semiconductor having a thickness of 10 nm is formed, and a first insulating film 105 made of a SiN film (thickness 5 nm) is formed on the whole surface of the laminated body, Al _2. A second insulating film 106 made of an O ₃ film (thickness 5 nm) is formed (FIG. 2A). Since a gate recess is not formed in the carrier supply layer 104 by dry etching, an Al composition is 20% or more and a film thickness is 30 nm or less with a threshold voltage of −8V or more as a guide for suppressing a decrease in gain. It is desirable to do. The SiN film, which is the first insulating film 105, desirably has a condition that the composition ratio of nitrogen to silicon in the film is rich in nitrogen, and further preferably has a hydrogen content in the film of 10% or less. The Al ₂ O _{3 as} the second insulating film 106 may be any insulating film containing aluminum that can be dissolved in an alkaline developer, and may be AlN, AlHfO, AlYO, or the like.

A resist is patterned on the formed second insulating film 106 (not shown), and at least the second insulating film in a region where the source electrode 108 and the drain electrode 109 are formed may be removed (FIG. 2 ( b)) The second insulating film may remain from the end of the source electrode 108 to the end of the drain electrode 109 as shown in FIG. The second insulating film 106 can be easily removed with an alkaline developer or the like, and the first insulating film 105 is not dissolved with an alkaline solution, so that only the second insulating film 106 is removed. be able to. Further, it is sufficient to leave the second insulating film 106 at least in a portion where a gate recess is formed.

  Next, the source electrode 108 and the drain electrode 109 are formed. Since the source electrode 108 and the drain electrode 109 are electrically connected to the 2DEG formed at the interface between the carrier supply layer 104 and the carrier traveling layer 103, the source electrode 108 and the drain electrode 109 are formed and annealed to form 2DEG. A contact region 111 is formed to form an ohmic contact with (FIG. 2C). Note that a part of the carrier supply layer 104 or a part of the carrier supply layer 104 and the carrier traveling layer 103 in a region where an ohmic contact is to be formed may be removed to form the source electrode 108 and the drain electrode 109, and annealing may be performed.

  Next, a third insulating film 107 made of a SiN film (thickness: 100 nm) is formed (FIG. 2D).

In order to remove the third insulating film 107 in the region where the gate recess is to be formed, a resist pattern having an opening in the gate recess portion is formed (not shown in the figure), and CF4 is used with an apparatus such as reactive ion etching (RIE). Dry etching is performed using a fluorine-based gas such as Here, although the etching rate of SiN and Al ₂ O ₃ using a fluorine-based gas depends on the conditions, both Si _{2 and} Al ₂ O ₃ and AlN are very slow at about 1 nm / min for SiN of 100 to 200 nm / min. , The selection ratio is 100 or more. Therefore, the etching can be accurately stopped at the second insulating film 106. Furthermore, the second insulating film 106 in the ohmic electrode formation region is removed with an alkaline solution and then annealed, whereby the dry etching rate can be further reduced and the recess controllability can be increased. In addition, since the semiconductor surface is not damaged because it is stopped on the insulating film, adverse effects such as gate leakage and collapse can be reduced.

  Finally, the gate electrode 110 is formed on the second and third insulating films including the region where the gate recess is formed.

  The substrate 101 of the present embodiment may be a high resistance substrate, such as silicon, sapphire, silicon carbide, GaN, or AlN.

As the buffer layer 102 made of the first GaN-based semiconductor, for example GaN, InN, AlN, _{and, In x Al y Ga 1-} xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y There is a nitride semiconductor represented by ≦ 1), and a structure in which several layers having different compositions are stacked may be employed. It is also possible to add an n-type impurity or a p-type impurity into the buffer layer 102 made of the first GaN-based semiconductor.

The carrier transit layer 103 made of the second GaN-based semiconductor, for example GaN, InN, AlN, _{and, In x Al y Ga 1-} xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ There is a nitride semiconductor indicated by 1). In particular, it is desirable to use GaN having excellent crystallinity that can reduce the influence of Coulomb scattering.

As the carrier supply layer 104 composed of the third GaN-based semiconductor, for example GaN, InN, AlN, _{and, In x Al y Ga 1-} xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ There is a nitride semiconductor represented by x + y ≦ 1). However, the carrier supply layer 104 in the embodiment of the present invention is N-type aluminum gallium nitride (Al _y Ga _1-y N (0.2 ≦ y ≦ 1.0)) having a thickness of 5 to 30 nm. In order to improve the gain in the high frequency region, it is necessary to reduce the thickness so that 2DEG does not disappear.

In addition, a heterojunction is preferably formed at the interface between the carrier traveling layer 103 made of the second GaN-based semiconductor and the carrier supply layer 104 made of the third GaN-based semiconductor. When electrons are selected as carriers traveling in the carrier traveling layer 103, the conduction band energy Ec of the second GaN-based semiconductor is made lower than the conduction band energy Ec of the third GaN-based semiconductor, and the band discontinuity ΔEc is It is preferable to have an embodiment that exists. Further, a barrier layer having a thickness of 1 to 2 nm made of high-resistance aluminum gallium nitride (Al _x Ga _1-x N (0.5 ≦ x ≦ 1)) is provided between the carrier supply layer 104 and the carrier traveling layer 103. It is good. By providing the barrier layer, the electron concentration of 2DEG is increased, the maximum drain current can be increased, and the output of the power device can be increased.

In addition, the SiN film as the first insulating film 105 preferably has a condition in which the composition ratio between nitrogen and silicon in the film is rich in nitrogen, and the hydrogen content in the film is preferably 10% or less. Further, in order to suppress contamination and damage introduced to the surface of the nitride semiconductor and form a good interface between the semiconductor and the insulating film, a crystalline SiN film is continuously formed in the growth apparatus after the carrier supply layer 104 is formed. May be formed. Further, a silicon oxide film (SiO ₂ ) or a silicon oxynitride film (SiON) may be used, but it is desirable to use a SiN film in view of adverse effects on characteristics such as collapse, and a crystalline SiN film is used. Better still.

The Al ₂ O ₃ that is the second insulating film 106 may be any insulating film containing aluminum that can be dissolved in an alkaline solution, and may be AlN, AlHfO, AlYO, or the like. The second insulating film 106 only needs to have a region where a gate recess is formed, and may cover the source and drain without any gap. Further, in order to suppress a decrease in gain, the film thicknesses of the first and second insulating films are each desirably 10 nm or less, and the total thickness of the first and second insulating films is preferably 10 nm or less. .

The third insulating film 107 is made of SiN, SiO ₂ , SiON, SiOC (carbon-containing SiO ₂ film), SiOB having an etching rate different from that of Al ₂ O _{3 in} order to increase the selectivity in dry etching using a fluorine-based gas. (Boron Silicate Glass) or SiOF (Fluorinated Silicate Glass) may be used, and the film thickness may be 20 to 500 nm in order to reduce the parasitic capacitance of the gate. Further, when a SiN film is selected as the third insulating film and the second insulating film is left only in the gate recess as shown in FIG. 1, the source and drain surfaces other than the gate are passivated with the SiN film. It is possible to increase the sheet carrier concentration and reduce the access resistance. Further, by adopting SiO ₂ , SiOC, SiOB, SiOF or the like having a low dielectric constant as the third insulating film, it becomes possible to reduce the parasitic capacitance of the gate and improve the gain. Further, unlike the general T-type gate structure, the third insulating film 107 is formed before the gate electrode 110 is formed, and the gate electrode 110 is formed on the recess structure, so that it is compared with the T-type gate structure. A structurally strong gate can be formed, and defects during formation such as the gate electrode falling can be avoided.

  In this embodiment, the source electrode 108 and the drain electrode 109 are made of Ti / Al, but may be any metal species that is in ohmic contact with 2DEG. For example, W, Mo, Si, Ti, Pt, Nb, Metals such as Al, Au, Ni, and V can be used, and a structure in which a plurality of the metals are stacked can also be used. Further, in this embodiment, the source electrode 108 and the gate electrode 110 and the drain electrode 109 and the gate electrode 110 are displayed at equal intervals. However, in order to improve the breakdown voltage of the semiconductor device, It is desirable that the gap between the gate electrodes 110 is wider than that between the source electrode 108 and the gate electrode 110.

  The configuration of the nitride semiconductor device shown in FIGS. 1 to 3 can control the etching amount of the third insulating film 107 with high accuracy by using the second insulating film 106 as an etching stopper layer. In addition, since damage to the semiconductor surface is suppressed and the gate is formed directly on the third insulating film 107, a device that is excellent in in-plane uniformity of the threshold voltage and structurally strong can be realized.

(Second Embodiment)
4 and 5 are cross-sectional views schematically illustrating the structure of the nitride semiconductor device according to the second embodiment and a diagram for explaining an example of a manufacturing process. In addition, description is abbreviate | omitted about the same location demonstrated in 1st Embodiment, and the place where the same number is provided has shown the same thing. As shown in FIG. 4, a buffer layer 102, a carrier traveling layer 103, and a carrier supply layer 104 are sequentially stacked on a substrate 101, and a first insulating film 105, a second insulating film 106, a SiN film ( A third insulating film 107 having a thickness of 100 nm is formed. A source electrode 108 (hereinafter referred to as a source) and a drain electrode 109 (hereinafter referred to as a drain) for applying a bias are formed on the carrier supply layer 104, and a contact region 111 is formed by applying heat treatment. Then, in order to form a gate electrode 110 (hereinafter referred to as a gate) between the source electrode 108 and the drain electrode 109, a part of the third insulating film 107 is removed to form a recess structure. A gate electrode 110 is formed so as to cover the recess structure portion.

  As shown in FIG. 5, the part from which the first insulating film 105 and the second insulating film 106 in FIG. 5B are removed is different from the manufacturing process of the first embodiment. Specifically, a resist is patterned on the formed second insulating film 106 (not shown), and at least the second insulating film in the region where the source electrode 108 and the drain electrode 109 are formed is subjected to alkaline development. Remove with a solution such as liquid. Further, the first insulating film 105 is removed using a solution such as hydrofluoric acid without removing the resist, and the resist is removed. Alternatively, after removing the second insulating film 106, the resist may be patterned again, and the first insulating film 105 may be removed with a solution of hydrofluoric acid or the like to obtain a shape as shown in FIG. As described later, it is desirable to leave the SiN film between the source and the drain as much as possible because the nitride semiconductor surface is not exposed to the atmosphere or other processes, and the surface passivation effect is great.

  The configuration of the nitride semiconductor device shown in FIGS. 4 and 5 can control the etching amount of the third insulating film 107 with high accuracy by using the second insulating film 106 as an etching stopper layer. In addition, since damage to the semiconductor surface is suppressed and the gate is formed directly on the third insulating film 107, a device that is excellent in in-plane uniformity of the threshold voltage and structurally strong can be realized. In addition, since the insulating film in the ohmic electrode formation portion is removed, the annealing temperature at the time of contact formation can be lower than that in the structure of FIG.

  According to the present invention, the etching amount of the third insulating film 107 can be controlled with high accuracy by using the second insulating film 106 as an etching stopper layer, and the in-plane uniformity of the threshold voltage is improved. be able to. In addition, since damage to the semiconductor surface is suppressed and the gate is formed directly on the third insulating film 107, a device that is excellent in in-plane uniformity of the threshold voltage and structurally strong can be realized.

101 substrate 102 buffer layer 103 carrier traveling layer 104 carrier supply layer 105 first insulating film 106 second insulating film 107 third insulating film 108 source electrode 109 drain electrode 110 gate insulating film 111 contact region 1001 substrate 1002 buffer layer 1003 Carrier traveling layer 1004 Carrier supply layer 1005 Etching stopper layer 1006 Ohmic contact layer 1007 Source electrode 1008 Drain electrode 1009 First insulating film 1010 Recess region 1011 Gate insulating film 1012 Gate electrode 1013 Protective film

Claims (8)

A substrate,
A buffer layer made of a first GaN-based semiconductor on the substrate;
A carrier traveling layer made of a second GaN-based semiconductor formed on the buffer layer;
A carrier supply layer made of a third GaN-based semiconductor formed on the carrier traveling layer;
A first insulating film made of any one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film formed on the carrier supply layer;
A second insulating film made of an insulating film containing aluminum formed on the first insulating film;
A third insulation made of any one of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, SiOC, SiOB, and SiOF formed on the second insulation film and having a thickness greater than that of the first insulation film. A membrane,
A source electrode, a drain electrode and a gate electrode;
The source electrode and the drain electrode are formed on the first insulating film,
The gate electrode has a recess structure in which the third insulating film is removed using the second insulating film as an etch stopper layer, and the second insulating film and the third insulating film including the recess structure A nitride semiconductor device formed over the nitride semiconductor device.   The nitride semiconductor device according to claim 1, further comprising a spacer layer made of aluminum nitride formed between the carrier traveling layer and the carrier supply layer.   3. The nitride semiconductor device according to claim 1, wherein the second insulating film exists under a gate recess portion from which at least the third insulating film is removed.   The nitride semiconductor device according to claim 1, wherein the first insulating film is made of crystalline silicon nitride. A substrate,
A buffer layer made of a first GaN-based semiconductor formed on the substrate;
A carrier traveling layer made of a second GaN-based semiconductor formed on the buffer layer;
A carrier supply layer made of a third GaN-based semiconductor formed on the carrier traveling layer;
A first insulating film made of any one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film formed on the carrier supply layer;
A second insulating film made of an insulating film containing aluminum formed on the first insulating film;
The third insulating film is formed of any one of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, SiOC, SiOB, and SiOF formed on the second insulating film, and is thicker than the first insulating film. An insulating film of
A source electrode, a drain electrode and a gate electrode;
The source electrode and the drain electrode are formed on the carrier supply layer,
The gate electrode has a recess structure in which the third insulating film is removed using the second insulating film as an etch stopper layer, and the second insulating film and the third insulating film including the recess structure A nitride semiconductor device formed over the nitride semiconductor device.   The nitride semiconductor device according to claim 5, further comprising a spacer layer made of aluminum nitride formed between the carrier traveling layer and the carrier supply layer.   The nitride semiconductor device according to claim 5, wherein the second insulating film is present under the gate recess portion from which at least the third insulating film is removed.   The nitride semiconductor device according to claim 5, wherein the first insulating film is made of crystalline silicon nitride.

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