JP2011192058A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor in which a memory access time does not affect an entire processing time even if performing processing requiring a large number of access to a memory. <P>SOLUTION: In the image processor including the memory, an external memory access device for performing read/write access from/to the memory, and an SIMD type microprocessor having a port for transmitting data to the external memory access device, the control of reducing the access to the memory by the external memory access device is executed by a control code generated on the basis of a connection relation between adjacent processor elements in the data stored in registers included in each of a plurality of processor elements constituting the SIMD type microprocessor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus.

  In the SIMD type microprocessor, the same arithmetic processing can be executed simultaneously on a plurality of data with one instruction. This structure is frequently used in applications related to processing (particularly image processing) in which the calculation is the same but the amount of data is very large. In normal image processing in a SIMD type microprocessor, a plurality of arithmetic units (Processor Elements [PE]; processor elements) are arranged in a direction corresponding to the main scanning direction, and the same arithmetic is simultaneously performed on a plurality of data. This enables high-speed arithmetic processing.

  By the way, an image processing apparatus including a SIMD type microprocessor and a memory device is a system in which access to the memory device greatly affects the entire processing cycle time. In a system (apparatus) in which such memory access greatly affects the overall processing time, if processing that frequently requires read access to the memory and write access to the memory, such as histogram processing, is performed, the processing time There is a problem of becoming longer.

  Note that Patent Documents 1 to 6 described later are listed as prior art documents of the present invention.

  The present invention provides an image processing apparatus in which the memory access time does not increase the overall processing time even when processing requiring a large number of read accesses to the memory and write accesses to the memory, such as histogram processing, is performed. For the purpose.

The present invention has been made to achieve the above object. An image processing apparatus according to claim 1 of the present invention is provided.
An image processing apparatus comprising: a memory; an external memory access device that performs read / write access to the memory; and a SIMD type microprocessor having a port that transmits data to the external memory access device.
The external memory access device by a control code generated based on a continuity relationship between adjacent processor elements in data stored in a register included in each of a plurality of processor elements constituting the SIMD type microprocessor The image processing apparatus is characterized in that control for reducing access to the memory is performed.

An image processing apparatus according to claim 2 of the present invention is provided.
The control code is
Indicates a match or mismatch between data stored in a register included in the target processor element and data stored in a register included in the processor element immediately preceding the target processor element adjacent to the target processor element The image processing apparatus according to claim 1, wherein the image processing apparatus is a first control code.

An image processing apparatus according to claim 3 of the present invention is provided.
The control code is
Indicates a match or mismatch between data stored in a register included in the target processor element and data stored in a register included in the processor element immediately after the target processor element adjacent to the target processor element The image processing apparatus according to claim 1, wherein the image processing apparatus is a second control code.

An image processing apparatus according to claim 4 of the present invention is provided.
The image processing apparatus according to claim 3, wherein the external memory access device further includes a temporary storage element that temporarily stores the second control code to give a delay.

An image processing apparatus according to claim 5 of the present invention is provided.
The control code is
When the data stored in the register included in the processor element of interest matches the data stored in the register included in the processor element immediately before the processor element of interest adjacent to the processor element of interest It is a specific code that is overwritten on the data stored in the register included in the processor element of interest,
The image processing apparatus according to claim 1, wherein the external memory access device includes a detection circuit for the specific code.

  In the image processing apparatus according to the present invention, in the external memory access apparatus that controls access between the SIMD type microprocessor and the external memory, part of the memory read access and memory write access can be omitted, and thereby the memory access cycle The number can be reduced and the processing time can be shortened. Furthermore, the scale of the control circuit in the external memory access device can be reduced.

FIG. 1 is a block diagram of an image processing apparatus according to the first embodiment of the present invention (FIG. 1 (1)), and shows how data is input and output when histogram processing is performed in the image processing apparatus according to the first embodiment. It is a figure shown (FIG. 1 (2)). It is a schematic block diagram of a SIMD type microprocessor. 1 is a configuration diagram of an external memory access device in an image processing device according to a first embodiment. FIG. It is a figure for demonstrating the production | generation of a control code (A, B). It is a figure which shows the time transition of the read data (Read Data) of an external memory access apparatus, and the write data (Write Data) when the data of attention PE do not correspond or the data of previous and subsequent PE. It is a block diagram of the external memory access apparatus in the image processing apparatus which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the production | generation of the control code in 2nd Embodiment. It is a figure for demonstrating the production | generation of the control code in 2nd Embodiment. It is a figure which shows the mode of the input / output of data when performing the look-up table conversion process in the image processing apparatus which concerns on 3rd Embodiment. It is a figure which shows memory access control at the time of reading table data from memory based on the input data from a SIMD type | mold microprocessor.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[First embodiment]
FIG. 1A is a block diagram of an image processing apparatus according to the first embodiment of the present invention. The image processing apparatus shown in FIG. 1A includes a SIMD type microprocessor 2, a memory 6, and an external memory access device 4.

  FIG. 2 is a schematic configuration diagram of the SIMD type microprocessor 2. The SIMD type microprocessor 2 includes a plurality of PEs (processor elements), and each PE 8 includes a plurality of registers 18. Specifically, the SIMD type microprocessor 2 includes PEs PE0, PE1, PE2,... PE (n-1), and n PEs numbered PEn. The n PEs are arranged in a direction corresponding to the main scanning direction of the image. Each PE 8 includes a register unit 12 and an operation unit 14, and each register unit 12 includes a plurality of registers 18. A plurality of registers 18 in each PE 8 are connected to the arithmetic unit 14 via the bus 16. The operation unit 14 performs an operation using data stored in the register 18 of the register unit 12. Each of the plurality of registers 18 in each PE 8 has a corresponding register 18 in each of all other PEs, and the corresponding registers 18 are connected to a common port 10. The SIMD type microprocessor 2 performs data communication with the outside via these ports 10.

  Returning to the block diagram of the image processing apparatus shown in FIG. 1A, a memory 6 including a RAM or the like is provided outside the SIMD type microprocessor 2. Read (read) / write (write) access from the SIMD type microprocessor 2 to the memory 6 is controlled by the external memory access device 4. As described above, the external memory access device 4 is connected to the SIMD microprocessor 2 through the port 10.

  Next, FIG. 1B is a diagram illustrating how data is input and output when histogram processing is performed in the image processing apparatus according to the first embodiment. Here, the histogram processing is processing for obtaining the number of appearances of data having the same value. Data input / output of the image processing apparatus according to the first embodiment when performing the histogram processing shown in FIG. 1 (2) is substantially the same as that shown in FIG. 1 (1), but from the external memory access device 4a. The difference is that there is no output data to the SIMD type processor 2.

  FIG. 3 is a configuration diagram of the external memory access device 4a in the image processing apparatus according to the first embodiment. The external memory access device 4a shown in FIG. 3 includes a selector 20, an adder (ADDR) 22, and a write data control circuit 24.

  The control code A input to the external memory access device 4a is the data value of the register of the target PE (for example, PE (k)) in the plurality of PEs 8 arranged in the SIMD type microprocessor 2, and one after that. If the data value of the register of the PE of PE (ie, PE (k + 1)) matches, the attention PE (PE (k)) is expressed as “1”, and if it does not match, the attention PE (PE (K)) is a code represented as “0”.

  Also, the control code B input to the external memory access device 4a is the data value of the register of the target PE (for example, PE (k)) in the plurality of PEs 8 arranged in the SIMD type microprocessor 2, and the 1 If the data value in the register of the previous PE (that is, PE (k−1)) matches, the attention PE (PE (k)) is expressed as “1”, and if it does not match, that This is a code expressed as “0” for the target PE (PE (k)). As described above, the control codes (A, B) are based on the continuous relationship between the adjacent processor elements in the data stored in the registers included in each of the plurality of PEs constituting the SIMD type microprocessor 2. Is the code that is being generated.

  The selector 20 corresponds to the value of the input data from the SIMD type microprocessor 2 and the data read from the memory (area) to which the appearance number of the value is added and the appearance of the previous input data. Selection is made by the control code B from among the data output immediately before by the adder 22. In other words, if the control code B is “1”, the data value of the register of the target PE matches the data value of the register of the previous PE, so the selector 20 The number of occurrences of the previous input data (that is, the number of occurrences of the data value of the register of the previous PE) and the data output by the adder 22 immediately before is selected. If the control code B is “0”, it means that the data value of the register of the target PE and the data value of the register of the previous PE are inconsistent. It is set to select data read from a memory (area) corresponding to the value of the input data from the PE of interest of the type microprocessor 2 and adding the number of appearances of that value.

  The adder 22 adds the number of appearances. Inversion of the control code A and the output of the adder 22 are input to the write data control circuit 24. If the control code A is “1”, the data value of the register of the PE of interest matches the data value of the register of the next PE, that is, a PE including a register having the same data value. Since it is not necessary to output a data value at this time, the write data control circuit 24 converts the output of the adder 22 into the corresponding address of the memory 6a by inverting the control code A (here, “0”). At this time, control is performed so that writing is not performed. If the control code A is “0”, the data value of the register of the target PE and the data value of the register of the next PE are inconsistent, that is, a PE including registers having the same data value. Therefore, the write data control circuit 24 outputs the output of the adder 22 by inverting the control code A (here, “1”). Control is performed to write to the corresponding address in the memory 6a.

  Therefore, in the external memory access device shown in FIG. 3, by adding the output of the adder 22 and the input of the selector 20, the addition is accumulated if the data value of the register continues in the same value in the continuous PE. Is indicated by the value of the control code B (that is, if the value of the control code B is “0”), the selector 20 corresponds to the value of the input data from the target PE. The data is selected by switching to the data read from the memory (area) in which the number of occurrences of the value is added. Further, if the value of the control code A indicates that the continuity is interrupted (that is, if the value of the control code A is “0”), the write data control circuit 24 sends the output of the adder 22 to the memory 6a. It is controlled to write to the corresponding address.

  Specific contents of the control code A and the control code B are generated by a SIMD type microprocessor. That is, a control code is generated based on register data match / mismatch information between the PE of interest and the PEs adjacent to (before and after) the PE. Generation of control codes (A, B) will be described with reference to FIG.

  As shown in FIG. 2, the SIMD type microprocessor 2 includes a plurality of PEs, and each PE includes a register 16 that holds data. FIG. 4 (1) shows PE0 to PE6. Further, it is assumed that data of 00h, 01h, 01h, 02h, 02h, 02h, 03h (“h” indicates hexadecimal notation) is held in each PE register (“ “PE data” means the data held in the PE register.) At this time, according to the instruction of the SIMD type microprocessor, the control code A is set to “1” if the data match / mismatch between the target PE and the subsequent PE is “1”, otherwise “0”. When set as “,” the control code A here becomes 0, 1, 0, 1, 1, 0, 0. Next, according to the instruction of the SIMD type microprocessor, the control code B is set to “1” if the data of the target PE and the previous PE match / does not match, and “0” otherwise. When set as “,” the control code B here becomes 0, 0, 1, 0, 1, 1, 0.

  The control codes (A, B) are transmitted from the SIMD type microprocessor 2 to the external memory access device 4a. The control code (A, B) may be stored in one of the registers in each PE. Further, as shown in FIG. 4B, when the register stores data in each PE, a control code may be assigned to some bits of the register.

  In “control code bit allocation data” shown in FIG. 4 (2), data is stored in 1 to 7 bits (bits) of the PE register, and the control code A described above is allocated to 0 bits (bits). Here, the control code B described above may be assigned. Further, data may be stored in 2 to 7 bits of the PE register, and the control code A and the control code B described above may be assigned to 0 to 1 bit.

  FIG. 5 is a diagram illustrating temporal transitions of read data (Read Data) and write data (Write Data) of the external memory access device 4a when the data of the target PE does not match or coincides with the data of the previous and subsequent PEs. . That is, it is a diagram showing memory access control in which the value of the number of appearances of the data value is read from the memory, incremented appropriately, and written back to the memory again. In FIG. 5, “RCLK” is a “register clock” and indicates a clock for a read operation and a write operation. FIG. 5 shows the transition from the first cycle to the ninth cycle.

  “ADD” indicates a data value stored in the register of the PE. “Ctl code A” and “ctl code B” indicate a control code A and a control code B, respectively. “RWEB” is “register write enable” and indicates an enable signal for a write operation to the memory. “Read Data” and “Write Data” are the contents of read data and write data.

  The memory access control in FIG. 5 depends on the control code (A, B), and four patterns of memory access control can be considered from the combination of the control code A and the control B.

  First, pattern 1 is a case where the data (register) of the target PE does not match the data (register) of any PE before or after. In this case, since none of the control codes (A, B) is asserted in the data of the noticed PE (that is, it is not “1”), it relates to any of the previous PE, the noticeable PE, and the subsequent PE. Also during operation, after the data read access from the memory, the appearance number is incremented by 1, and the data is accessed for writing to the memory.

  Next, pattern 2 is a case in which the data (register) of the target PE matches the data (register) of the next PE. At this time, since the control code A is asserted in the data of the target PE (4 to 6 cycles), only the data read access from the memory is performed for the data of the target PE (the number of occurrences), and the data write Access may not be performed. Further, the data of the next PE (occurrence number value) does not need to be read from the memory, and in addition, the memory write access is performed collectively in the cycle for the next PE. Just do it. Therefore, the fifth to seventh cycles can be omitted.

  Next, pattern 3 is a case where the data of the target PE (register) matches the data of the previous PE (register). At this time, since the control code B is asserted in the data of the PE of interest (4 to 6 cycles), the data of the PE of interest (the number of occurrences) is the data read from the memory when accessing the previous PE Therefore, read access from the memory does not have to be performed. As for the appearance count value of the data of the noticed PE, the appearance count value at the cycle of the noticeable PE is compared with the data read at the cycle of the previous PE as the appearance count value of the data of the previous PE. It is sufficient that the addition is performed to perform a write access to the memory. Further, regarding the data appearance value of the previous PE, the data write access to the memory may not be performed in the cycle related to the previous PE. Therefore, the second to fourth cycles can be omitted.

  Finally, the pattern 4 is a case where the data (register) of the target PE matches the data (register) of the previous PE and the data (register) of the next PE. At this time, the control code A and the control code B are asserted in the data of the target PE (4 to 6 cycles). Accordingly, it is not necessary to perform read access or write access to the memory during the cycle related to the PE of interest. In addition, in the cycle related to the previous PE, the memory does not need to be accessed for writing, and in the cycle related to the next PE, the memory does not need to be read. Therefore, the second to seventh cycles can be omitted.

  As described above, histogram processing is performed using the external memory access device according to the present embodiment for data stored in the PE register of the SIMD type microprocessor accompanied by the control code (A, B). Thus, the processing cycle in the image processing apparatus can be reduced.

[Second Embodiment]
FIG. 6 is a configuration diagram of the external memory access device 4 in the image processing apparatus according to the second embodiment of the present invention. The image processing apparatus according to the second embodiment shown in FIG. 6 is substantially the same as the image processing apparatus according to the first embodiment shown in FIG. Accordingly, the same portions are denoted by the same reference numerals, and the description thereof is omitted, and the difference will be mainly described.

  In addition to the selector 20, the adder (ADDR) 22, and the write data control circuit 24, the external memory access device shown in FIG. 6 performs the temporary storage element 28 for the control code A and the register storage data of the PE. A special data judgment circuit 25 for judging a special code to which a control code is assigned.

  Further, in the external memory access device shown in FIG. 6, the first logical sum that receives the output of the temporary storage element 28, the control code B, and the output of the special data determination circuit 25 as input, and gives the output to the selector 20. A circuit 30 is included. Also included is a second OR circuit 26 that takes the control code A and the output of the special data determination circuit 25 as inputs and gives an output to the write data control circuit 24. However, as will be described later, if the special code stored in the PE register corresponds to the control code B, the second OR circuit 26 is not provided, and the control code is the same as the circuit shown in FIG. A is configured to input directly to the write data control circuit 24. Further, if the special code stored in the PE register corresponds to the control code A, the first OR circuit 30 is configured not to input the output of the special data determination circuit 25.

  The operation of temporary storage element 28 included in the external memory access device shown in FIG. 6 will be described with reference to FIG. Assume that the registers of PE0 to PE6 hold data of 00h, 01h, 01h, 02h, 02h, 02h, 03h,... As shown in the first row of FIG. Here, as described above, when the control code A is generated by the instruction of the SIMD type microprocessor, it becomes 0, 1, 0, 1, 1, 0, 0 (see the second stage in FIG. 7). When a delay is given to this code using the temporary storage element 28, a code equal to the control code B is obtained as shown in the third and fourth stages in FIG. Therefore, the output of the temporary storage element 28 can be input to the first OR circuit 30.

  Next, the function of the special data determination circuit 25 included in the external memory access device shown in FIG. 6 will be described with reference to FIG. Assume that the registers PE0 to PE7 hold data of 00h, 01h, 01h, 02h, 02h, 02h, 03h,... As shown in the first row of FIG. Here, as described above, for the PE whose register data value is the same as that of the previous PE by the instruction of the SIMD type microprocessor, the data is rewritten (overwritten) to the special code “FFh”. Do. In this way, a control code (control code B in the case of FIG. 8) can be assigned to the data itself. With respect to the rewritten control code assignment data, the control code is taken out by the special code determination circuit 25 shown in FIG. Therefore, in the case of control code allocation data as shown in FIG. 8, the output of the special code determination circuit 25 can be used as the input of the first OR circuit 30. However, it is not an input to the second OR circuit 26.

  By the instruction of the SIMD type microprocessor, the processing that rewrites the data to the special code “FFh” is performed for the PE whose register data value is the same as the next PE, and the control code allocation data is generated. May be. In this case, the control code A is assigned to the data itself. For this control code assignment data, the control code A is taken out by the special code determination circuit 25. Therefore, in this case, the output of the special code determination circuit 25 is used as the input of the second OR circuit 26. However, it is not an input to the first OR circuit 30.

[Third embodiment]
An image processing apparatus according to the third embodiment of the present invention that performs lookup table conversion processing will be described with reference to FIG. FIG. 9 is a diagram illustrating a state of data input / output when the look-up table conversion process is performed in the image processing apparatus according to the third embodiment. Here, the look-up table process is a process of performing conversion using input data as an address and data in a memory corresponding to the address as table data. The data input / output of the image processing apparatus according to the third embodiment when performing the lookup table conversion process shown in FIG. 9 is substantially the same as that of the image processing apparatus according to the first embodiment shown in FIG. The difference is that there is no write to the memory 6 from the external memory access device 4b. The table data obtained by the conversion is used for subsequent processing, output to the outside, returned to the SIMD type microprocessor 2, and the like.

  Configuration for generating control code (A, B) by SIMD type microprocessor 2 and configuration for transmitting from SIMD type microprocessor 2 to external memory access device 4 in the image processing apparatus according to the third embodiment Is the same as that of the image processing apparatus according to the first embodiment.

  FIG. 10 is a diagram showing memory access control when reading table data from the memory 6 based on input data from the SIMD type microprocessor. In FIG. 10, “CLK” is “clock” and indicates a clock of the read operation. FIG. 10 shows the first cycle to the third cycle.

  “ADD” indicates a data value stored in the register of the PE, and the content is an address of a table to be looked up. “CtlcodeB” indicates the control code B. In the look-up table conversion process in the image processing apparatus according to the third embodiment, only the control code B is required. “Read Data” is the read data, that is, the contents of the read table data. “Previous holding Read Data” holds table data read based on the input data from the register data of the previous PE during the cycle related to the target PE.

  In the memory access control in FIG. 5, since the read access and the write access to the memory are performed, the number of cycles for each PE is three. On the other hand, in the memory access control in FIG. 10, only read access to the memory is performed, so the number of cycles for each PE is one cycle.

  The memory access control in FIG. 10 depends on the control code B, and two patterns of memory access control (pattern 5 and pattern 6 shown in FIG. 10) are conceivable.

  First, the pattern 5 is a case where the data of the target PE and the data of the previous PE do not match. In this case, since the control code B is not asserted in the data of the target PE, read access to the memory 6 is performed and the table data is read.

  Next, pattern 6 is a case where the data of the target PE matches the data of the previous PE. In this case, since the control code B is asserted in the data of the noticed PE, the table data read from the memory at the time of accessing the previous PE can be used in the lookup of the table by the data of the noticed PE. Therefore, it is not necessary to perform read access to the memory. As a result, the second cycle can be omitted.

  As described above, the data stored in the register of the PE constituting the SIMD type microprocessor accompanied with the control code B is subjected to the lookup table conversion process using the external memory access device according to the present embodiment. The processing cycle in the image processing apparatus can be reduced.

  The present invention can be used for all systems that use image processing (for example, digital cameras, digital televisions, printers, digital multifunction peripherals, etc.).

2 ... SIMD type microprocessors, 4, 4a, 4b ... external memory access device, 6 ... memory, 8 ... PE (processor element), 10 ... port, 18 ... register.

JP 2003-216950 A JP 2002-108604 A Japanese Patent No. 3969580 International Publication Number WO06 / 123822 JP-A-5-67203 Japanese Patent No. 3734869

Claims (5)

An image processing apparatus comprising: a memory; an external memory access device that performs read / write access to the memory; and a SIMD type microprocessor having a port that transmits data to the external memory access device.
The external memory access device by a control code generated based on a continuity relationship between adjacent processor elements in data stored in a register included in each of a plurality of processor elements constituting the SIMD type microprocessor The image processing apparatus is controlled to reduce access to the memory. The control code is
Indicates a match or mismatch between data stored in a register included in the target processor element and data stored in a register included in the processor element immediately preceding the target processor element adjacent to the target processor element The image processing apparatus according to claim 1, wherein the image processing apparatus is a first control code. The control code is
Indicates a match or mismatch between data stored in a register included in the target processor element and data stored in a register included in the processor element immediately after the target processor element adjacent to the target processor element The image processing apparatus according to claim 1, wherein the image processing apparatus is a second control code.   The image processing apparatus according to claim 3, wherein the external memory access device further includes a temporary storage element that temporarily stores the second control code to give a delay. The control code is
When the data stored in the register included in the processor element of interest matches the data stored in the register included in the processor element immediately before the processor element of interest adjacent to the processor element of interest It is a specific code that is overwritten on the data stored in the register included in the processor element of interest,
The image processing apparatus according to claim 1, wherein the external memory access device includes a detection circuit for the specific code.

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