JP2956390B2 - Drawing processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a drawing processor.
In particular, the present invention relates to a drawing processor for a digital image device having a configuration in which a predetermined operation is performed on a plurality of data in a bit map type data memory and the data is returned to the data memory.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional drawing processor.

[0004] The drawing processor is configured to transmit the transmitted destination data Da of the first drawing data and the second data.
, And second and third registers 1, 2, and 3 for respectively storing and outputting pattern data P of the third data and destination data Da according to the drawing operation signal DOP. , Source data S, pattern data P, and performs a predetermined operation to output as updated destination data Da
And destination data Da, source data S,
A drawing operation content storage unit 5 for storing the contents of the operation for the pattern data P and outputting a drawing operation signal DOP corresponding to the contents of the operation;
a, source data S, and pattern data P, an address signal AD and a read signal RDn are output to a data memory (not shown), and then the data transmitted from the data memory is fetched. After sequentially executing the cycles transmitted to the registers 1, 2, and 3, the updated destination data Db and the address signal AD and the write signal WT corresponding to the destination data Db are updated.
and a bus cycle controller 7a for executing a cycle for outputting n to the data memory.

Next, the operation of the drawing processor will be described. FIG. 4 is a timing chart of input / output signals for explaining the operation of the drawing processor.

As an input / output signal to / from the outside (data memory) of this drawing processor, 8-bit input / output data D
T (P, S, Da, Db), an 8-bit address signal AD, a read signal RDn indicating that a read cycle is being started for a data memory, and a write signal indicating that a write cycle is being started. WTn. Here, n at the end of the signal symbol indicates that the signal is negative logic.

In the read cycle of each data (P, S, Da), after outputting an effective value address signal AD to the address bus and setting the data bus to a high impedance state, the read signal RDn is activated. Make the level low. In response, the data memory keeps outputting the determined data to the data bus while the read signal RDn is at the active level. The drawing processor latches data on the data bus at the rising edge of the read signal RDn and transmits the data to the registers (1 to 3). This read cycle includes pattern data P, source data S,
The operation is sequentially performed on the destination data Da.

Each data transmitted to each register, ie, destination data register 1, source data register 2, and pattern data register 3, ie, destination data Da, source data S,
The pattern data P is latched by each of the registers and transmitted to the drawing operation unit 4. The drawing operation unit 4 executes an operation on the data according to the drawing operation signal DOP, and outputs updated destination data Db. Then, a write cycle, that is, a write-back cycle of the updated destination Db is started. In the write cycle, the address signal AD on the address bus and the data on the data bus are made valid and output, and then the write signal WTn is set to the active level (low level). In response, the data memory latches the updated destination data Db at the falling edge of write signal WTn.
These controls are performed by the bus cycle control unit 7a.

Next, the process in which the drawing processor updates the destination data in the data memory will be described with reference to the image diagram of FIG. FIG. 5 shows an image based on pattern data P, source data S, and destination data Da which are input data of a drawing operation, and updated destination data Db which is a drawing operation result.
Is a schematic representation of the image. These four
The data P, S, Da, and Db are binary image data, and the black and closed areas of each image (I (S), I (P), I (Da)) are “1” and the white area is “1”. 0 ".
The source data is font data existing in the data memory, and represents the character “F”. Source data S
In the image I (S), the character "F" in the foreground is "1"
The background is “0”. Similarly, the image I (P) based on the pattern data P is a thin oblique line, and the image I (Da) based on the destination data Da is a coarse oblique line. A drawing operation is performed on these three data (P, S, Da) by a drawing operation signal DOP to obtain an updated destination Db. The calculation based on the drawing calculation signal DOP conceptually has, for example, a content of “transferring the pattern data P cut out by the source data S to the destination data Da”.

Next, specific storage contents of the drawing calculation content storage unit 5 will be described. FIGS. 6A and 6B are diagrams showing the configuration of the drawing calculation content storage unit 5 and the configuration of the storage content.

The drawing operation content storage unit 5 has 8 bits (R0 to R0).
R7), and these 8 bits R0 to R7 indicate how the drawing operation to be performed is defined. FIG.
As shown in (B), there are eight combinations depending on whether the values of the pattern data P, the source data S, and the destination data Da are “0” or “1”, respectively. The drawing result (Db) for each of the eight combinations is represented by R0
8 bits of R7 are defined. For example, pattern data P
Is "1", the source data S is "0", and the destination data Da is "0", the updated destination Db, which is the operation result, is defined by the R4 bit.
If the value of R4 is "0", the updated destination data Db is "0", and if the value of R4 is "1", the updated destination data Db is "1". An equation representing this is shown in FIG. Where "+"
Represents a logical sum, and “•” represents a logical product.

A description will be given of what kind of drawing operation should be set to obtain the updated destination data Db shown in FIG. "The pattern data P is cut out by the source data S and the destination data D
In order to “transfer to a”, the source data S is used as a cutout pattern, that is, as mask data. Therefore, it is necessary to execute the following drawing operation.

IF S = 0 THEN Db = Da (1) IF S = 1 THEN Db = P (2) The expression (1) means that if the source data S is “0”, , Destination data Db as it is, updated destination data Db.
That is, the destination data is not rewritten.
On the other hand, the expression (2) means that if the source data S is “1”, the pattern data P is the updated destination data Db. The data stored in the rendering calculation content storage unit 5 for realizing this is (0, 1,
0, 0, 0, 1, 1, 1).

[0014]

In the above-described conventional drawing processor, pattern data, source data, and destination data are sequentially read in order to update the destination data, a drawing operation is performed, and the updated destination data is returned. Requires four cycles. However, some data does not require a read cycle depending on the contents of the drawing operation. For example, if the content of the drawing operation is (0,0,0,0,0,0,0,0),
Since the value “0” may be written back as updated destination data, the read cycle of the source data, pattern data, and destination data is unnecessary. In the case of (0, 0, 1, 1, 0, 0, 1, 1), the source data may be written back as the updated destination data, so that the read cycle of the pattern data and the destination data is performed. Is unnecessary.

However, in the conventional drawing processor, the pattern data, source data, and destination data are read even in such a case, so that the drawing speed is low.

An object of the present invention is to provide a drawing processor having an improved drawing speed.

[0017]

According to the present invention, there is provided a drawing processor for storing first, second, and third data corresponding to transmitted first, second, and third data for drawing, respectively. A register, a drawing operation unit for performing a predetermined operation on the first, second, and third data in accordance with the drawing operation signal and outputting the updated first data;
A drawing operation content storage unit for storing the contents of the operation for the data of the above, and outputting the drawing operation signal corresponding to the contents of the operation; and the drawing operation signal in the first, second, and third data. When there is data that does not participate in the calculation by the above, a read cycle omission instruction unit that outputs a read cycle omission instruction signal corresponding to the data, and the read cycle omission instruction signal of the first, second, and third data In response to the data that has not been output, an address signal and a read signal are output to a data memory, and then the data transmitted from the data memory is fetched.
After sequentially executing the cycle for transmitting to the third register,
A bus cycle control unit that executes a cycle of outputting the updated first data and an address signal and a write signal corresponding to the first data to the data memory;

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The difference between this embodiment and the conventional drawing processor shown in FIG.
a, source data S, and pattern data P, if there is data that is not involved in the operation by the drawing operation signal DOP, the read cycle omission instruction signal (DN
R, SNR, PNR), and a read cycle omission instruction unit 6 for outputting a read cycle omission instruction signal (DNR, SNR, PNR).
An address signal AD, for the data of the destination data Da, the source data S, and the pattern data P for which the read cycle omission instruction signal is not output, is output.
After outputting read signal RDn to the data memory, the data transmitted from this data memory is taken in. Destination data register 1, source data register 2,
After sequentially executing the cycle transmitted to the pattern data register 3, the updated destination data Db and the address signal AD and the write signal W corresponding to the updated destination data Db
Tn is a circuit for executing a cycle for outputting the data to the data memory.

Next, a destination data read cycle omission instruction signal DNP,
The process of generating the source data read cycle skip instruction signal SNR and the pattern data read cycle skip instruction signal PNR will be described.

First, the generation of the pattern data read cycle omission instruction signal PNR will be described. Pattern data P
Is determined from FIG. 6 (B) when the condition of the drawing operation is determined when the value is not related to the updated destination data Db, and the value is one of the following.

00H, 11H, 22H, 33H, 44
H, 55H, 66H, 77H, 88H, 99H, AA
H, BBH, CCH, DDH, EEH, FFH This is equivalent to the following conditional expression.

R0 = R4 and R1 = R5 and R2 = R6 and R3 = R7 (3) When this conditional expression is true, it is not necessary to start a pattern read cycle. That is, a pattern data read cycle omission instruction signal PNR is generated.

Next, generation of a source data read cycle omission instruction signal SNR will be described. When the condition of the drawing operation when the source data does not affect the updated destination data Db is obtained, similarly, the value is one of the following.

00H, 05H, 0AH, 0FH, 50
H, 55H, 5AH, A0H, A5H, AAH, AF
H, F0H, F5H, FAH, FFH This is equivalent to the following conditional expression.

R0 = R2 and R1 = R3 and R4 = R6 and R5 = R7 (4) When this condition is true, a source data read cycle omission instruction signal SNR is generated.

Finally, generation of a destination data read cycle omission instruction signal DNR will be described.
When the condition of the drawing operation when the destination data Da does not affect the updated destination data Db is obtained, the value is one of the following.

00H, 03H, 0CH, 0FH, 30
H, 33H, 3CH, C0H, C3H, CCH, CF
H, F0H, F3H, FCH, FFH This is equivalent to the following conditional expression.

R0 = R1 and R2 = R3 and R4 = R5 and R6 = R7 (5) When this conditional expression is true, a destination data read cycle omission instruction signal DNR is generated.

These read cycle omission instruction signals (P
(NR, SNR, DNR) eliminates the data read cycle that is not involved in the drawing operation, and thus the drawing speed can be increased accordingly.

Next, the process of improving the drawing processing speed according to the present invention will be described. FIG. 2 is a timing diagram of a bus cycle when the contents of the drawing operation according to the present invention are (0, 0, 1, 1, 0, 0, 1, 1).

In the conventional example, as shown in FIG. 4, it always takes four cycles. However, according to the present invention, since only two cycles are required, a drawing speed twice as high as that of the conventional example can be realized.

Similarly, when the contents of the drawing operation are (0, 0, 0,
0,0,0,0,0) or (1,1,1,1,
In the case of (1, 1, 1, 1), only the updated destination data write cycle is performed.
Double drawing speed can be expected.

Based on this fact, an improvement in the price / performance ratio of an apparatus using the drawing processor of the present invention is estimated.

First, the cost can be considered as follows. In general, to increase the bus bandwidth between the drawing processor and the data memory, the device cost increases. The performance of the drawing processor of the present invention can be improved under the condition that the bus bandwidth between the processor and the memory is exactly the same. That is, there is no cost increase by employing the drawing processor of the present invention.

Next, the performance improvement depends on how frequently it is possible to omit any of the three data read cycles of pattern, source, and destination. In other words, the question is "how often is the setting of the drawing calculation content that satisfies the expressions (3), (4), and (5)". This depends on the graphics application running on the graphics device, but consider a very common application.
Most of ordinary drawing rewrites destination data with updated data. That is, the value of the updated destination data Db can be determined without depending on the value of the destination data Da. It is assumed that the appearance rate of the destination-independent drawing operation in the total graphics processing time is 90%. Conventional drawing processors require one destination data read cycle. On the other hand, the drawing processor of the present invention requires an average of 0.1 destination data read cycles as shown in the following equation (6).

0 times × 0.9 + 1 times × 0.1 = 0.1 times (6) On the other hand, for pattern data and source data, the appearance rate of operations requiring both is 30%, and pattern data is required. The appearance rate of operations that do not require source data is 30%, the appearance rate of operations that require source data and does not require pattern data is 30%, and the remaining percentage is the appearance rate of operations that do not require pattern data or source data Assume that The conventional drawing processor uses pattern data and source data once each, for a total of 2
Two read cycles are required. In contrast, the drawing processor of the present invention requires an average of 1.2 pattern data source data read cycles as shown in the following equation (7).

2 times × 0.3 + 1 times × 0.3 + 1 times × 0.3 + 0 times ×
0.1 = 1.2 times (7) When the equations (6) and (7) are added, 1.3 times is obtained. When the updated destination data write cycle is added to this, an average of 2.3 bus cycles are activated for drawing 8 bits. Conventional drawing processor is 4
Since it is necessary to start the bus cycle twice, a drawing performance improvement of 1.7 times can be expected as shown in the following equation (8).

4 times / 2.3 times = 1.7 times (8)

As described above, according to the present invention, since the data read cycle not involved in the drawing operation is omitted, the drawing speed can be improved accordingly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram illustrating an example of a conventional drawing processor.

FIG. 4 is a timing chart of signals of respective units for explaining the operation of the drawing processor shown in FIG. 3;

FIG. 5 is an image diagram for explaining a process of updating destination data by a drawing processor shown in FIG. 3;

6 is a configuration diagram and a configuration diagram of storage contents of a drawing calculation content storage unit of the drawing processor shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Destination data register 2 Source data register 3 Pattern data register 4 Drawing operation part 5 Drawing operation content storage part 6 Read cycle omission instruction part 7, 7a Bus cycle control part

Claims (1)

(57) [Claims] The first, second, and third data for storing and outputting the transmitted first, second, and third data for drawing, respectively.
A third register, a drawing operation unit that performs a predetermined operation on the first, second, and third data in accordance with the drawing operation signal and outputs the first data as updated first data;
A rendering calculation content storage unit for storing the content of the calculation for the second and third data and outputting the rendering calculation signal corresponding to the content of the calculation; and When there is data that can be omitted from the operation input in the first, second, and third data, a read cycle omission instruction unit that outputs a read cycle omission instruction signal corresponding to the data; the reading from the cycle skip instruction signal is not output data, after outputting the address signal, a read signal to the data memory, capture the first data transferred from the data memory of the third data, After sequentially executing a cycle of transmitting to the second and third registers, an address signal and a write signal for writing the updated first data to the data memory. And a bus cycle control unit for executing a cycle for outputting bets in the data memory, the drawing
The first bit of each word in the image operation content storage unit contains
The first data, the second data, and the third data
Data indicating whether a logical AND operation with inverted data is necessary
In the second bit, the first data and the second
Indicate necessity of AND operation of data and the third data
Data is stored in the third bit as the first data.
The data obtained by inverting the second data and the third data
The data indicating the necessity of the AND operation is stored in the fourth bit.
Is a data obtained by inverting the first data and the second data.
AND operation of the data and the inverted data of the third data
The data indicating the necessity of the calculation is stored in the fifth bit.
Data obtained by inverting the first data, the second data,
Necessity of AND operation with inverted data of the third data
Is stored in the sixth bit.
Data, the second data, and the third data.
The data indicating the necessity of the logical AND operation of the data is stored in the seventh
The bits include data obtained by inverting the first data and the data
Theory of the inverted data of the second data and the third data
The data indicating the necessity of logical operation is added to the 8th bit.
Is that of the first, second, and third data
Data indicating whether or not the logical AND operation of the inverted data is required
Data according to the contents of the drawing operation, and read out
The cycle omission instruction unit is provided from the drawing operation content storage unit.
By the bit data of each word output in order,
The first and fifth bits, the second and sixth bits,
The third and seventh bits, and the fourth and eighth bits
The exclusive OR is calculated, and the exclusive OR signal is calculated.
A NOT signal of a logical sum is output to the first data read cycle.
Generated as an omission instruction signal, and
Bit data of each word sequentially output from the storage unit
, The first and fourth bits, and the second and third bits
Bits, the fifth and eighth bits, and the sixth and seventh bits.
The exclusive OR is calculated for each
The NOT signal of the logical sum of the logical sum signal is read by reading the second data.
Output cycle omission instruction signal.
The video of each word output in order from the drawing operation content storage unit
The first and second bits of the bit data, the third and
4 bits, the fifth and sixth bits, the seventh and eighth bits
Exclusive OR each bit of
The negation signal of the logical sum of the other logical sum signals is transmitted to the third data.
As a read cycle omission instruction signal for the
A drawing processor, wherein the drawing processor transmits the signal to a bus cycle control unit .