JP2011187278A - Electron emission element, and electron source substrate and image display device using the same - Google Patents

Electron emission element, and electron source substrate and image display device using the same Download PDF

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JP2011187278A
JP2011187278A JP2010050442A JP2010050442A JP2011187278A JP 2011187278 A JP2011187278 A JP 2011187278A JP 2010050442 A JP2010050442 A JP 2010050442A JP 2010050442 A JP2010050442 A JP 2010050442A JP 2011187278 A JP2011187278 A JP 2011187278A
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potential side
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Takanori Suwa
高典 諏訪
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electron emission element which can achieve both an increase of an electron emission current and focusing of a beam diameter simultaneously. <P>SOLUTION: A first low potential side electrode 4 is arranged on a first side surface 21 of a first insulation layer 2, a first high potential side electrode 5 is arranged on a second side surface 22, and a second low potential side electrode 6 is arranged on the first insulation layer 2 through a second insulation layer 3. In addition, a second high potential side electrode 8 is arranged on the low potential side electrode 6 through a third insulation layer 7. Electrons are emitted from a gap 9 between the first low potential side electrode 4 and the second high potential side electrode 8, and a gap 10 between the first high potential side electrode 5 and the second low potential side electrode 6, respectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、フラットパネルディスプレイに用いられる画像表示装置と、これを構成する電子源基板及び電子放出素子に関するものである。   The present invention relates to an image display device used for a flat panel display, and an electron source substrate and an electron-emitting device constituting the image display device.

従来より、低電位側電極から出た電子の多数が対向する高電位側電極に衝突、散乱した後に電子として取り出される電子放出素子が存在する。このような形態で電子を放出する素子として表面伝導型電子放出素子や積層型の電子放出素子が知られている。例えば、特許文献1,2には、低電位側電極、絶縁層、高電位側電極を積層してなる電子放出素子が開示されており、高電位側電極の両側に電子放出部を設けることで、電子放出電流の増大を図っている。   Conventionally, there are electron-emitting devices in which a large number of electrons emitted from a low-potential side electrode are taken out as electrons after colliding with and scattering the opposed high-potential side electrode. As devices that emit electrons in such a form, surface conduction electron-emitting devices and stacked electron-emitting devices are known. For example, Patent Documents 1 and 2 disclose an electron-emitting device formed by laminating a low-potential side electrode, an insulating layer, and a high-potential side electrode, and by providing electron emitting portions on both sides of the high-potential side electrode. The electron emission current is increased.

特開2000−311587号公報JP 2000-311587 A 米国特許第6288494号明細書US Pat. No. 6,288,494

しかしながら特許文献1に示された電子放出素子は、高電位側電極の両側に設けた電子放出部から放出された電子がそれぞれ、アノードに向かって逆方向に放出される。そのため、高電位側電極の幅(電子放出部間の距離)によってはビーム径が広がってしまい、高精細なディスプレイに応用するには問題があった。本発明の課題は、電子放出電流の増大と、ビーム径の集束とを同時に実現する電子放出素子を提供し、高精細で高画質表示の画像表示装置を提供することを目的とする。   However, in the electron-emitting device disclosed in Patent Document 1, electrons emitted from the electron-emitting portions provided on both sides of the high potential side electrode are emitted in the opposite direction toward the anode. Therefore, depending on the width of the high potential side electrode (distance between the electron emission portions), the beam diameter is widened, which is problematic for application to a high-definition display. An object of the present invention is to provide an electron-emitting device that can simultaneously increase an electron-emitting current and focus a beam diameter, and to provide a high-definition and high-quality image display device.

本発明の第1は、上面と、該上面を挟む第1及び第2の側面とを有し、第1の側面の上面側の端部に第1の凹部を、第2の側面の上面側の端部に第2の凹部を有する第1の絶縁部材と、
第1の側面に配置し、一端が前記第1の凹部の縁に沿った第1の低電位側電極と、
第2の側面に配置し、一端が前記第2の凹部の縁に沿った第1の高電位側電極と、
前記第1の凹部よりも内側に後退した位置に第3の側面と、前記第2の側面の延長面上に、その面が一致する第4の側面と、を有し、前記第1の絶縁部材の前記上面に配置され、前記第2の凹部を介して第1の高電位側電極に対向する第2の低電位側電極と、
前記第1の凹部よりも内側に後退した位置に第5の側面を、前記第4の側面よりも内側に後退した位置に第6の側面を有し、前記第2の低電位側電極の第3の側面を覆って前記第2の低電位側電極の上に配置される第2の絶縁部材と、
前記第1の側面の延長面上に、その面が一致する第7の側面を有し、前記第1の凹部を介して前記第1の低電位側電極に対向し、前記第1の絶縁部材及び第2の絶縁部材の上に配置される第2の高電位側電極と、
を有することを特徴とする電子放出素子である。
The first aspect of the present invention has an upper surface and first and second side surfaces sandwiching the upper surface, the first concave portion at the upper surface side end portion of the first side surface, and the upper surface side of the second side surface A first insulating member having a second recess at an end thereof,
A first low potential side electrode disposed on the first side and having one end along the edge of the first recess;
A first high-potential side electrode disposed on the second side surface and having one end along the edge of the second recess;
A first side surface having a third side surface at a position retracted inward from the first concave portion, and a fourth side surface that coincides with an extended surface of the second side surface; A second low-potential side electrode disposed on the upper surface of the member and facing the first high-potential side electrode via the second recess;
A fifth side surface at a position retracted inward from the first recess, a sixth side surface at a position retracted inward from the fourth side surface, and a second side of the second low potential side electrode. A second insulating member disposed on the second low-potential side electrode so as to cover the side surface of the second low-potential side electrode;
The first insulating member has a seventh side surface that coincides with the extended surface of the first side surface, and faces the first low potential side electrode through the first recess. And a second high potential side electrode disposed on the second insulating member;
It is an electron emission element characterized by having.

本発明の第2は、基板と、前記基板上に配置した、複数の電子放出素子と、前記電子放出素子に電圧を印加するための配線とを備えた電子源基板であって、前記電子放出素子が前記本発明の電子放出素子であることを特徴とする。   A second aspect of the present invention is an electron source substrate comprising a substrate, a plurality of electron-emitting devices disposed on the substrate, and wiring for applying a voltage to the electron-emitting devices, The device is the electron-emitting device of the present invention.

本発明の第3は、前記本発明の電子源基板と、
前記電子源基板に形成された電子放出素子の第2の高電位側電極を介在させて、前記第1の低電位側電極及び第1の高電位側電極と対向配置されるアノードと、前記アノードに積層して配置された、前記電子放出素子から放出された電子の照射によって発光する発光部材と、
を有することを特徴とする画像表示装置である。
According to a third aspect of the present invention, the electron source substrate of the present invention,
An anode disposed opposite to the first low potential side electrode and the first high potential side electrode with a second high potential side electrode of the electron-emitting device formed on the electron source substrate interposed therebetween; A light emitting member that is disposed in a stacked manner and emits light by irradiation of electrons emitted from the electron emitter,
It is an image display apparatus characterized by having.

本発明によれば、電子放出素子内の2箇所から電子放出を行うため、電子放出電流の増大を図ることができる上、該2箇所から放出される電子がアノードに対して同じ方向に飛翔するため、容易にビーム径の集束を図ることができる。よって、本発明によれば、従来よりもより高精細で高画質表示の画像表示装置が実現する。   According to the present invention, since electrons are emitted from two locations in the electron-emitting device, the electron emission current can be increased, and electrons emitted from the two locations fly in the same direction with respect to the anode. Therefore, it is possible to easily focus the beam diameter. Therefore, according to the present invention, an image display device with higher definition and higher image quality than before can be realized.

本発明の電子放出素子の一実施形態の構成とその電子放出特性を測定する時の電源の供給配置を示す図である。It is a figure which shows the structure of one Embodiment of the electron-emitting element of this invention, and the supply arrangement | positioning of a power supply when measuring the electron emission characteristic. 従来の積層型電子放出素子における電子放出の様子と、該素子による発光部材の発光パターンを示す図である。It is a figure which shows the mode of the electron emission in the conventional multilayer electron emission element, and the light emission pattern of the light emission member by this element. 低電位側電極を高電位側電極よりもアノード側に配置した電子放出素子における電子放出の様子と、該素子による発光部材の発光パターンを示す図である。It is a figure which shows the mode of the electron emission in the electron emission element which has arrange | positioned the low potential side electrode to the anode side rather than the high potential side electrode, and the light emission pattern of the light emission member by this element. 低電位側電極を高電位側電極よりもアノード側に配置した電子放出素子における電子放出の様子と、該素子による発光部材の発光パターンを示す図である。It is a figure which shows the mode of the electron emission in the electron emission element which has arrange | positioned the low potential side electrode to the anode side rather than the high potential side electrode, and the light emission pattern of the light emission member by this element. 本発明の電子放出素子における電子放出の様子と、該素子による発光部材の発光パターンを示す図である。It is a figure which shows the mode of the electron emission in the electron emission element of this invention, and the light emission pattern of the light emission member by this element. 図1に示した電子放出素子の製造工程例を示す図である。It is a figure which shows the example of a manufacturing process of the electron emission element shown in FIG. 本発明の実施例において作製した比較例の電子放出素子の製造工程を示す図である。It is a figure which shows the manufacturing process of the electron-emitting element of the comparative example produced in the Example of this invention. 本発明の実施例において作製した電子放出素子を複数有する電子源基板の構成を示す図である。It is a figure which shows the structure of the electron source board | substrate which has multiple electron-emitting elements produced in the Example of this invention. 本発明の画像表示装置と該画像表示装置を構成する電子源基板の模式図である。1 is a schematic diagram of an image display device of the present invention and an electron source substrate constituting the image display device.

以下に図面を参照して、本発明の好適な実施形態を例示的に詳しく説明する。但し、この実施形態に記載されている構成部品の寸法、材質、形状、その相対配置などは、特に特定的な記載がない限りは、この発明の範囲をそれらのみに限定する趣旨のものではない。   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only to those unless otherwise specified. .

〔構成の概要〕
本発明の電子放出素子は、第1及び第2の絶縁部材、第1及び第2の低電位側電極、第1及び第2の高電位側電極を備えている。本発明の電子源基板は、本発明の電子放出素子を基板上に複数配置し、該素子に電圧を印加するための配線を備えている。さらに、本発明の画像表示装置は、上記本発明の電子放出素子を有する電子源基板と、該電子放出素子から放出された電子が到達するアノード及び該電子の照射によって発光する発光部材とを備えている。
[Configuration overview]
The electron-emitting device of the present invention includes first and second insulating members, first and second low potential side electrodes, and first and second high potential side electrodes. The electron source substrate of the present invention includes a plurality of the electron-emitting devices of the present invention arranged on a substrate and wiring for applying a voltage to the device. Furthermore, an image display device of the present invention includes an electron source substrate having the electron-emitting device of the present invention, an anode to which electrons emitted from the electron-emitting device reach, and a light-emitting member that emits light when irradiated with the electrons. ing.

図1(a)は本発明の電子放出素子の好ましい実施形態の構成を示す断面模式図である。図中、1は基板、2は第1の絶縁層、3は第2の絶縁層であり、第1の絶縁層2と第2の絶縁層3とを合わせたものが本発明に係る第1の絶縁部材である。本発明においては、形成が容易であることから、第1の絶縁部材として第1の絶縁層2の上に第2の絶縁層3を積層したものが好ましいが、本発明はこれに限定されるものではない。本発明において、第1の絶縁部材は互いに接しない第1及び第2の側面21,22を有し、それぞれの側面が、該側面間に挟まれた上面側の端部に、第1及び第2の凹部13,14を有している。図1(a)において、係る凹部13,14は、第2の絶縁層3の側面が第1の絶縁層2の第1及び第2の側面21,22から内側に後退した部分である。   FIG. 1A is a schematic cross-sectional view showing the configuration of a preferred embodiment of the electron-emitting device of the present invention. In the figure, 1 is a substrate, 2 is a first insulating layer, 3 is a second insulating layer, and the combination of the first insulating layer 2 and the second insulating layer 3 is the first according to the present invention. It is an insulating member. In the present invention, since the formation is easy, the first insulating member is preferably formed by laminating the second insulating layer 3 on the first insulating layer 2, but the present invention is limited to this. It is not a thing. In the present invention, the first insulating member has first and second side surfaces 21 and 22 that are not in contact with each other, and the respective side surfaces are disposed at the end portions on the upper surface side sandwiched between the side surfaces. Two recesses 13 and 14 are provided. In FIG. 1A, the concave portions 13 and 14 are portions where the side surfaces of the second insulating layer 3 are recessed inward from the first and second side surfaces 21 and 22 of the first insulating layer 2.

尚、本発明の電子放出素子に係る各部材の「側面」、「上面」及び上下関係は、便宜上、図1(a)に示す配置を前提として規定するものであり、図1(a)の配置において各部材の側面や上面、上下関係が本発明の規定を満たしていればよい。よって、電子放出素子全体の配置によっては、必ずしも「側面」が水平方向を、「上面」が垂直上方を向くものではなく、画像表示装置を構成した状態で、上記「側面」が垂直上方或いは下方、「上面」が水平方向或いは下方に向く場合も本発明の範疇である。   For convenience, the “side surface”, “upper surface”, and vertical relationship of each member according to the electron-emitting device of the present invention are defined on the assumption of the arrangement shown in FIG. In the arrangement, it is only necessary that the side surface, the upper surface, and the vertical relationship of each member satisfy the provisions of the present invention. Therefore, depending on the arrangement of the entire electron-emitting device, the “side surface” does not necessarily face in the horizontal direction and the “upper surface” does not face upward in the vertical direction. The case where the “upper surface” is directed horizontally or downward is also within the scope of the present invention.

第1の絶縁層2の第1の側面21には第1の低電位側電極4が、第2の側面22には第1の高電位側電極5が配置し、それぞれ、一端が凹部13,14の縁に沿って位置している。図1(a)において、第1の側面21は第1の絶縁層2の左側面であり、第2の側面22は第1の絶縁層2の右側面である。そして、第1の絶縁部材の上面である第2の絶縁層2の上面に第2の低電位側電極6が配置されており、その一側面(第4の側面24)が第2の側面22の延長面上に一致し、第2の凹部14を介して第1の高電位側電極5と対向している。また、第2の低電位側電極6の第3の側面23は、第2の絶縁層3の側面(即ち、第1の凹部13)よりも内側に後退した位置にある。   The first low potential side electrode 4 is disposed on the first side surface 21 of the first insulating layer 2, and the first high potential side electrode 5 is disposed on the second side surface 22. 14 along the edge. In FIG. 1A, the first side surface 21 is the left side surface of the first insulating layer 2, and the second side surface 22 is the right side surface of the first insulating layer 2. The second low potential side electrode 6 is disposed on the upper surface of the second insulating layer 2 that is the upper surface of the first insulating member, and one side surface (fourth side surface 24) thereof is the second side surface 22. Of the first high potential side electrode 5 through the second recess 14. In addition, the third side surface 23 of the second low potential side electrode 6 is in a position that is recessed inward from the side surface of the second insulating layer 3 (that is, the first recess 13).

本発明に係る第2の絶縁部材である第3の絶縁層7は第2の低電位側電極6上に配置される。係る第3の絶縁層7の一方の側面(第5の側面25)は第1の凹部13より内側に後退した位置にあり、他方の側面(第6の側面26)は第2の低電位側電極6の第4の側面24よりも内側に後退した位置にある。そして第3の絶縁層7は、第2の低電位側電極6の第3の側面23を覆っている。   The third insulating layer 7 which is the second insulating member according to the present invention is disposed on the second low potential side electrode 6. One side surface (fifth side surface 25) of the third insulating layer 7 is in a position retracted inward from the first concave portion 13, and the other side surface (sixth side surface 26) is the second low potential side. The electrode 6 is in a position retracted inward from the fourth side surface 24. The third insulating layer 7 covers the third side surface 23 of the second low potential side electrode 6.

第2の高電位側電極8は、第2の絶縁層3及び第3の絶縁層7の上に配置され、一方の側面(第7の側面27)は、第1の絶縁層2の第1の側面21の延長面上に一致する位置にある。また、他方の側面(第8の側面28)は、後述する所定の電界を形成できればその位置は特に限定されないが、製造上の容易さから、第2の低電位側電極6の第4の側面24の延長面上に一致するのが好ましい。   The second high potential side electrode 8 is disposed on the second insulating layer 3 and the third insulating layer 7, and one side surface (seventh side surface 27) is the first of the first insulating layer 2. It is in the position which corresponds on the extended surface of the side surface 21 of this. The position of the other side surface (eighth side surface 28) is not particularly limited as long as a predetermined electric field to be described later can be formed. However, for ease of manufacturing, the fourth side surface of the second low potential side electrode 6 is used. It is preferred that they coincide on the 24 extended surfaces.

本発明の電子放出素子においては、第1の低電位側電極4と第2の高電位側電極8との距離が最短である間隙9と、第1の高電位側電極5と第2の低電位側電極6との距離が最短である間隙10とから電子が放出される。また、11,12はそれぞれ第1の低電位側電極4及び第1の高電位側電極5に接続された電極である。   In the electron-emitting device of the present invention, the gap 9 in which the distance between the first low potential side electrode 4 and the second high potential side electrode 8 is the shortest, the first high potential side electrode 5 and the second low potential side electrode 8 is the same. Electrons are emitted from the gap 10 having the shortest distance from the potential side electrode 6. Reference numerals 11 and 12 denote electrodes connected to the first low potential side electrode 4 and the first high potential side electrode 5, respectively.

本発明の画像表示装置は、第2の高電位側電極8の上方、即ち第2の高電位側電極8を介在させて第1の低電位側電極4、第1の高電位側電極5と対向する位置に、第2の高電位側電極8よりも高電位に規定されたアノードを有している(図1(b)の20)。本例においては、第1の絶縁層2が基板1上に配置しているため、アノード20は該基板1の第1の絶縁層2が配置している側に、該基板1に対向配置されているとも言える。尚、本発明の画像表示装置においては、アノード20の外側(電子放出素子が位置する側とは反対側)に発光部材が積層配置される。   The image display device according to the present invention includes a first low potential side electrode 4, a first high potential side electrode 5, and a second high potential side electrode 8 interposed therebetween. An anode defined at a higher potential than the second high potential side electrode 8 is provided at the opposing position (20 in FIG. 1B). In this example, since the first insulating layer 2 is disposed on the substrate 1, the anode 20 is disposed opposite to the substrate 1 on the side where the first insulating layer 2 is disposed. It can be said that it is. In the image display device of the present invention, a light emitting member is laminated on the outside of the anode 20 (on the side opposite to the side where the electron-emitting device is located).

図1(b)は本発明の電子放出素子の電子放出特性を測定する時の電源の供給配置を示す。図1(b)に示すように、本発明においては、アノード20は、基板1の第1の絶縁層2が配置している側に該基板1に対向して配置される。図1(b)において、Vfは第1の低電位側電極4と第2の高電位側電極8の間に、第1の低電位側電極4を低電位側として印加される電圧である。また、Vfは第2の低電位側電極6と第1の高電位側電極5の間に、第2の低電位側電極6を低電位側として印加される電圧でもある。IfはVfを印加した時に流れる素子電流である。Vaは第1の低電位側電極4及び第2の低電位側電極6とアノード20の間に、アノード20を高電位側として印加される電圧であり、Va>Vfである。IeはVaを印加した時に流れる電子放出電流である。ここで、電子放出素子に電圧を印加した時に検出される電流Ifと真空中に取り出される電流Ieを用いて、電子放出効率η=Ie/(If+Ie)で与えられる。   FIG. 1B shows a power supply arrangement when measuring the electron emission characteristics of the electron-emitting device of the present invention. As shown in FIG. 1B, in the present invention, the anode 20 is disposed opposite to the substrate 1 on the side where the first insulating layer 2 of the substrate 1 is disposed. In FIG. 1B, Vf is a voltage applied between the first low potential side electrode 4 and the second high potential side electrode 8 with the first low potential side electrode 4 as the low potential side. Vf is also a voltage applied between the second low potential side electrode 6 and the first high potential side electrode 5 with the second low potential side electrode 6 as the low potential side. If is a device current that flows when Vf is applied. Va is a voltage applied between the first low potential side electrode 4 and the second low potential side electrode 6 and the anode 20 with the anode 20 as a high potential side, and Va> Vf. Ie is an electron emission current that flows when Va is applied. Here, the electron emission efficiency η = Ie / (If + Ie) is given by using the current If detected when a voltage is applied to the electron-emitting device and the current Ie taken out in vacuum.

図1(b)のように本発明の電子放出素子に電圧Vfを印加すると、間隙9、間隙10において、低電位側電極4,6の先端からそれぞれ対向する高電位側電極8,5に向かって電子がトンネリングし、電子が高電位側電極8,5の表面で等方的に散乱する。低電位側電極4,6から放出された電子は高電位側電極8,5の表面で数回の弾性散乱を繰り返した後、電圧Vaによって加速され、アノード20に向かう。間隙9,10からアノード20に向かう電子は、間隙9,10とアノード20の間に形成される電位の影響を受けた軌道を描いてアノード20に到達する。   When a voltage Vf is applied to the electron-emitting device of the present invention as shown in FIG. 1B, in the gap 9 and the gap 10, the tips of the low-potential-side electrodes 4 and 6 face the high-potential-side electrodes 8 and 5, respectively. As a result, electrons tunnel, and the electrons are isotropically scattered on the surfaces of the high potential side electrodes 8 and 5. The electrons emitted from the low potential side electrodes 4 and 6 are repeatedly elastically scattered several times on the surfaces of the high potential side electrodes 8 and 5, and then accelerated by the voltage Va and directed toward the anode 20. The electrons heading from the gaps 9 and 10 toward the anode 20 reach the anode 20 while drawing a trajectory affected by the potential formed between the gaps 9 and 10 and the anode 20.

〔電極の配置による電子のアノード到達位置について〕
ここで、電子放出素子から放出された電子がアノード20に到達する時の到達位置について図2乃至図5を用いて説明する。
[Electron anode arrival position by electrode arrangement]
Here, the arrival position when the electrons emitted from the electron-emitting device reach the anode 20 will be described with reference to FIGS.

〈両側電子放出、順極〉
図2(a)は従来型の積層型電子放出素子を用いた画像表示装置の構成を示したもので、36は低電位側電極、31は高電位側電極、40は低電位側電極36に接続された電極、33、38は電子放出に必要な電界が形成される間隙である。間隙33は低電位側電極36と高電位側電極31との距離が最短である部位、間隙38は低電位側電極4と高電位側電極31との距離が最短である部位である。尚、図1(a)と同じ部材には同じ符号を付した。また、Vfは低電位側電極4、36と高電位側電極31の間に印加する電圧、Vaは低電位側電極4、36とアノード20の間に印加する電圧、IfはVfを印加した時に流れる素子電流、IeはVaを印加した時に流れる電子放出電流である。破線34はVf,Vaを印加した時に形成される電界の等電位線、35は後述するよどみ点である。また、不図示であるが、アノード20の外側(電子放出素子が位置する側とは反対側)に発光部材が配置される。
<Double-sided electron emission, forward polarity>
FIG. 2A shows the configuration of an image display device using a conventional stacked electron-emitting device. 36 is a low potential side electrode, 31 is a high potential side electrode, and 40 is a low potential side electrode. The connected electrodes 33 and 38 are gaps in which an electric field necessary for electron emission is formed. The gap 33 is a part where the distance between the low potential side electrode 36 and the high potential side electrode 31 is shortest, and the gap 38 is a part where the distance between the low potential side electrode 4 and the high potential side electrode 31 is shortest. In addition, the same code | symbol was attached | subjected to the same member as Fig.1 (a). Vf is a voltage applied between the low potential side electrodes 4 and 36 and the high potential side electrode 31, Va is a voltage applied between the low potential side electrodes 4 and 36 and the anode 20, and If is applied when Vf is applied. The flowing element current, Ie, is an electron emission current that flows when Va is applied. A broken line 34 is an equipotential line of an electric field formed when Vf and Va are applied, and 35 is a stagnation point described later. Although not shown, a light emitting member is disposed outside the anode 20 (on the side opposite to the side where the electron-emitting device is located).

図2(a)の低電位側電極4、36と高電位側電極31の間に電圧Vfを印加すると、間隙33、38から電子が放出する。放出された電子は、高電位側電極31に向かい、高電位側電極31の表面で数回散乱を繰り返す。電圧Vf、Vaを同時に印加すると、高電位側電極31の電位に相当する等電位線が、高電位側電極31の表面と交わる点が生じる。これがよどみ点35である。   When a voltage Vf is applied between the low potential side electrodes 4 and 36 and the high potential side electrode 31 in FIG. 2A, electrons are emitted from the gaps 33 and 38. The emitted electrons travel toward the high potential side electrode 31 and are repeatedly scattered several times on the surface of the high potential side electrode 31. When the voltages Vf and Va are applied simultaneously, a point where an equipotential line corresponding to the potential of the high potential side electrode 31 intersects the surface of the high potential side electrode 31 is generated. This is the stagnation point 35.

ここで、間隙33から放出された電子について考える。高電位側電極31の表面で数回散乱を繰り返した後、よどみ点35を通る等電位線よりも間隙33から見て外側(図2(a)では左側、もしくは上側)に出るまでの間に、図2(a)で見て水平方向左側にも加速されて速度成分を得る。よどみ点35より外側に出た電子は電圧Vaによって加速されアノード20に到達するが、その間は水平方向の電界成分はほとんど無いため、水平方向成分については図2(a)で見て左側に向けてほぼ等速運動となる。つまり、間隙33から放出された電子のアノード20における到達位置は、間隙33の直上よりも図2(a)で見て左側にずれた位置になる。同様に、間隙38から放出された電子は、間隙33から放出された電子と左右逆で考えることができるので、間隙38から放出された電子のアノード20における到達位置は、間隙38の直上よりも図2(a)で見て右側にずれた位置になる。   Here, consider the electrons emitted from the gap 33. After repeating scattering several times on the surface of the high potential side electrode 31, until it comes out of the equipotential line passing through the stagnation point 35 as viewed from the gap 33 (on the left side or the upper side in FIG. 2A). As shown in FIG. 2 (a), the velocity component is obtained by accelerating the horizontal direction left side as well. Electrons emitted outside the stagnation point 35 are accelerated by the voltage Va and reach the anode 20, but there is almost no horizontal electric field component in the meantime, so the horizontal direction component is directed to the left as seen in FIG. Almost constant speed movement. That is, the arrival position of the electrons emitted from the gap 33 at the anode 20 is shifted to the left side as viewed in FIG. Similarly, since the electrons emitted from the gap 38 can be considered to be opposite to the electrons emitted from the gap 33, the arrival position of the electrons emitted from the gap 38 at the anode 20 is more than just above the gap 38. The position is shifted to the right as viewed in FIG.

アノード20に到達した電子は、アノード20の外側に配置された発光部材を発光させて画像を表示する。図2(a)に示した構成の電子放出素子によって得られる発光部材の発光パターンを図2(b)に示す。図2(b)中、Aは図2(a)の間隙33から放出された電子がアノード20に到達して発光させる領域、Bは図2(a)の間隙38から放出された電子がアノード20に到達して発光させる領域である。各領域の輪郭線はピーク輝度の10%範囲を示している。図2(a)の間隙33、38から放出された電子のアノード20における到達位置はそれぞれ左右逆方向にずれた位置になるため、図2(b)に示す通り、発光パターンもA,Bの2つに分かれた形で表示される。発光パターンの輪郭線の大きさLx、Ly(ビーム径)をシミュレーションで見積もる。図2(a)の基板1の表面からアノード20までの垂直方向距離H=1.6mm、Va=11.8kV,Vf=23Vの時、Lx=250μm、Ly=230μmとなる。また、図2(a)の構成で電子放出効率η=Ie/(If+Ie)は5.5%となる。   The electrons that have reached the anode 20 cause the light emitting member disposed outside the anode 20 to emit light and display an image. FIG. 2B shows a light emission pattern of the light emitting member obtained by the electron-emitting device having the configuration shown in FIG. 2B, A is a region where electrons emitted from the gap 33 in FIG. 2A reach the anode 20 to emit light, and B is an electron emitted from the gap 38 in FIG. 2A. This is a region that reaches 20 and emits light. The outline of each region indicates a 10% range of peak luminance. Since the arrival positions of the electrons emitted from the gaps 33 and 38 in FIG. 2A in the anode 20 are shifted in the left and right reverse directions, the light emission patterns of A and B are also shown in FIG. It is displayed in two forms. The size Lx, Ly (beam diameter) of the contour line of the light emission pattern is estimated by simulation. When the vertical distance H = 1.6 mm, Va = 11.8 kV, and Vf = 23 V from the surface of the substrate 1 to the anode 20 in FIG. 2A, Lx = 250 μm and Ly = 230 μm. Further, in the configuration of FIG. 2A, the electron emission efficiency η = Ie / (If + Ie) is 5.5%.

このように、図2(a)の構成では、高電位側電極31の両側に電子放出する間隙33,38を有するため、得られる電流(If、Ie)は大きくなる。一方で、それぞれの間隙33,38から放出された電子のアノード到達位置は互いに逆方向に大きくずれた位置となり、アノード20でのビーム径が広くなってしまうため、高精細なディスプレイに応用するには不都合である。   2A has the gaps 33 and 38 for emitting electrons on both sides of the high potential side electrode 31, the current (If, Ie) obtained is large. On the other hand, the anode arrival position of the electrons emitted from the gaps 33 and 38 is greatly shifted in the opposite direction, and the beam diameter at the anode 20 becomes wide, so that it can be applied to a high-definition display. Is inconvenient.

〈片側電子放出、逆極〉
図3(a),図4(a)は、低電位側電極を高電位側電極より上方に配置した構成を有する積層型電子放出素子を用いた画像表示装置の模式図である。図3(a),図4(a)において、図1(a)と同じ部材には同じ符号を付した。また、間隙43は低電位側電極6と第1の高電位側電極5との距離が最短の部位である。また、不図示であるが、アノード20の外側(電子放出素子が位置する側とは反対側)に発光部材が配置される。図3(a)と図4(a)の違いは、図4(a)では低電位側電極6の上に第3の絶縁層7、第2の高電位側電極8が積層されていることである。Vfは低電位側電極6と第1の高電位側電極5の間、及び低電位側電極6と第2の高電位側電極8の間に印加する電圧、Vaは低電位側電極6とアノード20の間に印加する電圧である。
<One-sided electron emission, reverse polarity>
FIGS. 3A and 4A are schematic views of an image display device using a stacked electron-emitting device having a configuration in which a low potential side electrode is disposed above a high potential side electrode. 3A and 4A, the same members as those in FIG. 1A are denoted by the same reference numerals. The gap 43 is a portion where the distance between the low potential side electrode 6 and the first high potential side electrode 5 is shortest. Although not shown, a light emitting member is disposed outside the anode 20 (on the side opposite to the side where the electron-emitting device is located). The difference between FIG. 3A and FIG. 4A is that the third insulating layer 7 and the second high potential side electrode 8 are laminated on the low potential side electrode 6 in FIG. 4A. It is. Vf is a voltage applied between the low potential side electrode 6 and the first high potential side electrode 5 and between the low potential side electrode 6 and the second high potential side electrode 8, Va is a low potential side electrode 6 and the anode. 20 is a voltage to be applied.

図3(a),図4(a)の電子放出素子に電圧Vfを印加すると、間隙43から電子が放出する。図3(a)について考えると、間隙43から放出された電子は、高電位側電極5、電極12に向かい、高電位側電極5もしくは電極12の表面で数回散乱を繰り返す。電圧Vf、Vaを同時に印加すると、高電位側電極5の電位に相当する等電位線が、高電位側電極5もしくは電極12の表面と交わる点が生じる。これがよどみ点35である。高電位側電極5又は電極12の表面で数回散乱を繰り返した電子は、よどみ点35を通る等電位線よりも間隙43から見て外側(図3(a)では右側)に出るまでに水平方向(図3(a)で見て右側)に加速される。よどみ点を超えた電子は電圧Vaによって加速されアノード20に到達するが、その間、水平方向への力はほとんど受けないため、水平方向にはほぼ等速運動となる。よって間隙43から出た電子のアノード到達位置は間隙43の直上より図3(a)で見て右側にずれた位置となる。即ち、電子のアノード到達位置のずれる方向が、図2(a)のような従来型の構成と比べて逆方向になっている。これは、高電位側電極5と低電位側電極6の配置が、電子放出する間隙から見て逆になっているために、放出された電子が受ける水平方向の電界による力も逆向きになっているからである。   When the voltage Vf is applied to the electron-emitting devices shown in FIGS. 3A and 4A, electrons are emitted from the gap 43. Considering FIG. 3A, electrons emitted from the gap 43 are directed to the high potential side electrode 5 and the electrode 12 and repeatedly scattered several times on the surface of the high potential side electrode 5 or the electrode 12. When the voltages Vf and Va are simultaneously applied, a point where an equipotential line corresponding to the potential of the high potential side electrode 5 intersects the surface of the high potential side electrode 5 or the electrode 12 is generated. This is the stagnation point 35. Electrons that have repeatedly scattered several times on the surface of the high potential side electrode 5 or the electrode 12 are horizontal before appearing from the equipotential line passing through the stagnation point 35 to the outside (right side in FIG. 3A). It is accelerated in the direction (right side as viewed in FIG. 3A). Electrons that exceed the stagnation point are accelerated by the voltage Va and reach the anode 20, but during that time, almost no force is applied in the horizontal direction, so that the movement in the horizontal direction is substantially constant. Therefore, the anode arrival position of the electrons emitted from the gap 43 is shifted to the right side as viewed in FIG. That is, the direction in which the electron arrival position of the electrons is shifted is opposite to that in the conventional configuration as shown in FIG. This is because the arrangement of the high-potential-side electrode 5 and the low-potential-side electrode 6 is reversed when viewed from the gap where electrons are emitted, and the force due to the horizontal electric field received by the emitted electrons is also reversed. Because.

但し、図3(a)では低電位側電極6から見てアノード20が高電位側電極5と反対側に配置されている。間隙43から出た電子は先ず高電位側電極5のある下側に向けて加速され、下向きの速度を得る。アノード20は高電位側電極5と反対側にあるため、アノード5に印加する電圧Vaの影響は受けにくく、高電位側電極5に引っ張られる力の影響のみを受けて、さらに下側に向けて加速されるため、高電位側電極5での散乱回数が増大してしまう。   However, in FIG. 3A, the anode 20 is disposed on the side opposite to the high potential side electrode 5 when viewed from the low potential side electrode 6. The electrons emitted from the gap 43 are first accelerated toward the lower side where the high-potential-side electrode 5 is present to obtain a downward velocity. Since the anode 20 is on the side opposite to the high potential side electrode 5, it is not easily affected by the voltage Va applied to the anode 5, and is only affected by the force pulled by the high potential side electrode 5, and further toward the lower side. Because of the acceleration, the number of times of scattering at the high potential side electrode 5 increases.

次に図4(a)の構成について考えると、第1の高電位側電極5とそれと等電位な第2の高電位側電極8の間に低電位側電極6が挟まれる構成となっているため、第1の高電位側電極5と第2の高電位側電極8の間をつなぐような等電位線が生じる。間隙43から出た電子の中には、図3(a)と同様に図4(a)で見て右向きの速度成分を得るとともに、第1の高電位側電極5と第2の高電位側電極8のいずれからも離れていくような軌道を描く電子が比較的多数存在する。よって、間隙43から放出された電子のアノード到達位置は、図3(a)と同様に図4(a)で見て右側にずれる。同時に、図3(a)と比べ高電位側電極での散乱回数も低減することができる。   Next, considering the configuration of FIG. 4A, the low potential side electrode 6 is sandwiched between the first high potential side electrode 5 and the second high potential side electrode 8 that is equipotential thereto. Therefore, an equipotential line that connects between the first high potential side electrode 5 and the second high potential side electrode 8 is generated. Among the electrons emitted from the gap 43, a velocity component in the right direction as viewed in FIG. 4A is obtained as in FIG. 3A, and the first high potential side electrode 5 and the second high potential side are obtained. There are a relatively large number of electrons that draw orbits away from any of the electrodes 8. Therefore, the anode arrival position of the electrons emitted from the gap 43 is shifted to the right side as seen in FIG. 4A as in FIG. At the same time, the number of times of scattering at the high potential side electrode can be reduced as compared with FIG.

アノード20に到達した電子は、アノード20の外側に配置された発光部材を発光させ画像を表示する。図3(a)に示した構成の電子放出素子によって得られる発光部材の発光パターンを図3(b)に、図4(a)に示した構成の電子放出素子によって得られる発光部材の発光パターンを図4(b)に示す。発光パターンの輪郭線はピーク輝度の10%範囲を示している。発光パターンの輪郭線の大きさLx、Ly(ビーム径)をシミュレーションで見積もる。図3(a)、図4(a)の基板1の表面からアノード20までの垂直方向距離H=1.6mm、Va=11.8kV,Vf=23Vの時、図3(a)ではLx=140μm、Ly=250μm、図4(b)ではLx=130μm、Ly=250μmとなる。また図3(a)、図4(a)に示す構成で電子放出効率ηをシミュレーションで見積もると、図3(a)では1.5%、図4(a)では5.5%となる。よって、図4(a)のように電子放出する間隙43を挟んで両側に高電位側電極5,8を配置する構成とすることで、電子放出効率は大幅に改善する。   The electrons that have reached the anode 20 cause the light emitting member disposed outside the anode 20 to emit light and display an image. The light emission pattern of the light emitting member obtained by the electron emission element having the configuration shown in FIG. 3A is shown in FIG. 3B, and the light emission pattern of the light emission member obtained by the electron emission element having the configuration shown in FIG. Is shown in FIG. The contour line of the light emission pattern indicates a 10% range of the peak luminance. The size Lx, Ly (beam diameter) of the contour line of the light emission pattern is estimated by simulation. When the vertical distance H = 1.6 mm, Va = 11.8 kV, and Vf = 23 V from the surface of the substrate 1 to the anode 20 in FIGS. 3A and 4A, Lx = in FIG. 3A. 140 μm, Ly = 250 μm. In FIG. 4B, Lx = 130 μm and Ly = 250 μm. Further, when the electron emission efficiency η is estimated by simulation with the configuration shown in FIGS. 3A and 4A, it is 1.5% in FIG. 3A and 5.5% in FIG. 4A. Therefore, as shown in FIG. 4A, the electron emission efficiency is significantly improved by arranging the high potential side electrodes 5 and 8 on both sides of the gap 43 for emitting electrons.

〈両側、一方順極、他方逆極+第2の高電位側電極〉
図5(a)は本発明の画像表示装置の好ましい実施形態の構成と、形成される等電位線、電子軌道の軌跡を示す模式図である。図5(a)の電子放出素子の構成は、図2(a)の構成と比較して、一方の側面(図2(a)で見て右側面)を図4(a)のような構成に置き換えた電子放出素子の構成ということができる。図5(a)中、図1(a)と同じ部材には同じ符号を付した。また、不図示であるが、アノード20の外側(電子放出素子が位置する側とは反対側)に発光部材が配置される。
<Both sides, one forward electrode, the other reverse electrode + second high potential side electrode>
FIG. 5A is a schematic diagram showing the configuration of a preferred embodiment of the image display device of the present invention, and the equipotential lines and the trajectory of the electron trajectory formed. The configuration of the electron-emitting device in FIG. 5A is configured as shown in FIG. 4A on one side surface (right side as viewed in FIG. 2A) as compared to the configuration in FIG. It can be said that the structure of the electron-emitting device is replaced with. In FIG. 5A, the same members as those in FIG. Although not shown, a light emitting member is disposed outside the anode 20 (on the side opposite to the side where the electron-emitting device is located).

図5(a)の間隙9から放出された電子は、図2(a)の構成と同様に電子のアノード到達位置は図5(a)で見て右側にずれる。一方、図5(a)の間隙10から放出された電子は、図4(a)の構成と同等であるため、電子のアノード到達位置は図5(a)で見て右側にずれる。つまり、電子のアノード到達位置は間隙9、10のいずれから放出された電子についても図5(a)で見て同じ方向(右側)にずれることになる。アノード20に到達した電子は、アノード20の外側に配置された発光部材を発光させ画像を表示する。   As for the electrons emitted from the gap 9 in FIG. 5A, the anode arrival position of the electrons is shifted to the right as viewed in FIG. On the other hand, the electrons emitted from the gap 10 in FIG. 5A are equivalent to the configuration in FIG. 4A, so that the anode arrival position of the electrons is shifted to the right as viewed in FIG. That is, the position where electrons reach the anode is shifted in the same direction (right side) as viewed in FIG. The electrons that have reached the anode 20 cause the light emitting member disposed outside the anode 20 to emit light and display an image.

図5(a)に示した構成の電子放出素子によって得られる発光部材の発光パターンを図5(b)に示す。発光パターンの輪郭線はピーク輝度の10%範囲を示している。実線の輪郭線は主として間隙10から放出された電子によるもの、破線の輪郭線は主として間隙9から放出された電子によるものであり、間隙9,10から放出された電子のアノード到達位置はほぼ同じ位置となっている。発光パターンの輪郭線の大きさLx、Ly(ビーム径)をシミュレーションで見積もると、図5(a)の基板1の表面からアノード20までの垂直方向距離H=1.6mm、Va=11.8kV,Vf=23Vの時、Lx=130μm、Ly=250μmとなる。図2(a)のような構成で得られる発光パターン(図2(b)参照)と比べると、y方向のビーム径は多少広がっているものの、x方向のビーム径が大幅に抑制されていることがわかる。また図5(a)に示す構成で電子放出効率ηをシミュレーションで見積もると、5.5%となり、図2(a)に示す構成とほぼ同等といえる。   FIG. 5B shows a light emission pattern of the light emitting member obtained by the electron-emitting device having the configuration shown in FIG. The contour line of the light emission pattern indicates a 10% range of the peak luminance. The solid outline is mainly due to electrons emitted from the gap 10, and the dashed outline is mainly due to electrons emitted from the gap 9, and the anode arrival positions of the electrons emitted from the gaps 9 and 10 are almost the same. Is in position. When the sizes Lx and Ly (beam diameters) of the contour lines of the light emission pattern are estimated by simulation, the vertical distance H = 1.6 mm and Va = 11.8 kV from the surface of the substrate 1 to the anode 20 in FIG. , Vf = 23 V, Lx = 130 μm and Ly = 250 μm. Compared with the light emission pattern (see FIG. 2B) obtained with the configuration as shown in FIG. 2A, the beam diameter in the y direction is slightly widened, but the beam diameter in the x direction is greatly suppressed. I understand that. Further, when the electron emission efficiency η is estimated by simulation with the configuration shown in FIG. 5A, it is 5.5%, which is almost equivalent to the configuration shown in FIG.

以上より、図5(a)のような構成の電子放出素子では、電流が増大し、高い電子放出効率を得られ、且つアノード20におけるビーム径を抑制した特性を得られることがわかる。   From the above, it can be seen that in the electron-emitting device having the configuration as shown in FIG. 5A, the current increases, a high electron-emitting efficiency can be obtained, and the characteristics in which the beam diameter at the anode 20 is suppressed can be obtained.

〔製造方法〕
図6を参照して、図1(a)に例示した電子放出素子の製造方法の一例を説明する。図6は、図1(a)に示した電子放出素子の製造工程を示す模式図である。
〔Production method〕
With reference to FIG. 6, an example of the manufacturing method of the electron-emitting device illustrated in FIG. FIG. 6 is a schematic view showing a manufacturing process of the electron-emitting device shown in FIG.

〈基板1の形成〉
図6の基板1は素子を機械的に支えるための基板であり、石英ガラス、Na等の不純物含有量を減少させたガラス、青板ガラス及び、シリコン基板である。基板に必要な機能としては、機械的強度が高いだけでなく、ドライエッチング、ウェットエッチング、現像液等のアルカリや酸に対して耐性があり、ディスプレイパネルのような一体ものとして用いる場合は成膜材料や他の積層部材と熱膨張差が小さいものが望ましい。また熱処理に伴いガラス内部からのアルカリ元素等が拡散しづらい材料が望ましい。
<Formation of substrate 1>
A substrate 1 in FIG. 6 is a substrate for mechanically supporting the element, and is a quartz glass, glass with reduced impurity content such as Na, blue plate glass, and a silicon substrate. The necessary functions of the substrate include not only high mechanical strength but also resistance to alkalis and acids such as dry etching, wet etching, and developer, and film formation when used as an integrated display panel. A material or a material having a small difference in thermal expansion from other laminated members is desirable. Further, it is desirable to use a material in which alkali elements or the like from the inside of the glass are difficult to diffuse with heat treatment.

〈絶縁層101、102の形成〉
先ず最初に、図6(a)に示すように基板1上に第1の絶縁部材を形成するために絶縁層101、102を積層する。絶縁層101,102は、加工性に優れる材料からなる絶縁性の膜であり、例えばSiN(Sixy)やSiO2であり、その作製方法はスパッタ法等の一般的な真空成膜法、CVD法、真空蒸着法で形成される。またその厚さとしては、絶縁層101は20nm乃至50μmの範囲で設定され、好ましくは50nm乃至500nmの範囲に選択され、絶縁層102は20nm乃至500nmの範囲で設定され、好ましくは20nm乃至50nmの範囲で選択される。尚、絶縁層101と102を積層した後に絶縁層102の側面を後退させるため、絶縁層101と絶縁層102とはエッチングに対して異なるエッチング量を持つような関係に設定する。望ましくは絶縁層101と絶縁層102との間のエッチング量の比は、10以上が望ましく、50以上が望ましい。例えば、絶縁層101はSixyを用い、絶縁層102はSiO2等絶縁性材料、或いはリン濃度の高いPSG、ホウ素濃度の高いBSG膜等で構成する事ができる。
<Formation of insulating layers 101 and 102>
First, as shown in FIG. 6A, insulating layers 101 and 102 are stacked on the substrate 1 in order to form a first insulating member. The insulating layers 101 and 102 are insulating films made of a material with excellent workability, such as SiN (Si x N y ) or SiO 2 , and the manufacturing method thereof is a general vacuum film forming method such as a sputtering method. The CVD method and the vacuum deposition method are used. The thickness of the insulating layer 101 is set in the range of 20 nm to 50 μm, preferably in the range of 50 nm to 500 nm, and the insulating layer 102 is set in the range of 20 nm to 500 nm, preferably 20 nm to 50 nm. Selected by range. Note that in order to recede the side surface of the insulating layer 102 after the insulating layers 101 and 102 are stacked, the relationship between the insulating layer 101 and the insulating layer 102 is set so as to have different etching amounts with respect to etching. Desirably, the ratio of the etching amount between the insulating layer 101 and the insulating layer 102 is desirably 10 or more, and desirably 50 or more. For example, the insulating layer 101 can be made of Si x N y , and the insulating layer 102 can be made of an insulating material such as SiO 2 , PSG having a high phosphorus concentration, a BSG film having a high boron concentration, or the like.

〈導電層103の形成〉
さらに、図6(a)に示すように導電層103を積層する。導電層103は蒸着法、スパッタ法等の一般的真空成膜技術により形成されるものである。導電層103の材料は、導電性に加えて高い熱伝導率があり、融点が高い材料が望ましい。例えば、Be,Mg,Ti,Zr,Hf,V,Nb,Ta,Mo,W,Al,Cu,Ni,Cr,Au,Pt,Pd等の金属または合金材料が使用できる。また、TiC,ZrC,HfC,TaC,SiC,WC等の炭化物、HfB2,ZrB2,CeB6,YB4,GdB4等の硼化物、TiN,ZrN,HfN、TaN等の窒化物、Si,Ge等の半導体なども使用可能である。また、有機高分子材料、アモルファスカーボン、グラファイト、ダイヤモンドライクカーボン、ダイヤモンドを分散した炭素及び炭素化合物等も適宜使用可能である。また、導電層103の厚さとしては、20nm乃至500nmの範囲で設定され、好ましくは50nm乃至500nmの範囲で選択される。
<Formation of conductive layer 103>
Further, a conductive layer 103 is stacked as shown in FIG. The conductive layer 103 is formed by a general vacuum film forming technique such as vapor deposition or sputtering. The material of the conductive layer 103 is preferably a material having high thermal conductivity and high melting point in addition to conductivity. For example, metals or alloy materials such as Be, Mg, Ti, Zr, Hf, V, Nb, Ta, Mo, W, Al, Cu, Ni, Cr, Au, Pt, and Pd can be used. Also, carbides such as TiC, ZrC, HfC, TaC, SiC, WC, borides such as HfB 2 , ZrB 2 , CeB 6 , YB 4 , GdB 4 , nitrides such as TiN, ZrN, HfN, TaN, Si, A semiconductor such as Ge can also be used. Moreover, organic polymer materials, amorphous carbon, graphite, diamond-like carbon, carbon in which diamond is dispersed, a carbon compound, and the like can be used as appropriate. Further, the thickness of the conductive layer 103 is set in the range of 20 nm to 500 nm, and preferably selected in the range of 50 nm to 500 nm.

〈導電層103を加工〉
フォトリソグラフィー技術により導電層103上にレジストパターンを形成した後、エッチング手法を用いて導電層103を加工し、図6(b)に示すように、第3の側面23を形成する。このようなエッチング加工では一般的にエッチングガスをプラズマ化して材料に照射することで材料の精密なエッチング加工が可能なRIE(Reactive Ion Etching)が用いられる。この際の加工ガスとしては、加工する対象部材としてフッ化物を作る場合はCF4、CHF3、SF6のフッ素系ガスが選ばれる。またSiやAlのように塩化物を形成する場合はCl2、BCl3などの塩素系ガスが選ばれる。またレジストとの選択比を取るため、またエッチング面の平滑性の確保或いはエッチングスピードを上げるために水素や酸素、アルゴンガスなどが随時添加される。
<Processing the conductive layer 103>
After a resist pattern is formed on the conductive layer 103 by a photolithography technique, the conductive layer 103 is processed using an etching method, and the third side surface 23 is formed as shown in FIG. 6B. In such an etching process, RIE (Reactive Ion Etching) is generally used in which an etching gas is turned into plasma and irradiated on the material to enable precise etching of the material. As the processing gas at this time, a fluorine-based gas such as CF 4 , CHF 3 , or SF 6 is selected in the case of producing a fluoride as a target member to be processed. In the case of forming a chloride such as Si or Al, a chlorine-based gas such as Cl 2 or BCl 3 is selected. Further, hydrogen, oxygen, argon gas, or the like is added as needed to obtain a selection ratio with the resist, to ensure the smoothness of the etched surface, or to increase the etching speed.

〈絶縁層105の形成〉
続いて図6(c)に示すように絶縁層105を積層する。絶縁層105は、加工性に優れる材料からなる絶縁性の膜であり、例えばSiN(Sixy)やSiO2であり、その作製方法はスパッタ法等の一般的な真空成膜法、CVD法、真空蒸着法で形成される。また絶縁層105の厚さとしては20nm乃至50μmの範囲で設定され、好ましくは50nm乃至500nmの範囲に選択される。但し、第2の高電位側電極8と第2の低電位側電極6との間で電子放出しないように、絶縁層105の厚さは絶縁層102の厚さよりも大きくする必要がある。尚、絶縁層105を積層した後に第6の側面26を後退させるため、絶縁層101と絶縁層105とはエッチングに対して異なるエッチング量を持つような関係に設定する。望ましくは絶縁層101と絶縁層105との間のエッチング量の比は、10以上が望ましく、50以上が望ましい。例えば、絶縁層101はSixyを用い、絶縁層105はSiO2等絶縁性材料、或いはリン濃度の高いPSG、ホウ素濃度の高いBSG膜等で構成する事ができる。
<Formation of insulating layer 105>
Subsequently, an insulating layer 105 is stacked as shown in FIG. The insulating layer 105 is an insulating film made of a material with excellent workability, and is, for example, SiN (Si x N y ) or SiO 2 , and its manufacturing method is a general vacuum film forming method such as a sputtering method, CVD, or the like. Formed by a vacuum evaporation method. The thickness of the insulating layer 105 is set in the range of 20 nm to 50 μm, and preferably in the range of 50 nm to 500 nm. However, the thickness of the insulating layer 105 needs to be larger than the thickness of the insulating layer 102 so that electrons are not emitted between the second high potential side electrode 8 and the second low potential side electrode 6. Note that, since the sixth side surface 26 is retracted after the insulating layer 105 is stacked, the insulating layer 101 and the insulating layer 105 are set so as to have different etching amounts with respect to etching. Desirably, the ratio of the etching amount between the insulating layer 101 and the insulating layer 105 is desirably 10 or more, and desirably 50 or more. For example, the insulating layer 101 can be made of Si x N y , and the insulating layer 105 can be made of an insulating material such as SiO 2 , PSG having a high phosphorus concentration, a BSG film having a high boron concentration, or the like.

〈絶縁層105を加工〉
フォトリソグラフィー技術により絶縁層105上にレジストパターンを形成した後、エッチング手法を用いて加工し、図6(d)に示すように、第5の側面25を形成する。このようなエッチング加工としては、前記導電層103の加工で述べた方法を用いることができる。
<Processing the insulating layer 105>
A resist pattern is formed on the insulating layer 105 by a photolithography technique and then processed using an etching technique to form the fifth side face 25 as shown in FIG. As such etching processing, the method described in the processing of the conductive layer 103 can be used.

〈導電層107の形成〉
続いて図6(e)に示すように導電層107を積層する。導電層107は蒸着法、スパッタ法等の一般的真空成膜技術により形成されるものである。導電層107は導電性があり、電界放出する材料であればよく、一般的には2000℃以上の高融点、5eV以下の仕事関数材料であり、酸化物等の化学反応層の形成しづらい或いは簡易に反応層を除去可能な材料が好ましい。このような材料として例えば、Hf,V,Nb,Ta,Mo,W,Au,Pt,Pd等の金属又は合金材料が使用可能である。また、前記導電層103の形成材料として挙げた炭化物、硼化物、窒化物も使用可能である。またさらには、アモルファスカーボン、グラファイト、ダイヤモンドライクカーボン、ダイヤモンドを分散した炭素及び炭素化合物等も使用可能である。導電層107は、蒸着法、スパッタ法等の一般的真空成膜技術により形成される。また、導電層107の厚さとしては、20nm乃至500nmの範囲で設定され、好ましくは50nm乃至500nmの範囲で選択される。
<Formation of conductive layer 107>
Subsequently, a conductive layer 107 is laminated as shown in FIG. The conductive layer 107 is formed by a general vacuum film forming technique such as vapor deposition or sputtering. The conductive layer 107 may be any material that is conductive and emits electric field, and is generally a high melting point of 2000 ° C. or higher and a work function material of 5 eV or lower, and it is difficult to form a chemical reaction layer such as an oxide or A material capable of easily removing the reaction layer is preferable. As such a material, for example, a metal or alloy material such as Hf, V, Nb, Ta, Mo, W, Au, Pt, and Pd can be used. Further, the carbides, borides, and nitrides mentioned as the material for forming the conductive layer 103 can also be used. Furthermore, amorphous carbon, graphite, diamond-like carbon, carbon in which diamond is dispersed, a carbon compound, and the like can also be used. The conductive layer 107 is formed by a general vacuum film forming technique such as vapor deposition or sputtering. Further, the thickness of the conductive layer 107 is set in the range of 20 nm to 500 nm, and is preferably selected in the range of 50 nm to 500 nm.

〈各層をエッチング〉
フォトリソグラフィー技術により導電層107上にレジストパターンを形成した後、エッチング手法を用いて導電層107、絶縁層105、導電層103、絶縁層102、絶縁層101を順に加工する。その結果、図6(f)に示すように、第1の絶縁層2、絶縁層102、第2の低電位側電極6、絶縁層105、第2の高電位側電極8が得られる。また、当該工程により、第1の絶縁層2の第1の側面21及び第2の側面22、第1の側面21の延長面上に一致する高電位側電極8の第7の側面27、第2の側面22の延長面上に一致する第2の低電位側電極6の第4の側面24が形成される。また、第2の側面22の延長面上に第2の高電位側電極8の第8の側面28も一致して形成されるが、本発明においては、図5(a)で説明した電界が構成されれば、係る構成に限定されるものではない。このようなエッチング加工の方法としては、前記導電層103の加工で述べた方法を用いることができる。
<Etching each layer>
After a resist pattern is formed over the conductive layer 107 by a photolithography technique, the conductive layer 107, the insulating layer 105, the conductive layer 103, the insulating layer 102, and the insulating layer 101 are sequentially processed by an etching method. As a result, as shown in FIG. 6F, the first insulating layer 2, the insulating layer 102, the second low potential side electrode 6, the insulating layer 105, and the second high potential side electrode 8 are obtained. In addition, by this process, the first side surface 21 and the second side surface 22 of the first insulating layer 2, the seventh side surface 27 of the high potential side electrode 8 that coincides with the extended surface of the first side surface 21, A fourth side surface 24 of the second low potential side electrode 6 is formed on the extended surface of the second side surface 22. Further, although the eighth side surface 28 of the second high potential side electrode 8 is also formed on the extended surface of the second side surface 22, the electric field described with reference to FIG. As long as it is configured, it is not limited to such a configuration. As the etching method, the method described in the processing of the conductive layer 103 can be used.

〈絶縁層102、105の側面を後退させて第2の絶縁層3、第3の絶縁層7を形成〉
図6(g)に示すように、絶縁層102と絶縁層105をエッチングして、それぞれの露出した側面を内側に後退させる。これにより、第1の側面21,第2の側面22よりも内側に後退した側面を有する第2の絶縁層3が形成される。即ち、第1の絶縁部材の第1の凹部13と第2の凹部14とが形成される。同時に、第2の側面22及び第4の側面24よりも内側に後退した第6の側面26を有する第3の絶縁層7が形成される。エッチングは、例えば絶縁層102,105がSiO2からなる材料であれば、通称バッファーフッ酸(BHF)と呼ばれるフッ化アンモニウムとフッ酸との混合溶液を用い、Sixyからなる材料であれば熱リン酸系エッチング液を使用することが可能である。第1の絶縁層2の側面21から第2の絶縁層3の側面までの距離L(第1の凹部13の深さ)は、素子形成後のリーク電流に深く関わり、Lを大きく形成するほどリーク電流の値が小さくなる。しかし、あまり距離を深く形成すると高電位側電極が変形する等の課題が発生する。このため、Lはおよそ30nm乃至200nm程度で形成される。同様に、第2の凹部14の深さLも30nm乃至200nm程度で形成される。
<The second insulating layer 3 and the third insulating layer 7 are formed by retreating the side surfaces of the insulating layers 102 and 105>
As shown in FIG. 6G, the insulating layer 102 and the insulating layer 105 are etched to retract the exposed side surfaces inward. As a result, the second insulating layer 3 having side surfaces that recede inward from the first side surface 21 and the second side surface 22 is formed. That is, the first recess 13 and the second recess 14 of the first insulating member are formed. At the same time, the third insulating layer 7 having the sixth side face 26 that recedes inward from the second side face 22 and the fourth side face 24 is formed. For example, if the insulating layers 102 and 105 are made of SiO 2 , the etching may be a material made of Si x N y using a mixed solution of ammonium fluoride and hydrofluoric acid, commonly called buffer hydrofluoric acid (BHF). For example, a hot phosphoric acid etching solution can be used. The distance L (depth of the first recess 13) from the side surface 21 of the first insulating layer 2 to the side surface of the second insulating layer 3 is deeply related to the leakage current after the element is formed, and the larger L is formed. The value of the leakage current is reduced. However, if the distance is formed too deep, problems such as deformation of the high potential side electrode occur. For this reason, L is formed with a thickness of about 30 nm to 200 nm. Similarly, the depth L of the second recess 14 is also formed to be about 30 nm to 200 nm.

〈剥離層109の形成〉
図6(h)に示すように、第2の高電位側電極8と第2の低電位側電極6の表面に剥離層109を形成する。剥離層109の形成は、次の工程で堆積する導電性膜110を第2の高電位側電極8、第2の低電位側電極6から剥離することが目的である。このような目的のため、例えば電解メッキにて剥離金属を付着させるなどの方法によって剥離層109を形成する。
<Formation of release layer 109>
As shown in FIG. 6 (h), a release layer 109 is formed on the surfaces of the second high potential side electrode 8 and the second low potential side electrode 6. The purpose of forming the peeling layer 109 is to peel the conductive film 110 deposited in the next step from the second high potential side electrode 8 and the second low potential side electrode 6. For this purpose, the release layer 109 is formed by a method such as attaching a release metal by electrolytic plating, for example.

〈導電性膜110の形成〉
図6(i)に示すように、導電性膜110を第2の高電位側電極8の外表面、第2の低電位側電極6の第4の側面24、第1の絶縁層2の第1及び第2の側面21,22に付着させる。導電性膜110としては、前記した導電層107と同じ材料が好ましく用いられ、形成方法も同様である。次いで、図6(j)に示すように、剥離層110をエッチングで取り除くことで、第2の高電位側電極8と第2の低電位側電極6の外表面上の導電性膜110が取り除かれ、第1の低電位側電極4と第1の高電位側電極5が形成される。導電性膜110の好ましい厚さは5nm乃至80nmである。次に図6(k)に示すように、第1の低電位側電極4と電気的な導通を取るために電極11を形成し、第1の高電位側電極5と電気的な導通を取るために電極12を形成する。この電極11、12は、前記導電性膜110と同様に導電性を有しており、蒸着法、スパッタ法等の一般的真空成膜技術、フォトリソグラフィー技術により形成される。電極11、12の材料としては、前記した導電層103と同じ材料が好ましく用いられる。電極11、12の厚さとしては、50nm乃至5mmの範囲で設定され、好ましくは50nm乃至5μmの範囲で選択される。
<Formation of Conductive Film 110>
As shown in FIG. 6 (i), the conductive film 110 is formed on the outer surface of the second high potential side electrode 8, the fourth side surface 24 of the second low potential side electrode 6, and the first surface of the first insulating layer 2. The first and second side surfaces 21 and 22 are attached. For the conductive film 110, the same material as that of the conductive layer 107 is preferably used, and the formation method is also the same. Next, as shown in FIG. 6J, the peeling layer 110 is removed by etching, so that the conductive film 110 on the outer surfaces of the second high potential side electrode 8 and the second low potential side electrode 6 is removed. Thus, the first low potential side electrode 4 and the first high potential side electrode 5 are formed. A preferable thickness of the conductive film 110 is 5 nm to 80 nm. Next, as shown in FIG. 6 (k), an electrode 11 is formed to establish electrical continuity with the first low potential side electrode 4, and electrical continuity is established with the first high potential side electrode 5. Therefore, the electrode 12 is formed. The electrodes 11 and 12 have conductivity similar to the conductive film 110, and are formed by a general vacuum film forming technique such as vapor deposition or sputtering, or a photolithography technique. As the material of the electrodes 11 and 12, the same material as that of the conductive layer 103 is preferably used. The thickness of the electrodes 11 and 12 is set in the range of 50 nm to 5 mm, and preferably selected in the range of 50 nm to 5 μm.

次に、図9を参照し、本発明の電子源基板と画像表示装置について説明する。図9(a)は、本発明の電子源基板の好ましい実施形態を示す平面模式図である。また図9(b)は、本発明の画像表示装置の一例の断面構造を示す模式図である。   Next, the electron source substrate and the image display device of the present invention will be described with reference to FIG. FIG. 9A is a schematic plan view showing a preferred embodiment of the electron source substrate of the present invention. FIG. 9B is a schematic diagram showing a cross-sectional structure of an example of the image display device of the present invention.

本発明の電子源基板93は、図9(a)に示されるように、基板1上に本発明の電子放出素子92を複数備えている。該素子92は、信号線90、走査線91からなるマトリクス配線に接続され、不図示の駆動回路によって所定のアドレスからの電子放出が制御されるようになっている。   As shown in FIG. 9A, the electron source substrate 93 of the present invention includes a plurality of electron-emitting devices 92 of the present invention on the substrate 1. The element 92 is connected to a matrix wiring composed of a signal line 90 and a scanning line 91, and electron emission from a predetermined address is controlled by a drive circuit (not shown).

本例の画像表示装置96は、図9(b)に示すように、電子放出素子92を有する電子源基板93と、発光基板97とを対向させて組み合わせ、周囲に枠94を配置した真空容器を形成することで作製される。発光基板97は、少なくともアノードと、該アノードに積層配置された発光部材とを備えている。一般的には、ガラス基板のような透明基板の内側に発光部材として蛍光体等を配置し、さらに内側にアノードを配置する。また、真空容器として形成した画像表示装置96内には、通常、耐大気圧保持のために、上記発光基板97と電子源基板93との間にスペーサー(不図示)を介在させている。発光基板97のアノードには不図示の高圧電源から高圧電圧が供給され、電子源基板93から放出される電子を発光基板97の発光部材に照射して発光させることになる。   As shown in FIG. 9B, the image display device 96 of this example is a vacuum container in which an electron source substrate 93 having an electron-emitting device 92 and a light-emitting substrate 97 are combined so as to face each other, and a frame 94 is arranged around them. It is produced by forming. The light emitting substrate 97 includes at least an anode and a light emitting member stacked on the anode. In general, a phosphor or the like is disposed as a light emitting member inside a transparent substrate such as a glass substrate, and an anode is disposed further inside. In addition, in the image display device 96 formed as a vacuum container, a spacer (not shown) is usually interposed between the light emitting substrate 97 and the electron source substrate 93 in order to maintain atmospheric pressure resistance. A high voltage is supplied to the anode of the light emitting substrate 97 from a high voltage power source (not shown), and the light emitted from the electron source substrate 93 is irradiated to the light emitting member of the light emitting substrate 97 to emit light.

以上、本発明の好適な実施形態を説明したが、本発明の要旨を逸脱しない範囲で、上記実施形態とは異なる種々の態様で実施することができる。   The preferred embodiments of the present invention have been described above. However, the present invention can be implemented in various modes different from the above embodiments without departing from the gist of the present invention.

(実施例1)
図1に示した構成の電子放出素子を、図6の工程に従って作製した。先ず、図6(a)に示すように、低ナトリウムガラスであるPD200を基板1として用い、絶縁層101として厚さ500nmのSiN(Sixy)膜をスパッタ法にて形成し、次いで絶縁層102として厚さ23nmのSiO2膜をスパッタ法にて形成した。さらに、絶縁層102上に、導電層103として、厚さ30nmのTaN膜をスパッタ法にて形成した。次に、フォトリソグラフィー技術により導電層103上にレジストパターンを形成した後、ドライエッチング手法を用いて導電層103を加工し、図6(b)に示すように、第3の側面23を形成した。この時の加工ガスとしては、導電層103には前述のようにフッ化物を作る材料が選択されているためCF4系のガスが用いられた。レジストを剥離した後、図6(c)に示すように、絶縁層105として厚さ40nmのSiO2膜をスパッタ法にて形成した。
Example 1
The electron-emitting device having the configuration shown in FIG. 1 was fabricated according to the process of FIG. First, as shown in FIG. 6A, a low-sodium glass PD 200 is used as the substrate 1, and a SiN (Si x N y ) film having a thickness of 500 nm is formed as the insulating layer 101 by sputtering, followed by insulation. A SiO 2 film having a thickness of 23 nm was formed as the layer 102 by sputtering. Further, a TaN film having a thickness of 30 nm was formed as a conductive layer 103 on the insulating layer 102 by a sputtering method. Next, after forming a resist pattern on the conductive layer 103 by a photolithography technique, the conductive layer 103 was processed using a dry etching method, and the third side surface 23 was formed as shown in FIG. 6B. . As the processing gas at this time, a CF 4 -based gas was used for the conductive layer 103 because a material for forming a fluoride was selected as described above. After removing the resist, as shown in FIG. 6C, a SiO 2 film having a thickness of 40 nm was formed as the insulating layer 105 by sputtering.

次に、フォトリソグラフィー技術により絶縁層105上にレジストパターンを形成した後、ドライエッチング手法を用いて絶縁層105を加工し、図6(d)に示すように、第5の側面25を形成した。この時の加工ガスとしては、絶縁層105には前述のようにフッ化物を作る材料が選択されているためCF4系のガスを用いた。レジストを剥離した後、図6(e)に示すように、導電層107として厚さ30nmのモリブデン(Mo)膜をスパッタ法にて形成した。次に、フォトリソグラフィー技術により導電層107上にレジストパターンを形成した後、ドライエッチング手法を用いて導電層107、絶縁層105、導電層103、絶縁層102、絶縁層101を順に加工した。その結果、図6(f)に示すように、第1の絶縁層2、絶縁層102、第2の低電位側電極6、絶縁層105、第2の高電位側電極8からなる積層体を形成した。レジストパターンは、ドライエッチング加工後に高電位側電極8の幅(第1の側面21と第2の側面22との距離)が10μmとなるようにレジストパターンを形成した。この時の加工ガスとしては、導電層107、絶縁層105、導電層103、絶縁層102、絶縁層101には前述のようにフッ化物を作る材料が選択されているためCF4系のガスを用いた。 Next, after forming a resist pattern on the insulating layer 105 by a photolithography technique, the insulating layer 105 was processed using a dry etching method, and the fifth side surface 25 was formed as shown in FIG. . As the processing gas at this time, CF 4 -based gas was used for the insulating layer 105 because the material for producing fluoride was selected as described above. After the resist was peeled off, a molybdenum (Mo) film having a thickness of 30 nm was formed as the conductive layer 107 by sputtering as shown in FIG. Next, after a resist pattern was formed on the conductive layer 107 by a photolithography technique, the conductive layer 107, the insulating layer 105, the conductive layer 103, the insulating layer 102, and the insulating layer 101 were sequentially processed by a dry etching method. As a result, as shown in FIG. 6 (f), a laminate composed of the first insulating layer 2, the insulating layer 102, the second low potential side electrode 6, the insulating layer 105, and the second high potential side electrode 8 is formed. Formed. The resist pattern was formed so that the width of the high potential side electrode 8 (distance between the first side surface 21 and the second side surface 22) was 10 μm after dry etching. As a processing gas at this time, CF 4 type gas is used for the conductive layer 107, the insulating layer 105, the conductive layer 103, the insulating layer 102, and the insulating layer 101 because the material for forming fluoride is selected as described above. Using.

レジストを剥離した後、図6(g)に示すように、BHFを用いて凹部の深さが約120nmになるように絶縁層102と絶縁層105をエッチングし、第2の絶縁層3と第3の絶縁層7を形成した。次に、図6(h)に示すように、第2の高電位側電極8、第2の低電位側電極6の表面に電解めっきによりNiを電解析出させて剥離層109を形成した。図6(i)に示すように、導電性膜110としてモリブデン(Mo)をEB蒸着法を用いて形成した。始めに基板の角度を水平面に対し図6(i)から見て右回りに60°にセットして成膜後、続いて基板の角度を水平面に対し図6(i)から見て左回りに60°にセットして成膜した。蒸着は約12nm/minになるように蒸着速度を定めた。そして蒸着時間を精密に制御し(本例では右回り60°セットで1分、左回り60°セットで1分)、第1の絶縁層2の第1の側面21、第2の側面22にそれぞれ厚さ18nmのMoが形成されるようにした。Mo膜を形成後、図6(j)に示すように、ヨウ素とヨウ化カリウムからなるエッチング液を用いてNi剥離層109を除去することにより、第2の高電位側電極8、第2の低電位側電極6からMo材料110を剥離した。   After the resist is removed, as shown in FIG. 6G, the insulating layer 102 and the insulating layer 105 are etched using BHF so that the depth of the recess becomes about 120 nm, and the second insulating layer 3 and the second insulating layer 105 are etched. 3 insulating layers 7 were formed. Next, as shown in FIG. 6H, Ni was electrolytically deposited on the surfaces of the second high potential side electrode 8 and the second low potential side electrode 6 by electrolytic plating to form a release layer 109. As shown in FIG. 6 (i), molybdenum (Mo) was formed as the conductive film 110 by EB vapor deposition. First, the film is formed by setting the angle of the substrate to 60 ° clockwise as viewed in FIG. 6 (i) with respect to the horizontal plane, and then the counterclockwise angle of the substrate with respect to the horizontal plane as viewed in FIG. 6 (i). The film was set at 60 °. The deposition rate was determined so that the deposition was about 12 nm / min. Then, the deposition time is precisely controlled (in this example, 1 minute for a clockwise 60 ° set, 1 minute for a 60 ° counterclockwise set), and the first side surface 21 and the second side surface 22 of the first insulating layer 2 are applied. Each 18 nm thick Mo was formed. After forming the Mo film, as shown in FIG. 6 (j), the Ni peeling layer 109 is removed using an etching solution made of iodine and potassium iodide, whereby the second high potential side electrode 8, the second The Mo material 110 was peeled from the low potential side electrode 6.

以上の方法で電子放出素子を形成した後、図1(b)に示す構成にて電子放出特性を評価した。尚、アノード20の外側(電子放出素子が位置する側とは反対側)に発光部材を配置した。その結果、Vf=23V、Va=11.8kVを印加した時、If=61μA,Ie=3.2μA、η=5.2%であった。本例の電子線装置によって得られた発光パターンは、図5(b)に示す通りであり、ピーク輝度の範囲Lx、Lyを測ったところ、Lx=135μm、Ly=255μmであった。   After the electron-emitting device was formed by the above method, the electron emission characteristics were evaluated with the configuration shown in FIG. A light emitting member was disposed outside the anode 20 (on the side opposite to the side where the electron-emitting device is located). As a result, when Vf = 23 V and Va = 11.8 kV were applied, If = 61 μA, Ie = 3.2 μA, and η = 5.2%. The light emission pattern obtained by the electron beam apparatus of this example is as shown in FIG. 5B. When the peak luminance ranges Lx and Ly were measured, Lx = 135 μm and Ly = 255 μm.

(比較例1)
次に、図2(a)に示すような構成の電子放出素子を、図7に示す工程に従って作製した。先ず、実施例1と同様に絶縁層101、絶縁層102、導電層103を形成した(図7(a))。その後、導電層103上にフォトリソグラフィー技術でレジストパターンを形成後、ドライエッチング手法を用いて導電層103、絶縁層102、絶縁層101を順に加工し、絶縁層2、絶縁層102、高電位側電極31を形成した(図7(b))。レジストを剥離した後、実施例1と同様に絶縁層102をエッチングし、絶縁層3を形成した(図7(c))。その後、実施例1と同様に高電位側電極31の表面に剥離層109を形成し(図7(d))、絶縁層2の側面、高電位側電極31の表面、基板1の表面に導電性膜110を形成した(図7(e))。その後、剥離層109を除去して高電位側電極31上の導電性膜110を剥離した(図7(f))。
(Comparative Example 1)
Next, an electron-emitting device having a configuration as shown in FIG. 2A was fabricated according to the process shown in FIG. First, the insulating layer 101, the insulating layer 102, and the conductive layer 103 were formed as in Example 1 (FIG. 7A). Then, after forming a resist pattern on the conductive layer 103 by a photolithography technique, the conductive layer 103, the insulating layer 102, and the insulating layer 101 are sequentially processed using a dry etching method, and the insulating layer 2, the insulating layer 102, and the high potential side are processed. An electrode 31 was formed (FIG. 7B). After removing the resist, the insulating layer 102 was etched in the same manner as in Example 1 to form the insulating layer 3 (FIG. 7C). Thereafter, as in Example 1, a release layer 109 is formed on the surface of the high potential side electrode 31 (FIG. 7D), and the side surface of the insulating layer 2, the surface of the high potential side electrode 31, and the surface of the substrate 1 are electrically conductive. The property film | membrane 110 was formed (FIG.7 (e)). Thereafter, the release layer 109 was removed, and the conductive film 110 on the high potential side electrode 31 was peeled off (FIG. 7F).

以上の方法で電子放出素子を形成した後、実施例1と同様にアノードと発光部材を配置し、実施例1と同様の方法で電子放出素子の特性を評価した。その結果、Vf=23V、Va=11.8kVを印加した時、If=60μA,Ie=3.2μA、η=5.3%であった。本例の電子線装置によって得られた発光パターンは図2(a)の通りであり、ピーク輝度の範囲Lx、Lyを測ったところ、Lx=240μm、Ly=235μmであった。実施例1と比べると、本例では電流Ie,If,電子放出効率ηはほぼ同等で、アノードでのビーム径は実施例1の方がY方向(Ly)はやや広がっているものの、X方向(Lx)は大幅に狭まっており、本発明による効果を確認することができた。   After forming the electron-emitting device by the above method, the anode and the light emitting member were arranged in the same manner as in Example 1, and the characteristics of the electron-emitting device were evaluated in the same manner as in Example 1. As a result, when Vf = 23 V and Va = 11.8 kV were applied, If = 60 μA, Ie = 3.2 μA, and η = 5.3%. The light emission pattern obtained by the electron beam apparatus of this example is as shown in FIG. 2A. When the peak luminance ranges Lx and Ly were measured, Lx = 240 μm and Ly = 235 μm. Compared to Example 1, in this example, the currents Ie, If and electron emission efficiency η are substantially the same, and the beam diameter at the anode is slightly wider in the Y direction (Ly) in Example 1, but in the X direction. (Lx) was significantly narrowed, and the effect of the present invention could be confirmed.

(実施例2)
本例では、図8(a)に示すように、実施例1の電子放出素子を基板上に複数並べた電子源基板を構成した。基本的な作製方法は実施例1(図6(a)乃至(k))と同様である。電子放出素子が4つ横に並び、且つ、高電位側電極8の幅(W1)はいずれも10μm、高電位側電極8の端から隣接する高電位側電極8の端までの距離(W2)は10μmとなるようにレジストパターンを形成した。
(Example 2)
In this example, as shown in FIG. 8A, an electron source substrate in which a plurality of the electron-emitting devices of Example 1 are arranged on the substrate is configured. The basic manufacturing method is the same as that of Example 1 (FIGS. 6A to 6K). Four electron-emitting devices are arranged side by side, the width (W1) of the high potential side electrode 8 is 10 μm, and the distance (W2) from the end of the high potential side electrode 8 to the end of the adjacent high potential side electrode 8 A resist pattern was formed so as to be 10 μm.

以上の方法で電子源を形成した後、実施例1と同様にアノードと発光部材を配置し、実施例1と同様の方法で電子放出特性を評価した結果、Vf=23V、Va=11.8kVを印加した時、If=232μA,Ie=12.5μA、η=5.4%であった。本例の電子線装置によって得られた発光パターンを図8(b)に示す。発光パターンの輪郭線はピーク輝度の10%範囲を示している。図8(b)の発光パターンを見ると、実施例1で得られた発光パターン(図2(b))を横に重ね合わせた形状にほぼ等しく、隣接した積層体によって形成される電界の影響は大きくないことがわかった。図8(b)のピーク輝度の範囲Lx、Lyを測ったところ、Lx=200μm、Ly=255μmであった。   After the electron source was formed by the above method, the anode and the light emitting member were arranged in the same manner as in Example 1, and the electron emission characteristics were evaluated in the same manner as in Example 1. As a result, Vf = 23V and Va = 11.8kV. Were applied, If = 232 μA, Ie = 12.5 μA, and η = 5.4%. The light emission pattern obtained by the electron beam apparatus of this example is shown in FIG. The contour line of the light emission pattern indicates a 10% range of the peak luminance. Looking at the light emission pattern of FIG. 8B, the light emission pattern obtained in Example 1 (FIG. 2B) is almost equal to the shape of the horizontal superimposition, and the influence of the electric field formed by the adjacent laminates. Was not big. When the peak luminance ranges Lx and Ly in FIG. 8B were measured, Lx = 200 μm and Ly = 255 μm.

4:第1の低電位側電極、5:第1の高電位側電極、6:第2の低電位側電極、8:第2の高電位側電極、20:アノード、21:第1の側面、22:第2の側面、23:第4の側面、24:第4の側面、25:第5の側面、26:第6の側面、27:第7の側面   4: 1st low potential side electrode, 5: 1st high potential side electrode, 6: 2nd low potential side electrode, 8: 2nd high potential side electrode, 20: Anode, 21: 1st side surface , 22: second side, 23: fourth side, 24: fourth side, 25: fifth side, 26: sixth side, 27: seventh side

Claims (3)

上面と、該上面を挟む第1及び第2の側面とを有し、第1の側面の上面側の端部に第1の凹部を、第2の側面の上面側の端部に第2の凹部を有する第1の絶縁部材と、
第1の側面に配置し、一端が前記第1の凹部の縁に沿った第1の低電位側電極と、
第2の側面に配置し、一端が前記第2の凹部の縁に沿った第1の高電位側電極と、
前記第1の凹部よりも内側に後退した位置に第3の側面と、前記第2の側面の延長面上に、その面が一致する第4の側面と、を有し、前記第1の絶縁部材の前記上面に配置され、前記第2の凹部を介して第1の高電位側電極に対向する第2の低電位側電極と、
前記第1の凹部よりも内側に後退した位置に第5の側面を、前記第4の側面よりも内側に後退した位置に第6の側面を有し、前記第2の低電位側電極の第3の側面を覆って前記第2の低電位側電極の上に配置される第2の絶縁部材と、
前記第1の側面の延長面上に、その面が一致する第7の側面を有し、前記第1の凹部を介して前記第1の低電位側電極に対向し、前記第1の絶縁部材及び第2の絶縁部材の上に配置される第2の高電位側電極と、
を有することを特徴とする電子放出素子。
An upper surface and first and second side surfaces sandwiching the upper surface; a first recess on the upper surface side end portion of the first side surface; and a second recess surface on the upper surface side end portion of the second side surface. A first insulating member having a recess;
A first low potential side electrode disposed on the first side and having one end along the edge of the first recess;
A first high-potential side electrode disposed on the second side surface and having one end along the edge of the second recess;
A first side surface having a third side surface at a position retracted inward from the first concave portion, and a fourth side surface that coincides with an extended surface of the second side surface; A second low-potential side electrode disposed on the upper surface of the member and facing the first high-potential side electrode via the second recess;
A fifth side surface at a position retracted inward from the first recess, a sixth side surface at a position retracted inward from the fourth side surface, and a second side of the second low potential side electrode. A second insulating member disposed on the second low-potential side electrode so as to cover the side surface of the second low-potential side electrode;
The first insulating member has a seventh side surface that coincides with the extended surface of the first side surface, and faces the first low potential side electrode through the first recess. And a second high potential side electrode disposed on the second insulating member;
An electron-emitting device comprising:
基板と、前記基板上に配置した、複数の電子放出素子と、前記電子放出素子に電圧を印加するための配線とを備えた電子源基板であって、前記電子放出素子が請求項1に記載の電子放出素子であることを特徴とする電子源基板。   2. An electron source substrate comprising a substrate, a plurality of electron-emitting devices disposed on the substrate, and a wiring for applying a voltage to the electron-emitting devices, wherein the electron-emitting devices are defined in claim 1. An electron source substrate characterized by being an electron-emitting device. 請求項2に記載の電子源基板と、
前記電子源基板に形成された電子放出素子の第2の高電位側電極を介在させて、前記第1の低電位側電極及び第1の高電位側電極と対向配置されるアノードと、前記アノードに積層して配置された、前記電子放出素子から放出された電子の照射によって発光する発光部材と、
を有することを特徴とする画像表示装置。
An electron source substrate according to claim 2,
An anode disposed opposite to the first low potential side electrode and the first high potential side electrode with a second high potential side electrode of the electron-emitting device formed on the electron source substrate interposed therebetween; A light emitting member that is disposed in a stacked manner and emits light by irradiation of electrons emitted from the electron emitter,
An image display device comprising:
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