JP2011182288A - Power amplifier, and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce phase shift between a power source of an amplifier and an input of the amplifier. <P>SOLUTION: A power amplifier includes: an amplifier 101; a power source modulator 104 for varying a power supply voltage of the amplifier in accordance with a signal amplitude of an input signal; and a delay circuit 102a for delaying the input signal and providing it to an input of the amplifier. A control method is provided for a power amplifier including a power source modulator for varying a power supply voltage of an amplifier in accordance with a signal amplitude of an input signal and for delaying the input signal and controlling to provide the input signal to an input of the amplifier, thereby reducing phase shift between the power source of the amplifier and the input of the amplifier. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power amplifier and a control method thereof, and more particularly to an envelope tracking type power amplifier for amplifying a high-frequency signal, and a technique for correcting delay of an amplitude signal (AM signal) path and a phase signal (PM signal) path in the power amplifier. About.

  The power consumption of the power amplifier for amplifying the transmission signal in the radio equipment occupies a large proportion of the power consumption in the radio equipment. In order to reduce the power of the radio equipment, it is essential to reduce the power of the power amplifier. . The envelope tracking type power amplifier is connected to a power supply modulator for changing the power supply voltage in accordance with the signal amplitude. According to such a configuration, the power supply voltage supplied to the power amplifier (amplifier) is synchronized with the signal amplitude, so that the power consumed wasted is reduced, and as a result, the overall efficiency is improved, that is, the wireless device Overall power reduction is realized.

  By the way, the power supply modulator often uses a digital amplifier for higher efficiency, and therefore, various filters (mainly low-pass filters) are incorporated in order to remove quantization noise caused by digital amplification. Although the use of this filter is indispensable for noise removal, the delay due to the filter and the delay due to the feedback of the digital amplifier have values of several ns to several tens ns, which is useless between the signal amplitude and the power supply waveform. Causes a phase shift.

  Conventionally, as a method for solving this phase shift, the following four methods or combinations thereof are mainly known.

  The first method is a method of detecting the output of the power amplifier using a signal detection circuit or a detection circuit and feeding back the result to the power supply modulator. The method of Patent Document 1 corresponds to this.

  The second method is a method of inserting a digital delay circuit immediately before the signal input terminal of the power amplifier. The methods disclosed in Patent Documents 2 and 4 are a combination of this method and the feedback of the first method.

  The third method is a method in which a delay is applied at the time of generating a modulated waveform from the IQ signal. The technique of Patent Document 3 is a technique that combines this technique and the feedback of the first technique.

  The fourth method is a method of inserting an analog delay circuit. The simplest method is to insert a very long transmission line. As a variation, there is a method of amplifying the attenuation by the delay circuit through a circuit with a large delay as in Patent Document 5.

JP 2005-184866 A JP 2005-287011 A JP 2006-174418 A JP 2005-203960 A JP 2006-203456 A

  The following analysis is given in the present invention.

  By the way, the conventional method has the following various problems.

  The first method of feedback is the use of a carrier wave of about 2 GHz and a modulated wave of 5 MHz, like a WCDMA (Wideband Code Division Multiple Access) signal or LTE (Long Term Evolution) signal in a mobile phone, and a delay. When the amount is several tens of ns, the delay is too large. Therefore, when feedback is applied, the operation becomes unstable and may oscillate. Therefore, it is realistic to perform delay adjustment using the following second and third methods based on the feedback result.

  The second method, the insertion of a digital delay circuit, is the simplest method for delaying an early signal in order to correct the delay. However, in Patent Documents 2 and 4 using this method, the digital block is an oscillator using a voltage controlled oscillator (VCO). In this configuration, when a WCDMA signal or an LTE signal is used, the operating frequency of each block is severe, and many of the configurations cannot be realized with the current technology.

  The third method, delay generation from an IQ signal, is used in a radio base station, but it is difficult to use this method in a portable terminal. This is because in the current mobile terminal market, the producers of digital signal processing blocks and power amplifier blocks are different, so adding or changing blocks beyond the boundary between the two is the use of the corresponding product. It is difficult to realize this.

  The fourth method, the use of an analog delay device, is not practical in implementation. For example, in order to realize a delay of 1 ns with a simple transmission line, a wiring of 30 cm is necessary, and the size becomes very large. There is also a circuit that configures a normal analog delay circuit and changes the delay time by changing the constant of the low-pass filter. However, in the case of an envelope tracking type power amplifier used in a cellular phone or the like, the carrier wave has a frequency in the vicinity of 1 to 2 GHz, whereas the delay time is as large as several ns to several tens of ns. When used, the cutoff frequency is lower than the carrier wave included in the PM signal, and a necessary signal is cut off. In Patent Document 5, this attenuated signal is amplified by an amplifier. However, even if an envelope tracking type power amplifier is originally introduced for the purpose of lowering the power, if an additional amplifier is required, its consumption is reduced. The power cannot be reduced by power, and the meaning of using an envelope tracking type power amplifier is lost.

  Accordingly, an object of the present invention is to reduce the phase shift between the output potential (amplitude signal, AM signal) of the power supply modulator and the amplified signal (phase signal, PM signal) of the amplifier in the envelope tracking type power amplifier. It is an object of the present invention to provide a power amplifier and a control method thereof that perform delay compensation that is reduced, stable, and highly feasible.

  A power amplifier according to one aspect of the present invention includes an amplifier, a power supply modulator that changes the power supply voltage of the amplifier according to the signal amplitude of the input signal, and delays the input signal and supplies the input signal to the amplifier input. A delay circuit.

  A power amplifier control method according to another aspect of the present invention is a power amplifier control method including an amplifier and a power supply modulator that changes a power supply voltage of the amplifier according to the signal amplitude of an input signal. Thus, the input signal is controlled to be delayed and supplied to the input of the amplifier.

  According to the present invention, since the input signal is delayed and supplied to the input of the amplifier, the phase shift between the power supply of the amplifier and the input of the amplifier can be reduced.

1 is a block diagram showing a configuration of a power amplifier according to a first example of the present invention. It is a circuit diagram of a low-pass filter in which a unit circuit is configured as a ladder from an inductor and a capacitive element. FIG. 3 is a circuit diagram of a low-pass filter in which a unit circuit is configured as a ladder from a resistor element and a capacitor element. It is a block diagram which shows the structure of the power amplifier which concerns on the 2nd Example of this invention. It is a figure which shows the calculation result of the delay waveform by a filter. It is a block diagram which shows the structure of the power amplifier which concerns on the 3rd Example of this invention. It is a circuit diagram of one delay circuit concerning the 3rd example of the present invention. It is a circuit diagram of the other delay circuit based on the 3rd Example of this invention.

  A power amplifier according to an embodiment of the present invention includes an amplifier (corresponding to 101 in FIG. 1), a power supply modulator (corresponding to 104 in FIG. 1) that changes the power supply voltage of the amplifier according to the signal amplitude of the input signal, A delay device (corresponding to 102a in FIG. 1) that delays the input signal and supplies the input signal to the input of the amplifier.

  In the power amplifier, the delay unit (corresponding to 102b in FIG. 4) is composed of one or more types of multiple-stage analog delay circuits (corresponding to 107 in FIG. 4), and the total delay time in the multiple-stage analog delay circuits. However, it is preferable that the delay time be compensated for the delay associated with the power supply voltage change of the amplifier with respect to the input signal.

  In the power amplifier, the analog delay circuit (corresponding to 107a in FIG. 2 and 107b in FIG. 3) is configured by a ladder-type circuit, and a capacitance value, an inductor value, and a resistance value in a passive element that is a component of the ladder-type circuit. The delay time in the analog delay circuit may be changed by changing any one or a combination thereof.

  In the power amplifier, the delay time in the analog delay circuit may be changed by changing any one of a capacitance value, an inductor value, and a resistance value, or a combination thereof, by external control.

  In the power amplifier, the delay in the analog delay circuit (corresponding to 107c in FIG. 6) is changed by changing any one of the capacitance value, the inductor value, and the resistance value based on the detection result of the output of the amplifier. You may make it change time.

  In a power amplifier, a delay time in a delay device (corresponding to 102d in FIG. 8) is selected from any one of analog delay circuits in a plurality of stages of analog delay circuits by switching, short-circuiting, interrupting, or invalidating paths. May be set.

  The transmitter may include the above power amplifier.

  A wireless device may include the transmitter described above.

  A power amplifier according to an embodiment of the present invention is an envelope tracking type amplifier having an amplifier (power amplifier) that amplifies a signal and a power supply modulator that changes the power supply voltage of the power amplifier according to the signal amplitude of the signal to be amplified. In order to compensate for the delay between the amplified signal and the power supply voltage, a delay circuit is provided in the amplified signal path (PM signal path).

  In the delay circuit provided in the amplified signal path, the delay circuit is composed of one or more types of analog circuits, and the analog circuit has a feature of causing a delay at the same time as passing the amplified signal. It is preferable that the total delay value in the stage analog circuit is a delay time for compensating for the delay between the amplified signal and the power supply voltage.

  An analog delay circuit is used as the delay circuit. Each delay circuit is insufficient to compensate for the delay between the AM signal and the PM signal. However, by connecting the delay circuits in multiple stages, the amplified signal is delayed and output to obtain a necessary delay amount. Is possible. For this purpose, an analog delay circuit is inserted in the PM signal path. This analog delay circuit may have any configuration as long as it allows a signal to be amplified to pass through and generates a delay even if it has a small value.

  In the analog delay circuit, the capacitance value, the inductor value, the resistance value, the power supply voltage, or the current value constituting the analog circuit may be changed by external control, and the delay time of the analog circuit may be changed.

  In the analog delay circuit, the capacitance value, inductor value, resistance value, power supply voltage, and current value that make up the analog delay circuit may be changed based on the output detection result to set the optimal delay time. Good.

  In a multi-stage analog circuit, an optimum delay time may be set by switching, short-circuiting, blocking, and invalidating a part of the analog circuits of the multi-stage analog circuit.

  Embodiments will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a power amplifier according to a first embodiment of the present invention. In FIG. 1, the power amplifier includes a power amplifier 101, a power supply modulator 104, a delay device 102a, and a detector 115.

  The detector 115 detects an amplitude signal (AM signal) from the amplified signal that is an input signal, and outputs it to the power supply modulator 104. The power supply modulator 104 is, for example, a voltage controlled current parallel (VCCP) power supply modulator, amplifies the amplitude signal, and supplies the amplified signal to the power amplifier 101 as a power supply voltage of the power amplifier 101. The delay unit 102a includes an analog delay circuit 107. In order to correct a delay time in the power supply modulator 104, the detector 115, and the like with respect to the amplified signal, the delay unit 102a delays the amplified signal as a phase signal (PM signal). Output to the input terminal of the power amplifier 101. The power amplifier 101 modulates the power supply voltage by the power supply modulator 104 and amplifies and outputs the input phase signal.

  The analog delay circuit 107 has a delay between input and output signals, and is configured by a ladder circuit. An example of a ladder circuit is generally a filter. Examples of such circuits are shown in FIGS. FIG. 2 is a circuit diagram of a low-pass filter in which a unit circuit includes an inductor 121 and a capacitive element 122a and is configured in a ladder shape. FIG. 3 is a circuit diagram of a low-pass filter in which a unit circuit includes a resistor element 123 and a capacitor element 122b and is configured in a ladder shape. In FIGS. 2 and 3, the passive element includes five elements, but the present invention is not limited to this.

  According to the power amplifier having such a configuration, the delay device 102a delays the amplified signal that is an input signal and supplies the delayed signal to the input of the power amplifier 101. Can be reduced.

  Here, the low-pass filter has been described as an example, but the same operation can be performed using other filters (such as a high-pass filter, a band-pass filter, and a band rejection filter). When these filters are used, the signal to be amplified has a passable band, and the delay amount of each filter may be small, but the sum of the delay amounts of the circuits existing in the signal path to be amplified is It is important that the delay value is equal to the amplitude signal path and the phase signal path.

  FIG. 4 is a block diagram showing the configuration of the power amplifier according to the second example of the present invention. 4, the same reference numerals as those in FIG. 1 represent the same items, and the description thereof is omitted.

  The delay unit 102b includes a plurality of cascaded analog delay circuits 107. The delay unit 102b delays the amplified signal in order to correct the delay time of the amplified signal in the power supply modulator 104, the detector 115, and the like. Output to the input terminal of the amplifier 101.

  The delay device 102b is, for example, a low-pass filter, and it is necessary to set the cutoff frequency to a low frequency (several tens to 100 MHz) in order to obtain a delay time of several tens of ns. In this case, the carrier wave (several GHz) cannot pass. Therefore, in this embodiment, the analog delay circuit 107 which is a filter whose cutoff frequency is higher than the frequency of the input signal of the amplified signal is connected in a plurality of stages in series.

  FIG. 5 is a diagram illustrating a calculation result of a delay waveform by one filter. The time difference between the waveforms P1 and P2 representing the delay per filter is as small as about 0.1 ns. However, if 100 of these are connected in cascade, for example, a delay equivalent to 10 ns is obtained, and a sufficiently large delay can be obtained as a whole. According to such a configuration, it is possible to correct the delay of the path of the amplitude signal (AM signal) and the path of the phase signal (PM signal).

  FIG. 6 is a block diagram showing the configuration of the power amplifier according to the third example of the present invention. In FIG. 6, the same reference numerals as those in FIG.

  The detector 105 detects the output signal of the power amplifier 101, and adjusts the delay amount of the analog delay circuit 107c in the delay device 102c based on the detection result.

  FIG. 7 is a circuit diagram of the analog delay circuit 107c. The unit circuit includes a inductor 121, a capacitive element 122c, a capacitive element 126, and an FET 124, and is a low-pass filter configured in a ladder shape. The capacitive element 126 and the FET 124 are connected in series and further connected in parallel to the capacitive element 122c.

  The delay amount of the analog delay circuit 107c is adjusted by applying a control signal to the control terminal of the FET 124 based on the output from the detector 105 to turn the FET 124 on and off, thereby changing the capacitance value of the capacitor 126 to the capacitor 122c. Whether or not to add to the capacitance value is controlled, and the cut-off frequency and the delay time are changed.

  In the case of the circuit configuration of FIG. 7, the capacitance value is changed by the intermittent connection of the capacitive element. However, the present invention is not limited to such a configuration, and an inductance or a resistance value may be changed by intermittent connection of the inductor element or the resistance element of FIG. Even with such a circuit configuration, the delay time can be changed.

  Further, in place of the delay unit 102c, as shown in the delay unit 102d of FIG. 8, a signal path is obtained by turning on / off the switch 108 based on the output from the detector 105 for a part of the plurality of analog delay units 107. The delay time may be changed by switching. Further, the present invention is not limited to this, and the delay time may be changed by short-circuiting the path, blocking the path, or partially invalidating the path.

  It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

101 Power amplifier 102a, 102b, 102c, 102d Delay device 104 Power supply modulator 105, 115 Detector 107, 107a, 107b, 107c Analog delay circuit 108 Switch 121 Inductor 122a, 122b, 122c, 126 Capacitance element 123 Resistance element 124 FET

Claims (10)

An amplifier;
A power supply modulator that changes the power supply voltage of the amplifier according to the signal amplitude of the input signal;
A delay that delays the input signal and supplies it to the input of the amplifier;
A power amplifier comprising: The delay device is composed of one or more types of multi-stage analog delay circuits,
2. The power amplifier according to claim 1, wherein a total value of delay times in the analog delay circuits of a plurality of stages is set as a delay time for compensating for a delay associated with a change in power supply voltage of the amplifier with respect to the input signal.   The analog delay circuit is configured by a ladder-type circuit, and by changing a capacitance value, an inductor value, a resistance value, or a combination of passive elements that are components of the ladder-type circuit, 3. The power amplifier according to claim 2, wherein a delay time in the analog delay circuit is changed.   4. The electric power according to claim 3, wherein the delay time in the analog delay circuit is changed by changing any one or a combination of the capacitance value, the inductor value, and the resistance value by external control. amplifier.   The delay time in the analog delay circuit is changed by changing any one or a combination of the capacitance value, the inductor value, and the resistance value based on the detection result of the output of the amplifier. The power amplifier according to claim 3.   The delay time in the delay device is set by any one or a combination of path switching, short-circuiting, shut-off, and invalidity for a part of the analog delay circuits in the plurality of stages of the analog delay circuits. Item 3. The power amplifier according to Item 2.   A transmitter comprising the power amplifier according to claim 1.   A wireless device comprising the transmitter according to claim 7. A power amplifier control method comprising: an amplifier; and a power supply modulator that changes a power supply voltage of the amplifier according to a signal amplitude of an input signal,
A control method for a power amplifier, characterized in that the input signal is delayed and supplied to the input of the amplifier.   A delay in which the input signal is delayed by one or more types of analog delay circuits, and a total value of delay times in the analog delay circuits in a plurality of stages compensates for a delay associated with a change in power supply voltage of the amplifier with respect to the input signal 10. The method of controlling a power amplifier according to claim 9, wherein time is set.

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