JP2011135143A - Distortion compensating apparatus of predistortion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve distortion compensation precision in a distortion compensating apparatus for compensating for distortion occurring in an amplifier by a predistortion system. <P>SOLUTION: The distortion compensating apparatus includes memoryless predistortion means 21 to 23, and includes a delay processing unit of not less than one stage, an addition means 44, and a distortion imparting means 45 as memory predistortion means. Each of delay processing units includes delay selection means 32 to 34 of changing whether a level value of an input signal should be output or not, table means 35, 38, 41 of outputting a correction value according to the level value output from the delay selection means, delay means 36, 39, 42 of delaying the correction value output from the table means by a prescribed time in sample units for output, and difference detection means 37, 40, 43 of detecting a difference between a correction value output from the table means and a correction value output from the delay means to output the difference to the addition means 44. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a predistortion technique for compensating for distortion by giving distortion (predistortion) having a reverse characteristic of distortion generated by an amplifier that amplifies an input signal, and in particular, for example, a transmission amplifier using distortion compensation of a predistortion system. For example, the range of the number of past input samples to be considered in memory effect compensation is set appropriately, and efficient distortion compensation can be performed without being affected by amplifier variations, thereby improving distortion compensation accuracy. The present invention relates to a distortion type distortion compensation apparatus.

  In a base station apparatus provided in a mobile communication system, it is necessary to make a radio signal reach a mobile station apparatus that is physically far away from the base station apparatus. Therefore, it is necessary to amplify the signal with an amplifier. However, since the amplifier is an analog device, its input / output characteristics are nonlinear functions. In particular, after the amplification limit called the saturation point, the output power is almost constant even if the power input to the amplifier is increased. Then, nonlinear distortion is generated by this nonlinear output. The signal component outside the desired signal band of the transmitted signal before amplification is suppressed to a low level by the band limiting filter, but the signal component leaks outside the desired signal band (adjacent channel) due to nonlinear distortion in the signal after passing through the amplifier. To do. Since leakage of power to adjacent channels interferes with wireless communication to other systems, the magnitude of leakage power to adjacent channels is strictly defined, and how to reduce such adjacent channel leakage power is determined. It has become a big problem.

  One of the distortion compensation methods is a pre-distortion method. In recent years, since amplification efficiency is important, it can be configured in a digital circuit such as FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), and has high accuracy. A digital predistortion method capable of performing distortion compensation is often used.

  In order to keep the distortion low by the predistortion method, the distortion of the inverse characteristics of the AM (Amplitude Modulation) / AM characteristics and AM / PM (Phase Modulation) characteristics of the amplifier with respect to the instantaneous power is given in advance by the predistorter. A signal having a characteristic is input to the amplifier, whereby the output of the amplifier becomes a linear characteristic by canceling the non-linear region, and the distortion can be kept low while keeping the efficiency high. Recently, as the bandwidth of the transmission signal becomes wider, it is not possible to obtain a sufficient distortion compensation result simply by giving an inverse characteristic to the instantaneous power, and it seems to have the influence of the past input called the memory effect. Therefore, it is essential to take measures against the phenomenon that appears, and in the predistortion circuit, it is necessary to compensate for distortion in consideration of past inputs.

FIG. 4 shows a configuration example of an amplifying apparatus with a predistortion distortion compensation function according to the background art. The amplifying apparatus with a predistortion distortion compensation function of this example is provided in a transmitter of a base station apparatus, for example.
An amplifying apparatus with a predistortion distortion compensation function of this example includes a digital modulation unit 201, a predistortion unit (digital processing unit in this example) 202, and a D / A converter unit 203 including a D / A (Digital to Analog) converter. A frequency converter 204, an amplifier 205 including an amplifier, an antenna 206, a frequency converter 207, an A / D converter 208 including an A / D (Analog to Digital) converter, a signal synchronizer 209, a distortion compensation controller 210, A directional coupler 211 is provided.

An example of the operation in the amplifying apparatus with a predistortion distortion compensation function of this example is shown.
The digital modulation unit 201 performs band limitation and digital quadrature modulation for each carrier frequency on the input baseband signal (signal to be transmitted) including the I component and Q component, and performs multicarrier synthesis. These processing result signals are output to the predistortion unit 202 and the distortion compensation control unit 210.
The predistortion unit 202 gives an inverse characteristic of the nonlinear characteristic generated in the amplification unit 205 to the input signal and outputs the input signal to the D / A converter unit 203.

Thereafter, the D / A converter unit 203 converts the input signal from a digital signal to an analog signal and outputs the converted signal to the frequency conversion unit 204.
The frequency conversion unit 204 converts the frequency of the input signal into a radio frequency (RF) signal and outputs the signal to the amplification unit 205.
The amplifying unit 206 amplifies the input signal and outputs it to the antenna 206. As a result, the output signal from the amplifying unit 205 becomes a signal without distortion in such a way that the distortion generated in the amplifying unit 205 is canceled with the distortion given in advance by the predistortion unit 202, and is transmitted wirelessly from the antenna 206. Is output.

The directional coupler 211 extracts a part of the output signal from the amplifying unit 205 as a feedback signal and outputs it to the frequency converting unit 207.
The frequency conversion unit 207 converts the input signal into an intermediate frequency (IF) band signal and outputs the signal to the A / D converter unit 208.
The A / D converter unit 208 converts the input signal from an analog signal to a digital signal and outputs the signal to the signal synchronization unit 209.

The signal synchronization unit 209 includes an input signal (feedback signal) from the A / D converter unit 208 and an input signal (for example, an output signal from the digital modulation unit 201) on the input side to the amplification device with a predistortion distortion compensation function of this example. ) Are corrected, and the processed feedback signal (consisting of I component and Q component) is output to the distortion compensation amplifying unit 210.
The distortion compensation control unit 210 compares the input signal from the digital modulation unit 201 and the input signal (feedback signal) from the signal synchronization unit 209, and supplies correction parameters that reduce these errors to the predistortion unit 202. Set or update the settings. Thereby, adaptive control for following a temperature change or the like is performed.

A configuration example of the predistortion unit 202 shown in FIG. 4 will be described with reference to FIGS.
In any configuration, the predistortion units 301 and 401 (corresponding to the predistortion unit 202 shown in FIG. 4) are memories for compensating for the non-linearity of AM / AM characteristics and AM / PM characteristics with respect to instantaneous power. The memory includes pre-distortion units (memory-less PDs) 311 and 411 and memory pre-distortion units (memory PDs) 312 and 412 that compensate for distortion caused by a memory effect influenced by past inputs.

FIG. 5 shows a first configuration example of a predistortion unit 301 according to the background art, and also shows a digital modulation unit 201, a D / A converter unit 203, and a distortion compensation control unit 210.
The predistortion unit 301 of this example includes a memoryless PD 311 and a memory PD 312.
The memoryless PD 311 includes a power detection unit (first power detection unit) 321, a memoryless LUT (Look Up Table) 322, and a complex multiplication unit 323.
The memory PD 312 includes a power detection unit (second power detection unit) 331, a memory LUT 332, a one sample delay unit 333, a difference calculation unit 334, and a complex multiplication unit 335.

An example of the operation in the predistortion unit 301 of this example is shown.
An example of the operation in the memoryless PD 311 is shown.
The I component and Q component signals from the digital modulation unit 201 are input to the power detection unit 321 and the complex multiplication unit 323.
The power detection unit 321 calculates a signal level (for example, a power value or an amplitude value) for the input I and Q digital data signals, and outputs the result to the memoryless LUT 322.

The memoryless LUT 322 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 321 to the complex multiplication unit 323. Here, the memoryless LUT 322 stores the correspondence between the signal level and the correction value in the memory.
The complex multiplication unit 323 performs distortion compensation of the AM / AM characteristic and AM / PM characteristic by performing complex multiplication of the input signal from the digital modulation unit 201 and the correction value from the memoryless LUT 322, and the result is stored in the memory. Transmit (output) to PD 312.

An example of the operation in the memory PD 312 will be shown.
An output signal composed of an I component and a Q component from the complex multiplier 323 of the memoryless PD 311 is input to the power detector 331 and the complex multiplier 335.
The power detection unit 331 calculates a signal level (for example, a power value or an amplitude value) for the input I and Q digital signals, and outputs the result to the memory LUT 332.
The memory LUT 332 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 331 to the 1-sample delay unit 333 and the difference calculation unit 334. Here, the memory LUT 332 stores the correspondence between the signal level and the correction value in the memory.

The one sample delay unit 333 delays the input signal from the memory LUT 332 by one sample and outputs the delayed signal to the difference calculation unit 334.
The difference calculation unit 334 calculates the difference between the input signal from the memory LUT 332 and the input signal from the 1-sample delay unit 333 and outputs the resulting signal (consisting of an I component and a Q component) to the complex multiplication unit 335. .
The complex multiplication unit 335 performs the complex multiplication of the input signal from the complex multiplication unit 323 of the memoryless PD 311 and the input signal (difference value) from the difference calculation unit 334 to compensate for the memory effect, and A signal (consisting of an I component and a Q component) is output to the D / A converter unit 203.

  Here, the storage content (correspondence between the signal level and the correction value) of the memoryless LUT 322 of the memoryless PD 311 and the memory LUT 332 of the memory PD 312 is determined by an error between the input signal from the input side and the feedback signal by the distortion compensation control unit 210. Is updated adaptively so that becomes smaller.

FIG. 6 shows a second configuration example of the predistortion unit 401 according to the background art, and also shows a digital modulation unit 201, a D / A converter unit 203, and a distortion compensation control unit 210.
The predistortion unit 401 of this example includes a memoryless PD 411, a memory PD 412, a power detection unit 421, a compensation data addition unit 429, and a complex multiplication unit 430.
The memoryless PD 411 includes a memoryless LUT 422.
The memory PD 412 includes a 1-sample delay unit 423, a memory LUT (first memory LUT) 424, a 2-sample delay unit 425, a memory LUT (second memory LUT) 426, a 3-sample delay unit 427, and a memory LUT (third Memory LUT) 428.

An example of the operation in the predistortion unit 401 of this example will be shown.
I and Q digital data signals (I component and Q component signals) input from the digital modulation unit 201 are input to the power detection unit 421 and the complex multiplication unit 430.
The power detection unit 421 calculates a signal level (for example, a power value or an amplitude value) for the input I and Q digital data signals, and outputs the result. The output from the power detection unit 421 is distributed and input to the memoryless LUT 422 of the memoryless PD 411 and the 1 sample delay unit 423, the 2 sample delay unit 425, and the 3 sample delay unit 427 of the memory PD 412.

  In the memoryless PD 411, the memoryless LUT 422 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 421 to the compensation data adding unit 429. Thereby, the inverse characteristic of AM / AM characteristic and AM / PM characteristic is given. Here, the memoryless LUT 422 stores the correspondence between the signal level and the correction value in the memory.

In the memory PD 412, the 1-sample delay unit 423 delays the signal level input from the power detection unit 421 by one sample and outputs the delayed signal level to the memory LUT 424.
The memory LUT 424 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level input from the 1-sample delay unit 423 to the compensation data adding unit 429.
Further, the 2-sample delay unit 425 delays the signal level input from the power detection unit 421 by 2 samples and outputs the delayed signal level to the memory LUT 426.
The memory LUT 426 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level input from the 2-sample delay unit 425 to the compensation data adding unit 429.
In addition, the 3-sample delay unit 427 delays the signal level input from the power detection unit 421 by 3 samples and outputs the delayed signal level to the memory LUT 428.
The memory LUT 428 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level input from the 3-sample delay unit 427 to the compensation data adding unit 429.
These give the inverse characteristics of the memory effect.

The compensation data adding unit 429 adds the correction values input from the respective LUTs 422, 424, 426, and 428, and outputs the result (consisting of the I component and the Q component) to the complex multiplier 430.
The complex multiplication unit 430 performs memoryless and memory effect distortion compensation by performing complex multiplication of the input signal from the digital modulation unit 201 and the input signal from the compensation data addition unit 429, and the resultant signal (I Output to the D / A converter unit 203.

  Here, the storage contents (correspondence between the signal level and the correction value) of the memoryless LUT422 of the memoryless PD411, the memory LUT424, the memory LUT426, and the memory LUT428 of the memory PD412 are input to the input signal from the input side by the distortion compensation control unit 210. And the feedback signal are adaptively updated so that the error between them and the feedback signal becomes small.

  In the memory PD 412 of this example, the case where the signal up to 3 samples before is taken into account. However, the distortion compensation can be performed in consideration of the past signal by increasing the delay unit and the LUT in the digital circuit. it can.

JP 2007-243549 A

  With respect to the predistortion units 301 and 401 as shown in FIG. 5 and FIG. 6, in each conventional method, there is a problem of how much the memory PDs 312 and 412 take into account the past time. For example, if there are too few past inputs to be considered as in the configuration shown in FIG. 5, sufficient distortion compensation performance cannot be obtained, and even if there are too many past inputs to be considered as in the configuration shown in FIG. Due to the enormous number of parameters, there may be a problem that it takes a long time to converge or does not converge.

  Here, the past inputs that should be taken into account may vary depending on amplifier devices and adjustment variations, but in the past, they had to be pre-installed as a circuit rather than adaptively controlled. Therefore, it was not possible to cope with variations in the amplifiers subjected to distortion compensation.

  The present invention has been made in view of such conventional circumstances. For example, in a transmission amplifier using distortion compensation of a predistortion method, the range of the past number of input samples to be considered in the compensation of the memory effect is appropriately set. An object of the present invention is to provide a predistortion type distortion compensation apparatus that can perform efficient distortion compensation without being affected by variations in amplifiers and improve distortion compensation accuracy.

(Hereinafter, a configuration example corresponding to FIG. 1)
In order to achieve the above object, according to the present invention, a predistortion type distortion compensation apparatus that compensates for distortion generated in an amplifier by a predistortion system is configured as follows.
That is, the memoryless predistortion means applies distortion (predistortion for predistortion) corresponding to the value of the level of the input signal to the input signal with respect to distortion compensation of the AM / AM characteristic and AM / PM characteristic.
Further, the memory predistortion means gives distortion (predistortion for predistortion) corresponding to the value of the level of the input signal to the input signal regarding the distortion compensation of the memory effect. This memory predistortion means includes one or more stages of delay processing sections, the adding means adds (synthesizes) outputs (differences) from all delay processing sections, and the distortion applying means adds the result of the addition by the adding means. Is applied to the input signal (predistortion for predistortion) according to the above.

  In each of the delay processing units, it is possible to switch whether or not the delay selection means outputs the level value of the input signal, and the table means has a correction value corresponding to the level value output from the delay selection means. The delay means outputs the correction value output from the table means with a delay of a predetermined time in sample units, and the difference detection means outputs the correction value output from the table means and the delay means. The difference with the correction value is detected and the difference is output to the adding means.

In addition, the delay selection means provided in each of the delay processing units, when there is a next-stage delay processing unit, outputs the level value of the input signal to the next-stage delay processing unit. The value of the level of the input signal is output to the provided delay selection means.
When there are two or more delay processing units, the delay means provided in each of the delay processing units outputs the correction value output from the table means for a different time for each of the delay processing units. Delay.

  Therefore, by switching the presence / absence of the output from the delay selection means provided in each of the delay processing units, for example, in the transmission amplifier using predistortion type distortion compensation, the past input to be considered in the compensation of the memory effect By appropriately setting the range of the number of samples, efficient distortion compensation can be performed without being affected by variations in amplifiers, and distortion compensation accuracy can be improved.

  Here, the memoryless predistortion means includes, for example, a level detection means for detecting the level value of the input signal, a table means for outputting a correction value corresponding to the level value detected by the level detection means, and the table Distortion adding means for applying to the input signal distortion (predistortion for predistortion) corresponding to the correction value output from the means.

Further, the memory predistortion means includes level detection means for detecting the level value of the input signal, for example.
Further, as the one or more stages of delay processing units provided in the memory predistortion means, for example, a configuration in which one stage of delay processing unit is provided may be used, and preferably two or more stages of delay processing units are provided. Configuration is used. The number of stages of the delay processing unit may be arbitrary.
When two or more delay processing units are provided, as an example, the delay time of the delay means (predetermined time in units of samples) is the time for one sample in the first step and the amount for two samples in the second step. As the time, a configuration can be used in which the i-th stage (i is an integer value of 1 or more) is time for i samples.

  The arrangement relationship between the memoryless predistortion means and the memory predistortion means may be, for example, a configuration in which the memory predistortion means is arranged after the memoryless predistortion means, or the latter stage of the memory predistortion means. A configuration may be used in which memoryless predistortion means is arranged.

  Further, as one configuration example, the distortion compensation apparatus includes the storage contents of the table means provided in the memoryless predistortion means (correspondence between the signal level value and the correction value) and the storage of the table means provided in the memory predistortion means. Update control means for updating the contents (correspondence between signal level values and correction values) is provided. This update control may be performed based on various information, for example, an error between a signal after compensation for distortion (feedback signal) and an input signal, or residual distortion included in a signal after compensation for distortion (cannot be compensated for). The accuracy of distortion compensation is further improved based on the amount of distortion) remaining in the image.

As one configuration example, the distortion compensation apparatus includes delay selection control means for switching presence / absence (on / off) of output from the delay selection means provided in each of the delay processing units. This control may be performed based on various types of information. For example, an error between a distortion compensated signal (feedback signal) and an input signal, or residual distortion included in the signal after distortion compensation (remaining without being compensated). Is performed so as to realize sufficient distortion compensation accuracy based on the amount of distortion). As an example, in the initial state, the output of the delay selection means of all delay processing units is set to none (off), and the accuracy of distortion compensation is insufficient in order of the number of stages from the first delay processing unit When it is determined, a control method can be used in which the output of the delay selection means of the delay processing unit at the next stage is switched to ON (ON).
(The configuration example corresponding to FIG. 1 above)

(Hereinafter, a configuration example corresponding to FIG. 3)
In order to achieve the above object, according to the present invention, a predistortion type distortion compensation apparatus that compensates for distortion generated in an amplifier by a predistortion system is configured as follows.
In other words, the memoryless predistortion means outputs a correction value corresponding to the level value of the input signal with respect to AM / AM characteristic and AM / PM characteristic distortion compensation.
One or more delay processing units constituting the memory predistortion means output a correction value corresponding to the level value of the input signal with respect to memory effect distortion compensation.
The adding means adds (synthesizes) the correction values output from the memoryless predistortion means and the correction values output from all delay processing units constituting the memory predistortion means.
Distortion imparting means imparts distortion (predistortion for predistortion) according to the addition result by the adding means to the input signal.

  In each of the delay processing units, it is possible to switch whether or not the delay selection unit outputs the level value of the input signal, and the delay unit sets the level value output from the delay selection unit to a predetermined value in units of samples. The table means outputs a correction value corresponding to the level value output from the delay means.

In addition, the delay selection means provided in each of the delay processing units, when there is a next-stage delay processing unit, outputs the level value of the input signal to the next-stage delay processing unit. The value of the level of the input signal is output to the provided delay selection means.
When there are two or more stages of delay processing units, the delay means provided in each of the delay processing units has a level output from the delay selection unit for a different time for each of the delay processing units. Delay the value.

  Therefore, by switching the presence / absence of the output from the delay selection means provided in each of the delay processing units, for example, in the transmission amplifier using predistortion type distortion compensation, the past input to be considered in the compensation of the memory effect By appropriately setting the range of the number of samples, efficient distortion compensation can be performed without being affected by variations in amplifiers, and distortion compensation accuracy can be improved.

Here, the memoryless predistortion means and the memory predistortion means include, for example, level detection means for detecting the level value of the input signal, and such level detection means include the memoryless predistortion means and the memory predistortion means. It is possible to provide a common thing.
The memoryless predistortion means includes table means for outputting a correction value according to the level value of the input signal, for example.

Further, as the one or more stages of delay processing units provided in the memory predistortion means, for example, a configuration in which one stage of delay processing unit is provided may be used, and preferably two or more stages of delay processing units are provided. Configuration is used. The number of stages of the delay processing unit may be arbitrary.
When two or more delay processing units are provided, as an example, the delay time of the delay means (predetermined time in units of samples) is the time for one sample in the first step and the amount for two samples in the second step. As the time, a configuration can be used in which the i-th stage (i is an integer value of 1 or more) is time for i samples.

  Further, as one configuration example, the distortion compensation apparatus includes the storage contents of the table means provided in the memoryless predistortion means (correspondence between the signal level value and the correction value) and the storage of the table means provided in the memory predistortion means. Update control means for updating the contents (correspondence between signal level values and correction values) is provided. This update control may be performed based on various information, for example, an error between a signal after compensation for distortion (feedback signal) and an input signal, or residual distortion included in a signal after compensation for distortion (cannot be compensated for). The accuracy of distortion compensation is further improved based on the amount of distortion) remaining in the image.

As one configuration example, the distortion compensation apparatus includes delay selection control means for switching presence / absence (on / off) of output from the delay selection means provided in each of the delay processing units. This control may be performed based on various types of information. For example, an error between a distortion compensated signal (feedback signal) and an input signal, or residual distortion included in the signal after distortion compensation (remaining without being compensated). Is performed so as to realize sufficient distortion compensation accuracy based on the amount of distortion). As an example, in the initial state, the output of the delay selection means of all delay processing units is set to none (off), and the accuracy of distortion compensation is insufficient in order of the number of stages from the first delay processing unit When it is determined, a control method can be used in which the output of the delay selection means of the delay processing unit at the next stage is switched to ON (ON).
(The configuration example corresponding to FIG. 3 above)

  As described above, according to the predistortion type distortion compensation apparatus according to the present invention, for example, in a transmission amplifier using predistortion type distortion compensation, the range of the past number of input samples to be considered in the compensation of the memory effect Can be set appropriately, efficient distortion compensation can be performed without being affected by variations in amplifiers, and distortion compensation accuracy can be improved.

It is a figure which shows the structural example of the predistortion part which concerns on 1st Example of this invention. It is a figure of the flowchart which shows an example of the procedure of the process performed by the distortion compensation control part. It is a figure which shows the structural example of the predistortion part which concerns on 2nd Example of this invention. It is a figure which shows the structural example of the amplifier with a predistortion distortion compensation function which concerns on background art. It is a figure which shows the 1st structural example of the predistortion part which concerns on background art. It is a figure which shows the 2nd structural example of the predistortion part which concerns on background art.

Embodiments according to the present invention will be described with reference to the drawings.
This embodiment shows a case where the present invention is applied to an amplifying apparatus with a predistortion distortion compensation function having the same configuration as that shown in FIG. 4, and in particular, the predistortion unit 202 and distortion compensation control shown in FIG. A configuration example and an operation example of the unit 210 will be described.
In the following, portions different from the configuration and operation described with reference to FIG. 4 will be mainly described, and detailed descriptions of similar portions will be omitted.

A first embodiment of the present invention will be described.
In the first embodiment, a configuration example corresponding to the predistortion unit 301 shown in FIG. 5 is shown.
FIG. 1 shows a configuration example of a predistortion unit 1 (corresponding to the predistortion unit 202 shown in FIG. 4) according to an embodiment of the present invention, and also shows a digital modulation unit 201, a D / A A converter unit 203 and a distortion compensation control unit 2 (corresponding to the distortion compensation control unit 210 shown in FIG. 4) are shown.

The predistortion unit 1 of this example includes a memoryless PD 11 and a memory PD 12.
The memoryless PD 11 includes a power detection unit (first power detection unit) 21, a memoryless LUT 22 that constitutes a distortion compensation table, and a complex multiplication unit 23.
The memory PD12 includes a power detection unit (second power detection unit) 31, a delay selection unit (first delay selection unit) 32, a delay selection unit (second delay selection unit) 33, a delay selection unit (third (Delay selection unit) 34, memory LUT (first memory LUT) 35 constituting the distortion compensation table, 1 sample delay unit 36, difference calculation unit (first difference calculation unit) 37, memory LUT constituting the distortion compensation table (Second memory LUT) 38, two-sample delay unit 39, difference calculation unit (second difference calculation unit) 40, memory LUT (third memory LUT) 41 constituting the distortion compensation table, and three-sample delay unit 42 , A difference calculation unit (third difference calculation unit) 43, a compensation data addition unit 44, and a complex multiplication unit 45.

An example of the operation in the predistortion unit 1 of this example is shown.
The example of operation | movement in memoryless PD11 is shown.
The I component and Q component signals from the digital modulation unit 201 are input to the power detection unit 21 and the complex multiplication unit 23.
The power detection unit 21 calculates a signal level (for example, a power value or an amplitude value) for the input I and Q digital data signals, and outputs the result to the memoryless LUT 22.

The memoryless LUT 22 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 21 to the complex multiplication unit 23. Here, the memoryless LUT 22 stores the correspondence between the signal level and the correction value in the memory.
The complex multiplier 23 performs distortion compensation of the AM / AM characteristic and AM / PM characteristic by performing complex multiplication of the input signal from the digital modulator 201 and the correction value from the memoryless LUT 22, and stores the result in the memory. Transmit (output) to PD12.

An example of the operation in the memory PD12 is shown.
An output signal composed of an I component and a Q component from the complex multiplication unit 23 of the memoryless PD 11 is input to the power detection unit 31 and the complex multiplication unit 45.
The power detection unit 31 calculates a signal level (for example, a power value or an amplitude value) for the input I and Q digital signals, and outputs the result to the delay selection unit 32.

  The delay selection unit 32 controls whether the input data (the signal level calculated by the power detection unit 31) is passed through the subsequent blocks (processing units). This control setting is specified by the delay selection unit 32 from the distortion compensation control unit 2. Specifically, when considering past input (on), the delay selection unit 32 uses the input data (the signal level calculated by the power detection unit 31) as it is as the delay selection unit in the subsequent stage. 33, if the past input is not considered at all, 0 is output to the delay selection unit 33 and the memory LUT 35 in the subsequent stage, thereby turning off the memory PD12.

The memory LUT 35 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 31 input from the delay selection unit 32 to the one-sample delay unit 36 and the difference calculation unit 37. To do. Here, the memory LUT 35 stores the correspondence between the signal level and the correction value in the memory.
The one-sample delay unit 36 delays the input signal (input data) from the memory LUT 35 by one sample and outputs the delayed signal to the difference calculation unit 37.
The difference calculation unit 37 takes the difference between the input signal from the memory LUT 35 and the input signal from the 1-sample delay unit 36 and outputs the resulting signal (consisting of an I component and a Q component) to the compensation data addition unit 44. To do.

  The delay selection unit 33 controls whether or not the input data (the signal level calculated by the power detection unit 31 input from the delay selection unit 32) is passed through the subsequent blocks (processing units). This control setting is designated by the delay selection unit 33 from the distortion compensation control unit 2. Specifically, the delay selection unit 33 selects the input data (the signal level calculated by the power detection unit 31) as it is in the subsequent delay selection when considering a past input of two samples or more (when ON). When the past input of 2 samples or more is not considered, by outputting 0 to the delay selection unit 34 and the memory LUT 38 in the subsequent stage, the past of 2 samples or more is output in the memory PD12. The block (processing unit) depending on the input of is turned off.

The memory LUT 38 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 31 input from the delay selection unit 33 to the 2-sample delay unit 39 and the difference calculation unit 40. To do. Here, the memory LUT 38 stores the correspondence between the signal level and the correction value in the memory.
The 2-sample delay unit 39 delays the input signal (input data) from the memory LUT 38 by 2 samples and outputs the delayed signal to the difference calculation unit 40.
The difference calculation unit 40 takes the difference between the input signal from the memory LUT 38 and the input signal from the 2-sample delay unit 39 and outputs the resulting signal (consisting of an I component and a Q component) to the compensation data addition unit 44. To do.

  The delay selection unit 34 controls whether or not to pass the input data (the signal level calculated by the power detection unit 31 input from the delay selection unit 33) to subsequent blocks (processing units). This control setting is designated by the delay selection unit 34 from the distortion compensation control unit 2. Specifically, when considering a past input of three samples or more (when ON), the delay selection unit 34 uses the input data (the signal level calculated by the power detection unit 31) as it is as the subsequent memory LUT 41. If a past input of 3 samples or more is not considered, 0 is output to the memory LUT 41 in the subsequent stage, whereby a block (processing unit) depending on the past input of 3 samples or more in the memory PD12 Is turned off.

The memory LUT 41 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 31 input from the delay selection unit 34 to the 3-sample delay unit 42 and the difference calculation unit 43. To do. Here, the memory LUT 41 stores the correspondence between the signal level and the correction value in the memory.
The 3-sample delay unit 42 delays the input signal (input data) from the memory LUT 41 by 3 samples and outputs the delayed signal to the difference calculation unit 43.
The difference calculation unit 43 takes the difference between the input signal from the memory LUT 41 and the input signal from the 3-sample delay unit 42 and outputs the resulting signal (consisting of an I component and a Q component) to the compensation data addition unit 44. To do.

  In the memory PD12 of the present example, the case where the signal up to three samples before is taken into account is shown. However, for example, by increasing the delay selection unit, memory LUT, delay unit, and difference calculation unit in the digital circuit, the past Distortion compensation can be performed in consideration of the signal.

The compensation data adding unit 44 adds the input signals (outputs of all branches) from all the difference calculating units 37, 40, and 43, and complex-multiplies the resulting signal (consisting of I and Q components). To the unit 45.
The complex multiplication unit 45 performs complex multiplication between the input signal from the complex multiplication unit 23 of the memoryless PD 11 and the input signal from the compensation data addition unit 44 (memory effect distortion compensation data formed by adding difference values). Thus, the memory effect is compensated, and the resulting signal (consisting of I component and Q component) is output to the D / A converter unit 203.

Here, the setting and updating of the correction parameters of the LUTs 22, 35, 38, and 41 and the on / off setting of the delay selection units 32, 33, and 34 are performed by the distortion compensation control unit 2.
Specifically, the storage contents (correspondence between the signal level and the correction value) of the memoryless LUT22 of the memoryless PD11 and the memory LUT35, 38, 41 of the memory PD12 are respectively input from the input side by the distortion compensation control unit 2. It is adaptively updated so that the error between the input signal and the feedback signal becomes small.
Further, the on / off states of the delay selection units 32, 33, and 34 are set by the distortion compensation control unit 2, respectively.

With reference to FIG. 2, an example of a procedure of processing performed by the distortion compensation control unit 2 in the predistortion unit 1 of this example is shown.
First, when activated, all delay selection units 32, 33, and 34 are turned off to operate only the memoryless PD 11 as an initial state (step S1). As a result, only the memoryless PD 11 operates, the adaptive update of the memoryless PD11 is performed, and the memoryless LUT 22 is updated (step S2).

Then, whether or not the convergence is determined by whether or not the error improvement amount between the input signal (transmission signal) from the input side and the feedback signal is less than a predetermined threshold (or may be “below a predetermined threshold”). If it is determined (step S3) and it is determined that it has not converged, the process returns to step S2.
On the other hand, if it is determined that the error has converged, it is determined whether or not the error is sufficiently small (step S4). If it is determined that the error is sufficiently small, the memory PD12 is stored. There is no need to operate, and updating is stopped until error deterioration is detected (step S16). Whether or not the error has become sufficiently small can be determined, for example, based on whether or not the error is less than a predetermined threshold value (or may be “below a predetermined threshold value”).

  On the other hand, when it is determined that the error is not sufficiently small (the error still remains), the output of the delay selection unit 32 is turned on, and the memory PD12 is operated in consideration of the input of one sample in the past. (Step S5). Thereby, the memoryless PD11 and the memory PD12 operate, and the memoryless PD11 and the memory PD12 are adaptively updated to update the memoryless LUT22 and the memory LUT35 (step S6).

Then, whether or not the convergence is determined by whether or not the error improvement amount between the input signal (transmission signal) from the input side and the feedback signal is less than a predetermined threshold (or may be “below a predetermined threshold”). If it is determined (step S7) and it is determined that it has not converged, the process returns to step S6.
On the other hand, if it is determined that the error has converged, it is determined whether or not the error is sufficiently small (step S8). If it is determined that the error is sufficiently small, the error is deteriorated. Update is stopped until it is detected (step S16).

  On the other hand, if it is determined that the error is not sufficiently small (the error still remains), the output of the delay selection unit 33 is turned on, and the memory PD12 that takes into account the input up to two samples in the past is stored. It is made to operate (step S9). As a result, the memoryless PD11 and the memory PD12 operate, and the memoryless PD11 and the memory PD12 are adaptively updated to update the memoryless LUT22, the memory LUT35, and the memory LUT38 (step S10).

Then, whether or not the convergence is determined by whether or not the error improvement amount between the input signal (transmission signal) from the input side and the feedback signal is less than a predetermined threshold (or may be “below a predetermined threshold”). If it is determined (step S11) and it is determined that it has not converged, the process returns to step S10.
On the other hand, if it is determined that the error has converged, it is determined whether or not the error is sufficiently small (step S12). If it is determined that the error is sufficiently small, the error is deteriorated. Update is stopped until it is detected (step S16).

  On the other hand, if it is determined that the error is not sufficiently small (the error still remains), the output of the delay selection unit 34 is turned on, and the memory PD12 considering the input up to the past of three samples is stored. It is made to operate (step S13). As a result, the memoryless PD11 and the memory PD12 operate, the adaptive update of the memoryless PD11 and the memory PD12 is performed, and the memoryless LUT22, the memory LUT35, the memory LUT38, and the memory LUT41 are updated (step S14).

Then, whether or not the convergence is determined by whether or not the error improvement amount between the input signal (transmission signal) from the input side and the feedback signal is less than a predetermined threshold (or may be “below a predetermined threshold”). If it is determined (step S15) and it is determined that it has not converged, the process returns to step S14.
On the other hand, if it is determined that convergence has been achieved, the update is stopped until error deterioration is detected (step S16).

  In the memory PD12 of this example, the case where the signal up to 3 samples before is shown is shown. However, in the configuration in which the past signal is further considered, the past so that the past sample is considered as in this example. It is possible to increase the memory LUT to be updated by expanding the range that considers these samples.

As described above, the predistortion distortion compensation circuit constituting the predistortion unit 1 of this example includes the following processing units for the input digital I and Q signals.
That is, as a processing unit of the memoryless PD 11, a power detection unit 21 that obtains a signal level (for example, a power value or an amplitude value), a memoryless LUT 22 that outputs a correction value according to the signal level, an input signal and a correction value The complex multiplication unit 23 for performing complex multiplication is provided.
In addition, as a processing unit of the memory PD 12, a power detection unit 31 that obtains an output level (for example, a power value or an amplitude value) from the complex multiplication unit 23, and a range of the number of samples that considers past inputs in memory effect compensation. A plurality of delay selection units 32, 33, and 34 that switch on / off the output from the power detection unit 31 in order to switch, and a plurality of correction values that are output according to the output values from the delay selection units 32, 33, and 34 The memory LUTs 35, 38, 41, a plurality of delay units 36, 39, 42 for delaying outputs from the memory LUTs 35, 38, 41 in units of samples, outputs from the memory LUTs 35, 38, 41 and delay units 36, 39 , 42 for calculating the difference from the output from the plurality of difference calculation units 37, 40, 43, and compensation data addition for synthesizing the outputs from the difference calculation units 37, 40, 43 44, with a complex multiplier 45 for performing a complex multiplication of the output from the output compensation data adding unit 44 from the complex multiplier 23.

Further, a distortion compensation control unit 2 is provided outside (or inside) the predistortion unit 1 of this example, and the distortion compensation control unit 2 reduces an error between the input signal from the input side and the feedback signal. Thus, the memoryless LUT 22 and the memory LUTs 35, 38, and 41 are updated, and the delay selection units 32, 33, and 34 are turned on / off according to the magnitude of the error. Yes.
In the distortion compensation control method (method) in the predistortion unit 1 of this example, control is performed to increase the number of circuits to be operated according to the error convergence state and the convergence value.

The amplification device with a predistortion distortion compensation function of the present example includes the predistortion unit 1 and the distortion compensation control unit 2 of the present example as described above, and further includes the following processing unit.
That is, a digital modulation unit 201 that performs band quadrature modulation, digital quadrature modulation to a desired carrier frequency for each carrier, multi-carrier addition, and D / A converter that converts a digital signal into an analog signal Unit 203, frequency conversion unit (up-conversion unit) 204 that performs frequency conversion to RF frequency, amplification unit 205 that amplifies an RF signal, antenna 206, directional coupler 211 that extracts a part of the signal, and amplification unit 205 A frequency conversion unit (down-conversion unit) 207 that performs frequency conversion to an IF frequency using a part of the output of the signal as a feedback signal, an A / D converter unit 208 that converts an analog signal into a digital signal, and between transmission data and feedback data A signal synchronizer 209 that adjusts the level, delay, and phase difference is provided.

  Therefore, the predistortion unit 1 of this example does not update all the LUTs from the beginning, but increases the number of past samples to be considered as necessary, for example, sufficient distortion without updating. Is not updated, and if the amount of distortion compensation is insufficient, a new block (processing unit) is operated to perform distortion compensation. Therefore, distortion compensation can be performed efficiently.

  For example, in the conventional method, the circuit used for distortion compensation is fixed, and only the correction parameter of each LUT is adaptively controlled. In this example, however, the memory PD 12 considers the distortion compensation target amplifier or the like. By converging while changing the range of the past number of input samples, it is possible to appropriately set the past input range to be considered in the memory PD12 and perform efficient distortion compensation. Compensation accuracy can be improved.

  In the amplification device with a predistortion distortion compensation function (including the function of the distortion compensation device) of this example, the level detection means is configured by the function of the power detection unit 21 with respect to the configuration shown in FIG. The table means is constituted by the function of the less LUT 22, the distortion adding means is constituted by the function of the complex multiplier 23, and the memoryless predistortion means is constituted by these functions. Further, in this example, the level detection means is configured by the function of the power detection unit 31, the delay selection unit is configured by the function of each delay selection unit 32-34, and the function of each memory LUT 35, 38, 41. The table means is constituted by the delay means (1 sample delay part 36, 2 sample delay part 39, 3 sample delay part 42), and the delay means is constituted by each difference calculating part 37, 40, Difference detection means is configured by 43 functions. Further, in this example, from the three stages of delay processing units, the delay selection units 32, 33, 34 of each stage, the memory LUTs 35, 38, 41, the delay units 36, 39, 42, and the difference calculation units 37, 40, 43 A delay processing unit of each stage is configured. In this example, the adding means is configured by the function of the compensation data adding unit 44, and the distortion adding unit is configured by the function of the complex multiplying unit 45, and these functions and the level detecting unit (power The function of the detection unit 31) The memory predistortion means is configured by the function of the delay processing unit of three stages. In this example, the function of the distortion compensation control unit 2 constitutes an update control unit for each LUT 22, 35, 38, 41 and a delay selection control unit for each delay selection unit 32, 33, 34.

A second embodiment of the present invention will be described.
In the second embodiment, a configuration example corresponding to the predistortion unit 401 shown in FIG. 6 is shown.
FIG. 3 shows a configuration example of the predistortion unit 101 (corresponding to the predistortion unit 202 shown in FIG. 4) according to an embodiment of the present invention, and also shows a digital modulation unit 201, D / A A converter unit 203 and a distortion compensation control unit 102 (corresponding to the distortion compensation control unit 210 shown in FIG. 4) are shown.

The predistortion unit 101 of this example includes a memoryless PD 111, a memory PD 112, a power detection unit 121, a delay selection unit (first delay selection unit) 122, a delay selection unit (second delay selection unit) 123, and a delay selection unit. (Third delay selection unit) 124, compensation data addition unit 132, and complex multiplication unit 133.
The memoryless PD 111 includes a memoryless LUT 125 that constitutes a distortion compensation table.
The memory PD 112 includes a 1-sample delay unit 126, a memory LUT (first memory LUT) 127 that constitutes a distortion compensation table, a 2-sample delay unit 128, a memory LUT (second memory LUT) 129 that constitutes a distortion compensation table, A three-sample delay unit 130 and a memory LUT (third memory LUT) 131 constituting a distortion compensation table are provided.

An example of the operation in the predistortion unit 101 of this example is shown.
I and Q digital data signals (I component and Q component signals) input from the digital modulation unit 201 are input to the power detection unit 121 and the complex multiplication unit 133.
The power detection unit 121 calculates a signal level (for example, a power value or an amplitude value) for the input I and Q digital data signals, and outputs the result to the delay selection unit 122 and the memoryless LUT 125. .

  In the memoryless PD 111, the memoryless LUT 125 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 121 to the compensation data adding unit 132. Thereby, the inverse characteristic of AM / AM characteristic and AM / PM characteristic is given. Here, the memoryless LUT 125 stores the correspondence between the signal level and the correction value in the memory.

  The delay selection unit 122 controls whether the input data (the signal level calculated by the power detection unit 121) is passed through the subsequent blocks (processing units). This control setting is designated by the delay selection unit 122 from the distortion compensation control unit 102. Specifically, when considering past input (on), the delay selection unit 122 uses the input data (the signal level calculated by the power detection unit 121) as it is as the subsequent delay selection unit. 123, when the past input is not taken into account at all, by outputting 0 to the delay selection unit 123 at the subsequent stage and the one sample delay unit 126, the entire memory PD 112 is turned off ( OFF).

  The delay selection unit 123 controls whether or not to pass the input data (the signal level calculated by the power detection unit 121 input from the delay selection unit 122) to the subsequent blocks (processing units). This control setting is designated by the delay selection unit 123 from the distortion compensation control unit 102. Specifically, the delay selection unit 123 selects the input data (the signal level calculated by the power detection unit 121) as it is in the subsequent delay selection when considering a past input of two samples or more (when ON). When the past input of 2 samples or more is not taken into consideration, 0 is output to the delay selection unit 124 and the 2-sample delay unit 128 in the subsequent stage to output the memory PD 112. The block (processing unit) depending on the past input of 2 samples or more is turned off.

  The delay selection unit 124 controls whether or not the input data (the signal level calculated by the power detection unit 121 input from the delay selection unit 123) is passed through the subsequent blocks (processing units). This control setting is designated by the delay selection unit 124 from the distortion compensation control unit 102. Specifically, when considering a past input of 3 samples or more (when ON), the delay selection unit 124 uses the input data (the signal level calculated by the power detection unit 121) as it is in the subsequent 3 samples. Output to the delay unit 130, and if the past input of 3 samples or more is not considered, by outputting 0 to the subsequent 3-sample delay unit 130, depending on the past input of 3 samples or more in the memory PD112 The block (processing unit) to be turned off is turned off.

In the memory PD 112, the one-sample delay unit 126 delays the input signal (input data) from the delay selection unit 122 by one sample and outputs the delayed signal to the memory LUT 127.
The memory LUT 127 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 121 input from the one-sample delay unit 126 to the compensation data addition unit 132. Here, the memory LUT 127 stores the correspondence between the signal level and the correction value in the memory.
Further, the 2-sample delay unit 128 delays the input signal (input data) from the delay selection unit 123 by 2 samples and outputs the delayed signal to the memory LUT 129.
The memory LUT 129 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 121 input from the 2-sample delay unit 128 to the compensation data adding unit 132. Here, the memory LUT 129 stores the correspondence between the signal level and the correction value in the memory.
The 3-sample delay unit 130 delays the input signal (input data) from the delay selection unit 124 by 3 samples and outputs the delayed signal to the memory LUT 131.
Further, the memory LUT 131 outputs a correction value (consisting of an I component and a Q component) corresponding to the signal level calculated by the power detection unit 121 input from the 3-sample delay unit 130 to the compensation data addition unit 132. Here, the memory LUT 131 stores the correspondence between the signal level and the correction value in the memory.
These give the inverse characteristics of the memory effect.

  In the memory PD 112 of this example, the case where the signal up to 3 samples before is considered is shown. However, for example, by adding the delay selection unit, the delay unit, and the memory LUT in the digital circuit, the past signal is further considered. Distortion compensation.

The compensation data adding unit 132 adds the correction values input from the LUTs 125, 127, 129, and 131, and outputs the result (consisting of an I component and a Q component) to the complex multiplier 133.
The complex multiplication unit 133 performs memory-less and memory effect distortion compensation by performing complex multiplication of the input signal from the digital modulation unit 201 and the input signal (distortion compensation data) from the compensation data addition unit 132. The resulting signal (consisting of an I component and a Q component) is output to the D / A converter unit 203.

Here, the distortion compensation control unit 102 sets and updates the correction parameters of the LUTs 125, 127, 129, and 131 and sets on / off of the delay selection units 122, 123, and 124.
Specifically, the storage contents (correspondence between the signal level and the correction value) of the memoryless LUT 125 of the memoryless PD 111 and the memory LUTs 127, 129, and 131 of the memory PD 112 are respectively changed from the input side by the distortion compensation control unit 102. It is adaptively updated so that the error between the input signal and the feedback signal becomes small.
The on / off states of the delay selection units 122, 123, and 124 are set by the distortion compensation control unit 102, respectively.

  Here, in the predistortion unit 101 of this example, as an example of a procedure of processing performed by the distortion compensation control unit 102, for example, the same procedure as the flowchart shown in FIG. 2 can be used.

As described above, the predistortion distortion compensation circuit constituting the predistortion unit 101 of this example includes the following processing units for the input digital I and Q signals.
That is, a power detection unit 121 that obtains a signal level (for example, a power value or an amplitude value), a memoryless LUT 125 that outputs a correction value according to the signal level, and the number of samples that take into account past inputs in memory effect compensation A plurality of delay selection units 122, 123, and 124 for switching on / off the output from the power detection unit 121 in order to switch the range, and a plurality of delays for delaying outputs from the delay selection units 122, 123, and 124 in units of samples. Units 126, 128, 130, a plurality of memory LUTs 127, 129, 131 that output correction values according to the output values from the delay units 126, 128, 130, outputs from the memoryless LUT 125, and the memory LUTs 127, 129, 131. Compensation data adder 132 that synthesizes the output from digital signal, and the output from digital modulator 201 With a complex multiplier 133 performs complex multiplication of the output from the data addition unit 132.

In addition, a distortion compensation control unit 102 is provided outside (or inside) the predistortion unit 101 of this example, and the distortion compensation control unit 102 reduces an error between the input signal from the input side and the feedback signal. The memoryless LUT 125 and the memory LUTs 127, 129, and 131 are updated, and the delay selection units 122, 123, and 124 are turned on / off according to the magnitude of the error. Yes.
Further, in the distortion compensation control method (method) in the predistortion unit 101 of this example, control to increase the number of circuits to be operated is performed according to the convergence state and convergence value of the error.

The amplifying apparatus with a predistortion distortion compensation function of the present example includes the predistortion unit 101 and the distortion compensation control unit 102 of the present example as described above, and further includes the following processing unit.
That is, a digital modulation unit 201 that performs band quadrature modulation, digital quadrature modulation to a desired carrier frequency for each carrier, multi-carrier addition, and D / A converter that converts a digital signal into an analog signal Unit 203, frequency conversion unit (up-conversion unit) 204 that performs frequency conversion to RF frequency, amplification unit 205 that amplifies an RF signal, antenna 206, directional coupler 211 that extracts a part of the signal, and amplification unit 205 A frequency conversion unit (down-conversion unit) 207 that performs frequency conversion to an IF frequency using a part of the output of the signal as a feedback signal, an A / D converter unit 208 that converts an analog signal into a digital signal, and between transmission data and feedback data A signal synchronizer 209 that adjusts the level, delay, and phase difference is provided.

  Therefore, the predistortion unit 101 of this example does not update all the LUTs from the beginning, but increases the number of past samples to be considered as necessary, for example, sufficient distortion without updating. Is not updated, and if the amount of distortion compensation is insufficient, a new block (processing unit) is operated to perform distortion compensation. Therefore, distortion compensation can be performed efficiently.

  For example, in the conventional method, the circuit used for distortion compensation is fixed and only the correction parameter of each LUT is adaptively controlled. In this example, however, the memory PD 112 considers the distortion compensation target amplifier or the like. By converging while changing the range of the past number of input samples, the past input range to be considered in the memory PD 112 can be appropriately set, and efficient distortion compensation can be performed. Compensation accuracy can be improved.

  In the amplification device with a predistortion distortion compensation function (including the function of the distortion compensation device) of this example, a level detection unit is configured by the function of the power detection unit 121 with respect to the configuration shown in FIG. In this example, the table means is constituted by the function of the memoryless LUT 125, and the memoryless predistortion means is constituted by this function and the level detection means (function of the power detection unit 121). In this example, a delay selecting unit is configured by the functions of the delay selecting units 122 to 124, and the functions of the delay units (the 1-sample delay unit 126, the 2-sample delay unit 128, and the 3-sample delay unit 130) are used. A delay unit is configured, and a table unit is configured by the function of each of the memory LUTs 127, 129, and 131. Further, in this example, for each of the three stages of delay processing units, each stage of delay selection units 122, 123, 124, delay units 126, 128, 130, and memory LUTs 127, 129, 131 are configured. ing. Further, in this example, the memory predistortion means is configured by the level detection means (function of the power detection unit 121) and the function of the three-stage delay processing unit. Further, in this example, an adding unit is configured by the function of the compensation data adding unit 132, and a distortion adding unit is configured by the function of the complex multiplying unit 133. Further, in this example, the function of the distortion compensation control unit 102 constitutes an update control unit for each LUT 125, 127, 129, 131 and a delay selection control unit for each delay selection unit 122, 123, 124.

Here, the configuration of the system and apparatus according to the present invention is not necessarily limited to the configuration described above, and various configurations may be used. The present invention can also be provided as, for example, a method or method for executing the processing according to the present invention, a program for realizing such a method or method, or a recording medium for recording the program. It is also possible to provide various systems and devices.
The application field of the present invention is not necessarily limited to the above-described fields, and the present invention can be applied to various fields.
In addition, as various processes performed in the system and apparatus according to the present invention, for example, the processor executes a control program stored in a ROM (Read Only Memory) in hardware resources including a processor and a memory. A controlled configuration may be used, and for example, each functional unit for executing the processing may be configured as an independent hardware circuit.
The present invention can also be understood as a computer-readable recording medium such as a floppy (registered trademark) disk or a CD (Compact Disc) -ROM storing the control program, and the program (itself). The processing according to the present invention can be performed by inputting the program from the recording medium to the computer and causing the processor to execute the program.

  1, 101, 202, 301, 401 ··· Predistortion unit, 2, 102, 210, 311 · · Distortion compensation control unit, 11, 111, 312, 411 · · Memoryless PD, 12, 112, 412 · · · Memory PD, 21, 31, 121, 321, 331, 421... Power detection unit, 22, 125, 322, 422... Memoryless LUT, 23, 45, 133, 323, 335, 430. -34, 122-124-Delay selection unit, 35, 38, 41, 127, 129, 131, 332, 424, 426, 428-Memory LUT, 36, 126, 333, 423-Sample delay unit, 37, 40, 43, 334 ··· Difference calculation unit, 39, 128, 425 ··· 2 sample delay unit, 42, 130, 427 ··· 3 sun Delay unit 44, 132, 429... Compensation data addition unit 201 digital modulation unit 203 D / A converter unit 204 207 frequency conversion unit 205 amplification unit 206 Antenna, 208... A / D converter section, 209 .. signal synchronization section,

Claims (2)

In a predistortion type distortion compensation device that compensates for distortion generated in an amplifier by a predistortion method,
With respect to distortion compensation of AM / AM characteristics and AM / PM characteristics, it has a memoryless predistortion means for imparting distortion to the input signal according to the level value of the input signal,
Regarding memory effect distortion compensation, as a memory predistortion means that gives distortion to the input signal according to the level value of the input signal, one or more stages of delay processing units and an addition that adds outputs from all delay processing units Means, and distortion imparting means for imparting distortion to the input signal according to the addition result by the adding means,
Each of the delay processing units outputs a delay selection unit capable of switching whether or not to output the level value of the input signal, and a correction value corresponding to the level value output from the delay selection unit. A table means, a delay means for delaying the correction value output from the table means by a predetermined time in sample units, a correction value output from the table means, and a correction value output from the delay means. A difference detecting means for detecting a difference and outputting the difference to the adding means,
The delay selection means provided in each of the delay processing units is provided in the delay processing unit of the next stage in a state where the level value of the input signal is output when there is a delay processing unit of the next stage. Output the value of the level of the input signal to the delay selection means,
When the delay processing unit has two or more stages, the delay unit provided in each of the delay processing units delays the correction value output from the table unit by a different time for each of the delay processing units. ,
A predistortion distortion compensation device characterized by the above. In a predistortion type distortion compensation device that compensates for distortion generated in an amplifier by a predistortion method,
Memory-less predistortion means for outputting a correction value corresponding to the value of the level of the input signal with respect to distortion compensation of AM / AM characteristics and AM / PM characteristics;
With respect to memory effect distortion compensation, one or more delay processing units constituting memory predistortion means for outputting a correction value corresponding to the level value of the input signal;
Adding means for adding the correction values output from the memoryless predistortion means and the correction values output from all delay processing units constituting the memory predistortion means;
Distortion imparting means for imparting distortion to the input signal according to the addition result by the adding means,
Each of the delay processing units is capable of switching whether or not to output the level value of the input signal, and delays the level value output from the delay selection unit by a predetermined time in units of samples. And delay means for outputting, and table means for outputting a correction value corresponding to the level value output from the delay means,
The delay selection means provided in each of the delay processing units is provided in the delay processing unit of the next stage in a state where the level value of the input signal is output when there is a delay processing unit of the next stage. Output the value of the level of the input signal to the delay selection means,
When the delay processing unit has two or more stages, the delay unit provided in each of the delay processing units uses the level value output from the delay selection unit for a different time for each of the delay processing units. Delay,
A predistortion distortion compensation device characterized by the above.

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