JP2005203925A - Distortion compensated amplifier device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately adjust the delay time between a signal before amplification and a signal after the amplification, in a distortion compensated amplifier device for performing distortion compensation, by providing reverse characteristic distortions of distortions, generated in an amplifier, to a digital signal before amplification by the amplifier 6, which is subjected to distortion compensation. <P>SOLUTION: Distortion providing means 1, 2 provide distortion to a digital signal, before amplification by the amplifier in a predetermined mode; an analog converting means 5 converts the digital signal into an analog signal, the amplifier amplifies the analog signal; and digital converting means 9, 10 convert the amplified analog signal into a digital signal. Delay time adjusting means 11-13 adjust the delay time between two signals using processing, in which any one of the digital signal before being provided with the distortion and the converted digital signal is delayed using an interpolation method; and distortion providing mode control means 4, 3 control the mode at which the distortion is provided, on the basis of an error between the two signals, after delay time adjustment. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to, for example, a predistortion type distortion compensation amplifying apparatus that deforms and transmits a transmission signal in advance in order to compensate for nonlinearity of an amplifier in a wireless transmission apparatus. The present invention relates to a distortion compensation amplifying apparatus that improves the compensation characteristics of nonlinear distortion by improving the accuracy of adjustment of a delay time with a feedback signal after amplification.

For example, in an amplifier such as a power amplifier (PA) used in a radio base station apparatus of a mobile communication system, degradation of the transmission spectrum due to nonlinearity of the amplifier becomes a problem. Leakage power, intermodulation distortion, and the like become problems.
Here, the graph of FIG. 6 shows an example of the AM-AM conversion characteristic and the AM-PM conversion characteristic as the input / output characteristic of the nonlinear amplifier, the horizontal axis indicates the input amplitude, The vertical axis represents the output amplitude, and the right vertical axis represents the output phase.
As shown in the figure, in the input / output characteristics of a normal amplifier, the output amplitude saturation characteristic called AM-AM conversion in which the deviation from the ideal characteristic increases as the output amplitude increases, and as the output amplitude increases. There is a change due to the input amplitude of the output phase called AM-PM conversion in which the phase rotates. Specifically, when the input amplitude is sufficiently small from the saturation point, the amplitude characteristic is a straight line and there is no phase change. However, as the input amplitude approaches the saturation point, the output amplitude saturates and the output phase exhibits a so-called nonlinear characteristic that begins to rotate. As a result, degradation of the transmission spectrum occurs and leakage outside the transmission band occurs.

In order to improve the degradation of the transmission spectrum as described above, a predistortion method in which the amplifier output becomes an ideal characteristic by giving inverse characteristics to the amplitude and phase in front of the amplifier so as to compensate for the nonlinearity of the amplifier. It has been known.
Here, the graph of FIG. 7 shows an example of a distortion compensation characteristic for AM-AM conversion and an example of a distortion compensation characteristic for AM-PM conversion as predistortion characteristics that give the inverse characteristics of the input / output characteristics of the nonlinear amplifier. The horizontal axis indicates the input amplitude, the left vertical axis indicates the output amplitude, and the right vertical axis indicates the output phase.

FIG. 8 shows a configuration example of a distortion compensation amplifying apparatus having a predistortion type distortion compensation circuit.
As shown in the figure, the distortion compensation amplifying apparatus of this example includes a complex multiplication circuit 41, a distortion compensation table 42, a distortion compensation table update control circuit 43, and an error detection circuit between an input terminal I21 and an output terminal O21. 44, a predistortion circuit P11, a quadrature modulator 45, a power amplifier (PA) 46, a distributor 47, a reference clock (Mfs) 48, a sampling clock phase adjustment circuit 49, a quadrature detection circuit 50, An A / D (Analog to Digital) conversion circuit 51, a phase amplitude correction circuit 52, and a fixed delay circuit 53 are provided.
Here, the predistortion circuit P11, the quadrature modulator 45, the power amplifier (PA) 46, the divider 47, the quadrature detection circuit 50, the phase amplitude correction circuit 52, and the fixed delay circuit 53 provided in the distortion compensation amplification device of this example. The operations are generally the same as the operations of the corresponding processing units P1, 5, 6, 7, 9, 11, and 13 shown in FIG.

Hereinafter, with respect to the distortion compensation amplifying apparatus of the present example, portions different from the configuration and operation shown in FIG. 1 will be described.
The digital-analog conversion timing in the quadrature modulator 45 is based on the frequency Mfs (= M × fs) of the clock signal from the reference clock 48, and the frequency Mfs is a frequency M times the sampling frequency fs. The digital / analog conversion timing of the quadrature modulator 45 is controlled by a clock timing obtained by dividing the frequency by M to the sampling frequency fs rate (sampling rate) by the sampling clock phase adjustment circuit 49. The A / D conversion circuit 51 is also controlled at the same clock timing.

Here, the sampling clock that defines the conversion timings of the quadrature modulator 45 and the A / D conversion circuit 51 needs to be adjusted by the error detection circuit 44 so that the signal timings coincide with each other. Therefore, if the timing of the sampling clock for the quadrature modulator 45 is fsTX and the timing of the sampling clock for the A / D conversion circuit 51 is fsRX, the timing of fsRX can be adjusted by a control step of (1 / Mfs). Thus, the optimum value is fixedly adjusted at the time of shipment of the apparatus. As a method for adjusting the optimum value, a method for adjusting the output average of the error detection circuit 44 to be minimum, or a method for adjusting the distortion level of the RF transmission spectrum to be minimum is used.
Further, in this example, the fixed delay circuit 53 gives an approximate delay amount of the delay from the complex multiplier circuit 41 to the phase amplitude correction circuit 52, and together with the fine adjustment amount of the sampling clock phase adjustment circuit 49, The error detection circuit 44 detects a difference value between the output (transmission modulation signal) from the fixed delay circuit 53 and the adjusted reception modulation signal that is an output from the phase amplitude correction circuit 52 as an error signal.
Various studies have been made on the delay time in predistortion (see, for example, Patent Documents 1 to 3).

JP-A-9-83417 JP 2002-77285 A JP 2003-273663 A

However, the distortion compensation amplifying apparatus as shown in FIG. 8 has a problem of the timing error of the input signal to the error detection circuit 44 as a function that greatly affects the performance of the distortion compensation characteristic by the predistortion method. If there is a timing shift between the two signals input to the error detection circuit 44, the error due to the timing shift is superimposed on the error due to the original non-linear distortion, which causes the distortion compensation amount to deteriorate. . For this reason, the adjustment step by the sampling clock phase adjustment circuit 49 needs to be sufficiently smaller than the signal band (that is, make M of the reference clock frequency Mfs large), and in particular, CDMA (Code Division In a modulation system with a wide band of a transmission modulation signal such as a multiple access system, it has been difficult to set a sufficiently high M due to restrictions on the performance of a digital circuit.
The present invention has been made in view of such a conventional situation. For example, in predistortion type distortion compensation, a signal before amplification by an amplifier to be compensated for distortion and a feedback signal after amplification by the amplifier. An object of the present invention is to provide a distortion compensation amplifying apparatus that can improve the accuracy of adjustment of delay time and thereby improve the compensation characteristics of nonlinear distortion generated in the amplifier.

In order to achieve the above object, in the distortion compensation amplification apparatus according to the present invention, the inverse characteristic of the distortion generated in the amplifier is obtained with respect to the digital signal before being amplified by the amplifier as the distortion compensation target as follows. Distortion compensation is performed by applying the distortion having.
In other words, the distortion applying means applies distortion in a predetermined manner to the digital signal before being amplified by the amplifier that is the distortion compensation target. The analog conversion means converts the digital signal, which is distorted by the distortion applying means, into an analog signal. The distortion compensation target amplifier amplifies the analog signal converted by the analog conversion means. The digital conversion means converts the amplified analog signal output from the amplifier that is the distortion compensation target into a digital signal. The delay time adjusting unit uses a process of delaying at least one of the digital signal before being distorted by the distortion applying unit and the digital signal converted by the digital converting unit by an interpolation method. The delay time between the digital signal before being given and the digital signal converted by the digital conversion means is adjusted. The distortion imparting mode control unit controls the mode (predetermined mode) in which distortion is applied by the strain applying unit based on the error between the two digital signals after the delay time is adjusted by the delay time adjusting unit.
Therefore, a delay time between these two digital signals is obtained by using a process of delaying at least one of the digital signal before being distorted by the distortion applying means and the digital signal converted by the digital converting means by the interpolation method. By adjusting and matching the timing between these two digital signals, a highly accurate time adjustment is possible. For example, in predistortion type distortion compensation, the signal before amplification by the amplifier to be compensated for distortion The accuracy of adjustment of the delay time with the feedback signal after amplification by the amplifier can be improved, and thereby the compensation characteristic of the nonlinear distortion generated in the amplifier can be improved.

Here, various modes may be used as a mode (predetermined mode) in which distortion is applied by the strain applying unit. For example, an error between two digital signals is reduced by the strain applying mode control unit. By being updated, it is possible to approach a mode in which distortion having reverse characteristics of distortion generated in an amplifier that is a distortion compensation target is applied.
In addition, as an example (predetermined mode) for applying distortion by the distortion applying unit, a table value of a distortion compensation table is used as an example, and the table value corresponds to, for example, the amplitude value or power value of the signal. Information specifying the amplitude and phase of distortion to be generated is defined.
Moreover, as an analog conversion means, you may have a function which performs modulation processes, such as quadrature modulation, for example. Correspondingly, the digital conversion means may have a function of performing demodulation processing such as quadrature detection (orthogonal demodulation).
Further, various modes may be used as the interpolation method, for example, the Nyquist interpolation method.
Further, as the delay time adjusting means, for example, a means for performing a time adjustment by an interpolation method and a time adjustment by a method other than the interpolation method may be used.

As an example of the configuration, the delay time adjusting unit is a process for delaying at least one of the digital signal before being distorted by the distortion applying unit and the digital signal converted by the digital converting unit by an interpolation method as follows. Process by configuration.
That is, the interpolation means converts one digital signal of the digital signal before being distorted by the distortion applying means and the digital signal converted by the digital conversion means by each of interpolation methods using three or more different delay times. Delay. Interpolation error detection and selection means detects an error between the digital signal delayed by the respective interpolation method and the other digital signal, and selects an interpolation method that minimizes the error. The interpolation method delay time control means respectively sets the delay time used in the interpolation method selected by the interpolation error detection / selection means as the central delay time in the interpolation method using the three or more different delay times. Controls the delay time used in the interpolation method.
Here, various numbers may be used as the number of interpolation methods using three or more different delay times.
Various modes may be used as the central delay time in the interpolation method using three or more different delay times. As an example, as three or more different delay times, a delay time having a central value, one or more delay times on a side larger than the central value, and one or more delays on a side smaller than the central value When time is used, a mode in which the delay time having the central value is the central delay time can be used.
For example, a configuration in which a digital signal is delayed by an interpolation method using one delay time or a configuration in which a digital signal is delayed by an interpolation method using two different delay times may be used. Good.

  As described above, according to the distortion compensation amplifying apparatus of the present invention, distortion is applied in a predetermined manner to the digital signal before being amplified by the distortion compensation amplifier by the distortion applying unit, and the distortion is applied. The converted digital signal is converted into an analog signal, the analog signal is amplified by an amplifier that is a distortion compensation target, the amplified analog signal output from the amplifier that is the distortion compensation target is converted into a digital signal, and a distortion applying unit The delay time between these two digital signals is adjusted using a process of delaying at least one of the digital signal before being distorted by the digital signal and the converted digital signal by an interpolation method, and 2 after the delay time adjustment. Since the distortion imparting unit controls the mode of applying distortion (the predetermined mode) based on the error between two digital signals, for example, In distortion-type distortion compensation, it is possible to improve the accuracy of adjustment of the delay time between the signal before amplification by the amplifier to be compensated for distortion and the feedback signal after amplification by the amplifier, thereby generating the distortion in the amplifier. Nonlinear distortion compensation characteristics can be improved.

Embodiments according to the present invention will be described with reference to the drawings.
In this embodiment, a case is shown in which the present invention is applied to a distortion compensation amplifying apparatus having a predistortion type distortion compensation circuit in a wireless transmitter.

A distortion compensation amplifying apparatus according to a first embodiment of the present invention will be described.
FIG. 1 shows a configuration example of the distortion compensation amplifying apparatus of this example.
As shown in the figure, the distortion compensation amplifying apparatus of this example includes a complex multiplication circuit 1, a distortion compensation table 2, a distortion compensation table update control circuit 3, and an error detection circuit between an input terminal I1 and an output terminal O1. 4, predistortion circuit P 1, quadrature modulator 5, power amplifier (PA) 6, distributor 7, reference clock (fs) 8, quadrature detection circuit 9, and A / D (Analog to Digital) A conversion circuit 10, a phase amplitude correction circuit 11, a delay correction circuit 12, and a fixed delay circuit 13 are provided.

First, an example of the overall operation performed by the distortion compensation amplification apparatus of this example will be shown.
From the input terminal I1, a digital sampling value of a transmission modulation signal which is a complex signal composed of an in-phase signal and a quadrature signal is input. Here, the sampling rate is usually at least twice the frequency band of the modulation signal to be transmitted, and in this example, the sampling rate = fs.
The transmission modulation signal is input to the complex multiplication circuit 1, the distortion compensation table 2, and the distortion compensation table update control circuit 3 constituting the predistortion circuit P1, and subjected to predistortion processing. Further, the transmission modulation signal is input to the fixed delay circuit 1.

The distortion compensation table 2 is a complex multiplication of complex vectors that give predistortion characteristics (AM-AM distortion compensation characteristics and AM-PM distortion compensation characteristics) as shown in FIG. 7 using the input amplitude of the input transmission modulation signal as an address. It outputs to the circuit 1 and gives each element of the complex vector as a multiplication coefficient of the complex multiplication circuit 1.
The complex multiplication circuit 1 performs complex multiplication of the input transmission modulation signal and the multiplication coefficient, and outputs the complex multiplication result to the quadrature modulator 5 as a predistortion signal.
The predistortion signal is input to the quadrature modulator 5 and converted into a radio frequency (RF) signal by digital analog conversion and frequency conversion. Thereafter, the transmission power is amplified by the power amplifier 6, and the distributor 7. And output as an RF transmission signal from the output terminal O1. The output signal is finally spatially radiated from an antenna (not shown).
Here, in the power amplifier 6, as shown in FIG. 6, the amplified signal is subjected to nonlinear distortion by AM-AM conversion and AM-PM conversion. In this example, the predistortion characteristic given to the predistortion signal cancels out the non-linear distortion, so that the non-linear distortion is reduced at the output from the power amplifier 6, and an RF signal with little distortion that is almost the same as the original transmission modulation signal. Can be output.

The reference clock 8 generates a clock signal having a sampling frequency fs rate (sampling rate) and supplies the clock signal to the quadrature modulator 5 and the A / D conversion circuit 10 as a common clock signal.
The distributor 7 distributes a part of the RF signal input from the power amplifier 6 and outputs it to the quadrature detection circuit 9. The quadrature detection circuit 9 converts the signal input from the distributor 7 into a signal in the same frequency band as the transmission modulation signal by RF / baseband conversion, and then the A / D conversion circuit 10 outputs the signal after the frequency conversion. Is converted into a digital complex signal (detection signal) having the same sampling rate as that of the transmission modulation signal.
Here, since the output from the A / D conversion circuit 10 usually has an absolute phase shift and an absolute amplitude shift caused by the analog circuit and the line length, it is necessary to correct these shifts. The phase / amplitude correction circuit 11 is a circuit that realizes the correction function. As an example of a specific operation, a known pattern is used as a transmission modulation signal, based on an input from the fixed delay circuit 13. An operation of correcting an absolute phase shift and an absolute amplitude shift is performed on an input signal (received modulation signal) from the / D conversion circuit 10. Note that, as the known pattern, for example, a constant value that does not affect the delay is preferably used.

  The phase / amplitude correction circuit 11 is generally an indispensable technique in digital predistortion (DPD), and corrects phase rotation, amplitude deviation, and the like generated in a transmission signal generated through an analog system. is there. For example, in MMSE generally used as a DPD algorithm, a difference (error) between an original signal and a signal fed back with distortion in an amplifier is obtained, and the difference (the error) is minimized. In other words, predistortion is performed so that the signal after feedback approaches the original transmission signal and distortion in the amplifier disappears. For this reason, it is necessary to eliminate errors other than distortion in the amplifier as much as possible. Factors for such errors include, for example, sample timing error, absolute phase error, amplitude deviation, IQ imbalance, and DC offset deviation. In this example, in particular, the sample timing error is corrected with high accuracy.

The delay correction circuit 12 is a circuit that can adjust the delay with respect to the received modulated signal whose phase amplitude is corrected by the phase amplitude correction circuit 11 with a theoretically infinitesimal accuracy. The received modulation signal after delay adjustment based on the input is output to the error detection circuit 4.
The fixed delay circuit 13 applies an approximate delay amount of the delay from the complex multiplier circuit 1 to the delay correction circuit 12 to the input transmission modulation signal, and the transmission modulation signal to which the delay amount is applied is combined with the error detection circuit 4 and the phase amplitude. The data is output to the correction circuit 11 and the delay correction circuit 12.
The error detection circuit 4 detects a difference value between the transmission modulation signal that is an input from the fixed delay circuit 13 and the reception modulation signal that is an input from the delay correction circuit 12 as an error signal, and distortion-compensates the detection result. Output to the table update control circuit 3.
The distortion compensation table update control circuit 3 updates the table value of the distortion compensation table 2 based on the input transmission modulation signal so that the power of the error signal detected by the error detection circuit 4 is minimized. A good distortion compensation table is generated. Here, the power of the error signal detected by the error detection circuit 4 ideally corresponds to nonlinear distortion generated in the power amplifier 6. Further, as a method of updating the table value of the distortion compensation table 2, generally, a perturbation method that is a method of updating the table value in a direction in which error power is reduced by shifting the table value to plus or minus (±), or least squares, An error estimation method (LMS) or the like is used.

Next, the delay correction circuit 12 will be described in more detail.
FIG. 2 shows a configuration example of the delay correction circuit 12.
As shown in the figure, the delay correction circuit 12 of this example includes two input terminals I11 and I12 and one output terminal O11, and includes a first interpolation circuit 21 and a second interpolation circuit 22. A third interpolation circuit 23, an error detection circuit 24, and a delay amount control circuit 25.
Here, a reception modulation signal which is an output from the phase amplitude correction circuit 11 is input to one input terminal I11, and the reception modulation signal is input to each of the three interpolation circuits 21 to 23. Further, the other input terminal I12 receives a delayed transmission modulation signal that is an output from the fixed delay circuit 13, and the delayed transmission modulation signal is input to the error detection circuit 24.

An example of the operation performed by the delay correction circuit 12 of this example is shown.
The first interpolation circuit 21 gives a delay of the delay amount τ = x to the received reception modulation signal, and outputs the reception modulation signal after the delay to the output terminal O11 and the error detection circuit 24.
The second interpolation circuit 22 gives a delay of τ = (x + Δx) to the received reception modulation signal and outputs the delayed reception modulation signal to the error detection circuit 24.
The third interpolation circuit 23 gives a delay of τ = (x−Δx) to the received reception modulation signal and outputs the delayed reception modulation signal to the error detection circuit 24.
Here, the signal sequence of the received modulated signal input from the input terminal I11 is R (n) (n = −∞,..., −1, 0, 1, 2, 3, 4,...), Assuming that the output from each of the interpolation circuits 21 to 23 defined by the delay amount τ is DL (τ, n), each of the interpolation circuits 21 to 23 performs an operation as shown in Equation 1 using the Nyquist interpolation method. By doing so, a delay can be given to the received modulation signal.

  Specifically, the signal DL (x, n) output from the first interpolation circuit 21 is expressed as Equation 2, and the signal DL (x + Δx, n) output from the second interpolation circuit 22 is expressed as Equation 2. 3 and the signal DL (x−Δx, n) output from the third interpolation circuit 23 is expressed as in Expression 4. In this example, L is an integer of 4 or more.

Here, FIG. 3 schematically shows an example of the reception modulation signal R (n).
FIG. 4 also shows the received modulation signals DL (x, n), DL (x + Δx, n), and DL (x−Δx, n) delayed by the Nyquist interpolation method in each of the interpolation circuits 21 to 23. An example is shown schematically.
In this example, the signals shown in FIG. 3 are input to the interpolation circuits 21 to 23, and the signals shown in FIG. 4 are output as the processing results of the signals by the interpolation circuits 21 to 23. As shown in FIG. 4, by giving a delay of (x−Δx), x, (x + Δx), a timing shift of (± Δx) is generated with respect to the signal waveform with “X” in the figure as the center. be able to.

The error detection circuit 24 performs error comparison between the signals shown in the equations 2, 3 and 4 inputted from the interpolation circuits 21 to 23 and the delayed transmission modulation signal inputted from the input terminal I12. To select the signal with the smallest average error power from the signals shown in the above equations 2, 3 and 4 inputted from the interpolation circuits 21 to 23, and delay the selection result. Output to the quantity control circuit 25.
The delay amount control circuit 25 sets the value of τ of the signal selected by the error detection circuit 24 as a new value of x (that is, updates the value of x) and uses it in each of the interpolation circuits 21, 22, and 23. The Nyquist interpolation coefficient {sin (τ−mπ) / (τ−mπ)} is obtained by calculation and updated. In the delay amount control circuit 25, for example, not only the value of x but also the value of Δx can be updated.

Here, since there is usually no time restriction in the above-described calculation itself, for example, it is possible to cope with the problem by performing offline calculation and updating it in batches.
Specifically, in this calculation, a sequence of Nyquist interpolation coefficients {sin (τ−mπ) / (τ−mπ)} [m = −L−L] is calculated, and there are (2L + 1) coefficients. Further, since the value of the delay amount τ is different in each of the interpolation circuits 21, 22, and 23, the coefficient of three times (τ = x, τ = (x + Δx), τ = (x−Δx)) is held, and x The values are updated sequentially to converge to the optimum value.
The operation of each of the interpolation circuits 21, 22, and 23 in this example is realized by, for example, an FPGA (Field Programmable Gate Array) or the like, and performs a convolution operation between a sampling signal that is an input signal and a Nyquist interpolation coefficient in real time. To process. On the other hand, the update process of the Nyquist interpolation coefficient is a process of detecting the update state and the output of the error detection circuit 24 and leading the value of x to the optimum value while monitoring the error power. For example, the update process can be calculated by taking a sufficient amount of time.

In addition, the optimum value of the table value of the distortion compensation table 2 usually changes due to the ambient temperature, aging, etc., so it is desirable to constantly update it. For this reason, the delay correction circuit 12 always performs Nyquist interpolation. It is desirable. However, for example, when the optimum value of the table value of the distortion compensation table 2 does not change, it is possible to obtain a good table value even if the update is stopped after the optimum value is obtained.
Further, as an example of the update procedure, (1) accumulation of a difference (error vector) between a delayed transmission modulation signal as a transmission signal and a reception modulation signal as a feedback signal, and (2) a distortion compensation table for predistortion. (1), (2), (3) such as calculation of the table value of 2 or calculation of the Nyquist interpolation coefficient, (3) update of the table value of the distortion compensation table 2 for predistortion or update of the Nyquist interpolation coefficient The process is repeated all the time to reach the optimal solution. The accumulation method in the process (1) varies depending on the calculation method in the process (2). Specifically, for example, the calculation method is a minimum mean square error (MMSE) method. In this case, the error vector of all accumulated samples is accumulated as the accumulation method, and when the calculation method is the steepest descent method, the integral value of the power value of the error vector is accumulated as the accumulation method. In addition, it is necessary to perform observation in a certain time section.

Further, in order to increase the convergence speed to the optimum solution, it is desirable to use as many samples as possible. For example, the maximum speed can be achieved when all samples are used.
Further, as a procedure for updating the table value of the distortion compensation table 2 for predistortion and a process for optimizing the delay time, for example, a procedure for alternately performing these processes, or after the delay time has converged A procedure for updating the table value, or a procedure for alternately performing these processes after the delay time has converged to some extent can be used. It is considered preferable to use a procedure in which the above processes are alternately performed.

By sequentially performing the update by the delay amount control circuit 25 as described above, the optimum delay adjustment can be performed within the accuracy of Δx. Further, if Δx is reduced when the error power value becomes small, the accuracy of delay adjustment can be further improved. In this example, since the interpolation coefficient is obtained by calculation in this example, it is theoretical. There is no limit to the accuracy of delay adjustment.
Therefore, for example, in the conventional method, there is a problem that the accuracy of delay adjustment is limited by the clock speed of the digital circuit. In this example, the accuracy of delay adjustment can be greatly improved by processing the clock speed of the sampling rate. Therefore, an effect that the compensation amount of nonlinear distortion can be improved can be obtained.

As described above, in the distortion compensation amplifying apparatus of this example, the distortion compensation function (in this example, in the present example) is preceded by the transmission amplifier (in this example, the power amplifier 6) that amplifies and outputs the modulated signal transmitted by the wireless transmission apparatus. A predistortion circuit P1) is provided, and the modulation signal is multiplied by a distortion compensation coefficient in order to compensate for the signal distortion generated in the transmission amplifier by the following configuration.
That is, a distortion compensation table 2 that inputs a transmission modulation signal (transmission digital modulation signal) that is a digital value generated at a sampling rate fs and outputs a distortion compensation coefficient using the power value of the transmission digital modulation signal as an address, and the transmission A complex multiplication circuit 1 that performs complex multiplication of the digital modulation signal and the distortion compensation coefficient and outputs a distortion compensation signal; and inputs the distortion compensation signal to perform orthogonal modulation, and also performs digital analog conversion and radio frequency conversion to generate a radio frequency signal. , A transmission amplifier (in this example, a power amplifier 6) for amplifying the radio frequency signal, and distributing and outputting the amplified radio frequency signal to radiate one of the distribution signals to the antenna. A distributor 7 that outputs the other distributed signal to the quadrature detection circuit 9 and a quadrature detection of the other distributed signal to convert it into a reception modulation signal. A clock signal is supplied to the cross detection circuit 9, the A / D conversion circuit 10 that digitizes the received modulation signal in synchronization with the quadrature modulator 5, and the quadrature modulator 5 and the A / D conversion circuit 10. A reference clock 8; a phase amplitude correction circuit 11 that outputs a reception modulation signal after adjustment to make the digitized reception modulation signal and transmission digital modulation signal in phase and amplitude; and the reception modulation after adjustment A delay correction circuit 12 that adjusts the delay of the signal and uses the received modulation signal after the delay adjustment as one input of the error detection circuit 4, and a transmission after the fixed delay by giving a fixed delay to the transmission digital modulation signal A fixed delay circuit 13 that uses the modulation signal as the other input of the error detection circuit 4 and outputs the transmission modulation signal after the fixed delay to the phase amplitude correction circuit 11 and the delay correction circuit 12; An error detection circuit 4 that inputs a delayed modulated transmission signal and a received modulated signal after delay adjustment and obtains a difference between them, and distortion compensation so as to minimize the error power by inputting the difference signal A distortion compensation table update control circuit 2 for updating the table value of the table 2 is provided.

Further, in the distortion compensation amplifying apparatus of this example, the delay correction circuit 12 is configured as follows.
That is, it has at least three interpolation circuits 21, 22, and 23 that give different delay amounts, and detects error power between the output from each of these interpolation circuits 21, 22, and 23 and the transmission modulation signal after the fixed delay. The delay amount control circuit 25 sets the delay amount in the interpolation circuits 21, 22, and 23 based on the delay amount that is detected by the circuit 24 and that minimizes the average value of the error power.
In the distortion compensation amplifying apparatus of this example shown in FIG. 1, all digital signals are processed at the sampling rate except for the Nyquist interpolation coefficient calculation process in the delay correction circuit 12.

  Therefore, in the distortion compensation amplifying apparatus of this example, for example, even when a multi-code or multi-carrier transmission signal is amplified, the predistortion circuit P1 that increases the convergence speed of the distortion compensation table 2 can be realized. it can. Specifically, for example, after the amplified signal from the power amplifier 6 is sampled as a feedback signal, the digital signal processing is used to interpolate using arbitrary times x and Δx (in this example, Nyquist interpolation). By correcting the delay of the feedback signal, the timing alignment by adjusting the delay time between the input signal (transmission modulation signal in this example) and the feedback signal (reception modulation signal in this example) in digital predistortion is improved. can do. Thereby, the accuracy of distortion compensation can be improved.

In the distortion compensation amplifying apparatus of this example, the distortion applying means is configured by a function of applying distortion to the digital signal input by the complex multiplication circuit 1 in a predetermined manner defined by the distortion compensation table 2. An analog conversion means is configured by the function of the quadrature modulator 5 performing quadrature modulation and D / A (Digital to Analog) conversion, and the power amplifier 6 amplifies the signal to configure an amplifier that is a distortion compensation target. The digital conversion means is configured by the function of performing A / D conversion by the A / D conversion circuit 10 on the signal quadrature detected by the quadrature detection circuit 9, and includes a phase amplitude correction circuit 11 and a fixed delay circuit. 13 and the delay correction circuit 12 using the interpolation method constitute a delay time adjusting means by the function of adjusting the delay time of the two digital signals. 4 strain imparted mode control means is constituted by the functions of the distortion compensation table updating control circuit 3 updates the table value of the distortion compensation table 2 based on the detection result of the error due.
Further, in the delay correction circuit 12 of this example, the interpolation means is configured by the function of delaying the digital signal by an interpolation method in which the plurality of interpolation circuits 21, 22, and 23 have different delay times, and the error detection circuit 24 Interpolation error detection and selection means is configured by the function to detect the error between the digital signal delayed by each interpolation method and the digital signal to be compared and select the interpolation method with the smallest error, and control the delay amount The interpolation method delay time control means is configured by the function of controlling the delay time in each interpolation method so that the circuit 25 uses the delay time used in the selected interpolation method as the central delay time.

A distortion compensation amplifying apparatus according to a second embodiment of the present invention will be described.
FIG. 5 shows a configuration example of the distortion compensation amplifying apparatus of this example.
As shown in the figure, the distortion compensation amplifying apparatus of this example includes a complex multiplication circuit 1, a distortion compensation table 2, a distortion compensation table update control circuit 3, and an error detection circuit between an input terminal I1 and an output terminal O1. 4, predistortion circuit P 1, quadrature modulator 5, power amplifier (PA) 6, distributor 7, reference clock (fs) 8, quadrature detection circuit 9, and A / D (Analog to Digital) A conversion circuit 10, a phase amplitude correction circuit 11, and a delay correction circuit 31 are provided.
Here, the configuration of the distortion compensation amplifying apparatus of the present example is roughly the same as that of the distortion compensation amplifying apparatus shown in FIG. 1, except that the delay correction circuit 12 and the fixed delay circuit 13 shown in FIG. The delay correction circuit 31 having the same function as the delay correction circuit 12 shown in FIG. 1 is provided between the input terminal I1 and the error detection circuit 4. In this example, the same processing units as those shown in FIG. 1 are denoted by the same reference numerals.

Specifically, in this example, the transmission modulation signal input from the input terminal I1 includes the complex multiplication circuit 1, the distortion compensation table 2, the distortion compensation table update control circuit 3, the delay correction circuit 31, and the phase amplitude. Input to the correction circuit 11. Then, the phase amplitude correction circuit 11 corrects the reception modulation signal input from the A / D conversion circuit 10 based on the input transmission modulation signal. The corrected reception modulation signal output from the phase amplitude correction circuit 11 is input to the error detection circuit 4 and the delay correction circuit 31.
The delay correction circuit 31 has a configuration similar to that shown in FIG. 2, for example. In this example, the transmission modulation signal input from the input terminal I1 is input to one input terminal I11, and the other The reception modulation signal input from the phase amplitude correction circuit 11 is input to the input terminal I12 of the signal, and thereby the delay of the transmission modulation signal is adjusted, and the transmission modulation signal after the delay adjustment has an error from the output terminal O11. It is output to the detection circuit 4. The error detection circuit 4 detects an error between the signal input from the phase amplitude correction circuit 11 and the signal input from the delay correction circuit 31.

As described above, in the distortion compensation amplifying apparatus of this example, the delay time of the transmission modulation signal input from the input terminal I1 is corrected by the delay correction circuit 31, for example, as described in the first embodiment. Effects can be obtained.
In the distortion compensation amplification device of this example, the delay time adjusting means is configured by the function of adjusting the delay times of the two digital signals by the phase amplitude correction circuit 11 and the delay correction circuit 31 using the interpolation method.

Here, the configuration of the distortion compensation amplification device and the like according to the present invention is not necessarily limited to the above-described configuration, and various configurations may be used. The present invention can also be provided as, for example, a method or method for executing the processing according to the present invention, a program for realizing such a method or method, or a recording medium for recording the program. It is also possible to provide various devices and systems.
The application field of the present invention is not necessarily limited to the above-described fields, and the present invention can be applied to various fields.

In addition, as various kinds of processing performed in the distortion compensation amplifying apparatus according to the present invention, for example, a processor executes a control program stored in a ROM (Read Only Memory) in a hardware resource including a processor and a memory. May be used, and for example, each functional unit for executing the processing may be configured as an independent hardware circuit.
Further, the present invention can also be grasped as a computer-readable recording medium such as a floppy (registered trademark) disk or a CD (Compact Disc) -ROM storing the above control program, or the program (itself). The processing according to the present invention can be performed by inputting a program from the recording medium to a computer and causing the processor to execute the program.

It is a figure which shows the structural example of the distortion compensation amplifier which concerns on 1st Example of this invention. It is a figure which shows the structural example of a delay correction circuit. It is a figure which shows an example of a receiving modulation signal. It is a figure which shows an example of the receiving modulation signal which gave the delay by the Nyquist interpolation method. It is a figure which shows the structural example of the distortion compensation amplifier which concerns on 2nd Example of this invention. It is a figure which shows an example of the input-output characteristic of a nonlinear amplifier. It is a figure which shows an example of the predistortion characteristic which gives the reverse characteristic of the input-output characteristic of a nonlinear amplifier. It is a figure which shows the structural example of the distortion compensation amplifier which has a predistortion type distortion compensation circuit.

Explanation of symbols

  I1, I11, I12, I21... Input terminal, O1, O11, O21... Output terminal, P1, P11 .. Predistortion circuit, 1, 41. , 43 .. Distortion compensation table update control circuit, 4, 24, 44 .. Error detection circuit, 5, 45 .. Quadrature modulator, 6, 46 .. Power amplifier (PA), 7, 47. 8, 48 ... Reference clock 9, 50 ... Quadrature detection circuit 10, 51 ... A / D conversion circuit 11, 52 ... Phase amplitude correction circuit 12, 31 ... Delay correction circuit 13, 53 ..Fixed delay circuit 21, 22, 23..Interpolation circuit 25..Delay amount control circuit 49..Sampling clock phase adjustment circuit,

Claims (1)

In a distortion compensation amplifying apparatus that performs distortion compensation by giving a distortion having an inverse characteristic of distortion generated by the amplifier to a digital signal before being amplified by an amplifier that is a distortion compensation target,
Distortion applying means for applying distortion in a predetermined manner to the digital signal before being amplified by the amplifier to be subjected to distortion compensation;
Analog conversion means for converting the digital signal distorted by the distortion applying means into an analog signal;
An amplifier for distortion compensation that amplifies the analog signal converted by the analog conversion means;
Digital conversion means for converting the amplified analog signal output from the amplifier to be compensated for distortion into a digital signal;
The digital signal before being distorted by the distortion applying means using a process of delaying at least one of the digital signal before being distorted by the distortion applying means and the digital signal converted by the digital converting means by an interpolation method And a delay time adjusting means for adjusting a delay time between the digital signal converted by the digital converting means,
Distortion applying mode control means for controlling a mode of applying distortion by the distortion applying means based on an error between the two digital signals after the delay time is adjusted by the delay time adjusting means;
A distortion compensation amplifying apparatus comprising:

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