JP2011181173A - Shift register circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bidirectional shift register that requires no end-pulse to be input. <P>SOLUTION: Each stage of the bidirectional unit shift register includes: a transistor Q1 between a clock terminal CK and an output terminal OUT; a transistor Q2 which discharges the output terminal OUT; and transistors Q3, Q4 which supply first and second voltage signals Vn, Vr, respectively, mutually complementary to a first node which is a gate node of the transistor Q1. A unit shift register SR<SB>1</SB>of the first stage includes a transistor Q3D which discharges the gate of the transistor Q1 according to an output signal D<SB>1</SB>of a first dummy shift register SRD<SB>1.</SB>A unit shift register SR<SB>n</SB>of the last stage includes a transistor Q3D which discharges the gate of the transistor Q1 according to an output signal D<SB>2</SB>of a second dummy shift register SRD<SB>2</SB>. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a shift register circuit composed of only field effect transistors of the same conductivity type used in, for example, a scanning line driving circuit of an image display device. The present invention relates to a direction shift register.

  In an image display device such as a liquid crystal display device (hereinafter “display device”), a gate line (scanning line) is provided for each pixel row (pixel line) of a display panel in which a plurality of pixels are arranged in a matrix, and a display signal is displayed. The display image is updated by sequentially selecting and driving the gate lines in the period of one horizontal period. As such a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving the pixel lines, that is, the gate lines, a shift register that performs a shift operation that makes a round in one frame period of the display signal can be used. .

  The shift register used in the gate line driver circuit is preferably composed of only field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display device. For this reason, various shift registers composed only of N-type or P-type field effect transistors and display devices equipped with the shift registers have been proposed. As the field effect transistor, a MOS (Metal Oxide Semiconductor) transistor, a thin film transistor (TFT), or the like is used.

  The gate line driving circuit is constituted by a shift register having a plurality of stages. That is, the gate line driving circuit is configured by cascading a plurality of shift register circuits provided for each pixel line, that is, for each gate line. In this specification, for convenience of explanation, each of the plurality of shift register circuits constituting the gate line driving circuit is referred to as a “unit shift register”.

  For example, in a matrix type liquid crystal display device in which liquid crystal pixels are arranged in a matrix, there are frequent requests for changing the display pattern, such as inverting the display image vertically and horizontally, and changing the display order at the time of display. Arise.

  For example, display inversion is desired when a liquid crystal display device is applied to a projector for OHP (Overhead Projector) and a transmission screen is used. This is because when a transmissive screen is used, an image is projected from the back side of the screen as viewed from the viewer, and the image on the screen is inverted compared to the case of projecting from the front side of the screen. In addition, changing the display order has a dramatic effect on the display of bar graphs, histograms, etc. by causing the display image to gradually appear from the top to the bottom or vice versa. Desired if you want to get.

  One method for changing the display pattern of such a display device is to switch the signal shift direction in the gate line driving circuit. Therefore, a shift register (hereinafter referred to as a “bidirectional shift register”) capable of switching the signal shift direction has been proposed.

  For example, FIG. 13 of the following Patent Document 1 shows a unit shift register (hereinafter also referred to as “bidirectional unit shift register”) used for a bidirectional shift register, and includes only an N-channel field effect transistor. (A circuit similar to that is shown in FIG. 3 of the present specification, and the reference numerals in parentheses below correspond to those of FIG. 3).

  The output stage of the unit shift register supplies a first transistor (Q1) that supplies a clock signal (CLK) input to the clock terminal (CK) to the output terminal (OUT) and a reference voltage (VSS) to the output terminal. The second transistor (Q2). Here, the gate node (N1) of the first transistor is defined as a first node, and the gate node (N2) of the second transistor is defined as a second node.

  The unit shift register includes a third transistor (Q3) that supplies a first voltage signal (Vn) to a first node based on a signal input to a predetermined first input terminal (IN1), and a predetermined second input. A fourth transistor (Q4) that supplies a second voltage signal (Vr) to the first node based on a signal input to the terminal (IN2) is provided. The first and second voltage signals are complementary signals in which one voltage level (hereinafter simply referred to as “level”) is H (High) level and the other is L (Low) level.

  The first transistor is driven by the third and fourth transistors. The second transistor is driven by inverters (Q6, Q7) having the first node as an input terminal and the second node as an output terminal. That is, when the unit shift register outputs an output signal, the first node is set to the H level by the operation of the second and third transistors, and accordingly, the inverter sets the second node to the L level. As a result, the first transistor is turned on and the second transistor is turned off. In this state, the clock signal is transmitted to the output terminal, whereby an output signal is output. On the other hand, when the output signal is not output, the first node is set to L level by the operation of the second and third transistors, and accordingly, the inverter sets the second node to H level. Accordingly, the first transistor is turned off and the second transistor is turned on, and the voltage level of the output terminal is held at the L level.

  For example, when the first voltage signal is at the H level and the second voltage signal is at the L level, when the signal is input to the first input terminal, the first node becomes the H level, and accordingly the second node is It becomes L level, and the first transistor is turned on and the second transistor is turned off. Therefore, the output signal is output from the unit shift register at the timing when the clock signal is input thereafter. That is, when the first voltage signal is at the H level and the second voltage signal is at the L level, the unit shift register operates to shift the signal input to the first input terminal in time and output it. .

  Conversely, when the first voltage signal is L level and the second voltage signal is H level, when the signal is input to the second input terminal, the first node becomes H level, and accordingly the second node Becomes L level, the first transistor is turned on, and the second transistor is turned off. Therefore, the output signal is output from the unit shift register at the timing when the clock signal is input thereafter. That is, when the first voltage signal is at the L level and the second voltage signal is at the H level, the unit shift register operates to shift and output the signal input to the second input terminal in terms of time.

  As described above, the bidirectional unit shift register (FIG. 3 in the present specification) of FIG. 13 of Patent Document 1 switches the level of the first voltage signal and the second voltage signal for driving the first transistor, thereby changing the signal. The shift direction is switched.

JP 2001-350438 A (pages 13-19, FIGS. 13-25)

  First, the first problem of the conventional bidirectional shift register will be described. When a gate line driving circuit is configured by cascading the above-described conventional bidirectional unit shift registers, the output signal of the previous stage is input to the first input terminal (IN1) of the unit shift register of each stage, The output signal of the next stage is input to the second input terminal (IN2) (see FIG. 2 of this specification). Further, since the gate line driving circuit operates so as to select each gate line in order in a cycle of one frame period, each unit shift register outputs an output signal (gate) only in one specific horizontal period within one frame period. Line drive signal) is output and not output during other periods. Therefore, in each unit shift register, the third and fourth transistors (Q3, Q4) that drive the first transistor (Q1) are turned off in most of the one frame period.

  In the conventional unit shift register, when the third and fourth transistors are turned off, the gate of the first transistor, that is, the first node (N1) is in a floating state. In particular, the period during which no output signal is output (non-selection period) lasts for about one frame period, and the first node is kept off by maintaining the first node at the L level in the floating state during that period. It is. At this time, if a leakage current is generated in the third transistor (when the first voltage signal is at the H level) or the fourth transistor (when the second voltage signal is at the H level), the charge associated therewith is floating in the first node. And the potential of the first node gradually rises.

  Further, the clock signal continues to be input to the clock terminal (CK) (the drain of the first transistor) even in the non-selection period, and the clock signal is coupled by the coupling via the overlap capacitance between the drain and the gate of the first transistor. While the voltage becomes H level, the potential of the first node also rises.

  As a result of the rise in the potential of the first node due to the leakage current and the clock signal, if the gate-source voltage of the first transistor exceeds the threshold voltage, the first transistor to be turned off This causes a problem of malfunction that the gate line is activated unnecessarily. As a result, when the pixel switch element (active transistor) provided in each pixel is turned on, the data in the pixel is rewritten and a display defect occurs.

  Next, the second problem will be described. In the period (selection period) in which the bidirectional unit shift register outputs an output signal, the first node (N1) is kept at the H level in the floating state, so that the first transistor (Q1) is kept on. . Then, when the clock signal at the clock terminal (CK) (the drain of the first transistor) becomes H level, the output terminal (OUT) becomes H level following this and the gate line is activated. At this time, the first node is boosted while the clock signal is at the H level due to the coupling via the drain-gate overlap capacitance, the gate-channel capacitance, and the gate-source overlap capacitance of the first transistor. This step-up of the first node has an advantage that the driving capability (capability of flowing current) of the first transistor is increased, so that the unit shift register can charge the gate line at high speed.

  However, when the first node is boosted, the drain and source of the third transistor (Q3) (when the first voltage signal is L level) or the fourth transistor (Q4) (when the second voltage signal is L level) Since a high voltage is applied between them, a leak current is likely to occur depending on the withstand voltage characteristics between the drain and the source. When the level of the first node is lowered due to the leakage current, the driving capability of the first transistor is lowered, and the falling speed of the output signal when the clock signal returns from the H level to the L level becomes slow. As a result, when the pixel transistor is delayed to be turned off, the data in the pixel is rewritten to the data of the next line, causing a problem that display failure occurs.

  The third problem will be described. In a gate line driving circuit composed of a conventional bidirectional shift register, for example, in the case of a forward shift in which a signal is shifted in the direction from the preceding stage to the subsequent stage, the first input terminal (IN1) of the unit shift register in the forefront stage In addition, a control pulse called “start pulse” corresponding to the head of each frame period of the image signal is input as an input signal. The input signal is sequentially transmitted to the cascaded unit shift registers and reaches the last unit shift register. In the conventional bidirectional shift register, immediately after the last unit shift register outputs an output signal, the “end” corresponding to the end of each frame period of the image signal is sent to the second input terminal (IN2) of the last stage. It was necessary to input a control pulse called “pulse”. Otherwise, the first transistor in the last stage cannot be turned off, and the output signal continues to be output from the last stage.

  If it is a normal shift register that shifts the signal only in one direction, a dummy stage is provided at the next stage and the output signal is used for the role of the end pulse, or the clock signal input to the last stage is Since clock signals with different phases could be used for the role of the end pulse, the end pulse was rarely necessary, and only the start pulse was often sufficient. Accordingly, many drive control devices that control the operation of a normal gate line drive circuit that shifts a signal (gate line drive signal) only in one direction output only a start pulse.

  However, in the case of a bidirectional shift register, not only the end pulse is input to the second input terminal at the last stage, but it starts at the time of reverse shift that shifts the signal from the rear stage to the front stage. It is necessary to input a pulse. Also, simply providing a dummy stage is not as simple as in the case of a shift in only one direction because the output signal of the dummy stage may become an erroneous start pulse when the shift direction is reversed. Therefore, a drive control device for a gate line drive circuit that shifts a signal in both directions employs an output circuit for an end pulse as well as a start pulse as described above, which increases the cost of the drive control device, that is, The problem of the cost increase of the display device has been invited.

  Further, the fourth problem will be described. As described above, when the bidirectional unit shift register is in the selection period, the first node (N1) is at the H level, the second node (N2) is at the L level, the first transistor (Q1) is on, The two transistors (Q2) are off. For example, in the case of the forward shift, when shifting from the state to the non-selection period, the output signal of the next stage is input to the second input terminal (IN2), so that the first node becomes L level and the first The transistor is turned off. Accordingly, the inverters (Q6, Q7) in the unit shift register set the second node to the H level, so that the second transistor is turned on.

  There is a parasitic capacitance between the gate line and the data line of the display panel, and the voltage change of the data line can be applied as noise to the gate line, that is, the output terminal (OUT) of the unit shift register due to the coupling through the parasitic capacitance. There is sex. At this time, if the second transistor is not sufficiently turned on, the charge accompanying the noise cannot be discharged from the output terminal, thereby causing a problem that the pixel transistor is turned on and erroneous data is written to the pixel. . Accordingly, when shifting to the non-selection period, it is preferable to raise the potential of the second node (the gate of the second transistor) at high speed. For this purpose, the on-resistance of the transistors (Q6, Q7) constituting the inverter may be lowered. However, since the inverter is a ratio type inverter composed of field effect transistors of the same conductivity type, if the on-resistance of the transistor is lowered, the through current flowing through the inverter increases when the output of the inverter is at the L level. An increase in power consumption becomes a problem.

  The present invention has been made to solve the above problems, and a first object of the present invention is to suppress malfunction caused by a leakage current of a transistor constituting the bidirectional unit shift register. A second object is to provide a bidirectional shift register that does not require input of an end pulse. Furthermore, in the bidirectional unit shift register, a third object is to reduce the influence of noise applied to the output terminal.

  A shift register circuit according to the present invention is a shift register circuit including a plurality of stages including a first first dummy stage and a last second dummy stage, each stage including first and second input terminals, an output A first transistor for supplying a clock signal input to the clock terminal to the output terminal, a second transistor for discharging the output terminal, and first and second voltage signals complementary to each other. Based on the input first and second voltage signal terminals and the first input signal input to the first input terminal, the first voltage signal is connected to a first node to which the control electrode of the first transistor is connected. A third transistor to be supplied; and a fourth transistor to supply the second voltage signal to the first node based on a second input signal input to the second input terminal. The foremost stage excluding the first dummy stage has a control electrode connected to the output terminal of the first dummy stage, further comprising a fifth transistor for discharging the first node of the foremost stage, The last stage excluding the second dummy stage has a control electrode connected to the output terminal of the second dummy stage, and further includes a sixth transistor for discharging the first node of the last stage.

  According to the present invention, at the time of forward shift in which a signal is shifted from the preceding stage toward the subsequent stage, the last stage is deactivated by the output signal of the second dummy stage, and the signal is shifted from the subsequent stage toward the preceding stage. During the reverse shift, the front stage is deactivated by the output signal of the first dummy stage. That is, the output signal of the second dummy stage functions as an end pulse at the time of forward shift, and the output terminal of the first dummy stage functions as an end pulse at the time of reverse shift. Therefore, it is not necessary to input an end pulse from the outside for driving the shift register circuit. In other words, a bidirectional shift operation can be performed using a drive control device that does not have an end pulse generation circuit, and cost can be reduced.

It is a schematic block diagram which shows the structure of the display apparatus which concerns on embodiment of this invention. It is a block diagram which shows the structural example of the gate line drive circuit using a bi-directional unit shift register. It is a circuit diagram of a conventional bidirectional unit shift register. FIG. 10 is a timing diagram illustrating an operation of the gate line driving circuit. It is a block diagram which shows the structural example of the gate line drive circuit using a bi-directional unit shift register. FIG. 10 is a timing diagram illustrating an operation of the gate line driving circuit. 3 is a circuit diagram of a bidirectional unit shift register according to the first embodiment. FIG. FIG. 6 is a timing chart showing an operation of the bidirectional unit shift register according to the first embodiment. 6 is a circuit diagram of a bidirectional unit shift register according to a second embodiment. FIG. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to a third embodiment. FIG. 6 is a circuit diagram of a bidirectional unit shift register according to a fourth embodiment. FIG. 10 is a timing diagram illustrating an operation of the bidirectional unit shift register according to the fourth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to a fifth embodiment. FIG. 10 is a timing diagram illustrating an operation of the bidirectional unit shift register according to the fifth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to a sixth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to a seventh embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 10 is a circuit diagram of a bidirectional unit shift register according to an eighth embodiment. FIG. 20 is a block diagram illustrating a configuration example of a gate line driving circuit using a bidirectional unit shift register according to a ninth embodiment. FIG. 20 is a circuit diagram illustrating a configuration example of a gate line driving circuit according to a ninth embodiment. FIG. 20 is a circuit diagram illustrating a configuration example of a gate line driving circuit according to a ninth embodiment. FIG. 30 is a timing diagram illustrating an operation of the gate line driving circuit according to the ninth embodiment. FIG. 30 is a timing diagram illustrating an operation of the gate line driving circuit according to the ninth embodiment. FIG. 20 is a circuit diagram illustrating a configuration example of a gate line driving circuit according to a ninth embodiment. FIG. 20 is a circuit diagram illustrating a configuration example of a gate line driving circuit according to a ninth embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

<Embodiment 1>
FIG. 1 is a schematic block diagram showing a configuration of a display device according to Embodiment 1 of the present invention, and shows an overall configuration of a liquid crystal display device 10 as a representative example of the display device.

  The liquid crystal display device 10 includes a liquid crystal array unit 20, a gate line driving circuit (scanning line driving circuit) 30, and a source driver 40. As will become clear later, the bidirectional shift register according to the embodiment of the present invention is mounted on the gate line driving circuit 30 and formed integrally with the liquid crystal array unit 20.

The liquid crystal array unit 20 includes a plurality of pixels 25 arranged in a matrix. Each of the pixel rows (hereinafter also referred to as “pixel lines”) is provided with a gate line GL ₁ , GL ₂ ... (Generically referred to as “gate line GL”). Are also provided with data lines DL ₁ , DL ₂ ... (Generic name “data line DL”). FIG. 1 representatively shows the pixels 25 in the first and second columns of the first row, and the corresponding gate lines GL ₁ and data lines DL ₁ and DL ₂ .

  Each pixel 25 includes a pixel switch element 26 provided between the corresponding data line DL and the pixel node Np, a capacitor 27 and a liquid crystal display element 28 connected in parallel between the pixel node Np and the common electrode node NC. have. The orientation of the liquid crystal in the liquid crystal display element 28 changes according to the voltage difference between the pixel node Np and the common electrode node NC, and the display brightness of the liquid crystal display element 28 changes in response to this. Thereby, the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 26. That is, by applying an intermediate voltage difference between the voltage difference corresponding to the maximum luminance and the voltage difference corresponding to the minimum luminance between the pixel node Np and the common electrode node NC, the intermediate luminance is reduced. Obtainable. Therefore, gradation brightness can be obtained by setting the display voltage stepwise.

  The gate line driving circuit 30 sequentially selects and drives the gate lines GL based on a predetermined scanning cycle. In the present embodiment, the gate line driving circuit 30 is composed of a bidirectional shift register, and the direction of the order of activating the gate line GL can be switched. The gate electrodes of the pixel switch elements 26 are connected to the corresponding gate lines GL. While a specific gate line GL is selected, the pixel switch element 26 is in a conductive state in each pixel connected thereto, and the pixel node Np is connected to the corresponding data line DL. The display voltage transmitted to the pixel node Np is held by the capacitor 27. In general, the pixel switch element 26 includes a TFT formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 28.

The source driver 40 is for outputting a display voltage, which is set stepwise by a display signal SIG that is an N-bit digital signal, to the data line DL. Here, as an example, the display signal SIG is a 6-bit signal and is composed of display signal bits DB0 to DB5. Based on the 6-bit display signal SIG, 2 ⁶ = 64 gradation display is possible in each pixel. Furthermore, if one color display unit is formed by three pixels of R (Red), G (Green), and B (Blue), approximately 260,000 colors can be displayed.

  As shown in FIG. 1, the source driver 40 includes a shift register 50, data latch circuits 52 and 54, a gradation voltage generation circuit 60, a decode circuit 70, and an analog amplifier 80.

  In the display signal SIG, display signal bits DB0 to DB5 corresponding to the display brightness of each pixel 25 are serially generated. That is, the display signal bits DB0 to DB5 at each timing indicate the display luminance in any one pixel 25 in the liquid crystal array unit 20.

  The shift register 50 instructs the data latch circuit 52 to take in the display signal bits DB0 to DB5 at a timing synchronized with a cycle in which the setting of the display signal SIG is switched. The data latch circuit 52 sequentially takes in the serially generated display signal SIG and holds the display signal SIG for one pixel line.

  The latch signal LT input to the data latch circuit 54 is activated at the timing when the display signal SIG for one pixel line is taken into the data latch circuit 52. In response thereto, the data latch circuit 54 takes in the display signal SIG for one pixel line held in the data latch circuit 52 at that time.

  The gradation voltage generation circuit 60 is composed of 63 voltage dividing resistors connected in series between the high voltage VDH and the low voltage VDL, and generates 64 gradation voltages V1 to V64, respectively.

The decode circuit 70 decodes the display signal SIG held in the data latch circuit 54 and outputs it to each of the decode output nodes Nd ₁ , Nd ₂ ... (Generic name “decode output node Nd”) based on the decode result. The voltage to be selected is selected from the gradation voltages V1 to V64 and output.

As a result, at the decode output node Nd, a display voltage (one of the gradation voltages V1 to V64) corresponding to the display signal SIG for one pixel line held in the data latch circuit 54 is simultaneously (in parallel). ) Is output. In FIG. 1, the decode output nodes Nd ₁ and Nd ₂ corresponding to the data lines DL ₁ and DL ₂ in the first column and the second column are representatively shown.

The analog amplifier 80 outputs analog voltages corresponding to the display voltages output from the decode circuit 70 to the decode output nodes Nd ₁ , Nd ₂ ... To the data lines DL ₁ , DL ₂ .

The source driver 40 repeatedly outputs a display voltage corresponding to a series of display signals SIG to the data line DL for each pixel line based on a predetermined scanning cycle, and the gate line driving circuit 30 is synchronized with the scanning cycle. By driving the gate lines GL ₁ , GL ₂ ... In this order or in the reverse order, an image based on the display signal SIG or an inverted image thereof is displayed on the liquid crystal array unit 20.

FIG. 2 is a diagram illustrating a configuration of the gate line driving circuit 30. The gate line driving circuit 30 is composed of a bidirectional shift register having a plurality of stages. That is, the gate line driving circuit 30 includes n bidirectional unit shift registers SR ₁ , SR ₂ , SR ₃ ,... SR _n connected in cascade (cascade connection) (hereinafter referred to as unit shift register SR). ₁ , SR ₂ ,..., SR _n are collectively referred to as “unit shift register SR”). One unit shift register SR is provided for each pixel line, that is, for each gate line GL.

  The clock generator 31 shown in FIG. 2 inputs two-phase clock signals CLK and / CLK having different phases to the unit shift register SR of the gate line driving circuit 30. These clock signals CLK and / CLK are controlled to be activated alternately at a timing synchronized with the scanning period of the display device.

The voltage signal generator 32 shown in FIG. 2 generates a first voltage signal Vn and a second voltage signal Vr that determine the shift direction of the signal in the bidirectional shift register. The voltage signal generator 32 shifts the signal in the direction from the front stage to the rear stage (in the order of the unit shift registers SR ₁ , SR ₂ , SR ₃ ,...) (This direction is defined as “forward direction”). The first voltage signal Vn is set to H level and the second voltage signal Vr is set to L level. Conversely, when the signal is shifted in the direction from the subsequent stage to the previous stage (in the order of the unit shift registers SR _n , SR _n−1 , SR _n−2 ,...) (This direction is defined as “reverse direction”). The second voltage signal Vr is set to H level, and the first voltage signal Vn is set to L level.

  Each unit shift register SR has a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a clock terminal CK, a first voltage signal terminal T1, and a second voltage signal terminal T2. As shown in FIG. 2, one of the clock signals CLK and / CLK is input to the clock terminal CK of each unit shift register SR so that a clock signal different from that of the adjacent unit shift register SR is input before and after that.

  The clock signals CLK and / CLK generated by the clock generator 31 can be exchanged in phase with each other in accordance with the shift direction of the signal by changing the connection of the program or wiring. The exchange by changing the connection of the wiring is effective when the shift direction is fixed in one direction before the display device is manufactured. The replacement by the program is effective when the shift direction is fixed in one direction after the display device is manufactured, or when the shift direction can be changed during use of the display device.

  A gate line GL is connected to each output terminal OUT of the unit shift register SR. That is, the signal (output signal) output to the output terminal OUT becomes a horizontal (or vertical) scanning pulse for activating the gate line GL.

The first input terminal IN1 of the unit shift register SR ₁ of the first stage is the leading stage (first stage), the first control pulse STn is input. The first control pulse STn is a start pulse corresponding to the head of each frame period of the image signal in the case of forward shift, and an end pulse corresponding to the end of each frame period of the image signal in the case of reverse shift. It becomes. The first input terminal IN1 of the unit shift register SR after the second stage is connected to the output terminal OUT of the unit shift register SR of the preceding stage. That is, the output signal of the preceding stage is input to the first input terminal IN1 of the unit shift register SR in the second and subsequent stages.

The second input terminal IN2 of the unit shift register SR _n of the n-th stage is the last stage (stage n), the second control pulse STr is input. The second control pulse STr is a start pulse in the reverse direction and an end pulse in the forward shift. The second input terminal IN2 before the (k-1) th stage is connected to the output terminal OUT of the subsequent stage. That is, the output signal of the subsequent stage is input to the second input terminal IN2 after the second stage.

  Each unit shift register SR is synchronized with the clock signals CLK and / CLK, and in the case of forward shift, the corresponding gate line GL and itself are shifted while shifting the input signal (previous output signal) input from the previous stage. To the next unit shift register SR. In the case of reverse shift, an input signal (output signal of the subsequent stage) input from the subsequent stage is shifted and transmitted to the corresponding gate line GL and the unit shift register SR of the preceding stage (unit shift register SR). Details of the operation will be described later). As a result, the series of unit shift registers SR function as a so-called gate line driving unit that sequentially activates the gate lines GL at a timing based on a predetermined scanning cycle.

  Here, in order to facilitate the description of the present invention, a conventional bidirectional unit shift register will be described. FIG. 3 is a circuit diagram showing a configuration of a conventional bidirectional unit shift register SR similar to that disclosed in Patent Document 1 described above. In the gate line driving circuit 30, the configuration of each unit shift register SR connected in cascade is substantially the same, and therefore only the configuration of one unit shift register SR will be representatively described below. Further, all the transistors constituting the unit shift register SR are field effect transistors of the same conductivity type, but in the present embodiment, all the transistors are N-type TFTs.

  As shown in FIG. 3, the conventional bidirectional unit shift register SR includes the first and second input terminals IN1 and IN2, the output terminal OUT, the clock terminal CK and the first and second voltage signal terminals T1 and T1 already shown in FIG. In addition to T2, it has a first power supply terminal S1 to which a low potential power supply potential VSS is supplied and a second power supply terminal S2 to which a high potential power supply potential VDD is supplied. In the following description, the low-potential-side power supply potential VSS is the reference potential (= 0V) of the circuit. However, in actual use, the reference potential is set based on the voltage of data written to the pixel. The potential VDD is set to 17V, the low potential side power supply potential VSS is set to -12V, and the like.

  The output stage of the unit shift register SR includes a transistor Q1 connected between the output terminal OUT and the clock terminal CK, and a transistor Q2 connected between the output terminal OUT and the first power supply terminal S1. That is, the transistor Q1 is an output pull-up transistor that supplies a clock signal input to the clock terminal CK to the output terminal OUT, and the transistor Q2 is an output pull-down transistor that supplies the potential of the first power supply terminal S1 to the output terminal OUT. It is. Hereinafter, a node to which the gate (control electrode) of the transistor Q1 constituting the output stage of the unit shift register SR is connected is defined as a node N1, and a gate node of the transistor Q2 is defined as a node N2.

  A transistor Q3 is connected between the node N1 and the first voltage signal terminal T1, and its gate is connected to the first input terminal IN1. A transistor Q4 is connected between the node N1 and the second voltage signal terminal T2, and its gate is connected to the second input terminal IN2.

  A transistor Q6 is connected between the node N2 and the second power supply terminal S2, and a transistor Q7 is connected between the node N2 and the first power supply terminal S1. The transistor Q6 has a gate connected to the second power supply terminal S2 like the drain, and is so-called diode-connected. Transistor Q7 has its gate connected to node N1. The transistor Q7 is set to have a sufficiently larger driving capability (ability to flow current) than the transistor Q6. That is, the on-resistance of the transistor Q7 is smaller than the on-resistance of the transistor Q6. Therefore, when the gate potential of the transistor Q7 increases, the potential of the node N2 decreases. Conversely, when the gate potential of the transistor Q7 decreases, the potential of the node N2 increases. That is, the transistor Q6 and the transistor Q7 constitute an inverter having the node N1 as an input end and the node N2 as an output end. The inverter is a so-called “ratio inverter” whose operation is defined by the ratio of the on-resistance values of the transistor Q6 and the transistor Q7. The inverter functions as a “pull-down drive circuit” that drives the transistor Q2 to pull down the output terminal OUT.

The operation of the unit shift register SR in FIG. 3 will be described. Since the operations of the unit shift registers SR constituting the gate line driving circuit 30 are substantially the same, the operation of the _k-th unit shift register SR _k will be representatively described here.

For simplicity, a clock terminal CK of the unit shift register SR _k will be described assuming that the clock signal CLK is inputted (in FIG. 2, for example, such unit shift register SR _1, SR ₃ corresponds to this). Further, the output signal of the unit shift register SR _k is G _k , the output signal of the previous unit (k−1 stage) unit shift register SR _k−1 is G _k−1 , and the next stage (k + 1 stage) unit. An output signal of the shift register SR _{k + 1} is defined as G _{k + 1} . The H level potentials of the clock signals CLK, / CLK, the first voltage signal Vn, and the second voltage signal Vr are assumed to be equal to the high potential side power supply potential VDD. Further, it is assumed that the threshold voltages of the transistors constituting the unit shift register SR are all equal, and the value is Vth.

  First, the case where the gate line driving circuit 30 performs the forward shift operation will be described. At this time, the voltage signal generator 32 sets the first voltage signal Vn to H level (VDD) and the second voltage signal Vr to L level (VSS). That is, in the case of the forward shift, the transistor Q3 functions as a transistor that charges (pulls up) the node N1, and the transistor Q4 functions as a transistor that discharges (pulls down) the node N1.

First, as an initial state, it is assumed that the node N1 is at L level (VSS) and the node N2 is at H level (VDD-Vth) (hereinafter, this state is referred to as “reset state”). The clock terminal CK (clock signal CLK), the first input terminal IN1 (previous stage output signal G _k-1 ), and the second input terminal IN2 (next stage output signal G _{k + 1} ) are all at L level. And In this reset state, the transistor Q1 is off (cut-off state) and the transistor Q2 is on (conduction state), so the output terminal OUT (output signal G _k ) is independent of the level of the clock terminal CK (clock signal CLK). Maintained at L level. That is, the gate line GL _k to which the unit shift register SR _k is connected is in a non-selected state.

From this state, when the output signal G _k-1 (first control pulse STn as a start pulse in the first stage) of the previous unit shift register SR _k-1 becomes H level, this is the unit shift register. transistor Q3 is input to the first input terminal IN1 of SR _k is turned on, the node N1 becomes the H level (VDD). Accordingly, since the transistor Q7 is turned on, the node N2 becomes L level (VSS). Thus, in a state where the node N1 is at the H level and the node N2 is at the L level (hereinafter, this state is referred to as “set state”), the transistor Q1 is turned on and the transistor Q2 is turned off. Thereafter, when the output signal G _k-1 in the previous stage returns to the L level, the transistor Q3 is turned off, but the node N1 becomes the H level in the floating state, and this set state is maintained.

Subsequently, the clock signal CLK input to the clock terminal CK becomes H level. At this time, since the transistor Q1 is on and the transistor Q2 is off, the level of the output terminal OUT rises accordingly. Further, the level of the node N1 in the floating state is boosted by a specific voltage due to the coupling through the gate-channel capacitance of the transistor Q1. Therefore, the level of the output terminal OUT drivability also transistor Q1 rises is kept large, the level of the output signal G _k changes following the level of the clock terminal CK. In particular, when the gate-source voltage of the transistor Q1 is sufficiently large, the transistor Q1 operates in a non-saturated region (non-saturated operation), so there is no loss of threshold voltage and the output terminal OUT is connected to the clock signal CLK. To the same level. Therefore, the output signal G _k becomes H level only during the period when the clock signal CLK is H level, and the gate line GL _k is activated to be in a selected state.

Thereafter, when the clock signal CLK returns to the L level, the output signal G _k also changes to the L level following this, and the gate line GL _k is discharged to return to the non-selected state.

Since the output signal G _k is input to the first input terminal IN1 of the next stage, the next stage output signal G _{k + 1} becomes the H level at the next timing when the clock signal / CLK becomes the H level. Sonaruto, the node N1 and the transistor Q4 of the unit shift register SR _k is turned on becomes L level. Accordingly, transistor Q7 is turned off and node N2 goes to H level. That is, the transistor Q1 is turned off and the transistor Q2 is turned on.

Thereafter, when the output signal G _{k + 1 of} the next stage returns to the L level, the transistor Q4 is turned off. At this time, since the transistor Q3 is also turned off, the node N1 is in a floating state, and the L level is maintained. That state continues until the next signal to the first input terminal IN1 is input, the unit shift register SR _k is kept in the reset state.

To summarize the above-described forward shift operations, the unit shift register SR maintains the reset state while no signal (start pulse or preceding stage output signal G _k-1 ) is input to the first input terminal IN1. In the reset state, since the transistor Q1 is off and the transistor Q2 is on, the output terminal OUT (gate line GL _k ) is maintained at the L level (VSS) with low impedance. When the signal is input to the first input terminal IN1, the unit shift register SR is switched to the set state. Since the transistor Q1 is on and the transistor Q2 is off in the set state, the output terminal OUT is at the H level and the output signal _Gk is output during the period when the signal at the clock terminal CK (clock signal CLK) is at the H level. . After that, when a signal (next-stage output signal G _{k + 1} or end pulse) is input to the second input terminal IN2, the original reset state is restored.

Thus a plurality of unit shift register SR operates cascaded as shown in FIG 2, when forming the gate line drive circuit 30, is input to the first input terminal IN1 of the unit shift registers SR ₁ of the first stage As shown in the timing chart of FIG. 4, the first control pulse STn as the start pulse is shifted in synchronization with the clock signals CLK, / CLK, and sequentially with the unit shift registers SR ₂ , SR _3. Communicated. As a result, the gate line driving circuit 30 can drive the gate lines GL ₁ , GL ₂ , GL ₃ ... In this order in a predetermined scanning cycle.

In the case of the forward shift, as shown in FIG. 4, immediately after the last unit shift register SR _n outputs the output signal G _n , the second control pulse STr as the end pulse is supplied to the second shift pulse SR _n of the unit shift register SR _n . It is necessary to input to the two input terminals IN2. As a result, the unit shift register SR _n returns to the set state.

On the other hand, when the gate line driving circuit 30 performs the backward shift operation, the voltage signal generator 32 sets the first voltage signal Vn to L level (VSS) and the second voltage signal Vr to H level (VDD). To. That is, in the case of the reverse shift, the transistor Q3 functions as a transistor that discharges (pulls down) the node N1, and the transistor Q4 functions as a transistor that charges (pulls up) the node N1, as opposed to the forward shift. To do. The second control pulse STr is input to the second input terminal IN2 of the unit shift register SR _n of the last stage as a start pulse, a first control pulse STn the first as an end pulse of the unit shift register SR ₁ of the first stage 1 input to the input terminal IN1. As described above, in the unit shift register SR of each stage, the operations of the transistors Q3 and Q4 are interchanged with those in the case of the forward shift.

Therefore, in the case of reverse shift, the unit shift register SR maintains the reset state while no signal (start pulse or next stage output signal G _{k + 1} ) is input to the second input terminal IN2. Since the transistor Q1 is off and the transistor Q2 is in the reset state, the output terminal OUT (gate line GL _k ) is maintained at a low impedance L level (VSS). When a signal is input to the second input terminal IN2, the unit shift register SR is switched to the set state. Since the transistor Q1 is on and the transistor Q2 is off in the set state, the output terminal OUT is at the H level and the output signal _Gk is output while the signal (clock signal CLK) at the clock terminal CK is at the H level. . Thereafter, when a signal (the previous stage output signal G _k-1 or the end pulse) is input to the first input terminal IN1, the original reset state is restored.

When a plurality of unit shift registers SR operating in such a manner are connected in cascade as shown in FIG. 2 and the gate line driving circuit 30 is configured, the second input terminal IN2 of the last stage (n-th stage) unit shift register SR _n is formed. As shown in the timing chart of FIG. 5, the second control pulse STr input as the start pulse is shifted at the timing synchronized with the clock signals CLK and / CLK, while being shifted by the unit shift registers SR _n−1 and SR _{n. -2} , ... are transmitted in order. Thereby, the gate line driving circuit 30 can drive the gate lines GL _n , GL _n−1 , GL _n−2 ,... In this order, that is, in the order opposite to the forward shift. it can.

In the case of reverse shift, as shown in FIG. 5, immediately after the first stage unit shift register SR ₁ outputs the output signal G1, the first control pulse STn as an end pulse is applied to the unit shift register SR _1. It is necessary to input to the first input terminal IN1. As a result, the unit shift register SR ₁ returns to the set state.

  In the above example, the example in which the plurality of unit shift registers SR operate based on the two-phase clock is shown, but it is also possible to operate using the three-phase clock signal. In that case, the gate line driving circuit 30 may be configured as shown in FIG.

  In this case, the clock generator 31 outputs clock signals CLK1, CLK2, and CLK3, which are three-phase clocks having different phases. One of the clock signals CLK1, CLK2, and CLK3 is input to the clock terminal CK of each unit shift register SR so that different clock signals are input to the adjacent unit shift registers SR. These clock signals CLK1, CLK2, and CLK3 can be changed according to the direction in which the signals are shifted by changing the connection of the program or wiring. For example, in the case of forward shift, it becomes H level in the order of CLK1, CLK2, CLK3, CLK1,. Become.

  Even when the gate line driving circuit 30 is configured as shown in FIG. 6, the operation of each unit shift register SR is the same as in the case of FIG.

  In the gate line driving circuit 30 configured as shown in FIGS. 2 and 6, for example, in the case of forward shift, each unit shift register SR must be after the next unit shift register SR operates at least once. The reset state (that is, the initial state described above) is not entered. On the other hand, in the case of reverse shift, each unit shift register SR is not in a reset state until after its previous unit shift register SR has been operated at least once. Each unit shift register SR cannot perform a normal operation without passing through a reset state. Therefore, prior to the normal operation, it is necessary to perform a dummy operation for transmitting a dummy input signal from the first stage to the last stage (or from the last stage to the first stage) of the unit shift register SR. Alternatively, a reset transistor is separately provided between the node N2 of each unit shift register SR and the second power supply terminal S2 (high potential side power supply), and a reset operation for forcibly charging the node N2 before the normal operation is performed. You may do it. In this case, however, a reset signal line is required separately.

  The bidirectional shift register according to the present invention will be described below. FIG. 7 is a circuit diagram showing a configuration of the bidirectional unit shift register SR according to the first embodiment. As shown in the figure, the output stage of the unit shift register SR also includes a transistor Q1 connected between the output terminal OUT and the clock terminal CK, and a transistor Q2 connected between the output terminal OUT and the first power supply terminal S1. It is comprised by. That is, the transistor Q1 is a first transistor that supplies a clock signal input to the clock terminal CK to the output terminal OUT, and the transistor Q2 is a second transistor that discharges the output terminal OUT. Again, a node (first node) to which the gate (control electrode) of the transistor Q1 is connected is defined as a node N1, and a node (second node) to which the gate of the transistor Q2 is connected is defined as a node N2.

  A transistor Q3 having a gate connected to the first input terminal IN1 is connected between the node N1 and the first voltage signal terminal T1, and a gate is connected between the node N1 and the second voltage signal terminal T2. The transistor Q4 connected to the second input terminal IN2 is connected. That is, the transistor Q3 is a third transistor that supplies the first voltage signal Vn to the node N1 based on a signal (first input signal) input to the first input terminal IN1. The transistor Q4 is a fourth transistor that supplies the second voltage signal Vr to the node N1 based on a signal (second input signal) input to the second input terminal IN2.

  A diode-connected transistor Q6 is connected between the node N2 and the second power supply terminal S2, and a transistor Q7 whose gate is connected to the node N1 is connected between the node N2 and the first power supply terminal S1. . The transistor Q7 has a driving capability (capability of flowing current) sufficiently larger than that of the transistor Q6. The transistors Q6 and Q7 constitute a ratio type inverter having the node N1 as an input end and the node N2 as an output end. ing.

  The above configuration is the same as the circuit of FIG. 3, but the bidirectional unit shift register SR according to the present embodiment is further connected between the node N1 and the second voltage signal terminal T2 and connected to the node N1. A transistor Q5 having a gate is provided.

  The operation of the bidirectional unit shift register SR in FIG. 7 will be described. The operation is substantially the same as that of FIG. 3, but will be described with reference to the timing chart of FIG. 8 in order to specifically show the effect of the present invention.

Again, the operation of the k-th stage unit shift register SR _k will be described representatively. Also for simplicity, a clock terminal CK of the unit shift register SR _k is assumed that the clock signal CLK is inputted. Further, the output signal of the unit shift register SR _k is G _k , the output signal of the previous unit (k−1 stage) unit shift register SR _k−1 is G _k−1 , and the next stage (k + 1 stage) unit. An output signal of the shift register SR _{k + 1} is defined as G _{k + 1} . Further, it is assumed that the H level potentials of the clock signals CLK, / CLK, the first voltage signal Vn, and the second voltage signal Vr are equal to the high potential side power supply potential VDD, and the threshold voltages of the transistors are all equal. The value is Vth.

  A case where the gate line driving circuit 30 performs a forward shift operation will be described. That is, the first voltage signal Vn generated by the voltage signal generator 32 is at the H level (VDD), and the second voltage signal Vr is at the L level (VSS).

First, as an initial state, assuming a reset state in which the node N1 is at L level (VSS) and the node N2 is at H level (VDD-Vth), the clock terminal CK (clock signal CLK) and the first input terminal IN1 (previous stage output signal) G _k-1 ) and the second input terminal IN2 (next stage output signal G _{k + 1} ) are both at L level. In the reset state, since the transistor Q1 is off and the transistor Q2 is on, the output terminal OUT (output signal G _k ) is kept at the L level regardless of the level of the clock terminal CK (clock signal CLK).

From this state, the clock signal CLK at time t ₀ becomes L level, then the previous stage of the unit shift register with at time t ₁ clock signal / CLK becomes H level SR _k-1 of the output signal G _k-1 ( when the first control pulse STn for the case of the first stage as a start pulse) becomes H level, it is input to the first input terminal IN1 of the unit shift register SR _k, the transistor Q3 is turned on. While the immediately preceding time t ₁ the node N2 is also turned on so H level, the transistor Q5, the transistor Q3 is driven capability than the transistor Q5 is set sufficiently large, the ON resistance of the transistor Q3 is in the on-resistance of the transistor Q5 Since the level is sufficiently low, the level of the node N1 rises.

Thereby, the transistor Q7 starts to conduct and the level of the node N2 falls. As a result, the resistance of the transistor Q5 increases, and the level of the node N1 rises rapidly to turn on the transistor Q7 sufficiently. As a result, the node N2 becomes L level (VSS), the transistor Q5 is turned off, and the node N1 becomes H level (VDD-Vth). That is, the unit shift register SR _k is set.

Thereafter, at time t ₂ , the clock signal / CLK becomes L level, and at this time, the output signal G _{k-1 in the} previous stage returns to L level. Then, the transistor Q3 is turned off, but the node N1 becomes the H level of the floating state, so that this set state is maintained.

Since the set state transistor Q1 is on, transistor Q2 is off, the clock signal CLK in the subsequent time t ₃ is becomes H level, the level of the output terminal OUT to follow to increase it. At this time, the level of the node N1 in the floating state is boosted by a specific voltage due to the coupling through the gate-channel capacitance of the transistor Q1. Whereby the driving capability of the transistor Q1 is increased, the level of the output signal G _k changes following the level of the clock terminal CK. Therefore, the output signal G _k becomes H level (VDD) only during the period when the clock signal CLK is H level, and the gate line GL _k is activated to be in a selected state.

When the clock signal CLK returns to L level at time t ₄ , the output signal G _k also changes to L level following this, and the gate line GL _k is discharged and returns to the non-selected state.

Since the output signal G _k is input to the first input terminal IN1 of the next stage, the output signal G _{k + 1} of the next stage becomes H level at time t ₅ when the clock signal / CLK becomes H level next. Sonaruto, the node N1 becomes L level, the transistor Q4 of the unit shift register SR _k is turned on, the node N2 and the transistor Q7 is turned off in response to the H level. That is, the transistor Q1 is turned off and the transistor Q2 is turned on. At this time, in the unit shift register SR _{k according} to the present embodiment, the transistor Q5 is turned on.

When the output signal G _{k + 1} at the next stage returns to the L level at time t ₆ , the transistor Q4 is turned off. However, since the node N2 is still at the H level, the transistor Q5 is kept on and the node N1 has a low impedance At L level. That state continues until the next signal to the first input terminal IN1 is input, the unit shift register SR _k is kept in the reset state.

  As described above, in the conventional circuit shown in FIG. 3, since the node N1 becomes the L level in the floating state after the transistor Q4 is turned off, if a leak current is generated in the transistor Q3, the accompanying charge is transferred to the node N1. And the potential of the node N1 gradually rises. Further, due to the coupling through the overlap capacitance between the drain and gate of the transistor Q1, the potential of the node N1 rises while the clock signal CLK is at the H level. Therefore, in the conventional circuit, the gate-source voltage of the transistor Q1 exceeds the threshold voltage due to the potential increase of the node N1 due to this leakage current and the potential increase of the node N1 when the clock signal CLK becomes H level. There is concern. Then, a malfunction problem (the first problem described above) occurs in which the transistor Q1 that should be turned off is turned on and the gate line is activated unnecessarily.

  On the other hand, in the unit shift register SR of FIG. 7, the transistor Q5 is turned on during the reset state in which the node N1 is at the L level, and the node N1 is maintained at the VDD level with a low impedance. . Therefore, the pixel switch element (active transistor) provided in each pixel is prevented from being turned on unnecessarily, and the occurrence of display defects in the display device is suppressed.

On the other hand, when the gate line driving circuit 30 performs the backward shift operation, the voltage signal generator 32 sets the first voltage signal Vn to L level (VSS) and the second voltage signal Vr to H level (VDD). To. The second control pulse STr is input to the second input terminal IN2 of the unit shift register SR _n of the last stage as a start pulse, a first control pulse STn the first as an end pulse of the unit shift register SR ₁ of the first stage 1 input to the input terminal IN1. Thereby, in each unit shift register SR, the operations of the transistor Q3 and the transistor Q4 are interchanged with each other as compared with the case of the forward shift, and the backward shift operation is enabled.

  Even if the operations of the transistor Q3 and the transistor Q4 are interchanged, the basic operation of the unit shift register SR is the same as in the forward shift, and the transistor Q5 also functions in the same way as in the forward shift. Therefore, even when the unit shift register SR of FIG. 7 performs the backward shift operation, the same effect as that of the forward shift described above can be obtained.

  In the above description, the example in which the gate line driving circuit 30 is configured as shown in FIG. 2 by the bidirectional unit shift register SR and is driven by the two-phase clock signal has been described. It is not limited to that. For example, the present invention can be applied to the case where the gate line driving circuit 30 is configured as shown in FIG. 6 and driven by a three-phase clock signal.

<Embodiment 2>
FIG. 9 is a circuit diagram of the bidirectional unit shift register SR according to the second embodiment. As shown in the figure, the unit shift register SR according to the present embodiment has a configuration in which a transistor Q12 and a transistor Q13 having a relatively large driving capability are further provided with respect to the conventional circuit of FIG.

  The transistor Q12 is connected between the node N2 and the first voltage signal terminal T1, and its gate is connected to the second input terminal IN2. That is, the transistor Q12 functions to supply the first voltage signal Vn to the node N2 (second node) based on the signal (second input signal) input to the second input terminal IN2. The transistor Q13 is connected between the node N2 and the second voltage signal terminal T2, and its gate is connected to the first input terminal IN1. That is, the transistor Q13 functions to supply the second voltage signal Vr to the node N2 based on a signal (first input signal) input to the first input terminal IN1.

The operation of the unit shift register SR of FIG. 9 is basically the same as that of the conventional circuit of FIG. 3, with the following differences. Here again, the k-th unit shift register SR _k will be described as a representative.

First, a forward shift operation is assumed. At this time, the first voltage signal Vn is at the H level and the second voltage signal Vr is at the L level. In the conventional circuit of FIG. 3, when the output signal G _k-1 of the previous stage (first control pulse STn as a start pulse in the first stage) is input to the first input terminal IN1, the transistor Q3 is turned on. Then, the node N1 becomes H level, and the transistor Q7 is turned on accordingly, so that the node N2 becomes L level. In the unit shift register SR _k of FIG. 9, together with the operation, the node N2 since the transistor Q13 is turned on large driving ability becomes L level (VSS) to a high speed.

In the conventional circuit of FIG. 3, when the next stage output signal G _{k + 1} (second control pulse STr as an end pulse in the last stage) is input to the second input terminal IN2, the transistor Q4 is turned on. Then, the node N1 becomes L level, and the transistor Q7 is turned off accordingly, so that the node N2 becomes H level. On the other hand, in the unit shift register SR _k of FIG. 9, the transistor Q12 having a large driving capability is turned on along with the operation thereof, so that the node N2 is at the H level (VDD−Vth) at high speed.

Next, a reverse shift operation is assumed. At this time, the first voltage signal Vn is at the L level and the second voltage signal Vr is at the H level. Therefore, in the unit shift register SR _k of FIG. 9, when the next stage output signal G _{k + 1} is input to the second input terminal IN2, the transistor Q12 is turned on and the node N2 is rapidly brought to the L level (VSS). Become. Further, when the output signal G _{k−1 of the} previous stage is input to the first input terminal IN1, the transistor Q13 is turned on, so that the node N2 becomes H level (VDD−Vth) at high speed.

  As described above, according to the present embodiment, the rise and fall of the level of node N2 are speeded up by the action of transistors Q12 and Q13. In particular, when the unit shift register SR shifts from the selection period to the non-selection period, the level of the node N2 quickly becomes H level, so that the transistor Q2 is turned on at high speed and sufficiently, so that the output terminal OUT is connected via the gate line. The influence of noise applied to the noise can be suppressed, and the problem of malfunction caused by the noise (the fourth problem described above) can be solved.

Also in the conventional circuit of FIG. 3, if the size of the transistor Q6 is increased to increase its driving capability, the node N2 can be quickly brought to the H level, and the problem of malfunction due to noise can be suppressed. However, since the transistors Q6 and Q7 constitute a ratio type inverter, when the size of the transistor Q6 is large, the transistor Q7 is turned on and the node N2 is set to the L level (time t _{1 to} t in FIG. 8). (Corresponding to ₅ ), the through current flowing through the inverter increases and the power consumption increases.

  On the other hand, in the unit shift register SR of FIG. 9, the node N2 can be quickly set to the H level without increasing the size of the transistor Q6, and power consumption is not increased. The effect that the node N2 can be set to the H level at a high speed increases as the drive capability of the transistors Q12 and Q13 increases. However, the transistors Q12 and Q13 do not turn on at the same time and do not form a through current path. However, there is almost no increase in power consumption.

  Note that the driving capability of the transistor Q6 in this embodiment has such a driving capability that the node N2 can be maintained at the H level after the node N2 becomes the H level, that is, at least the leakage current generated in the node N2 is compensated. It only has to be. That is, there is an advantage that the driving capability of the transistor Q6 can be made smaller than before, and the through current generated in the inverter composed of the transistors Q6 and Q7 can be reduced.

<Embodiment 3>
FIG. 10 is a circuit diagram showing a configuration of the bidirectional unit shift register according to the third embodiment. As shown in the figure, the unit shift register SR according to the third embodiment is different from the unit shift register SR (FIG. 7) of the first embodiment in that the transistors Q12 and Q13 having relatively large driving capability shown in the second embodiment. Is further provided.

As described in the first embodiment, the circuit of FIG. 7 can operate when the output signal G _k−1 of the previous stage is input to the first input terminal IN1 in the case of forward shift operation (time t in FIG. 8). ₁ ) The node N1 operates to transition from the L level to the H level. However, since this operation is performed from the state in which the transistor Q5 is on, the level of the node N1 is unlikely to increase at this time. Accordingly, there is a concern that the rising speed of the level of the node N1 is slow, which hinders the speeding up of the operation and causes a problem.

On the other hand, in the unit shift register SR according to the present embodiment, when the output signal G _k-1 of the previous stage is input to the first input terminal IN1, the transistor Q13 having a large driving capability is turned on, so that the node N2 immediately It becomes L level and the transistor Q5 is turned off. As a result, the level of the node N1 is quickly raised, and the above problem does not occur. That is, according to the present embodiment, the unit shift register SR includes the transistor Q5, so that the same effect as in the first embodiment can be obtained, and even in that case, the rising speed of the level of the node N1 is slow. Can be suppressed.

In the case of reverse shift, when the output signal G _{k + 1} of the next stage is input to the second input terminal IN2, the transistor Q12 is turned on, the node N2 is immediately turned to L level, and the transistor Q5 is turned off. To do. Therefore, the same effect as in the case of the forward shift can be obtained.

<Embodiment 4>
FIG. 11 is a circuit diagram of the bidirectional unit shift register SR according to the fourth embodiment. As shown in the figure, the unit shift register SR has a configuration in which transistors Q3A, Q4A, Q8, and Q9 are further provided to the conventional circuit of FIG.

  As shown in FIG. 11, the transistor Q3 is connected to the first voltage signal terminal T1 via the transistor Q3A, and the transistor Q4 is connected to the second voltage signal terminal T2 via the transistor Q4A. The gate of the transistor Q3A is connected to the first input terminal IN1 like the gate of the transistor Q3, and the gate of the transistor Q4A has a gate connected to the gate of the transistor Q4. Here, a connection node (third node) between the transistor Q3 and the transistor Q3A is defined as a node N3, and a connection node (fourth node) between the transistor Q4 and the transistor Q4A is defined as a node N4.

  Between the output terminal OUT and the node N3, a transistor Q8 (unidirectional first switching element) diode-connected so that a direction from the output terminal OUT to the node N3 is a forward direction (a direction in which a current flows). Is connected. Between the output terminal OUT and the node N4, a diode-connected transistor Q9 (a unidirectional first switching element) is connected so that the direction from the output terminal OUT to the node N4 is a forward direction. The transistor Q8 flows a current from the output terminal OUT to the node N3 to charge the node N3 when the output terminal OUT becomes H level (when activated). Similarly, when the output terminal OUT becomes H level, the transistor Q9 flows current from the output terminal OUT to the node N4 to charge the node N4. That is, the transistors Q8 and Q9 function as a charging circuit that charges the nodes N3 and N4.

  Hereinafter, the operation of the bidirectional unit shift register SR of FIG. 11 will be described. FIG. 12 is a timing chart showing an operation at the time of forward shift of the unit shift register SR of FIG.

Here again, the operation of the k-th unit shift register SR _k when the gate line driving circuit 30 performs the forward shift operation will be described as a representative. That is, the first voltage signal Vn generated by the voltage signal generator 32 is at the H level (VDD), and the second voltage signal Vr is at the L level (VSS).

First, as an initial state, assuming a reset state in which the node N1 is at L level (VSS) and the node N2 is at H level (VDD-Vth), the clock terminal CK (clock signal CLK) and the first input terminal IN1 (previous stage output signal) G _k-1 ) and the second input terminal IN2 (next stage output signal G _{k + 1} ) are both at L level. In the reset state, since the transistor Q1 is off and the transistor Q2 is on, the output terminal OUT (output signal G _k ) is at the L level.

From this state, the clock signal CLK at time t ₀ becomes L level, then the previous stage of the unit shift register with at time t ₁ clock signal / CLK becomes H level SR _k-1 of the output signal G _k-1 ( In the case of the first stage, when the first control pulse STn) as the start pulse becomes H level, the transistors Q3 and Q3A are both turned on. Accordingly, the node N1 becomes H level (VDD−Vth), and accordingly, the transistor Q7 is turned on and the node N2 becomes L level (VSS). That is, the unit shift register SR _k is set. At this time, the node N3 is at the H level (VDD−Vth), but the transistor Q8 functions as a diode whose forward direction is from the output terminal OUT to the node N3. No current flows to OUT.

Thereafter, at time t ₂ , the clock signal / CLK becomes L level, and at this time, the output signal G _{k-1 in the} previous stage returns to L level. Then, the transistors Q3 and Q3A are turned off, but the node N1 becomes the H level in the floating state, so that this set state is maintained. Further, the node N3 also becomes the H level in the floating state.

Since the set state transistor Q1 is on, transistor Q2 is off, the clock signal CLK in the subsequent time t ₃ is becomes H level, the level of the output terminal OUT to follow to increase it. At this time, the level of the node N1 is boosted by a specific voltage. Whereby the driving capability of the transistor Q1 is increased, the level of the output signal G _k changes following the level of the clock terminal CK. Therefore, the output signal _Gk is at the H level (VDD) while the clock signal CLK is at the H level.

As described above, in the conventional circuit of FIG. 3, when the node N1 is boosted, a high voltage is applied between the drain and source of the transistor Q4, so that a leak current is generated in the transistor Q4 and the level of the node N1 is increased. Was concerned about the decline. Sonaruto, can not be sufficiently secured driving capability of the first transistor, the falling speed of the output signal G _k is a problem that slows down (second problem described above) occurs.

  On the other hand, in the unit shift register SR of FIG. 11, when the node N1 is boosted, that is, when the output terminal OUT becomes H level (VDD), the diode-connected transistor Q9 is turned on and the level of the node N4 becomes VDD−. Vth. At this time, the transistor Q4 has a gate potential of VSS and a source potential of VDD-Vth, and the gate is negatively biased with respect to the source. Therefore, the leak current between the drain and source of the transistor Q4 is sufficiently suppressed, and the level decrease of the node N1 is suppressed.

Accordingly, when the clock signal CLK becomes L level at the subsequent time t ₄ , the output signal G _k quickly changes to L level following that, and the gate line GL _k is discharged at high speed and becomes L level. Therefore, each pixel transistor is also quickly turned off, and the occurrence of a display defect due to the data in the pixel being rewritten to the next line data is suppressed.

Next, at time t ₅ when the clock signal / CLK becomes H level, the output signal G _{k + 1} of the next stage becomes H level. Sonaruto, the node N1 transistors Q4, Q4A of the unit shift register SR _k is turned on becomes L level, the node N2 and the transistor Q7 is turned off in response to the H level. That is, the transistor Q1 is turned off and the transistor Q2 is turned on. At this time, the node N4 is also at the L level.

When the next stage output signal G _{k + 1} returns to the L level at time t ₆ , the transistors Q4 and Q4A are turned off, so that the nodes N1 and N4 are in the floating L level. That state continues until the next signal to the first input terminal IN1 is input, the unit shift register SR _k is kept in the reset state.

  Next, a reverse shift operation is assumed. In this case, since the first voltage signal Vn is at the L level and the second voltage signal Vr is at the H level, in the conventional circuit of FIG. 3, when the node N1 is boosted, a high voltage is applied between the drain and source of the transistor Q3. Therefore, there is a concern about the leakage current.

On the other hand, when the unit shift register SR _k of FIG. 11 performs the reverse shift operation, when the node N1 is boosted, a current flows to the node N3 via the transistor Q8, and the level of the node N3 is VDD−. Vth. At this time, the transistor Q3 has a gate potential of VSS, a source potential of VDD-Vth, and the gate is negatively biased with respect to the source. Therefore, the leak current between the drain and source of the transistor Q3 is sufficiently suppressed, and the decrease in the level of the node N1 is suppressed. That is, the same effect as in the case of the forward shift can be obtained.

  11 shows a configuration in which the transistors Q3A, Q4A, Q8, and Q9 according to the present embodiment are provided in the conventional circuit of FIG. 3, but this embodiment is the same as in the first to third embodiments. The present invention is also applicable to bidirectional unit shift registers SR such as (FIGS. 7, 9, and 10).

<Embodiment 5>
A display device in which a shift register of a gate line driving circuit is composed of an amorphous silicon TFT (a-Si TFT) is easy to increase in area and has high productivity. For example, a notebook PC screen or a large screen display device Widely adopted in On the other hand, it has been found that the threshold voltage of the a-Si TFT is shifted when the gate electrode is continuously biased, which affects the driving capability.

  While the bidirectional unit shift register SR (FIG. 11) according to the fourth embodiment is performing the forward shift operation, as shown in FIG. 12, the node N3 continuously has a positive potential (VDD− Vth). This means that both the gate-source and the gate-drain of transistor Q3A are negatively biased, resulting in a large shift in the negative direction of the threshold voltage of transistor Q3A. As the threshold voltage shifts in the negative direction, the transistor becomes substantially normally on, and a current flows between the drain and source even when the gate-source voltage is 0V. If the transistor Q3 is normally turned on in this way, the following problem occurs when the unit shift register SR performs a reverse shift operation thereafter.

  That is, in the unit shift register SR of the fourth embodiment, when the first voltage signal Vn is shifted in the reverse direction in which the first voltage signal Vn is at the L level (VSS), the output terminal OUT becomes the H level (the node N1 is boosted). Current) for charging node N3 flows through transistor Q8. However, since the transistor Q3A is normally on, the electric charge due to the current flows out to the first input terminal IN1 through the transistor Q3A, and the power consumption increases. In addition, since the node N3 cannot be charged sufficiently, the effect of the fourth embodiment of suppressing the leakage current of the transistor Q3 cannot be obtained. Therefore, the fifth embodiment proposes a bidirectional unit shift register SR that can solve this problem.

  FIG. 13 is a circuit diagram showing a configuration of the bidirectional unit shift register according to the fifth embodiment. As shown in the figure, with respect to the unit shift register SR (FIG. 11) of the fourth embodiment, a transistor Q10 whose gate is connected to the second input terminal IN2 is connected between the node N3 and the first power supply terminal S1 (VSS). In addition, a transistor Q11 having a gate connected to the first input terminal IN1 is provided between the node N4 and the first power supply terminal S1. That is, the transistor Q11 is a transistor that discharges the node N4 (fourth node) based on a signal (first input signal) input to the first input terminal IN1, and the transistor Q10 is connected to the second input terminal IN2. The transistor discharges the node N3 (third node) based on the input signal (second input signal).

  FIG. 14 is a timing chart showing an operation at the time of forward shift of the bidirectional unit shift register according to the fifth embodiment. Since the operation is substantially the same as that shown in FIG. 12, detailed description thereof is omitted, and only the characteristic part of the present embodiment will be described.

In the present embodiment, the transistor Q10 is turned on when the output signal G _{k + 1} of the next stage becomes H level at time t ₅ , so that the node N3 is discharged to L level (VSS) at that timing. When the next stage output signal G _{k + 1} returns to the L level at the subsequent time t ₆ , the transistor Q10 is turned off, but the node N3 enters the floating state, and then the previous stage output signal G _k-1 goes to the H level. Until this time, the node N3 is maintained at the L level. In other words, it will be charged only about one horizontal period of the node N3 at time t ₃ ~t ₅ as shown in FIG. 14, between transistors Q3A its period only the gate-source and gate-drain is biased negatively It will be. Therefore, the threshold voltage of the transistor Q3A hardly shifts and the above problem is prevented.

In the reverse shift operation, when the output signal G _{k-1 in the} previous stage becomes H level, the transistor Q11 is turned on and the node N4 is discharged to L level (VSS). As a result, the gate-source and the gate-drain of the transistor Q4A are prevented from being negatively biased continuously, and the threshold voltage of the transistor Q4 hardly shifts. That is, the same effect as in the case of the forward shift can be obtained.

<Embodiment 6>
FIG. 15 is a circuit diagram of the bidirectional unit shift register SR according to the sixth embodiment. In the fifth embodiment, the drains of the transistors Q8 and Q9 constituting the charging circuit for charging the nodes N3 and N4 are connected to the output terminal OUT, and the transistors Q8 and Q9 function as diodes. In contrast, in the present embodiment, the drains of the transistors Q8 and Q9 are connected to a third power supply terminal S3 to which a predetermined high potential side power supply potential VDD1 is supplied.

  The operation of the unit shift register SR of FIG. 15 is basically the same as that of the fifth embodiment, and the same effect can be obtained. However, the fifth embodiment is different from the fifth embodiment in that the charge supply source for charging the node N3 and the node N4 is not an output signal appearing at the output terminal OUT but a power supply for supplying the high potential side power supply potential VDD1.

  According to the present embodiment, the load capacity of the output terminal OUT is reduced as compared with the unit shift register SR of the fifth embodiment, so that the charging speed of the gate line is increased. Therefore, the operation can be speeded up.

  The high potential side power supply potential VDD1 supplied to the third power supply terminal S3 may be the same potential as the high potential side power supply potential VDD supplied to the second power supply terminal S2. In that case, the second power supply terminal S2 and the third power supply terminal S3 may be connected to each other and configured as one power supply terminal. In addition, although described here as a modification of the fifth embodiment, the present embodiment can also be applied to the unit shift register SR (FIG. 11) of the fourth embodiment.

<Embodiment 7>
FIG. 16 is a circuit diagram showing a configuration of the bidirectional unit shift register SR according to the seventh embodiment. In the fifth embodiment, the sources of the transistors Q10 and Q11 are connected to the first power supply terminal S1 to which the low potential side power supply potential VSS is supplied, but the source of the transistor Q10 is connected to the second voltage signal Vr as shown in FIG. May be connected to the second voltage signal terminal T2 to which the first voltage signal Vn is supplied, and the source of the transistor Q11 may be connected to the first voltage signal terminal T1 to which the first voltage signal Vn is supplied.

  The operation of the unit shift register SR in FIG. 16 is basically the same as that in the fifth embodiment. That is, for example, in the forward shift operation, since the second voltage signal Vr is at the L level, the transistor Q10 can discharge the node N3 as in the case of the fifth embodiment. In the reverse shift operation, since the first voltage signal Vn is at the L level, the transistor Q11 can discharge the node N4 as in the case of the fifth embodiment.

  Therefore, the same effects as in the fifth embodiment can be obtained in the present embodiment. In other words, the configuration of FIG. 13 and the configuration of FIG. 16 can provide the effects of the fifth embodiment, so that the degree of freedom in circuit layout is increased and the area occupied by the circuit is reduced. Can contribute.

  This embodiment can also be applied to the unit shift register SR (FIG. 15) of the sixth embodiment.

<Eighth embodiment>
The techniques of the first to seventh embodiments can be combined with each other, and an effect according to the combination can be obtained. In this embodiment, an example of the combination is shown.

For example, FIG. 17 shows a circuit combining the second embodiment (FIG. 9) and the fourth embodiment (FIG. 11). FIG. 18 is a circuit in which the first embodiment (FIG. 7) and the fourth embodiment (FIG. 11) are combined. As described above, the fourth embodiment prevents a decrease in the level of the node N1 due to the leakage current. Therefore, when the fourth embodiment and the first embodiment are combined, the leakage current of the transistor Q5 is also suppressed. Is effective. Therefore, as shown in FIG. 18, the source of the transistor Q5 is connected to the first power supply terminal S1 (VSS) via the transistor Q5A, and the connection node (node N5) between the transistor Q5 and the transistor Q5A is connected to the output signal G. Biased at _k . Thereby, the gate of the transistor Q5 is negatively biased with respect to the source when the node N1 is boosted, so that the leakage current of the transistor Q5 is reduced.

  Although FIG. 18 shows a configuration in which the output terminal OUT is connected to the node N5, the biasing method of the node N5 is not limited to this. For example, by applying the technique of the sixth embodiment, as shown in FIG. 19, a transistor Q5B connected between the node N5 and a third power supply terminal S3 to which a predetermined high potential side power supply potential VDD1 is supplied is provided, and its gate is connected. It may be connected to the output terminal OUT. According to this configuration, when the node N1 is boosted, the node N5 is biased to the potential VDD1, and the same effect as in FIG. 18 can be obtained. Furthermore, since the load capacity of the output terminal OUT is reduced as compared with the case of FIG. 18, there is also an advantage that the charging speed of the gate line is improved.

  20 is a circuit combining the first embodiment (FIG. 7) and the fifth embodiment (FIG. 13), and FIG. 21 is the same as the first embodiment (FIG. 7) and the seventh embodiment (FIG. 16). It is a circuit that combines.

  Furthermore, the number of embodiments to be combined is not limited to two, and three or more embodiments may be combined. For example, FIG. 22 shows a circuit combined with Embodiment 1 (FIG. 7), Embodiment 2 (FIG. 9) and Embodiment 4 (FIG. 11), and FIG. 23 shows Embodiment 1 (FIG. 7). This circuit is a combination of the second embodiment (FIG. 9) and the seventh embodiment (FIG. 16).

  Although only representative combinations are shown here, combinations other than those described above are possible.

<Embodiment 9>
The bidirectional unit shift register SR according to the present invention described above can constitute the gate line driving circuit 30 by being cascaded as shown in FIGS. However, in the gate line driving circuit 30 shown in FIGS. 2 and 6, for example, when a forward shift is performed, the first input terminal IN1 of the foremost stage (unit shift register SR ₁ ) is started as shown in FIG. It is necessary to input the first control pulse STn as a pulse, and then input the second control pulse STr as an end pulse to the second input terminal IN2 of the last stage (unit shift register SR _n ). Further, when performing reverse shift, as shown in FIG. 5, the second control pulse STr as the start pulse is input to the second input terminal IN2 at the last stage, and then the end of the first input terminal IN1 at the foremost stage is input. It is necessary to input the first control pulse STn as a pulse.

  That is, in the operation of the gate line driving circuit 30 in FIGS. 2 and 6, two kinds of control pulses, that is, a start pulse and an end pulse are necessary. For this reason, a drive control device that controls the operation of the gate line drive circuit 30 employs not only a start pulse output circuit but also an end pulse output circuit, which increases the cost (the above-mentioned first problem). 3 problems). Therefore, the ninth embodiment proposes a bidirectional shift register that can operate only with a start pulse.

24 to 26 are diagrams showing the configuration of the gate line driving circuit 30 according to the ninth embodiment. As shown in the block diagram of FIG. 24, the gate line driving circuit 30 according to the present embodiment is also configured by a bidirectional shift register having a plurality of stages, and the gate line GL1 is driven in the plurality of stages. A first dummy shift register SRD ₁ that is a first dummy stage is provided further before the unit shift register SR _{1 at} the foremost stage, and is further next to the unit shift register SR _{n at} the last stage that drives the gate line GL _n. The stage is provided with a second dummy shift register SRD ₂ as a second dummy stage. That is, the gate line driving circuit 30 is composed of a plurality of stages including a first first dummy stage and a last second dummy stage. Each stage of the gate line driving circuit 30 may be any of the bidirectional unit shift registers SR of the above embodiments, and the conventional one shown in FIG. 3 may be applied.

As shown in FIG. 24, is input to the (first first except dummy shift register SRD ₁ is a dummy stage) the first input terminal IN1 of the unit shift register SR ₁ of the leading stage first control pulse STn, than Also, the output signal of the previous stage is input to the first input terminal IN1 of the subsequent stage (unit shift register SR2 to second dummy shift register SRD ₂ ). And said second control pulse STr is input to the first dummy shift register first input terminal IN1 of the SRD _1.

Further, (second dummy stage is a second except for dummy shift register SRD ₂₎ to the second input terminal IN2 of the final stage is input a second control pulse STr, it from even the previous stage (unit shift register SR _{n- 1} to the first dummy shift register SRD ₁ ), the output signal of the next stage is input to the second input terminal IN2. The first control pulse STn above is input to the second dummy shift register second input terminal IN2 of the SRD _2.

In the present embodiment, the unit shift register SR _{1 at} the front stage, the unit shift register SR _n at the last stage, the first dummy shift register SRD ₁ and the second dummy shift register SRD ₂ have predetermined reset terminals RST1, RST2, Each has RST3 and SRT4. As shown in FIG. 24, to the reset terminal RST1 of the unit shift register SR _1, the output signal D ₁ of the first dummy shift register SRD ₁ is input to the reset terminal RST2 of the unit shift register SR _n, second dummy shift is input the output signal D ₂ of register SRD ₂ is, in the first dummy shift register SRD ₁ of the reset terminal RST3 is input first control pulse STn, the second dummy shift register SRD ₂ of the reset terminal RST4 second control A pulse STr is input. The unit shift register SR ₁ , the unit shift register SR _n , the first dummy shift register SRD ₁ and the second dummy shift register SRD ₂ are reset when signals are input to the respective reset terminals RST 1, RST 2, RST 3 and SRT 4. It is configured to be in a state (a state where the node N1 is at the L level and the node N2 is at the H level) (details will be described later).

In the following description, it is assumed that each stage of each bidirectional shift register constituting the gate line driving circuit 30 has the configuration of the bidirectional unit shift register SR (FIG. 7) of the first embodiment. . As described above, the unit shift register SR ₁ at the foremost stage, the unit shift register SR _n at the last stage, the first dummy shift register SRD ₁ and the second dummy shift register SRD ₂ have different configurations from the other stages. Each of them also includes the configuration of the bidirectional unit shift register SR of the first embodiment.

FIG. 25 is a specific circuit diagram of the first dummy shift register SRD ₁ and the unit shift register SR ₁ in the gate line driving circuit 30 of the present embodiment, and FIG. 26 shows the unit shift register SR _n and the second dummy shift register SR ₁ . FIG. 4 is a specific circuit diagram of a shift register SRD ₂ ;

First, focusing on the unit shift register SR ₁ of FIG. 25, the unit shift register SR _1, except that in parallel with the transistor Q3 transistor Q3D is connected, has the same configuration as FIG. The gate of the transistor Q3D is connected to the reset terminal RST1.

Similarly, the first dummy shift register SRD ₁ has the same configuration as that of FIG. 7 except that the transistor Q4D is connected in parallel to the transistor Q4. The gate of the transistor Q4D is connected to the reset terminal RST3.

Also Focusing on the unit shift register SR _n of FIG. 26, the unit shift register SR _n, except that in parallel with the transistor Q4 transistor Q4D is connected, has the same configuration as FIG. 7 (i.e. The circuit configuration is the same as that of the first dummy shift register SRD ₁ ). The gate of the transistor Q4D is connected to the reset terminal RST2.

Similarly, the second dummy shift register SRD ₂ has the same configuration as that of FIG. 7 except that the transistor Q3D is connected in parallel to the transistor Q3 (ie, the same circuit as the unit shift register SR ₁ ). Configuration). The gate of the transistor Q3D is connected to the reset terminal RST4.

An operation of the gate line driving circuit 30 according to the present embodiment will be described. First, the operation when performing forward shift will be described. In the case of forward shift, the first voltage signal Vn supplied from the voltage signal generator 32 is set to the H level, and the second voltage signal Vr is set to the L level. That is, in this case, the transistor Q4D transistors Q4D and the unit shift register SR _n of the first dummy shift register SRD ₁ operates to discharge the respective node N1. For the sake of simplicity, it is assumed that the unit shift registers SR _{1 to} SR _n are already in the reset state (the node N1 is at the L level and the node N2 is at the H level).

FIG. 27 is a timing chart showing an operation at the time of forward shift of the gate line driving circuit 30 according to the present embodiment. As shown in FIG. 27, when the forward shift, the first control pulse STn as the start pulse at a predetermined timing, is input to the first input terminal IN1 of the unit at the first stage shift register SR _1. As a result, unit shift register SR ₁ enters a set state (node N1 is at H level and node N2 is at L level). On the other hand, the second control pulse STr is not activated and is maintained at the L level.

First control pulse STn (start pulse) is also input to the second input terminal IN2 of the first dummy shift register SRD ₁ of the reset terminal RST3 and second dummy shift register SRD _2. Therefore, in the first dummy shift register SRD ₁ , the transistor Q 4 D is turned on, the node N 1 becomes L level, and the first dummy shift register SRD ₁ is reset. Accordingly, the output signal D ₁ of the first dummy shift register SRD ₁ becomes L level, and the transistor Q3D of the unit shift register SR ₁ is turned off.

In the second dummy shift register SRD ₂ , the transistor Q 4 is turned on, the node N 1 becomes L level, and the second dummy shift register SRD ₂ is also reset. Therefore, the output signal D ₂ of the second dummy shift register SRD ₂ becomes L level, the transistor Q3D of the unit shift register SR ₁ is turned off.

Thereafter, by the forward shift operation similar to that of the first embodiment, the unit shift registers SR _{1 to} SR _n and the second dummy shift register SRD ₂ are synchronized with the clock signals CLK and / CLK as shown in FIG. , And their output signals G ₁ , G ₂ , G ₃ ,..., G _n , D ₂ sequentially become H level.

As can be seen from FIG. 27, the output signal D ₂ of the second dummy shift register SRD ₂ becomes H level immediately after the last unit shift register SR _n outputs the output signal G _n . The output signal D ₂ is input to the reset terminal RST2 of the unit shift register SR _n, turn on the transistor Q3D to reset the unit shift register SR _n. In other words, the output signal D ₂ functions as an end pulse for resetting the last unit shift register SR _n . Since the second dummy shift register SRD ₂ is reset by the first control pulse STn as the start pulse of the next frame, it can operate in the same manner in the next frame.

  Thus, the forward shift operation of the gate line driving circuit 30 according to the present embodiment requires only the start pulse (first control pulse STn), and does not require an end pulse.

Next, the operation when the backward shift is performed will be described. In the case of reverse shift, the first voltage signal Vn is L level and the second voltage signal Vr is H level. That is, this case, the transistor Q3D and second transistor Q3D dummy shift register SRD ₂ of the unit shift register SR ₁ is operable to discharge the respective node N1. Here again, it is assumed that the unit shift registers SR _{1 to} SR _n are already in the reset state (the node N1 is at the L level and the node N2 is at the H level).

FIG. 28 is a timing chart showing an operation at the time of reverse shift of the gate line driving circuit 30 according to the present embodiment. As shown in FIG. 28, when the reverse shift, the second control pulse STr as the start pulse at a predetermined timing, is inputted to the second input terminal IN2 of the unit shift register SR _n of the last stage. As a result, the unit shift register SR _n is set (the node N1 is at the H level and the node N2 is at the L level). On the other hand, the first control pulse STn is not activated and is maintained at the L level.

Second control pulse STr (the start pulse) is input to the first dummy shift register SRD ₁ of the first input terminal IN1 and the second dummy shift register SRD ₂ of the reset terminal RST4. In the first dummy shift register SRD ₁ Therefore, the node N1 transistor Q3 is turned ON becomes L level, the first dummy shift register SRD ₁ becomes the reset state. Accordingly, the output signal D ₁ of the first dummy shift register SRD ₁ becomes L level, and the transistor Q3D of the unit shift register SR ₁ is turned off.

In the second dummy shift register SRD _2, node N1 transistor Q3D is turned ON becomes L level, the second dummy shift register SRD ₂ also becomes the reset state. Therefore, the output signal D ₂ of the second dummy shift register SRD ₂ becomes L level, the transistor Q4D unit shift register SR4 is turned off.

Thereafter, by the reverse shift operation similar to that of the first embodiment, the unit shift registers SR _{n to} SR ₁ and the first dummy shift register SRD ₁ are synchronized with the clock signals CLK and / CLK as shown in FIG. sequentially transmitted, their output signals _{G n, G n-1,} G n-2, ···, G 1, D 1 becomes H level in order to.

As can be seen from FIG. 28, the output signal D ₁ of the first dummy shift register SRD ₁ becomes H level immediately after the unit shift register SR _{1 in the} foremost stage outputs the output signal G1. The output signal D ₁ is inputted to the reset terminal RST1 of the unit shift register SR _1, to the unit shift register SR ₁ and the transistor Q3 is turned on in the reset state. That is, the output signal D ₁ functions as an end pulse that resets the unit shift register SR ₁ in the forefront stage. The first dummy shift register SRD ₁ is reset in response to the second control pulse STr as the start pulse of the next frame, and can operate in the same manner in the next frame.

  Thus, only the start pulse (second control pulse STr) is required for the backward shift operation of the gate line driving circuit 30 according to the present embodiment, and no end pulse is required.

  As described above, according to the present embodiment, in the bidirectional shift register, the forward shift operation and the reverse shift operation can be performed using only the start pulse without using the end pulse. In other words, the drive control device that controls the operation of the gate line drive circuit 30 only needs to have a start pulse output circuit, so that the problem of cost increase (the third problem described above) can be solved. it can.

Further, as described above, the transistor Q3D or the transistor Q4D provided in the unit shift registers SR ₁ , SR _n , the first and second dummy shift registers SRD ₁ , SRD ₂ of the bidirectional shift register of the present embodiment are: It functions to discharge each node N1. When discharging the node N1 of each unit shift register SR, it is possible to ensure a large driving capability (capability of flowing current) and to not require high speed as compared to charging the node N1. Therefore, the size of the transistors Q3D and Q4D may be smaller than that of the transistors Q3 and Q4, and may be, for example, about 1/10. Further, when the transistors Q3D and Q4D are large in size, the parasitic capacitance of the node N1 increases, so that the boosting action of the node N1 by the clock signal CLK or / CLK becomes small. For this reason, the driving capability of the transistor Q1 is reduced, so it is desirable that the transistor Q1 be somewhat small.

  In the above description, each stage of the bi-directional shift register has the configuration of the unit shift register SR of the first embodiment. However, as described above, the bi-directional unit shift applied to the present embodiment. The register SR may be any of the bidirectional unit shift registers SR of the above embodiments, and the conventional one shown in FIG. 3 can be applied.

Even in such a case, the unit shift register SR ₁ of the leading stage, provided the transistor Q3D connected in parallel to the transistors Q3, in the unit shift register SR _n of the last stage, provided the transistor Q4D connected in parallel to the transistors Q4, the The first dummy shift register SRD ₁ may be provided with a transistor Q4D connected in parallel to the transistor Q4, and the second dummy shift register SRD ₂ may be provided with a transistor Q3D connected in parallel with the transistor Q3.

  However, as in the fourth embodiment (FIG. 11) and the fifth embodiment (FIG. 13), the transistor Q3 is connected to the first voltage signal terminal T1 via the transistor Q3A, and the transistor Q4 is connected via the transistor Q4A. When connecting to the second voltage signal terminal T2, it is necessary to add a transistor in parallel to the transistors Q3A and Q4A.

29 and 30 show an example in which the unit shift register SR of the fourth embodiment (FIG. 11) is applied to each stage of the gate line driving circuit 30 of the present embodiment. As shown in FIG. 29, in the unit shift register SR _{1 at} the front stage, transistors Q3D and Q3AD are provided in parallel with the transistors Q3 and Q3A, respectively, and both gates thereof are connected to the reset terminal RST1. In the first dummy shift register SRD _1, the transistors Q4, Q4A each transistor in parallel to Q 4 D, the provided Q4AD, together is connected to the reset terminal RST3 gates of both.

As shown in FIG. 30, in the last unit shift register SR _n , transistors Q4D and Q4AD are provided in parallel with the transistors Q4 and Q4D, and both gates thereof are connected to the reset terminal RST2. In the second dummy shift register SRD _2, the transistors Q3, Q3A the transistors in parallel in Q3D, the provided Q3A, together is connected to the reset terminal RST4 gates of both. With this configuration, forward shift and reverse shift operations can be performed using only the start pulse as described above.

  Also in this case, since the transistors Q3D, Q3AD, Q4D, and Q4AD function to discharge the level of the node N1, respectively, their sizes may be smaller than those of the transistors Q3, Q3A, Q4, and Q4A. It may be about 10. Further, when the size of the transistors Q3D, Q3AD, Q4D, and Q4AD is large, the parasitic capacitance of the node N1 increases, so that the boosting action of the node N1 by the clock signal CLK or / CLK is reduced, and the driving capability of the transistor Q1 is reduced. I will invite you. For this reason, it is desirable that it be somewhat small.

30 gate line driving circuit, SR unit shift register, SRD ₁ first dummy shift register, SRD ₂ second dummy shift register, Q1 to Q13, Q3A, Q4A, Q3D, Q4D, Q3AD, Q4AD transistor, CK clock terminal, IN1 first 1 input terminal, IN2 second input terminal, OUT output terminal, s1 to s3 power supply terminal, T1 first voltage signal terminal, T2 second voltage signal terminal.

Claims (4)

A shift register circuit comprising a plurality of stages including a first first dummy stage and a last second dummy stage,
Each stage is
First and second input terminals, output terminals and clock terminals;
A first transistor for supplying a clock signal input to the clock terminal to the output terminal;
A second transistor for discharging the output terminal;
First and second voltage signal terminals to which first and second voltage signals complementary to each other are respectively input;
A third transistor for supplying the first voltage signal to a first node to which a control electrode of the first transistor is connected based on a first input signal input to the first input terminal;
A fourth transistor for supplying the second voltage signal to the first node based on a second input signal input to the second input terminal;
The forefront stage excluding the first dummy stage is:
A control transistor connected to the output terminal of the first dummy stage, and further comprising a fifth transistor for discharging the first node of the foremost stage;
The last stage excluding the second dummy stage is
A shift register circuit, further comprising: a sixth transistor having a control electrode connected to the output terminal of the second dummy stage and discharging the first node of the last stage. The shift register circuit according to claim 1,
The first dummy stage has the same circuit configuration as the last stage,
The shift register circuit, wherein the second dummy stage has the same circuit configuration as the foremost stage. The shift register circuit according to claim 1,
A predetermined first control pulse is input to the first input terminal in the foremost stage, and an output signal of the previous stage is input to the first input terminal in the subsequent stage.
A shift characterized in that a predetermined second control pulse is input to the second input terminal of the last stage, and an output signal of the next stage is input to the second input terminal of the preceding stage. Register circuit. A shift register circuit according to claim 3,
The first dummy stage is
The second control pulse is input to the first input terminal;
A seventh transistor for discharging the first node of the first dummy stage based on the first control pulse;
The second dummy stage is
The first control pulse is input to the second input terminal;
The shift register circuit further comprising: an eighth transistor that discharges the first node of the second dummy stage based on the second control pulse.

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