JP2011171892A - Imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine the address of a detection element for substitution for the address of a defective element in a short time. <P>SOLUTION: This imaging device (10) includes logic circuits (334-342) which read first defect information of an address generated according to a first address sequence (308) and second defect information of an address generated according to a second address sequence (306) from defect determination storage devices (442, 312), and write the address generated according to the second address sequence in the address generated according to the first address sequence in a defect substitution storage device (446) when the first defect information shows a defect and the second defect information shows no defect. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an imaging device, and more particularly, to an imaging device having a pixel replacement function at a defective element position.

  An image sensor such as a detector for an infrared camera and a CCD element for a color camera device generally includes a defective element called a defective element. The defective element cannot supply normal imaging pixel data, and adversely affects the quality of the image displayed on the monitor. In the case of infrared camera detectors, the number of detectors may occupy 1% or more of the entire detector element if the number is large. For example, this number exceeds 3000 elements when converted into the number of elements of VGA size of 640 × 480 pixels.

  In order to compensate for defective pixels due to such defective elements, the defective pixel values are generally replaced with normal peripheral pixel values in the vicinity.

  A known pixel replacement method of an infrared imaging device forms a two-dimensional image on a frame memory using a multi-element infrared detector to display a two-dimensional image. The infrared imaging device includes a reference temperature data memory that stores high-temperature data and low-temperature data of each sensing element with respect to high and low reference temperatures. The infrared imaging device further calculates the difference between the high temperature data and the low temperature data of each sensing element, calculates the average value of the differences for all the sensing elements, and the sum of the average value and the upper limit set value is calculated from the difference value. When it is larger or the sum of the average value and the lower limit set value is smaller than the difference value, a defect determination unit is provided that determines the detection element as a defective element. The infrared imaging device further includes a replacement memory that replaces the address of the sensing element corresponding to the defective pixel in the frame memory with the address of the sensing element corresponding to the normal pixel adjacent to the defective pixel. Thereby, automatic replacement of defective pixels and adjacent pixels is performed.

  A known imaging device extracts defective elements based on read data of an image serving as a reference by an array-shaped reading element, and replaces pixel data of the defective element at the time of target imaging with pixel data of another element. The imaging apparatus determines an insensitive or small element as a defective element. Further, the imaging device selects the strictest threshold value for a plurality of types of noise levels, and counts the number of defective elements for which any detected noise level exceeds the corresponding threshold value for all elements of the array-shaped reading element, Each time the number of defective elements is equal to or less than a predetermined number, the selection of the threshold of the noise level type that records the maximum number of defects is switched to a looser one. Further, the imaging apparatus extracts and accumulates a uniform level of imaging data string in a predetermined direction from imaging data at the time of target imaging, and uses it as read data of a reference image. Thereby, the sensitivity of the display image is improved, the optimum threshold for defective pixel replacement can be easily set, and the frequency of use of the reference image source can be greatly reduced.

JP 9-163228 A Japanese Patent Laid-Open No. 10-341375

  In order to determine the address of the defective element of the camera device, the image data is transferred to a personal computer or the like, and the defect and address of the detection element are determined by software, or the operator confirms and detects on the display. Determine device defects and addresses. The address data of the determined defective element is transferred to the camera device and stored in the nonvolatile memory inside. When used, the camera device replaces defective pixel values with normal neighboring pixel values based on the address data of the defective elements.

  After determining the address of the defective element outside or inside the camera device, the address of the sensing element after replacement with respect to the address of the defective device can be determined and stored in a nonvolatile or volatile memory in the camera device.

  The defect of an image pickup device such as a CCD for an infrared camera device or an image pickup device includes an initial defect detected at the time of manufacture and a defect detected after the start of use mainly due to deterioration over time. It is not possible to deal with defects detected after the start of use only by compensating for the initial defective elements detected at the time of manufacture. Therefore, it is desirable to determine the address of the defective element in the camera device so that the defective pixel can be compensated or replaced.

  Operate the microcontroller or digital signal processor according to software to determine the address of the normal sensing element for replacement with respect to the address of the defective element according to the priority order of the relative address position of the sensing element of the replacement candidate with respect to the defective element of the camera device it can. However, in the method of determining the address of the detection element for replacement with respect to the address of the defective element by software, it is necessary to frequently interrupt the use of the camera device and perform processing for replacement of the defective pixel over time. . In addition, if the address, defect flag, and replacement flag are processed one by one for each detection element using a memory such as SRAM or SDRAM with a large storage capacity, the access delay to the memory is large, so replacement is performed. It takes time to determine the detection element.

  The inventor has recognized that it is necessary to be able to determine the address of the detection element for replacement with respect to the address of the defective element of the camera device in a short time by hardware.

An object of the present invention is to enable hardware to determine the address of a sensing element for replacement with respect to the address of a defective element.
Another object of the present invention is to enable determination of the address of a sensing element for replacement with respect to the address of a defective element in a short time.

  According to one aspect (feature) of an embodiment of the present invention, an imaging device includes: an imaging element having a plurality of detection elements that detect infrared rays emitted from an object; and each address of each of the plurality of detection elements. A defect determination storage device that stores the defect information of the detection element at the address of the defect, a defect replacement storage device that stores a replacement destination address corresponding to the address at which the defect information is stored, and a first including the respective addresses A first address generator for generating an address sequence; a second address generator for generating a second address sequence obtained by adding an offset value to the first address sequence; The first defect information of the address generated according to the sequence and the second defect information of the address generated according to the second address sequence. Information is read from the defect determination storage device, and when the first defect information indicates a defect and the second defect information indicates no defect, the defect replacement storage device has the first address And a logic circuit for writing the address generated according to the second address sequence to the address generated according to the sequence.

  According to one aspect of the embodiment of the present invention, the address of the detection element for replacement with respect to the address of the defective element can be determined by hardware, and can be determined in a short time.

FIG. 1 shows an example of a schematic configuration of a camera device according to the embodiment. FIG. 2 shows an example of a schematic configuration of the defect determination and defect replacement unit. FIG. 3 shows an example of a defect address map stored in the defect replacement memory. FIG. 4A shows an example of arrangement of priorities of neighboring replacement candidate detection elements with respect to the element of interest. FIG. 4B shows an offset / address generation table that represents the relative offset address of the detection element as a replacement candidate with respect to the address of each element of interest in FIG. FIG. 5 shows an example of the arrangement of the defective elements in the array of detection elements of the infrared imaging device 16 for explaining the operation of the defect replacement address generation unit. FIG. 6 shows an example of a schematic configuration of a defect replacement address generation unit that can be implemented by, for example, FPGA, ASIC, LSI, or the like. FIG. 7A shows a logical configuration for frame 0 in the defect replacement address generation unit of FIG. 6 set by the control unit. FIG. 7B shows a logical configuration for frames 1 to 8 in the defect replacement address generation unit of FIG. 6 set by the control unit. 8A to 8D show time charts for frame 0, which are used in the operation of the defect replacement address generation unit having the logical configuration of FIG. 7A. 9A to 9G show time charts for the frame 1 used for the operation of the defect replacement address generation unit having the logical configuration of FIG. 7B. FIGS. 10A to 10G show time charts for the frame 2 used for the operation of the defect replacement address generation unit having the logic configuration of FIG. 7B. 11A to 11G show time charts for the frame 3 used for the operation of the defect replacement address generation unit having the logical configuration of FIG. 7B. 12A to 12G show time charts for the frame 4 used for the operation of the defect replacement address generation unit having the logical configuration of FIG. 7B. 13A to 13G show time charts for the frame 5 used in the operation of the defect replacement address generation unit having the logical configuration of FIG. 7B.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

  Non-limiting embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components and elements are provided with the same reference numerals.

FIG. 1 shows an example of a schematic configuration of a camera device or an imaging device 10 according to the embodiment.
The camera device 10 includes a lens unit 12, an infrared filter 14, an infrared imager or infrared detector (IRID) 16, an analog signal amplifier (AMP) 18, and an analog-digital converter (A / D) 20. It is out. The camera device 10 further includes a control unit 22, a memory 24, a level corrector 28, a defect determination and defect replacement unit 30, and a formatted image data generator 70.

  The control unit 22 controls the memory 24, the sensing element level corrector 28, the defect determination and defect replacement unit 30, the formatted image data generator 70, and the like. The level corrector 28, the defect determination and defect replacement unit 30, and a part of the formatted image data generator 70 may be implemented on a digital signal processor (DSP) that operates according to a program stored in the memory 25.

  The infrared imager or infrared detector 16 includes, for example, an array of infrared detection elements arranged in a matrix. An infrared imaging element or device can use different structures and materials depending on the wavelength band to be detected. The material may be, for example, mercury cadmium tellurium (HgCdTe) with high temperature resolution used at a low temperature, or a bolometer used at room temperature. The infrared imager 16 is expensive. Therefore, even if there are some defects in the sensing element of the imager 16, the defective pixel value generated by the defective element is compensated or replaced with the pixel value generated by another normal sensing element, It is desirable to use the imager 16.

  However, in the method of determining the address of the normal image sensor for replacement with respect to the address of the defective element by software, it is necessary to frequently interrupt the use of the camera apparatus and perform processing for defective pixel replacement over time. is there. In addition, when the image sensor or device address and flag are processed one element at a time using software with a large storage capacity memory, the memory has a large access delay, so it takes a long time to determine the detection element for replacement. Cost.

  FIG. 2 shows an example of a schematic configuration of the defect determination and defect replacement unit 30.

  The defect determination and defect replacement unit 30 includes a defect determination unit 32, a defect replacement address generation unit 34, and a pixel replacement control unit 36. The defect determination and defect replacement unit 30 uses the memory areas of the memory 24 such as the defect determination memory 42, the defect replacement memory 44, and the frame image memory 46. The memory 24 may be, for example, a large capacity SRAM or SDRAM.

  At the time of shipment of the camera apparatus 10 and after the start of use, the operator or user first images two types of reference image plates of high temperature and low temperature or light and dark by the infrared imager 16 of the camera apparatus 10. The imager 16 receives two types of analog signals of each sensing element representing the high temperature and low temperature or light and dark through the analog amplifier 22 to the analog-to-digital converter 20. Next, the analog-to-digital converter 20 converts each analog signal into digital data and stores it as reference image data in the area of the reference image memory 46 of the memory 24.

  The level corrector 28 processes the reference image data representing the reference high / low temperature or light / dark in the region of the reference image memory 46 to generate a correction coefficient for correcting the signal level variation between the sensing elements. And stored in the area of the correction coefficient memory 26 of the memory 24. For this purpose, the level correction unit 28 determines the high / low temperature or light / dark level difference of each detection element in the region of the reference image memory 46, stores it in the defect determination memory 42, and according to the level difference. A correction coefficient for each sensing element is determined. The value of the correction coefficient may be a value such that the level difference after correction obtained by multiplying the high temperature and low temperature or light and dark values of each detection element by the correction coefficient becomes a standardized level difference. It may be the reciprocal of the difference between the high and low temperatures or the light and dark levels of each sensing element. When the camera device 10 is used, each pixel data of the image data imaged by the infrared imager 16 and generated by the analog-digital converter 26 is multiplied by a corresponding correction coefficient at the corresponding address position. Image data can be corrected.

  The defect determination unit 32 can be mounted on a digital signal processor (DSP), for example. The defect determination unit 32 compares the level difference between the high and low temperatures or the brightness and darkness of each detection element in the defect determination memory 42 with data representing the allowable range in the defect determination memory 42, and determines each pixel of the image data. Determine if the data is defective or normal. The defect determination unit 32 stores a corresponding defect flag (0/1) in the defect determination memory 42 at each address position of the n-row / m-column detection element or pixel. For example, the defect flag 0 represents that there is no defect and is normal, and the defect flag 1 represents a defect.

  In order to determine the presence or absence of a defect in the detection element, the defect determination unit 32 determines whether the difference between the high and low temperatures or the light and dark levels of each detection element in the reference image memory 25 of the memory 24 is the defect determination memory 4 It may be determined whether or not it is within the allowable range stored in. When the level difference of a certain detection element is larger or smaller than the allowable range, the defect determination unit 32 determines that the detection element is defective, and the defect flag at the address position of the detection element in the defect replacement memory 44 of the memory 25. A value of 1 (has a defect) is written in The allowable range is, for example, the upper threshold value expressed by the sum of the average value of the high and low temperature or light and dark level differences for all the sensing elements and the upper allowable value (positive), and the average value and the lower allowable value. It may be defined by a lower threshold value represented by a (negative) sum.

  The detection of the defective element is not limited to this, and can be performed by a known method disclosed in, for example, JP-A-9-163228 and JP-A-10-341375. These documents are hereby incorporated by reference.

  Next, the defect replacement address generation unit 34 determines the address of the defective element and the address of the detection element after replacement. The defect replacement address generation unit 34 can be mounted in a hardware form on a circuit such as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or an LSI (Large Integrated Circuit). The defect replacement address generation unit 34 generates an address of the detection element as a replacement candidate in accordance with the information regarding the address of the defective element in the defect replacement memory 44, and converts the defective element address to the address of the normal detection element after replacement. Information representing the map (mapping) is stored in the defect replacement memory 44.

  Thereafter, after the use of the camera device 10 is started, the pixel replacement control unit 36 performs pixel data of defective elements on the image data after level correction from the level correction unit 28 according to the replacement address map in the defect replacement memory 44. Is replaced with the pixel data of the detecting element for replacement. The pixel replacement control unit 36 assembles an image frame of the processed pixel data and stores it in the frame image memory 46.

  The frame image memory 46 supplies the image frame to the image format generation unit 70. Next, the formatted image generation unit 70 formats the image data of the frame after the replacement process, and generates formatted image data.

  The output image data from the formatted image data generator 70 is supplied to, for example, a recording device, a monitor device, an alarm device (not shown) or the like for monitoring persons who have entered and exited the room.

FIG. 3 shows an example of a defect address map stored in the defect replacement memory 44.
The defect address map in FIG. 3 is a table for mapping the address of the defective element to the address of the detection element for replacement or replacement in the array of detection elements of n rows and m columns. By the mapping, the pixel data of the defective element is replaced with the pixel data of the replacement or replacement destination detection element.

  The defect address map shown in FIG. 3 shows the detection element address (row, column) to be replaced or not replaced, and a defect flag (0/1) indicating the presence / absence of a defect for an array of n-row / m-column detection elements. ), A processing completion flag (0/1) indicating completion of replacement, and the address (row, column) of the detection element after replacement or replacement. In FIG. 3, the pixel data of the detection element of the defect flag 1 at the address (1, 1) is replaced with the pixel data of the detection element at the address (0, 1), and the completion of the replacement process is represented by the completion flag 1. An example is shown.

FIG. 4A shows an example of the arrangement of the priorities 1 to 8 of the neighboring replacement candidate detection elements with respect to the element of interest X. Here, it is assumed that the smaller the numerical value of the priority, the higher the priority.
FIG. 4B shows an offset address generation that represents the relative offset address of the detection element that is a replacement candidate with respect to the address (0, 0) of each element of interest X in FIG. Shows the table.

  In FIG. 4A, when the element of interest X in the i-th row and j-th column, that is, the address (i, j) is normal and not defective, the pixel of the sensing element X is naturally not replaced. The pixel itself of the detection element X can also be regarded as a replacement candidate detection element with the highest priority 0. However, if the target element X in the i-th row and j-th column, that is, the address (i, j) is defective, the detection element at the address (i, j−1) in the same row and the previous column is 1 in priority. This is a detection element for replacement candidates. When the detection element at the address (i, j-1) is normal, the pixel of the detection element X at the address (i, j) is replaced with the pixel of the detection element at the address (i, j-1).

  However, when the detection element at the address (i, j−1) is also defective, the detection element at the address (i, j + 1) after one column in the same row becomes the detection element for the replacement candidate of priority 2. When the sensing element at the address (i, j + 1) is normal, the pixel of the sensing element X at the address (i, j) is replaced with the pixel of the sensing element at the address (i, j + 1).

  If the sensing element at address (i, j + 1) is also defective, the sensing element at address (i-1, j) in the same column as sensing element X one row before sensing element X is a sensing element with priority 3. Become. When the detection element at the address (i-1, j) is normal, the pixel of the detection element X at the address (i, j) is replaced with the pixel of the detection element at the address (i-1, j).

  When the detection element at the address (i−1, j) is also defective, the detection element at the address (i + 1, j) in the same column as the detection element X after the first row of the detection element X is a detection element with priority 4 Become. When the sensing element at the address (i + 1, j) is normal, the pixel of the sensing element X at the address (i, j) is replaced with the pixel of the sensing element at the address (i + 1, j).

  When the detection element at the address (i + 1, j) is also defective, the detection element at the address (i, j-2) two columns before in the same row as the detection element X becomes the detection element of the replacement candidate with priority 5. . When the detection element at the address (i, j-2) is normal, the pixel of the detection element X at the address (i, j) is replaced with the pixel of the detection element at the address (i, j-2).

  When the detection element at the address (i, j-2) is also defective, the detection element at the address (i, j + 2) after two columns in the same row as the detection element X becomes a detection candidate for the priority 6 replacement candidate. . When the detection element at the address (i, j + 2) is normal, the pixel of the detection element X at the address (i, j) is replaced with the pixel of the detection element at the address (i, j + 2).

  If the detection element at the address (i, j + 2) is also defective, the detection element at the address (i-2, j) in the same column as the detection element X two rows before the detection element X is a detection element with priority 7. Become. When the detection element at the address (i-2, j) is normal, the pixel of the detection element X at the address (i, j) is replaced with the pixel of the detection element at the address (i-2, j).

  If the detection element at the address (i−1, j) is also defective, the detection element at the address (i + 2, j) in the same column as the detection element X after the second row of the detection element X is a detection element with priority 8 Become. When the sensing element at the address (i + 2, j) is normal, the pixel of the sensing element X at the address (i, j) is replaced with the pixel of the sensing element at the address (i + 2, j).

  If the detection element at the address (i + 2, j) is also defective, since the priority lower than the priority 8 is not set here, the pixel of the detection element X at the address (i, j) is not replaced. Also good. As an alternative, another detection element with a priority lower than priority 8 may be set and processed as a replacement candidate in the same manner.

  In the offset address generation table of FIG. 4B, for frame 0, the offset address is (± 0, ± 0). Therefore, the defect replacement address generation unit 34 performs a process of confirming whether the target element X at the address (i, j) = (i ± 0, j ± 0) is normal or defective.

  For frame 1, the offset address is (± 0, −1). Accordingly, the defect replacement address generation unit 34 performs processing for confirming whether the address (i, j−1) one column before the target element X of the address (i, j) is normal or defective.

  For frame 2, the offset address is (± 0, +1). Therefore, the defect replacement address generation unit 34 performs a process of confirming whether the address (i, j + 1) after one column of the target element X of the address (i, j) is normal or defective.

  For frame 3, the offset address is (-1, ± 0). Accordingly, the defect replacement address generation unit 34 performs processing for confirming whether the address (i−1, j) one row before the target element X of the address (i, j) is normal or defective.

  For frame 4, the offset address is (+1, ± 0). Therefore, the defect replacement address generation unit 34 performs processing for confirming whether the address (i + 1, j) after one row of the target element X of the address (i, j) is normal or defective.

  Similarly, for frame 5, the offset address is (± 0, -2). For frame 6, the offset address is (± 0, +2). For frame 7, the offset address is (−2, ± 0). For frame 8, the offset address is (+2, ± 0). The defect replacement address generation unit 34 performs processing for confirming whether the address (i + Δi, j + Δj) obtained by adding the respective offset addresses (Δi, Δj) to the target element X of the address (i, j) is normal or defective. Do.

  FIG. 5 shows an example of the arrangement of defective elements in the array of detection elements of the infrared imager 16 for explaining the operation of the defect replacement address generation unit 34. In this case, the infrared imager 16 includes an array of 5 × 5 matrix detector elements, and addresses (0,0), (0,1), (0,2), (0) indicated by dark shadows. , 3), (3,4), (4, 3) and (4, 4) are assumed to be defective. In this case, in the address map of FIG. 3, the addresses (0,0), (0,1), (0,2), (0,3), (3,4), (4,3) and (4 , 4) is set to a value of 1 in the defect flag.

  FIG. 6 shows an example of a schematic configuration of the defect replacement address generation unit 34 that can be implemented by, for example, FPGA, ASIC, LSI, or the like.

  The defect replacement address generator 34 includes a frame counter 302, an adder 306, an address counter 308, and a defect flag memory or register 312 (, 442). The defect replacement address generation unit 34 uses the areas of the offset address generation table 404, the defect flag memory 442, the processing completion flag memory 444, and the replacement address memory 446 in the defect replacement memory 44. Each area of the defect flag memory 442, the processing completion flag memory 444, and the replacement address memory 446 stores information of a corresponding portion in the address map of FIG. The defect replacement address generation unit 34 reads the defect flag from the defect flag memory 442 and copies and stores it in the internal defect flag memory or register 312. As an alternative, in addition to the defect flag memory 312, the defect flag memory 442 is a register in the defect replacement address generation unit 34 that reads and stores a defect flag for each address from the address map of the defect replacement memory 44. There may be.

  The defect replacement address generation unit 34 starts an operation according to a control signal from the control unit 22. The frame counter 302 starts its operation in accordance with the activation signal from the control unit 22 and sequentially generates frame numbers 0 to 8 for replacement processing corresponding to the respective priorities. The offset address generation table 404 in the defect replacement memory 44 supplies an adder 306 with an offset address or a difference address corresponding to the current frame number. The address counter 308 functions as an address generator. The address counter 308 generates a sequence (a series of consecutive sequential addresses) of all the addresses (0, 0) to (n, m) of the sensing element array. The adder 306 functions as another address generator. The adder 306 adds the offset address for the current frame number to each output address of the address counter 308 in synchronization with the address counter 308 or its output address sequence, and the sequence of the sum addresses ( A series of consecutive sequential addresses).

  The defect replacement address generation unit 34 further includes knot circuits 320, 334, 337 and 338, an AND circuit 342, an OR circuit 346, a frame determination unit 352, a replacement number determination unit 354, and an OR circuit 360. In the defect replacement address generation unit 34, the logical configuration is switched by the switches SW 1, SW 2 a, SW 2 b, SW 3 in accordance with the control signal from the control unit 22. It is obvious that the same function of the defect replacement address generation unit 34 can be realized with another logical configuration.

FIG. 7A shows a logical configuration for frame 0 in the defect replacement address generation unit 34 of FIG. 6 set by the control unit 22. In this case, elements 334, 336, 337, 338, 342 and 346 of FIG. 6 are not used.
8A to 8D show time charts for the frame 0 used for the operation of the defect replacement address generation unit 34 having the logical configuration of FIG. 7A.

  Referring to FIG. 7A, according to the time charts of FIGS. 8A to 8D, the defect replacement address generation unit 34 determines whether the detection element at each address is defective, that is, the pixel of the detection element at each address is replaced with another replacement candidate. It is determined whether it is necessary to replace with a pixel of the sensing element. When a certain detection element is a normal element and does not require replacement, a value 1 indicating the completion of the replacement process for the detection element is set in the processing completion flag in the processing completion flag memory 444. To do. On the other hand, when a certain detection element is a defective element and does not require replacement, a value 0 indicating that the replacement process has not been completed for that detection element is set to a process completion flag in the process completion flag memory 444. Set to.

  For the replacement process, the control unit 22 for the frame 0, from the defect flag memory 442 area in the defect replacement memory 44, detects a series of defect flags or information (0/1) of the sensing element for the sequence of addresses. ) Are sequentially read and stored in the defect flag memory 312. The controller 22 may further store the series of defect flags for the address sequence in an internal defect flag memory (442).

  The address counter 308, as shown in FIG. 8A, includes the (row, column) address (0,0), (0,1), (0,2),. . . A sequence of (n, m) is sequentially generated. The address counter 308 sequentially supplies the sequence of addresses to each address input of the defect flag memory 442, the process completion flag memory 444, and the replacement address memory 446.

  For the sequence of addresses (0, 0) to (n, m) from the address counter 308, the adder 306 performs the offset address of the replacement candidate address for frame 1 (FIG. 4B) of the offset address generation table 404. Add (± 0, ± 0). Accordingly, the adder 306 sequentially generates the same address (0, 0) to (n, m) sequence as that from the address counter 308 as the address of the detection element as the replacement candidate. The adder 306 supplies the generated address to the address input of the defect flag memory 312 and the data input of the replacement address memory 446.

  The defect flag memory 442 provides the input of the knot circuit 320 with a series of sense element defect flags (0/1) for the generated and specified sequence of addresses. The defect flag has a value of 1 for a detection element having a defect and a value of 0 for a normal detection element having no defect. Accordingly, the defect flag memory 442 provides the addresses (0,0), (0,1), (0,2), (0,2) for the array of sensing elements of FIG. 5 as shown in FIG. 8B. The value 1 is supplied to the input of the knot circuit 320 as a defect flag for 3), (3, 4), (4, 3) and (4, 4). The defect flag memory 442 receives the value 0 indicating normal for the other addresses (0, 4) to (3, 3) and (4, 0) to (4, 2) as inputs to the knot circuit 320. To supply.

  The knot circuit 320 supplies a value (1/0) obtained by inverting the value (0/1) of the defect flag for each address to the processing completion flag memory 444 as data indicating processing completion. Here, the value 1 of the process completion flag represents the completion of the process, and the value 0 represents the incomplete process. In this case, the knot circuit 320 does not need replacement for the addresses (0, 4) to (3, 3) and (4, 0) to (4, 2), or the processing for replacement is completed. As a process completion flag or data indicating this, the value (1/0) is supplied to the process completion flag memory 444.

  In frame 0, the write enable signal (1) is supplied to the processing completion flag memory 444 and the replacement address memory 446 for all addresses. The process completion flag memory 444 stores a value obtained by inverting the defect flag value (0/1) for each address in the process completion flag memory 444 as a process completion flag indicating completion of the replacement process. In this case, in the processing completion flag memory 444, processing is completed for the addresses (0, 4) to (3, 3) and (4, 0) to (4, 2) for the array of sensing elements in FIG. The value 1 is set in the flag, and the value 0 is maintained in the processing completion flag for the addresses (0,0) to (0,3), (3,4), (4,3) to (4,4). Is done. For the address for which the processing completion flag is set to the value 1, the replacement address memory 446 may be left unset without being written to the address of the detection element after replacement. As an alternative, for the address for which the processing completion flag is set to the value 1, the same address as that before replacement may be written in the replacement address memory 446 as the address of the detection element after replacement. In this case, the detection element at the address before replacement can be regarded as the replacement element detection element with the highest priority 0.

  Further, the processing completion flag (1/0) from the knot circuit 320 is supplied to a processing number determination unit 354 that determines the number of addresses for which replacement processing for all addresses (0, 0) to (n, m) has been completed. The For the array of sensing elements of FIG. 5, the number of addresses that do not require replacement or have completed replacement processing is eighteen. When all the detection elements are normal and free of defects or the number of addresses for which replacement processing has been completed is equal to the total number of all addresses (n + 1) × (m + 1) (for example, 25), the processing number determination unit 354 outputs 1 is supplied to one input of the OR circuit 360. Thereby, the logic including the AND circuit 342 of FIG. 7B when the replacement process is completed for all the sensing elements regardless of whether the replacement process is completed for all predetermined priorities (for example, 1 to 8). The replacement process by can be completed. On the other hand, if the number of addresses for which replacement processing has been completed is not equal to or less than the total number (n + 1) × (m + 1) (for example, 25) of all addresses, the processing number determination unit 354 determines that processing has not been completed. A representative output 0 is provided to one input of the OR circuit 360.

  The frame determination unit 352 determines whether the frame number from the frame counter 302 is equal to the last frame number (for example, 8). If the frame number from the frame counter 302 is equal to the last frame number or priority (e.g., 8), the frame regardless of whether or not the replacement process has been completed for all the sensing elements in the sensing element array. The determination unit 352 supplies the output 1 to another input of the OR circuit 360. Accordingly, the AND circuit 342 of FIG. 7B is included when the replacement process is completed for all predetermined priorities (for example, 1 to 8) regardless of whether or not the replacement process is completed for all the detection elements. The replacement process by logic can be completed.

  The OR circuit 360 takes the logical sum of the inputs from the processing number determination unit 354 and the frame determination unit 352 and generates an output. Accordingly, when the replacement process is completed for all the detection elements in the detection element array or the frame number is equal to the last frame number, the OR circuit 360 controls the value 1 indicating the completion of the replacement process as a replacement process completion flag. Supplied to the unit 22. When both the inputs are the value 0, the OR circuit 360 supplies the control unit 22 with a value 0 indicating that the replacement process is not completed as a replacement process completion flag. In response to the replacement process completion flag 1, the control unit 22 can execute a process for replacing a pixel.

FIG. 7B shows a logical configuration for frames 1 to 8 in the defect replacement address generation unit 34 of FIG. 6 set by the control unit 22. In this case, the element 320 of FIG. 6 is not used.
9A to 9G show time charts for the frame 1 used for the operation of the defect replacement address generation unit 34 having the logical configuration of FIG. 7B.

  Referring to FIG. 7B, as shown in FIG. 9A, the address counter 308 performs the address (0,0), (0,1), (0,2), FIG. . . . A sequence of (n, m) is sequentially generated. The address counter 308 sequentially supplies the sequence of addresses to each address input of the defect flag memory 442, the process completion flag memory 444, and the replacement address memory 446.

  For the sequence of addresses (0, 0) to (n, m) from the address counter 308, the adder 306 performs the offset address of the replacement candidate address for frame 1 (FIG. 4B) of the offset address generation table 404. Add (± 0, -1). The adder 306 includes addresses (0, −1), (0, 0), (0, 1),. . . , (0, m-1), (1, -1),. . . A sequence of (n, m-1) is sequentially generated. In this case, the adder 306, as shown in FIG. 9C, addresses (0, −1), (0, 0), (0, 1),. . . , (0,3), (1, -1),. . . The sequence of (4, 3) is sequentially generated. The adder 306 supplies the generated address to the address input of the defect flag memory 312 and the data input of the replacement address memory 446.

  As shown in FIG. 9B, the defect flag memory 442 supplies a series of detection element defect flags (0/1) for the sequence of generated and designated addresses to one input of the AND circuit 342 as it is. To do. Therefore, the defect flag memory 442 has addresses (0, 0), (0, 1), (0, 2), (0, 3), (3, 4), as shown in FIG. 9B. For (4, 3) and (4, 4), the value 1 is supplied as a defect flag to one input of the AND circuit 342. The defect flag memory 442 uses the value 0 representing normality for other addresses (0, 4) to (3, 3), (4, 0) to (4, 2) as a defect flag, and is 1 in the AND circuit 342. Supply to one input.

  As shown in FIG. 9D, the defect flag memory 312 receives a series of defect flags (0/1) of the sensing elements for the sequence of each address from the adder 306 and inputs the knot circuit 334 as a replacement candidate defect flag. To supply. In this case, the defect flag memory 312 receives the address of FIG. 9C from the adder 306 with respect to the addresses (0, 0) and (1, 0) to (4, 3) of the sensing element before replacement in FIG. 9A. (0, -1), (1, -1) to (1,3), (2, -1) to (2,3), (3, -1) to (3,3), (4,- The defect flag value 0 of the detection element as the replacement candidate for 1) to (4, 2) is supplied to the input of the knot circuit 334. The knot circuit 334 supplies a value (1/0) obtained by inverting the defect flag (0/1) for the designated address to another input of the AND circuit 342 as a replacement candidate non-defect flag. In this case, the knot circuit 334 uses the addresses (0, -1), FIG. 9C, and the addresses (0, 0), (1,0) to (4, 3) of the sensing elements before replacement in FIG. 9A. The value 1 obtained by inverting the defect flag 0 indicating that the replacement candidate detection elements for (1, -1) to (4, 2) are non-defective elements is input to the AND circuit 342 as a replacement candidate non-defective flag. Supply.

  The address range determination unit 336 determines whether the addresses (0, −1) to (n, m−1) from the adder 306 are within the range of the detection element addresses (0, 0) to (n, m). And a value 0 is generated for the address from the adder 306 within the range, and a value 1 is generated for the address from the adder 306 outside the range. In this case, the address range determination unit 336 has addresses (0, 0) to (0, 3), (1, 0) to (1, 3), (2, 0) to (2, 3) within the range. , (3,0) to (3,3), (4,0) to (4,3) are generated with a value of 0. In addition, the address range determination unit 336 applies the addresses (0, -1), (1, -1), (2, -1), (3, -1), and (4, -1) outside the range. Value 1 is generated. The address range determination unit 336 supplies the value (0/1) of the determination result to the input of the knot circuit 337. The knot circuit 337 supplies a value (1/0) obtained by inverting the value of the determination result to yet another input of the AND circuit 342. In this case, the knot circuit 337 includes addresses (0, 0) to (0, 3), (1, 0) to (1, 3), (2, 0) to (2, 3), ( The value 1 is generated for (3,0) to (3,3) and (4,0) to (4,3). Further, the knot circuit 337 has values for addresses (0, -1), (1, -1), (2, -1), (3, -1), and (4, -1) outside the range. Generate 0.

  As shown in FIG. 9E, the processing completion flag memory 444 receives a series of sensing element processing completion flags (0/1) for the sequence of addresses specified by the address counter 308 and inputs to the knot circuit 338. Supply to one input of OR circuit 346. In this case, the processing completion flag memory 444 receives processing completion flags for the addresses (0, 4) to (3, 3) and (4, 0) to (4, 2) in FIG. 9A from the address counter 308. The value 1 is supplied to the input of the knot circuit 338. Further, the processing completion flag memory 444 is provided for the addresses (0, 0) to (0, 3), (3,4), (4, 3) to (4, 4) from the address counter 308. A process completion flag value 0 representing the incomplete process is supplied to the input of the knot circuit 338. The knot circuit 338 supplies a value (0/1) obtained by inverting the process completion flag value to another input of the AND circuit 342. In this case, the knot circuit 338 generates an output 0 for the addresses (0, 4) to (3, 3) and (4, 0) to (4, 2) in FIG. 9A from the address counter 308. The knot circuit 338 outputs 1 to the addresses (0,0) to (0,3), (3,4), (4,3) to (4,4) from the address counter 308. Generate.

  The AND circuit 342 generates a logical product of the four inputs as its output. In the AND circuit 342, (a) the detection element of the address from the address counter 308 is defective, (b) the detection element for the replacement candidate at the offset or priority position is a non-defective element, and (c) the detection of the replacement candidate. When the element address is within the actual address range and (d) the processing completion flag for the address from the address counter 308 indicates incomplete, an output value 1 is generated. In other cases, the AND circuit 342 generates an output value 0. In this case, the AND circuit 342 generates the write enable signal 1 as an output for the addresses (3, 4) and (4, 3) from the address counter 308, as shown in FIG. 9F. The write enable signal 1 is also the value 1 of the process completion flag as write data to the process completion flag memory 444.

  When the output of the AND circuit 342 is 1, the write enable signal 1 and the write flag data 1 are supplied to the processing completion flag memory 444, and the write enable signal 1 is supplied to the replacement address memory 446. As a result, the processing completion flag in the processing completion flag memory 444 at the corresponding address position in FIG. 9A from the address counter 308 is changed from the value 0 to the value 1. In the case of processing in the order of frames 1 to 8, the processing completion flag and the processing completion flag in the memory 444 at that address are not changed or overwritten thereafter. In this case, in the processing completion flag memory 444, a value 1 is additionally written to the processing completion flag for the addresses (3, 4) and (4, 3). Further, the address of the detection element of the replacement candidate in FIG. 9C from the adder 306 is the data of the detection element address after replacement (replacement destination), and the address of the detection element before replacement in FIG. The associated address is stored in the replacement address memory 446. In this case, in the replacement address memory 446, the addresses (3, 3), (4, 4) of the detection elements after replacement are associated with the addresses (3,4), (4, 3) of the detection elements before replacement. 3) is written.

  A processing completion flag from the processing completion flag memory 444 and a write flag data to the processing completion flag memory 444 or an enable signal are supplied to respective inputs of the OR circuit 346. As shown in FIG. 9G, the OR circuit 346 supplies the logical sum of the two inputs to the output as a written processing completion flag. In this case, the OR circuit 346 generates a process completion flag value 1 that has been written to the addresses (0, 4) to (4, 3).

  The written processing completion flag from the OR circuit 346 is supplied to a processing number determination unit 354 that determines the number of addresses for which replacement processing for all addresses (0, 0) to (n, m) has been completed. In this case, the number of addresses that have completed the replacement process is 20. When the number of addresses for which replacement processing has been completed is equal to the total number of all addresses (n + 1) × (m + 1) (for example, 25), the processing number determination unit 354 supplies output 1 to one input of the OR circuit 360. . On the other hand, when the number of addresses for which replacement processing has been completed is not equal to or less than the total number of all addresses (for example, 25), the processing number determination unit 354 outputs an output 0 indicating that processing has not been completed to the OR circuit 360. To one input.

  The frame determination unit 352 determines whether the frame number from the frame counter 302 is equal to the last frame number (for example, 8). When the frame number is equal to the last frame number, the frame determination unit 352 supplies the output 1 indicating the completion of processing to another input of the OR circuit 360. On the other hand, when the frame number is not equal to the last frame number, the frame determination unit 352 supplies the output 0 indicating the incomplete processing to the other input of the OR circuit 360.

  The OR circuit 360 takes the logical sum of the inputs from the processing number determination unit 354 and the frame determination unit 352, and when either one is the value 1 indicating the completion of the processing, the replacement processing is completed with the value 1 indicating the completion of the replacement processing. The flag is supplied to the control unit 22 as a flag. On the other hand, when both of the inputs are the value 0, the OR circuit 360 supplies the control unit 22 with a value 0 indicating that the replacement process is not completed as a replacement process completion flag. In response to the replacement process completion flag 1, the control unit 22 can execute a process for replacing a pixel.

  FIGS. 10A to 10G show time charts for the frame 2 used in the operation of the defect replacement address generation unit 34 having the logical configuration of FIG. 7B.

  Referring to FIG. 7B, as shown in FIG. 10A, the address counter 308 performs the operations for the addresses (0, 0) to (n, m) of FIG. Generate sequences sequentially.

  For the sequence of addresses (0, 0) to (n, m) from the address counter 308, the adder 306 offsets the replacement candidate address for frame 2 (FIG. 4B) of the offset address generation table 404. Add (± 0, +1). The adder 306 includes addresses (0, 1), (0, 2),. . . , (M + 1), (1,1),. . . A sequence of (n, m + 1) is sequentially generated. In this case, the adder 306, as shown in FIG. 10C, addresses (0, 1), (0, 2),. . . , (0,5), (1,1),. . . The sequence of (4, 5) is sequentially generated.

  As shown in FIG. 10B, the defect flag memory 442 performs an AND circuit for a series of defect flags (0/1) of the sensing element for the generated and specified sequence of addresses, as shown in FIG. 10B. It is supplied to one input of 342 as it is.

  As shown in FIG. 10D, the defect flag memory 312 receives a series of defect flags (0/1) of the sensing element for each address sequence from the adder 306 as an input to the knot circuit 334 as a replacement candidate defect flag. To supply. In this case, the defect flag memory 312 stores the addresses (0, 3) to (3, 2), (3, 4) to (4, 1), and (4, 4) of the sensing elements before replacement in FIG. 10A. On the other hand, the defect flag of the detection element of the replacement candidate for the addresses (0, 4) to (3, 3), (3, 5) to (4, 2), (4, 5) of FIG. The value 0 is supplied to the input of the knot circuit 334. The knot circuit 334 supplies a value (0/1) obtained by inverting the defect flag (1/0) for the designated address to another input of the AND circuit 342 as a replacement candidate non-defect flag. In this case, the knot circuit 334 applies the address (0, 3) to (3, 2), (3,4) to (4, 1), (4, 4) of the sensing element before replacement to the address ( 0,4) to (3,3), (3,5) to (4,2), (4,5), the defect flag 0 indicating that the replacement candidate detection element is a non-defective element is inverted. The value 1 is supplied to the input of the AND circuit 342 as a replacement candidate non-defective flag.

  The address range determination unit 336 determines whether the addresses (0, 1) to (n, m + 1) from the adder 306 are in the range of the detection element addresses (0, 0) to (n, m). The value 0 is generated for the address from the adder 306 within the range, and the value 1 is generated for the address from the adder 306 outside the range. In this case, the address range determination unit 336 has addresses (0, 1) to (0, 4), (1, 1) to (1, 4), (2, 1) to (2, 4) within the range. , (3,1) to (3,4), (4,1) to (4,4), the value 0 is generated. The address range determination unit 336 generates a value 1 for addresses (0, 5), (1, 5), (2, 5), (3, 5), and (4, 5) outside the range. To do. The address range determination unit 336 supplies the value (0/1) of the determination result to the input of the knot circuit 337. The knot circuit 337 supplies a value (1/0) obtained by inverting the value of the determination result to yet another input of the AND circuit 342.

  As shown in FIG. 10E, the processing completion flag memory 444 provides a series of sensing element processing completion flags (0/1) for the sequence of addresses from the address counter 308 to the input and OR circuit of the knot circuit 338. 346 to one input. In this case, the processing completion flag memory 444 supplies the processing completion flag value 1 to the input of the knot circuit 338 for the addresses (0, 4) to (4, 3) of FIG. Further, the processing completion flag memory 444 sets a processing completion flag value 0 indicating that processing has not been completed to the addresses (0, 0) to (0, 3), (4, 4) from the address counter 308. Supply to the input of the knot circuit 338. The knot circuit 338 supplies a value (0/1) obtained by inverting the processing completion flag to yet another input of the AND circuit 342.

  The AND circuit 342 takes the logical product of the four inputs and generates its output as shown in FIG. 10F, as in FIG. 9F. In this case, the AND circuit 342 generates the write enable signal 1 as an output for the address (0, 3) from the address counter 308.

  When the output of the AND circuit 342 is 1, the write enable signal 1 and the write flag data 1 are supplied to the processing completion flag memory 444, and the write enable signal 1 is supplied to the replacement address memory 446. A processing completion flag in the processing completion flag memory 444 at the corresponding address position in FIG. 10A from the address counter 308 is changed from 0 to 1. In this case, in the processing completion flag memory 444, the processing completion flag 1 is additionally written to the address (0, 3). Also, the replacement candidate detection element address in FIG. 10C from the adder 306 is replaced with the detection element address data after replacement in association with the detection element address in FIG. 10A from the address counter 308 before replacement. Stored in the address memory 446. In this case, in the replacement address memory 446, the address (0, 4) of the detection element after replacement is written in association with the address (0, 3) of the detection element before replacement.

  A processing completion flag from the processing completion flag memory 444 and a write flag data to the processing completion flag memory 444 or an enable signal are supplied to respective inputs of the OR circuit 346. As shown in FIG. 10G, the OR circuit 346 supplies the logical sum of the two inputs to the output as a written processing completion flag. In this case, the OR circuit 346 generates a process completion flag value 1 that has been written to the addresses (0, 3) to (4, 3). The defect replacement address generation unit 34 operates in the same manner as the process for the frame 1 for the other processes for the frame 2.

  11A to 11G show time charts for the frame 3 used for the operation of the defect replacement address generation unit 34 having the logical configuration of FIG. 7B.

  As shown in FIG. 11A, the address counter 308 sequentially generates the sequence of addresses (0, 0) to (n, m) in FIG. 5 for the frame 3 as in FIG. 9A.

  For the sequence of addresses (0, 0) to (n, m) from the address counter 308, the adder 306 offsets the replacement candidate address for frame 2 (FIG. 4B) of the offset address generation table 404. Add (-1, 0). In this case, the adder 306, as shown in FIG. 11C, addresses (−1, 0), (−1, 0),. . . , (-1, 4), (0, 0),. . . The sequence (3, 4) is sequentially generated.

  As shown in FIG. 11B, the defect flag memory 442 performs an AND circuit for a series of defect flags (0/1) of the sensing element corresponding to the generated and specified sequence of addresses, as shown in FIG. 11B. It is supplied to one input of 342 as it is.

  As shown in FIG. 11D, the defect flag memory 312 receives a series of defect flags (0/1) of the detection elements for each address sequence from the adder 306 as an input to the knot circuit 334 as a replacement candidate defect flag. To supply. In this case, the defect flag memory 312 receives the figure from the adder 306 for the addresses (0, 0) to (0, 4) and (1, 4) to (4, 3) of the sensing elements before replacement. The defect flag value 0 of the replacement candidate detection element for the addresses (−1, 0) to (−1, 4) and (0, 4) to (3, 3) of 11C is supplied to the input of the knot circuit 334.

  In this case, the address range determination unit 336 determines whether the addresses (−1, 0) to (3, 4) from the adder 306 are in the range of addresses (0, 0) to (4, 4) of the detection elements. And a value 0 is generated for the address from the adder 306 within the range, and a value 1 is generated for the address from the adder 306 outside the range. The address range determination unit 336 generates a value 0 for the addresses (0, 0) to (3, 4) within the range. Further, the address range determination unit 336 generates a value 1 for addresses (−1, 0) to (−1, 4) outside the range.

  As shown in FIG. 11E, the processing completion flag memory 444 supplies a series of sensing element processing completion flags (0/1) for the sequence of addresses from the address counter 308 to the input of the knot circuit 338. . In this case, the processing completion flag memory 444 supplies the processing completion flag value 1 to the input of the knot circuit 338 for the addresses (0, 3) to (4, 3) of FIG. Further, the processing completion flag memory 444 knots the processing completion flag 0 indicating that processing is incomplete for the addresses (0, 0) to (0, 2), (4, 4) from the address counter 308. Supply to input of circuit 338.

  The AND circuit 342 takes the logical product of the four inputs and generates its output as shown in FIG. 11F, as in FIG. 9F. In this case, the AND circuit 342 does not generate the write enable signal 1 because there is no combination of a defective element for which the replacement process has not been completed and a normal replacement candidate detecting element having no defect.

  A processing completion flag from the processing completion flag memory 444 and a write flag data to the processing completion flag memory 444 or an enable signal are supplied to respective inputs of the OR circuit 346. As shown in FIG. 11G, the OR circuit 346 supplies the logical sum of the two inputs to the output as a written processing completion flag. The defect replacement address generation unit 34 operates in the same manner as the process for the frame 1 for the other processes for the frame 3.

  12A to 12G show time charts for the frame 4 used in the operation of the defect replacement address generation unit 34 having the logical configuration of FIG. 7B.

  As shown in FIG. 12A, for the frame 4, the address counter 308 sequentially generates the sequence of addresses (0, n) to (4, m) in FIG. 5 as in FIG. 9A.

  For the sequence of addresses (0, 0) to (n, m) from the address counter 308, the adder 306 offsets the replacement candidate address for the frame 4 (FIG. 4B) of the offset address generation table 404. Add (+1, ± 0). As shown in FIG. 12C, the adder 306 includes addresses (1, 0), (1, 1),. . . , (1,4), (2,0),. . . The sequence (5, 4) is sequentially generated.

  As shown in FIG. 12B, the defect flag memory 442 performs an AND circuit for a series of defect flags (0/1) of the sensing element for the generated and specified sequence of addresses, as shown in FIG. 12B. It is supplied to one input of 342 as it is.

  As shown in FIG. 12D, the defect flag memory 312 receives a series of defect flags (0/1) of the sensing elements for each address sequence from the adder 306 and inputs the knot circuit 334 as a replacement candidate defect flag. To supply. In this case, the defect flag memory 312 stores the addresses (0,0) to (3,3), (3,0) to (3,2), (4,0) to (4,4) of the sensing element before replacement. 4), the addresses (1, 0) to (3, 3), (4, 0) to (4, 2), (5, 0) to (5, 4) of FIG. Is supplied to the input of the knot circuit 334.

  The address range determination unit 336 determines whether the addresses (1, 0) to (5, 4) from the adder 306 are in the range of the detection element addresses (0, 0) to (4, 4). The value 0 is generated for the address from the adder 306 within the range, and the value 1 is generated for the address from the adder 306 outside the range. In this case, the address range determination unit 336 generates a value 0 for the addresses (1, 0) to (4, 4) within the range. The address range determination unit 336 generates a value 1 for addresses (5, 0) to (5, 4) outside the range.

  As shown in FIG. 12E, the processing completion flag memory 444 provides a series of sensing element processing completion flags (0/1) for the sequence of addresses from the address counter 308 to the input and OR circuit of the knot circuit 338. 346 to one input. In this case, the processing completion flag memory 444 supplies the processing completion flag 1 to the input of the knot circuit 338 for the addresses (0, 3) to (4, 3) in FIG. Further, the processing completion flag memory 444 knots the processing completion flag 0 indicating that processing is incomplete for the addresses (0, 0) to (0, 2), (4, 4) from the address counter 308. Supply to input of circuit 338.

  The AND circuit 342 takes the logical product of the four inputs and generates its output as shown in FIG. 12F, as in FIG. 9F. In this case, the AND circuit 342 generates the write enable signal 1 as an output for the addresses (0, 0) to (0, 2) from the address counter 308.

  When the output of the AND circuit 342 is 1, the write enable signal 1 and the write flag data 1 are supplied to the processing completion flag memory 444, and the write enable signal 1 is supplied to the replacement address memory 446. The processing completion flag in the corresponding address position in FIG. 12A from the address counter 308 is changed from 0 to 1. In this case, the processing completion flag 1 is additionally written in the processing completion flag memory 444 to the addresses (0, 0) to (0, 2). Also, the replacement candidate detection element address of FIG. 12C from the adder 306 is replaced with the detection element address data after replacement in association with the detection element address before replacement of FIG. 12A from the address counter 308. Stored in the address memory 446. In this case, in the replacement address memory 446, the addresses (1,0) to (1,2) of the detection elements after replacement in association with the addresses (0,0) to (0,2) of the detection elements before replacement. Is written.

  A processing completion flag from the processing completion flag memory 444 and a write flag data to the processing completion flag memory 444 or an enable signal are supplied to respective inputs of the OR circuit 346. As shown in FIG. 12G, the OR circuit 346 supplies the logical sum of the two inputs to the output as a written processing completion flag. In this case, the OR circuit 346 generates the processing completion flag 1 for the addresses (0, 0) to (4, 3). The defect replacement address generation unit 34 operates in the same manner as the process for the frame 1 for the other processes for the frame 4.

  13A to 13G show time charts for the frame 5 used for the operation of the defect replacement address generation unit 34 having the logical configuration of FIG. 7B.

  As shown in FIG. 13A, the address counter 308 sequentially generates the sequence of addresses (0, 0) to (4, 4) in FIG. 5 for the frame 5 as in FIG. 9A.

  For the sequence of addresses (0, 0) to (4, 4) from the address counter 308, the adder 306 offsets the replacement candidate address for the frame 5 (FIG. 4B) of the offset address generation table 404. Add (± 0, -2). As shown in FIG. 13C, the adder 306 includes addresses (0, -2), (0, -1),. . . , (0,2), (1, -2),. . . The sequence of (4, 2) is sequentially generated.

  As shown in FIG. 13B, the defect flag memory 442 performs an AND circuit for a series of defect flags (0/1) of the sensing element for the generated and specified sequence of addresses, as shown in FIG. 13B. It is supplied to one input of 342 as it is.

  As shown in FIG. 13D, the defect flag memory 312 inputs a knot circuit 334 using a series of defect flags (0/1) of the sensing elements for each address sequence from the adder 306 as replacement candidate defect flags. To supply. In this case, the defect flag memory 312 receives the figure from the adder 306 for the addresses (0, 0) to (0, 1) and (1, 0) to (4, 4) of the sensing elements before replacement. The defect flag value 0 of the replacement candidate detection element for the addresses (0, -2) to (0, -1) and (1, -2) to (4, 2) of 13C is supplied to the input of the knot circuit 334.

  The address range determination unit 336 determines whether the addresses (0, -2) to (4, 2) from the adder 306 are in the range of the detection element addresses (0, 0) to (4, 4). Thus, the value 0 is generated for the address from the adder 306 within the range, and the value 1 is generated for the address from the adder 306 outside the range. In this case, the address range determination unit 336 has addresses (0, 0) to (0, 2), (1, 0) to (1, 2), (2, 0) to (2, 2) within the range. , (3,0) to (3,2) and (4,0) to (4,2) are generated with a value of 0. The address range determination unit 336 also includes addresses (0, -2) to (0, -1), (1, -2) to (1, -1), (2, -2) to ( 2, -1), (3, -2) to (3, -1), and (4, -2) to (4, -1).

  As shown in FIG. 13E, the processing completion flag memory 444 supplies a series of sensing element processing completion flags (0/1) for the sequence of addresses from the address counter 308 to the input of the knot circuit 338. . In this case, the processing completion flag memory 444 supplies the processing completion flag value 1 to the input of the knot circuit 338 for the addresses (0, 0) to (4, 3) in FIG. The processing completion flag memory 444 supplies a processing completion flag 0 indicating that processing is not completed to the input of the knot circuit 338 for the address (4, 4) from the address counter 308.

  The AND circuit 342 takes the logical product of the four inputs and generates its output as shown in FIG. 13F, as in FIG. 9F. In this case, the AND circuit 342 generates the write enable signal 1 as an output for the address (4, 4) from the address counter 308.

  When the output of the AND circuit 342 is 1, the write enable signal 1 and the write flag data 1 are supplied to the processing completion flag memory 444, and the write enable signal 1 is supplied to the replacement address memory 446. The processing completion flag at the corresponding address position in FIG. 13A from the address counter 308 is changed from 0 to 1. In this case, the processing completion flag 1 is additionally written to the address (4, 4) in the processing completion flag memory 444. Further, the replacement candidate detection element address of FIG. 13C from the adder 306 is replaced with the detection element address data after replacement in association with the detection element address before replacement of FIG. 13A from the address counter 308. Stored in the address memory 446. In this case, in the replacement address memory 446, the address (4, 2) of the detection element after replacement is written in association with the address (4, 4) of the detection element before replacement.

  A processing completion flag from the processing completion flag memory 444 and a write flag data to the processing completion flag memory 444 or an enable signal are supplied to respective inputs of the OR circuit 346. As shown in FIG. 13G, the OR circuit 346 supplies the logical sum of the two inputs to the output as a written processing completion flag. In this case, the OR circuit 346 generates the processing completion flag 1 for all addresses (0, 0) to (4, 4).

  A processing completion flag from the processing completion flag memory 444 and a write enable signal to the processing completion flag memory 444 are supplied to respective inputs of the OR circuit 346. As shown in FIG. 13G, the OR circuit 346 supplies all 1 signals as the logical sum of the two inputs to the output as a written processing completion flag.

  The written processing completion flag from the OR circuit 346 is supplied to a processing number determination unit 354 that determines the number of addresses for which replacement processing for all addresses has been completed. In this case, since the number of addresses 25 for which the replacement process has been completed is equal to the sum 25 of all addresses, the processing number determination unit 354 supplies the output 1 to one input of the OR circuit 360.

  The frame determination unit 352 determines whether or not the frame number from the frame counter 302 is equal to the last frame number 8. Since the frame number is not equal to the last frame number 8, the frame determination unit 352 supplies the output 0 to another input of the OR circuit 360. The defect replacement address generation unit 34 operates in the same manner as the process for the frame 1 for the other processes for the frame 4.

  The OR circuit 360 calculates the logical sum of the inputs from the processing number determination unit 354 and the frame determination unit 352 and supplies the output 1 to the control unit 22 because the input from the processing number determination unit 354 is 1. Thereby, the replacement process of the defect replacement address generation unit 34 of the logical configuration of FIGS. 7A and 7B is completed.

  When the frame number from the frame counter 302 is equal to the last frame number 8, the frame determination unit 352 determines whether or not the replacement process for all defective detection elements has been completed. Output 1 is provided to another input of OR circuit 360. In this case, the OR circuit 360 takes the logical sum of the inputs from the processing number determination unit 354 and the frame determination unit 352 and supplies the output 1 to the control unit 22 because the input from the frame determination unit 352 is 1.

  In frame 5, when the processing completion flag from the OR circuit 346 is not 1 for all addresses (0, 0) to (4, 4), the processing completion flag from the OR circuit 346 is set to all addresses (0, 0). The process similar to that in the case of FIGS. 9A to 13G is repeated by the defect replacement address generation unit 34 for the subsequent frames 6 to 8 until it becomes 1 for 0) to (4, 4). On the other hand, in the last frame 8, even when the processing completion flag from the OR circuit 346 is not 1 for all addresses (0, 0) to (4, 4), the frame number is set to the last frame number. If they are equal, the replacement process is complete.

  As an alternative, the defect replacement address generation unit 34 performs the replacement process in the order of the frames 8 to 1 from the low priority to the high priority after processing the frame 0 according to FIGS. 8A to 8D with the logical configuration of FIG. 7A. May be performed. In this case, regardless of whether the processing completion flag 1 is set in the processing completion flag memory 444 for each address, as long as there is a combination with a normal replacement candidate detection element having no defect, the processing completion flag 1 is overwritten by the processing completion flag 1, and the replaced address is overwritten with the new replaced address having a higher priority.

  According to the above-described embodiment, compared with the case where the memory is accessed by the random address control by software, the time for the replacement process of the sensing element is reduced by, for example, approximately one time by accessing the memory by high-speed sequential address control by hardware. It can be shortened to 1/10 or less.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be interpreted without being limited to the conditions. Also, the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

Regarding the embodiment including the above examples, the following additional notes are further disclosed.
(Appendix 1) An image sensor having a plurality of detection elements for detecting infrared rays emitted from an object;
A defect determination storage device for storing respective addresses of the plurality of detection elements and defect information of the detection elements of the respective addresses;
A defect replacement storage device for storing a replacement destination address corresponding to the address where the defect information is stored;
A first address generator for generating a first address sequence including the respective addresses;
A second address generator for generating a second address sequence by adding an offset value to the first address sequence;
First defect information of an address generated according to the first address sequence and second defect information of an address generated according to the second address sequence are read from the defect determination storage device, and When the first defect information indicates a defect and the second defect information indicates no defect, the second address is added to the address generated according to the first address sequence in the defect replacement storage device. A logic circuit for writing addresses generated according to a sequence;
An imaging apparatus comprising:
(Supplementary Note 2) The imaging apparatus according to Supplementary Note 1, wherein the logic circuit further writes information indicating processing completion when writing the defect-free address.
(Supplementary Note 3) According to the first address sequence from the first address generation unit, a corresponding series of defect information is sequentially read out from the defect determination storage device, and the plurality of detection elements in the defect replacement storage device The imaging apparatus according to appendix 1 or 2, further comprising another logic circuit that writes information indicating processing completion to an address of a defect-free sensing element.
(Supplementary Note 4) For each of the different priorities, the first logic circuit sequentially designates the address of the defect determination storage device according to the first address sequence, and at the same time, according to the second address sequence. 4. The imaging apparatus according to any one of appendices 1 to 3, wherein a series of corresponding defect information is sequentially read from the defect determination storage device.
(Supplementary Note 5) Further, when information indicating completion of the processing is stored in all the addresses of the plurality of detection elements in the defect replacement storage device by the first logic circuit, the first logic circuit The imaging apparatus according to appendix 2, further comprising a third logic circuit that completes the operation.
(Additional remark 6) It is provided with the 4th logic circuit which completes operation | movement of a said 1st logic circuit, when it determines with the said 1st address sequence having been produced | generated about all the predetermined number of priorities. 6. The imaging device according to appendix 2 or 5, which is characterized.

DESCRIPTION OF SYMBOLS 10 Camera apparatus 302 Frame counter 306 Adder 308 Address counter 312 Defect flag memory 320, 334, 337, 338 Not circuit 342 AND circuit 346, 360 OR circuit 352 Frame determination part 354 Replacement number determination part 336 Address range determination part 336 442 Defect flag memory (register)
444 Processing completion flag memory 446 Replacement address memory

Claims (3)

An image sensor having a plurality of detection elements for detecting infrared rays emitted from an object;
A defect determination storage device for storing respective addresses of the plurality of detection elements and defect information of the detection elements of the respective addresses;
A defect replacement storage device for storing a replacement destination address corresponding to the address where the defect information is stored;
A first address generator for generating a first address sequence including the respective addresses;
A second address generator for generating a second address sequence by adding an offset value to the first address sequence;
First defect information of an address generated according to the first address sequence and second defect information of an address generated according to the second address sequence are read from the defect determination storage device, and When the first defect information indicates a defect and the second defect information indicates no defect, the second address is added to the address generated according to the first address sequence in the defect replacement storage device. A logic circuit for writing addresses generated according to a sequence;
An imaging apparatus comprising:   The imaging apparatus according to claim 1, wherein the logic circuit further writes information indicating processing completion when writing the defect-free address.   Further, according to the first address sequence from the first address generation unit, a series of corresponding defect information is sequentially read from the defect determination storage device, and the defect replacement storage device stores the plurality of detection elements. The imaging apparatus according to claim 1, further comprising another logic circuit that writes information indicating processing completion at an address of the defect-free sensing element.

Images