JP2011170961A - Recording method for nonvolatile magnetic thin film memory device - Google Patents

Recording method for nonvolatile magnetic thin film memory device Download PDF

Info

Publication number
JP2011170961A
JP2011170961A JP2011067330A JP2011067330A JP2011170961A JP 2011170961 A JP2011170961 A JP 2011170961A JP 2011067330 A JP2011067330 A JP 2011067330A JP 2011067330 A JP2011067330 A JP 2011067330A JP 2011170961 A JP2011170961 A JP 2011170961A
Authority
JP
Japan
Prior art keywords
thin film
magnetic thin
temperature
memory cell
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011067330A
Other languages
Japanese (ja)
Other versions
JP5188590B2 (en
Inventor
Kazuhisa Okano
一久 岡野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2011067330A priority Critical patent/JP5188590B2/en
Publication of JP2011170961A publication Critical patent/JP2011170961A/en
Application granted granted Critical
Publication of JP5188590B2 publication Critical patent/JP5188590B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1675Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008Marginal testing, e.g. race, voltage or current testing of impedance
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002Characteristic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006Current

Abstract

<P>PROBLEM TO BE SOLVED: To provide a recording method for a nonvolatile magnetic thin film memory device which stably operates even when temperature of the device increases. <P>SOLUTION: The nonvolatile magnetic thin film memory device has: a substrate; and a memory cell array composed of memory cells each having a magnetoresistance effect element, the memory cells being two-dimensionally arranged on the substrate. Before recording information on the nonvolatile magnetic thin film memory device, test information is written on the memory cell, and after checking the test information recorded, regular data is recorded. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は磁気抵抗効果素子を用いた不揮発磁気薄膜メモリ装置に関するものであり、特に垂直磁化膜の保磁力の温度変化に対応した不揮発磁気薄膜メモリ装置に関するものである。   The present invention relates to a nonvolatile magnetic thin film memory device using a magnetoresistive effect element, and more particularly to a nonvolatile magnetic thin film memory device corresponding to a temperature change of a coercive force of a perpendicular magnetization film.

従来より磁気薄膜メモリは、半導体メモリと同様に移動部のない固体メモリとして知られている。このような磁気薄膜メモリは、電源が遮断されても情報が消失しない、情報の繰り返し書き換え回数が無限回である、放射線が入射しても情報が消失する危険性がない等の条件を満たしており、従来の半導体メモリと比較して有利な点を数多く持っている。   Conventionally, a magnetic thin film memory is known as a solid-state memory having no moving part, like a semiconductor memory. Such a magnetic thin film memory satisfies the conditions such that information is not lost even when the power is turned off, the number of repeated rewrites of information is infinite, and there is no risk of information being lost even when radiation is incident. Therefore, it has many advantages compared with the conventional semiconductor memory.

その中でも、最近において提案されているトンネル磁気抵抗(TMR;Tunnel Magneto Resistive)効果を利用した磁気薄膜メモリは特に注目されている。トンネル磁気抵抗効果を利用した磁気薄膜メモリは、従来の異方性磁気抵抗効果、巨大磁気抵抗効果を利用した磁気薄膜メモリと比較して大きな出力を得ることができる。   Among them, a magnetic thin film memory using a tunnel magnetoresistive (TMR) effect that has been recently proposed is particularly attracting attention. The magnetic thin film memory using the tunnel magnetoresistive effect can obtain a larger output than the conventional magnetic thin film memory using the anisotropic magnetoresistive effect and the giant magnetoresistive effect.

トンネル磁気抵抗効果を利用した磁気薄膜メモリでは、2つの強磁性層が薄い絶縁層(トンネルバリア層)によって隔てられ、この2つの強磁性層のスピン分極率の差に応じた磁気抵抗が生じる。トンネル電流の大きさは、2つの強磁性層の磁化が相対的に平行か、反平行かに依存する。   In a magnetic thin film memory using the tunnel magnetoresistive effect, two ferromagnetic layers are separated by a thin insulating layer (tunnel barrier layer), and a magnetoresistance is generated according to the difference in spin polarizability between the two ferromagnetic layers. The magnitude of the tunnel current depends on whether the magnetizations of the two ferromagnetic layers are relatively parallel or antiparallel.

図11は、従来のトンネル磁気抵抗効果を利用した磁気薄膜メモリの一構成例を示す概略図である。   FIG. 11 is a schematic diagram showing a configuration example of a magnetic thin film memory using a conventional tunnel magnetoresistive effect.

図11に示すように、保磁力が互いに異なる磁性層111,113間にトンネルバリア層112を挟み込んだ構造より成っている。   As shown in FIG. 11, the tunnel barrier layer 112 is sandwiched between magnetic layers 111 and 113 having different coercive forces.

上記のように構成された磁気薄膜メモリにおいては、磁性層111,113間に電圧114が印加されると、一方の磁性層からの電子がトンネルバリア層112を貫通して他方の磁性層に進入してトンネル電流を発生させる。このトンネル電流の大きさは印加電圧に依存する。抵抗は磁性層111、113の両層の磁化の状態に依存し、両層が相対的に平行のとき最小の抵抗値をとり、反平行のとき最大の抵抗値をとる。この現象は磁性層111,113が面内磁化膜の場合にも、垂直磁化膜の場合にも確認されている(日本応用磁気学会誌 24,563−566(2000))。   In the magnetic thin film memory configured as described above, when a voltage 114 is applied between the magnetic layers 111 and 113, electrons from one magnetic layer penetrate the tunnel barrier layer 112 and enter the other magnetic layer. Thus, a tunnel current is generated. The magnitude of this tunnel current depends on the applied voltage. The resistance depends on the magnetization state of both layers of the magnetic layers 111 and 113, and takes the minimum resistance value when both layers are relatively parallel and takes the maximum resistance value when they are antiparallel. This phenomenon has been confirmed both when the magnetic layers 111 and 113 are in-plane magnetization films and perpendicular magnetization films (Journal of the Japan Society of Applied Magnetics 24, 563-566 (2000)).

このような現象を利用した磁気薄膜メモリとして、MRAM(Magnetic Random Access Memory)と呼ばれる不揮発性の磁気記憶装置がある。   As a magnetic thin film memory using such a phenomenon, there is a nonvolatile magnetic memory device called MRAM (Magnetic Random Access Memory).

従来より、トンネル磁気抵抗効果膜の強磁性層にFe,Co,Niなどの面内磁気異方性が大きい面内磁化膜を用いたトンネル磁気抵抗効果素子の開発が盛んであるが、特開平11−213650号公報には垂直磁化膜を用いた磁気抵抗効果素子が紹介されている。垂直磁化膜を用いた磁気抵抗効果素子では、素子サイズを小さくしても、反磁界が生じないため、微細化に優位であることが示されている。   Conventionally, a tunnel magnetoresistive element using an in-plane magnetic film having a large in-plane magnetic anisotropy such as Fe, Co, Ni, etc. as a ferromagnetic layer of the tunnel magnetoresistive film has been actively developed. No. 11-213650 introduces a magnetoresistive effect element using a perpendicular magnetization film. It has been shown that a magnetoresistive effect element using a perpendicular magnetization film is superior in miniaturization because a demagnetizing field does not occur even if the element size is reduced.

垂直磁化膜を用いたトンネル磁気抵抗効果素子は、電界効果型トランジスタにより駆動させる。   A tunnel magnetoresistive element using a perpendicular magnetization film is driven by a field effect transistor.

図12は、トンネル磁気抵抗効果素子に垂直磁化膜を用いた磁気薄膜メモリの一構成例を示す図である。   FIG. 12 is a diagram showing a configuration example of a magnetic thin film memory using a perpendicular magnetization film as a tunnel magnetoresistive effect element.

図12の磁気薄膜メモリは、基板上にトランジスタ121のゲート及びソースを備え、さらに、トンネル磁気抵抗効果素子122を記憶素子としている。また、書き込み線123から生じる膜面垂直方向の電流磁界により、書き込みが行われる。この図では単ビット分のメモリセルしか示していないが、実際には基板上に複数のメモリセルが配されており、各メモリセルは層間絶縁膜により電気的に孤立した状態になっている。   The magnetic thin film memory of FIG. 12 includes a gate and a source of a transistor 121 on a substrate, and further uses a tunnel magnetoresistive element 122 as a storage element. Further, writing is performed by a current magnetic field in the direction perpendicular to the film surface generated from the write line 123. Although only a single-bit memory cell is shown in this figure, a plurality of memory cells are actually arranged on the substrate, and each memory cell is electrically isolated by an interlayer insulating film.

特開平11−213650号公報Japanese Patent Laid-Open No. 11-213650

日本応用磁気学会誌 24,563−566(2000)Journal of the Japan Society of Applied Magnetics 24,563-366 (2000)

一般に磁性体の保磁力は温度上昇に伴って変化する。上記の不揮発磁気薄膜メモリ装置を構成するトンネル磁気抵抗効果素子の温度が上昇すると、素子の一構成要素である磁性層の保磁力が変化する。保磁力が低下したときには、隣接セルのクロストークが問題となり、保磁力が上昇すると、書き込み不良などの問題が生じる。   In general, the coercive force of a magnetic material changes as the temperature rises. When the temperature of the tunnel magnetoresistive element constituting the nonvolatile magnetic thin film memory device increases, the coercive force of the magnetic layer that is one component of the element changes. When the coercive force is reduced, crosstalk between adjacent cells becomes a problem, and when the coercive force is increased, problems such as writing failure occur.

特に、電流によって生じる磁界を印加して情報の記録を行なうようなMRAMにおいては、情報を書き込むべきメモリセルの周辺のメモリセルに磁界が印加されるのを防止するのは難しい。特に携帯機器などに応用する場合には使用温度も様々であり、温度の影響によって、周辺のメモリセルに誤書き込みなどが頻繁に起こる可能性がある。   In particular, in an MRAM that records information by applying a magnetic field generated by an electric current, it is difficult to prevent a magnetic field from being applied to memory cells around the memory cell to which information is to be written. In particular, when applied to a portable device or the like, the operating temperature varies, and erroneous writing or the like may frequently occur in peripheral memory cells due to the influence of the temperature.

加えて、垂直磁化膜を用いたトンネル磁気抵抗効果素子の保磁力は一般に大きい。従って、素子に書き込みを行うための書き込み線による電流値は非常に大きいものとなるため、デバイス全体の発熱が顕著である。   In addition, the coercivity of a tunnel magnetoresistive element using a perpendicular magnetization film is generally large. Therefore, since the current value due to the write line for writing to the element becomes very large, heat generation of the entire device is remarkable.

本発明は上記のような問題点を解消するためになされたもので、デバイスの温度が上昇しても、安定的に動作する不揮発磁気薄膜メモリ装置の記録方法を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a recording method for a nonvolatile magnetic thin film memory device that operates stably even when the temperature of the device rises.

本発明は上記課題に鑑み、基板上に磁気抵抗効果素子を有するメモリセルが二次元状に配された不揮発磁気薄膜メモリ装置のメモリセルに正規のデータの書き込みを行う前に試し書きを行って安定的に動作することを確認することを特徴とするものである。   In view of the above problems, the present invention performs test writing before writing regular data to a memory cell of a nonvolatile magnetic thin film memory device in which memory cells having magnetoresistive elements are two-dimensionally arranged on a substrate. It is characterized by confirming that it operates stably.

以上説明したように本発明の不揮発磁気薄膜メモリ装置の記録方法によれば、環境温度が変化した場合にも、情報の書き込み電流を最適条件にすることにより、正確に情報を記録することができるという効果がある。   As described above, according to the recording method of the nonvolatile magnetic thin film memory device of the present invention, even when the environmental temperature changes, information can be recorded accurately by setting the information write current to the optimum condition. There is an effect.

第1の実施例のトンネル磁気抵抗効果素子の構成要素である磁性膜の飽和磁化の温度変化を示す図である。It is a figure which shows the temperature change of the saturation magnetization of the magnetic film which is a component of the tunnel magnetoresistive effect element of 1st Example. 第1の実施例の磁性膜における保磁力の温度変化を示す図である。It is a figure which shows the temperature change of the coercive force in the magnetic film of a 1st Example. 第1の実施例の磁性層のスピンの状態を示す図である。It is a figure which shows the state of the spin of the magnetic layer of a 1st Example. 第2の実施例におけるMRAMの構成を示す簡略図である。It is a simplified diagram showing the configuration of the MRAM in the second embodiment. 第2の実施例におけるMRAMの環境温度の検出と最適記録条件で情報を記録する記録処理の流れを示すフローチャートである。It is a flowchart which shows the flow of the recording process which detects the environmental temperature of MRAM in a 2nd Example, and records information on optimal recording conditions. 環境温度の検出に用いる温度センサの構成を示す図である。It is a figure which shows the structure of the temperature sensor used for detection of environmental temperature. 温度センサで利用するゲート電極閾値電圧の温度依存性を示す図である。It is a figure which shows the temperature dependence of the gate electrode threshold voltage utilized with a temperature sensor. 第3の実施例におけるMRAMの構成を示す簡略図である。It is a simplified diagram showing the configuration of the MRAM in the third embodiment. 第3の実施例におけるMRAMの環境温度毎の最適記録条件で情報を記録する記録処理の流れを示すフローチャートである。It is a flowchart which shows the flow of the recording process which records information on the optimal recording conditions for every environmental temperature of MRAM in a 3rd Example. 試し書きトンネル磁気抵抗効果素子の構成を示す図である。It is a figure which shows the structure of a trial writing tunnel magnetoresistive effect element. 従来のトンネル磁気抵抗効果を利用した磁気薄膜メモリの一構成例を示す概略図である。It is the schematic which shows one structural example of the magnetic thin film memory using the conventional tunnel magnetoresistive effect. トンネル磁気抵抗効果素子に垂直磁化膜を用いた磁気薄膜メモリの一構成例を示す図である。It is a figure which shows one structural example of the magnetic thin film memory which used the perpendicular magnetization film for the tunnel magnetoresistive effect element.

以下、本発明の不揮発磁気メモリ装置の実施例を詳細に説明する。
(第1の実施例)
図1は第1の実施例のトンネル磁気抵抗効果素子の構成要素である磁性膜の飽和磁化の温度変化を示す図である。また、図2は第1の実施例の磁性膜における保磁力の温度変化を示す図である。
Hereinafter, embodiments of the nonvolatile magnetic memory device of the present invention will be described in detail.
(First embodiment)
FIG. 1 is a diagram showing a change in temperature of saturation magnetization of a magnetic film which is a component of the tunnel magnetoresistive effect element of the first embodiment. FIG. 2 is a graph showing a change in coercive force with temperature in the magnetic film of the first embodiment.

図1、図2に示された磁性膜は室温で印加磁界がない状態で垂直磁化膜となっている。希土類金属としてTb、遷移金属としてFe及びCoの合金薄膜を用いている。   The magnetic films shown in FIGS. 1 and 2 are perpendicularly magnetized films in the absence of an applied magnetic field at room temperature. An alloy thin film of Tb as the rare earth metal and Fe and Co as the transition metal is used.

図3に示すように本実施例の磁性層は、Tbの副格子磁化の向きと、Fe及びCoの副格子磁化の向きとは、室温で反平行状態で磁気的に結合している。   As shown in FIG. 3, in the magnetic layer of this example, the direction of the sublattice magnetization of Tb and the direction of the sublattice magnetization of Fe and Co are magnetically coupled in an antiparallel state at room temperature.

磁性層を昇温していくと、図1に示すようにTbの磁化の大きさと、Fe及びCoの磁化の大きさとが等しくなって打ち消しあう補償温度が存在し、さらに昇温していくと磁化が消失するキュリー温度が存在する。   As the temperature of the magnetic layer is increased, there is a compensation temperature in which the magnitude of the magnetization of Tb is equal to the magnitude of the magnetization of Fe and Co as shown in FIG. There is a Curie temperature at which the magnetization disappears.

本実施例では、補償温度が室温より高く、キュリー温度よりも低いような磁性膜を用いている。更に、補償温度が100[℃]以上であると好適である。このような条件を満たすように、TbFeCo合金薄膜の組成を調整することにより、図2に示すように動作温度−20[℃]〜100[℃]の範囲内で保磁力の変化量を10[Oe]以内に制御することができた。   In this embodiment, a magnetic film having a compensation temperature higher than room temperature and lower than the Curie temperature is used. Further, the compensation temperature is preferably 100 [° C.] or higher. By adjusting the composition of the TbFeCo alloy thin film so as to satisfy such a condition, the amount of change in coercive force is 10 [° C. within the operating temperature −20 [° C.] to 100 [° C.] as shown in FIG. Oe].

ここでは、TbFeCoのみを例としてあげたが、例えば保磁力の大きさを小さく制御したいような場合には、Gdを含むような磁性膜を用いればよく、その際にも組成や成膜条件によって、飽和磁化や保磁力の温度依存性を適宜制御すればよい。   Here, only TbFeCo is taken as an example. However, for example, when it is desired to control the magnitude of the coercive force small, a magnetic film containing Gd may be used. The temperature dependence of saturation magnetization and coercive force may be appropriately controlled.

また、遷移金属はNiを含んでもよく、希土類金属はDyを含んでもよい。これによっても、飽和磁化や保磁力の温度依存性を制御可能である。   Further, the transition metal may include Ni, and the rare earth metal may include Dy. This also makes it possible to control the temperature dependence of saturation magnetization and coercivity.

(第2の実施例)
本実施例では、MRAMのメモリセルアレイの端に、MOS−FETを設けて温度センサとする。
(Second embodiment)
In this embodiment, a MOS-FET is provided at the end of the memory cell array of the MRAM to form a temperature sensor.

図4は、第2の実施例におけるMRAMの構成を示す簡略図である。図5は第2の実施例におけるMRAMの環境温度の検出と最適記録条件で情報を記録する記録処理の流れを示すフローチャートである。図6は環境温度の検出に用いる温度センサの構成を示す図である。図7は温度センサで利用するゲート電極閾値電圧の温度依存性を示す図である。図7においては、例としてp−MOSを用いた場合の閾値電圧の温度依存性を示している。   FIG. 4 is a simplified diagram showing the configuration of the MRAM in the second embodiment. FIG. 5 is a flowchart showing a flow of a recording process for detecting the environmental temperature of the MRAM and recording information under the optimum recording conditions in the second embodiment. FIG. 6 is a diagram showing a configuration of a temperature sensor used for detecting the environmental temperature. FIG. 7 is a diagram showing the temperature dependence of the gate electrode threshold voltage used in the temperature sensor. FIG. 7 shows the temperature dependence of the threshold voltage when a p-MOS is used as an example.

図4に示すように本実施例におけるMRAMは、温度センサ46と、トンネル磁気抵抗効果素子41と、書き込み線42と、書き込み線用デコーダ44と、ビット線43と、ビット線用デコーダ45とを備えている。書き込み線42は、トンネル磁気抵抗効果素子に情報を書き込むためのものである。書き込み線用デコーダ44は、書き込み線42を制御する。ビット線43は、トンネル磁気抵抗効果素子の情報を読み出すためのものである。ビット線用デコーダ45はビット線43を制御する。   As shown in FIG. 4, the MRAM in this embodiment includes a temperature sensor 46, a tunnel magnetoresistive effect element 41, a write line 42, a write line decoder 44, a bit line 43, and a bit line decoder 45. I have. The write line 42 is for writing information to the tunnel magnetoresistive element. The write line decoder 44 controls the write line 42. The bit line 43 is for reading information of the tunnel magnetoresistive effect element. The bit line decoder 45 controls the bit line 43.

本実施例における温度センサ46は、トンネル磁気抵抗効果素子41下部に設けられたMOS−FETを利用する。   The temperature sensor 46 in this embodiment uses a MOS-FET provided under the tunnel magnetoresistive effect element 41.

図6に示すようにメモリセルアレイ64から領域を隔てたところに、余分にMOS−FETを設ける。本実施例では、このMOS−FETを温度センサ65として利用する。   As shown in FIG. 6, an extra MOS-FET is provided at a location separated from the memory cell array 64. In this embodiment, this MOS-FET is used as the temperature sensor 65.

図7に示すように、MOS−FETのゲート電極の閾値は温度による依存性を示す。   As shown in FIG. 7, the threshold value of the gate electrode of the MOS-FET shows dependence on temperature.

図6に示す温度センサ65の温度検知は、電界効果型トランジスタの構造をそのままにして、温度検知を行う。トランジスタの特性は温度に対して敏感に変化するために、この温度依存性を温度検知に利用でき、かつ、駆動用に設けたトランジスタと同一のプロセスで基板上に形成できるため、好適である。   The temperature detection of the temperature sensor 65 shown in FIG. 6 is performed with the structure of the field effect transistor as it is. Since the characteristics of the transistor change sensitively with respect to temperature, this temperature dependency can be used for temperature detection and can be formed on the substrate by the same process as the transistor provided for driving.

実際には、ゲート63のゲート電圧を上げなから、ソース61−ドレイン62間に電流を流す。ゲート電圧がしきい値電圧より高くなったときに、ソース61−ドレイン62間に電流が流れるので、そのときの電圧を読み取って動作温度を検知する。   Actually, since the gate voltage of the gate 63 is not increased, a current is passed between the source 61 and the drain 62. When the gate voltage becomes higher than the threshold voltage, a current flows between the source 61 and the drain 62, and the operating temperature is detected by reading the voltage at that time.

こうして、正規の情報書き込みを行う前に温度センサ65により環境温度を検出し、最適の書き込み電流で書き込みを行えば、動作温度の変化によるクロストークや書き込み不良などの問題を解決することができる。   In this way, if the ambient temperature is detected by the temperature sensor 65 before writing regular information and writing is performed with the optimum writing current, problems such as crosstalk and writing failure due to changes in the operating temperature can be solved.

また、図5に示すように、正規のデータ書き込みを行う前に、温度センサにより周囲温度を測定する(ステップS51)。さらにMOS−FETのゲート電極閾値の温度依存データが格納されている比較器内のデータと比較して最適書き込み電流値を検出する(ステップS52)。最適書き込み電流値は、トンネル磁気抵抗効果素子の保磁力の温度変化のデータと周囲温度とから得られる。トンネル磁気抵抗効果素子の保磁力の温度変化は、別に備えたデバイスに予め記録しておけばよい。   Further, as shown in FIG. 5, the ambient temperature is measured by the temperature sensor before the regular data is written (step S51). Further, the optimum write current value is detected by comparison with the data in the comparator in which the temperature-dependent data of the gate electrode threshold value of the MOS-FET is stored (step S52). The optimum write current value is obtained from the temperature change data of the coercive force of the tunnel magnetoresistive element and the ambient temperature. The temperature change of the coercive force of the tunnel magnetoresistive element may be recorded in advance in a separately provided device.

その後、書き込み電流値の制御を行って正規データの書き込みを行えば(ステップS53)、正常に書き込みができる。   After that, if normal data is written by controlling the write current value (step S53), the data can be written normally.

なお、本実施例では、MRAMにおける下部MOS−FET部のゲート電極の閾値電圧を温度センサとして利用しているが、ゲート電極、ドレイン電極、ソース電極の抵抗値の温度変化を利用して、温度センサとすることも可能である。   In this embodiment, the threshold voltage of the gate electrode of the lower MOS-FET portion in the MRAM is used as a temperature sensor, but the temperature change is made by using the temperature change of the resistance values of the gate electrode, the drain electrode, and the source electrode. It can also be a sensor.

更に、各ビット線、書き込み線ごとに温度センサを設けて温度を検知し、各カラムもしくはローごとに電流値を制御することも可能である。もちろん任意のエリアを設定して、各エリアごとに流す電流値を制御してもよい。   Further, it is possible to provide a temperature sensor for each bit line and write line to detect the temperature and control the current value for each column or row. Of course, an arbitrary area may be set to control the current value flowing for each area.

本実施例によれば、メモリセルアレイ内の温度変化を検知して、情報の記録を行なうので、温度変化による誤書き込みや書き込み不良を低減させることが可能となる。
(第3の実施例)
第3の実施例では、MRAMのメモリセルアレイのマージン領域のメモリセルを試し書きメモリセルとして試し書きを行うことにより、情報の書き込みを環境温度に合わせて段階的に制御するものである。すなわち、任意のメモリセルに、ある電流値で書き込みを行ない、記録の確認を行なった後に、情報の記録動作を開始する。試し書きの際に正常な記録動作が行なわれているかどうかを確認することによって、メモリセルの状況を判断することができる。
According to the present embodiment, since the temperature change in the memory cell array is detected and information is recorded, it is possible to reduce erroneous writing and writing failure due to the temperature change.
(Third embodiment)
In the third embodiment, information writing is controlled step by step according to the environmental temperature by performing test writing using the memory cells in the margin area of the memory cell array of the MRAM as test write memory cells. That is, information is written into an arbitrary memory cell with a certain current value, and after recording is confirmed, an information recording operation is started. The status of the memory cell can be determined by checking whether or not a normal recording operation is performed during the trial writing.

図8は、第3の実施例におけるMRAMの構成を示す簡略図である。図9は第3の実施例におけるMRAMの環境温度毎の最適記録条件で情報を記録する記録処理の流れを示すフローチャート、図10は試し書きトンネル磁気抵抗効果素子の構成を示す図である。   FIG. 8 is a simplified diagram showing the configuration of the MRAM in the third embodiment. FIG. 9 is a flowchart showing the flow of a recording process for recording information under the optimum recording conditions for each environmental temperature of the MRAM in the third embodiment, and FIG. 10 is a diagram showing the configuration of the trial write tunnel magnetoresistive element.

図8に示すように本実施例におけるMRAMは、試し書きメモリセル86と、トンネル磁気抵抗効果素子81と、書き込み線82と、書き込み線用デコーダ84と、ビット線83と、ビット線用デコーダ85とを備えている。トンネル磁気抵抗効果素子81には正規のデータが書き込まれる。書き込み線82は、トンネル磁気抵抗効果素子81に情報を書き込むためのものである。書き込み線用デコーダ84は書き込み線82を制御する。ビット線83は、トンネル磁気抵抗効果素子81の情報を読み出すためのものである。ビット線用デコーダ85はビット線83を制御する。本実施例では、正規データの書き込みの前に試し書き用メモリセル86にデータ書き込みを行い、正常に書き込みが行なわれているかを確認した後に正規のデータ書き込みを行う。   As shown in FIG. 8, the MRAM according to the present embodiment includes a test write memory cell 86, a tunnel magnetoresistive effect element 81, a write line 82, a write line decoder 84, a bit line 83, and a bit line decoder 85. And. Regular data is written in the tunnel magnetoresistive element 81. The write line 82 is for writing information to the tunnel magnetoresistive effect element 81. The write line decoder 84 controls the write line 82. The bit line 83 is for reading information from the tunnel magnetoresistive effect element 81. The bit line decoder 85 controls the bit line 83. In the present embodiment, data is written to the test write memory cell 86 before normal data is written, and normal data is written after confirming whether data is normally written.

図10に示すように、試し書き用トンネル磁気抵抗効果素子102を有する試し書きメモリセル86は正規データ用メモリセル101のマージン領域に設けられる。   As shown in FIG. 10, the test write memory cell 86 having the test write tunnel magnetoresistive element 102 is provided in the margin area of the normal data memory cell 101.

図9に示すように、先ず、マージン領域すなわち試し書きを行う領域の書き込み線デコーダをONにする(ステップS91)。次に、試し書き用メモリセル86に記録を行う(ステップS92)。次に、ステップS92で記録を行った試し書き用メモリセル86と、その試し書き用メモリセル86に隣接する試し書き用メモリセル86の再生を行い(ステップS93)、書き込み不良があったか否か確認する(ステップS94)。   As shown in FIG. 9, first, the write line decoder in the margin area, that is, the area where trial writing is performed is turned ON (step S91). Next, recording is performed in the test writing memory cell 86 (step S92). Next, the test write memory cell 86 recorded in step S92 and the test write memory cell 86 adjacent to the test write memory cell 86 are reproduced (step S93), and it is confirmed whether or not there is a write failure. (Step S94).

MRAMのように、マトリックス状にメモリセルが配置され、電流による磁界によって特定のメモリセルを選択して情報の記録を行なう場合には、書き込みを行なうべきメモリセルに隣接するメモリセルにまで磁界が印加されるのは免れない。そのため、温度変化などによって、磁性膜の保磁力が小さくなっていると、誤書き込みされる可能性が高くなる。したがって、記録の確認を行なう場合には、記録を行なう試し書き用メモリセルとそれに隣接するメモリセルの双方に誤書き込みされていないことを確認する必要がある。   When memory cells are arranged in a matrix like an MRAM and a specific memory cell is selected by a magnetic field caused by current and information is recorded, the magnetic field is applied to the memory cell adjacent to the memory cell to be written. It is inevitable that it is applied. Therefore, if the coercive force of the magnetic film is reduced due to a temperature change or the like, the possibility of erroneous writing increases. Therefore, when confirming the recording, it is necessary to confirm that no erroneous writing is performed in both the test writing memory cell for recording and the memory cell adjacent thereto.

書き込み不良があった場合には、書き込み電流値を変化させて、ステップS91に戻り、正常書き込みが確認できるまで同じ作業を繰り返す。   If there is a write failure, the write current value is changed, the process returns to step S91, and the same operation is repeated until normal writing is confirmed.

書き込み不良が無かった場合には、書き込み電流値を確定し(ステップS95)、正規データの書き込みを行う(ステップS96)。   If there is no write failure, the write current value is determined (step S95), and regular data is written (step S96).

以上のような情報の書き込みを行うことにより、正規データを正常に書き込むことができた。   By writing information as described above, normal data could be written normally.

41 トンネル磁気抵抗効果素子
42 書き込み線
43 ビット線
44 書き込み線用デコーダ
45 ビット線用デコーダ
61 ソース
62 ドレイン
63 ゲート
64 メモリセルアレイ
65 温度センサ
81 トンネル磁気抵抗効果素子
82 書き込み線
83 ビット線
84 書き込み線用デコーダ
85 ビット線用デコーダ
86 試し書き用メモリセル
S51〜S53、S91〜S96 ステップ
41 tunnel magnetoresistive effect element 42 write line 43 bit line 44 write line decoder 45 bit line decoder 61 source 62 drain 63 gate 64 memory cell array 65 temperature sensor 81 tunnel magnetoresistive effect element 82 write line 83 bit line 84 for write line Decoder 85 Decoder for bit line 86 Memory cell for trial writing S51 to S53, S91 to S96 Steps

Claims (3)

基板と、該基板上に磁気抵抗効果素子を有するメモリセルが二次元状に配されたメモリセルアレイと、を有する不揮発磁気薄膜メモリ装置の記録方法において、
情報の記録を行なう前に、メモリセルに情報の試し書きを行ない、試し書きの記録を確認した後、正規のデータを記録することを特徴とする不揮発磁気薄膜メモリ装置の記録方法。
In a recording method of a non-volatile magnetic thin film memory device having a substrate and a memory cell array in which memory cells having magnetoresistive elements are two-dimensionally arranged on the substrate,
A recording method for a non-volatile magnetic thin film memory device, wherein, before performing information recording, trial writing of information is performed in a memory cell, and after recording of the trial writing is confirmed, regular data is recorded.
情報の試し書きは、試し書きに専ら用いられる試し書きメモリセルに対して行うことを特徴とする請求項1記載の不揮発磁気薄膜メモリ装置の記録方法。   2. The recording method for a nonvolatile magnetic thin film memory device according to claim 1, wherein the trial writing of information is performed on a trial writing memory cell used exclusively for the trial writing. 試し書きの記録を確認する際に、試し書きしたメモリセルに隣接するメモリセルの情報も同様に記録を確認することを特徴とする請求項1又は2のいずれかに記載の不揮発磁気薄膜メモリ装置の記録方法。   3. The nonvolatile magnetic thin film memory device according to claim 1, wherein when confirming the record of the test writing, the information of the memory cell adjacent to the test-written memory cell is also confirmed. Recording method.
JP2011067330A 2011-03-25 2011-03-25 Recording method for nonvolatile magnetic thin film memory device and nonvolatile thin film memory Expired - Fee Related JP5188590B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011067330A JP5188590B2 (en) 2011-03-25 2011-03-25 Recording method for nonvolatile magnetic thin film memory device and nonvolatile thin film memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011067330A JP5188590B2 (en) 2011-03-25 2011-03-25 Recording method for nonvolatile magnetic thin film memory device and nonvolatile thin film memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2008040090A Division JP4739360B2 (en) 2008-02-21 2008-02-21 Nonvolatile magnetic thin film memory device

Publications (2)

Publication Number Publication Date
JP2011170961A true JP2011170961A (en) 2011-09-01
JP5188590B2 JP5188590B2 (en) 2013-04-24

Family

ID=44684910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011067330A Expired - Fee Related JP5188590B2 (en) 2011-03-25 2011-03-25 Recording method for nonvolatile magnetic thin film memory device and nonvolatile thin film memory

Country Status (1)

Country Link
JP (1) JP5188590B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257167B2 (en) 2014-03-13 2016-02-09 Katsuyuki Fujita Resistance change memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05314780A (en) * 1992-05-08 1993-11-26 Toshiba Corp Data writing device for memory
JPH113585A (en) * 1997-06-12 1999-01-06 Canon Inc Magnetic thin film memory element and its recording and reproducing method
JP2001202800A (en) * 2000-01-19 2001-07-27 Oki Electric Ind Co Ltd Non-volatile semiconductor memory
JP2002197852A (en) * 2000-12-25 2002-07-12 Mitsubishi Electric Corp Thin film magnetic substance storage device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05314780A (en) * 1992-05-08 1993-11-26 Toshiba Corp Data writing device for memory
JPH113585A (en) * 1997-06-12 1999-01-06 Canon Inc Magnetic thin film memory element and its recording and reproducing method
JP2001202800A (en) * 2000-01-19 2001-07-27 Oki Electric Ind Co Ltd Non-volatile semiconductor memory
JP2002197852A (en) * 2000-12-25 2002-07-12 Mitsubishi Electric Corp Thin film magnetic substance storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257167B2 (en) 2014-03-13 2016-02-09 Katsuyuki Fujita Resistance change memory
US9589621B2 (en) 2014-03-13 2017-03-07 Kabushiki Kaisha Toshiba Resistance change memory

Also Published As

Publication number Publication date
JP5188590B2 (en) 2013-04-24

Similar Documents

Publication Publication Date Title
TWI622049B (en) Magnetic memory
US6436526B1 (en) Magneto-resistance effect element, magneto-resistance effect memory cell, MRAM and method for performing information write to or read from the magneto-resistance effect memory cell
US6621731B2 (en) Magnetic memory device
JP3667244B2 (en) Magnetoresistive element, memory element using the same, magnetic random access memory, and method for recording / reproducing magnetic random access memory
JP2002314164A (en) Magnetic tunnel element and its manufacturing method, thin film magnetic head, magnetic memory and magnetic sensor
EP2232495A1 (en) Magnetic memory with a thermally assisted writing procedure
US8809978B2 (en) Magnetic memory element and memory apparatus having multiple magnetization directions
JP5152672B2 (en) Magnetic random access memory and operation method thereof
JP4666775B2 (en) Magnetic thin film memory device, magnetic thin film memory, and information recording method
JP4739360B2 (en) Nonvolatile magnetic thin film memory device
KR101586271B1 (en) Magnetic random access memory device and Data writing and reading method of the Same
JP4100892B2 (en) Nonvolatile magnetic thin film memory device
JP5356377B2 (en) Magnetic memory cell and magnetic random access memory
US7466585B2 (en) Magnetic random access memory
JPWO2007111318A1 (en) Magnetic random access memory and operation method thereof
JP5188590B2 (en) Recording method for nonvolatile magnetic thin film memory device and nonvolatile thin film memory
US20120281463A1 (en) Magnetoresistive effect element, and magnetic random access memory
JP2011119537A (en) Memory cell, and magnetic random access memory
JP2002208680A (en) Magnetic thin-film memory element, magnetic thin-film memory, and information recording and reproducing method
JP3658331B2 (en) Recording / reproducing method of memory element, magnetoresistive element, and magnetic random access memory
JP2002353418A (en) Magnetoresistive effect element and magnetic memory device
JP4626149B2 (en) Magnetic memory initialization method
JP2009176806A (en) Nonvolatile magnetic memory element
KR20090105788A (en) Magnetic random access memory device and Data writing and reading method of the Same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110325

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121023

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121220

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130115

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130122

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160201

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 5188590

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160201

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees