JP2001202800A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an one time PROM in which there is not the possibility of that data is written in a main memory cell at the time of test. SOLUTION: This ROM is provided with a main memory cell 101, and a spare memory cell 102 for test. When an address An is in a low level or a high level, a HV detecting circuit 111 judges that the main memory cell 101 is selected, when it is in a HV level, the circuit 111 judges that the spare memory cell 102 is selected. A signal generating circuit 113 inputs control signals CEB, OEB and VPPHB and an HV detecting signal. The signal generating circuit 113 generates a write-in mode signal when a control signal is a write-in mode and a HV detecting signal is the main memory cell 101 and when a control signal is write-in standby mode and the HV detecting signal is the spare memory cell 102. Drivers 103, 114, 105 input a write-in mode signal, and perform write-in control for the memory cells 101, 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a nonvolatile semiconductor memory having a spare memory cell for performing a write operation test.

[0002]

2. Description of the Related Art Conventional non-volatile semiconductor memories include:
OTPROM (One Time Programmable Read Only Memor
This is explained using y) as an example.

Conventionally, EPROM (Erasable Programmable
An OTPROM is known as a kind of “able read only memory”. The OTPROM uses a memory element capable of erasing data by irradiating ultraviolet rays, like a general EPROM. However, OTPR
Since the OM is sealed in a package without an ultraviolet irradiation window, once the package is packaged, the data once written cannot be rewritten or erased.

For this reason, the OTPROM is required at the final stage of manufacturing.
When the write operation test is performed, a spare memory cell used only for the operation test may be provided separately from the present memory cell. That is, by providing a spare memory cell, a write operation test can be performed after packaging.

FIG. 4 is a block diagram showing an example of a configuration of a main part of a conventional OTPROM.

[0006] As shown in FIG.
00 has a main memory cell 401 and a spare memory cell 402. Each of the main memory cell 401 and the spare memory cell 402 has a word line, a drain line, and a bit line (not shown). Generally, a transistor having a floating gate structure is used as a memory element (not shown) in the main memory cell 401 and the spare memory cell 402.

When writing / reading the memory cell 401, the word line driver 403 selects one of the word lines (not shown) based on the address signals A0 to Am, and the drain line driver 414 selects one of the drain lines. A line (not shown) is selected, and the bit line driver 404 and the multiplexer 408 select any bit line (not shown). Then, the memory cell 401 is selected according to the selected word line and drain line.
Is specified, and any of the memory elements in the block is specified by the selected bit line. The address signals A0 to Am are input via an address buffer 406.

On the other hand, at the time of writing / reading to / from the spare memory cell 402, the spare cell driver 405 selects one of the word lines and the drain line driver 414 selects one of the drain lines based on the address signals A0 to Am. Then, the bit line driver 404 and the multiplexer 408 select one of the bit lines.
Thereby, the memory element is specified. Then, the spare cell driver 405 inputs the address signals A0 to Am via the spare cell buffer 407.

Sense amplifier 409 and output buffer 4
Numeral 10 amplifies and outputs the data read on the bit line.

The main memory cell 401 and the spare memory cell 40
The selection of 2 is made by the potential of the n-th address signal An. When the address signal An is at a high level or a low level, this memory cell is selected and the address signal A
When n is at the HV (High Voltage) level (potential higher than the high level), the spare memory cell is selected. When the address signal An is at the HV level, the HV detection circuit 411 sends a signal to the spare cell buffer 407 indicating that the spare memory cell 402 has been selected.

The write mode signal generation circuit 413 includes a chip enable signal CEB and an output enable signal OEB.
And whether or not the mode is the write mode, based on the Vpp detection signal VPPHB and the driver 40
3, 405, 414 and the sense amplifier 409.
Here, the Vpp detection signal VPPHB is applied to the Vpp terminal (supply terminal of the voltage applied to the word line and the drain line) by Vcc
This signal indicates whether a higher voltage is applied or a voltage lower than Vcc is applied. When a transistor having a floating gate structure is used as a memory element, the voltage of the word line and the drain line at the time of reading is higher than that of the transistor.
It is necessary to increase the word line / drain line voltage at the time of writing. In the OTPROM 400 of FIG. 4, the word line and the drain line at the time of reading are each set to Vcc, and the word line and the drain line at the time of writing are set to Vpp.

FIG. 5 shows a write mode signal generation circuit 41.
3 is a logic circuit showing an example of the internal configuration of the third embodiment. Also, FIG.
OTPROM 400 mode and control signals CEB, OE
6 shows the relationship with the signal values of B, VPPHB, and An.

The chip enable signal CEB and the output enable signal OEB are both negative logic. The Vpp detection signal VPPHB goes high when the voltage is lower than Vcc, and goes low when the voltage is Vpp. As described above, when the address signal An is at the high level or the low level, it indicates that the present memory cell is selected, and when it is at the HV level, it indicates that the spare memory cell is selected. .

As shown in FIG. 5, NOR gate 502
Are the chip enable signal CEB and the Vpp detection signal V
PPHB is input, and an output enable signal OEB is input via a NOT gate 501. And N
The output of the OR gate 502 is inverted by the NOT gate 503 and becomes the output mode signal PGMYB.

In FIG. 6, a read mode is a mode of a read operation state, a standby mode is a mode of a read operation standby state, and a program mode is a memory cell 401 of the present embodiment.
And the program inhibit mode is a mode in a write operation standby state.
The special mode is a mode of a write operation state for the spare memory cell 402, that is, a mode of a write operation test.

As can be seen from FIGS. 5 and 6, the write mode signal PGMYB goes low when the chip enable signal CEB is low, the output enable signal OEB is high, and the Vpp detection signal VPPHB is low. In other cases, the level is high. That is, in the OTPROM 400, writing (program mode) to the main memory cell 401 and the spare memory cell 402
Writing (special mode) differs from that of the other signals CEB, OEB and VPPHB only in the value of the address signal An.
Are the same. Then, whether the write destination is the main memory cell 401 or the spare memory cell 402 is specified based on the detection result of the HV detection circuit 411.

[0017]

As described above, only the potential of the address signal An differs between the program mode and the special mode.

However, in the conventional OTPROM, even though the address signal An is set at the HV level, the level may be high or low due to the influence of noise or malfunction of the measuring instrument. For this reason, in the conventional OTPROM, data may be written to the main memory cell 401 in spite of an attempt to write data to the spare memory cell 402. If data is written to the memory cell 401 in the special mode, that is, during the write operation test, the OTPROM cannot be shipped.

Also, when a variation occurs in the threshold value of the HV detection circuit 405 due to manufacturing variations in the wafer process, the high level or the low level regardless of the address signal An being at the HV level. There is a case where it is determined that the level. Also in this case, OTPR
The OM cannot be shipped because data is written in the memory cell 401.

In particular, in recent years, with the miniaturization of integrated circuits, the breakdown voltage and the signal voltage have been reduced.
For this reason, erroneous writing as described above may further increase.

Therefore, there has been a demand for a non-volatile semiconductor memory which does not have a risk of erroneously recognizing the special mode as the program mode and writing data in the memory cell.

[0022]

A nonvolatile semiconductor memory according to the present invention receives a main memory cell for storing main data, a spare memory cell for performing a write operation test, and a memory cell selection signal. A signal level detector for determining whether the present memory cell is selected or a spare memory cell is selected; a control signal including at least a chip enable signal and an output enable signal; and a detection result of the signal level detector. The case where the logical value of the control signal indicates the write mode and the detection result indicates the selection of the present memory cell, and the case where the logical value of the control signal indicates the specific non-write mode and the detection result indicates the selection of the spare memory cell. And a write mode signal generator for generating a write mode signal and a write mode signal And a driver unit that controls writing to Le and spare memory cell.

According to the present invention, when the logical value of the control signal indicates a specific non-write mode and the detection result of the write destination detecting section indicates the write to the spare memory cell, the write to the spare memory cell is performed. I decided to do it,
Even if the potential of the n-th bit address signal is erroneously recognized, writing to this memory cell is not performed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory according to an embodiment of the present invention will be described below with reference to the drawings, taking an OTPROM as an example. In the drawings, the size, shape, and arrangement of each component are only schematically shown to an extent that the present invention can be understood, and numerical conditions described below are merely examples. .

FIG. 1 shows an OTPRO according to this embodiment.
FIG. 3 is a block diagram schematically showing a configuration of a main part of M.

In the OTPROM 100 shown in FIG. 1, the main memory cell 101 is a memory cell for storing main data, that is, user data. As a storage element of the memory cell 101, for example, a transistor having a floating gate structure is used.

The spare memory cell 102 is a memory cell for performing a write operation test. Spare memory cell 10
As the second storage element, for example, a transistor having a floating gate structure is used.

The word line driver 103 inputs the row address portions of the address signals A0 to Am from an address buffer 106 (described later). Then, a word line (not shown) corresponding to the row address is selected. When the write mode signal PGMYB is at a low level, a write operation (program mode) is established, and the voltage Vpp is applied to the selected word line. On the other hand, when the write mode signal PGMYB is at a high level, a read operation (read mode) is established, and the voltage V is applied to the selected word line.
cc is applied.

The bit line driver 104 inputs a part of the column address of the address signals A0 to Am from an address buffer 106 (described later). Then, a selection signal for selecting a bit line (not shown) corresponding to the column address is output to multiplexer 108.

The drain line driver 114 receives the rest of the address signals A0 to Am from the address buffer 106 (described later). Then, a drain line (not shown) corresponding to this address is selected. A drain voltage is applied to the drain line selected by the drain line driver 114 by a drain voltage generation circuit (not shown). The drain voltage is set to an optimized intermediate voltage between the voltage Vpp and the voltage Vcc in the case of a write operation (program mode). In the case of a read operation (read mode), the drain voltage is set to an optimized intermediate voltage between the voltage Vcc and the low level.

The spare cell driver 105 notifies the HV detection circuit 11 that the HV level has been applied to the address signal An.
1 is detected, the spare cell buffer 107
(Described later), the row address portions of the address signals A0 to Am are input. Then, a word line (not shown) corresponding to the row address is selected. Spare cell driver 105
Is used in special mode. Spare cell driver 105
Write mode signal PGMY
The voltage Vpp is applied when B is at a low level, and the voltage Vcc is applied when the write mode signal PGMYB is at a high level.

The address buffer 106 receives address signals A0 to Am. Then, the HV detection circuit 111
When the detection result (described later) is at a low level or a high level, when the chip enable signal CEB is at a low level, these address signals A0 to Am are applied to the word line driver 103, the bit line driver 104, and the drain line driver 114. Output to On the other hand, when the detection result of the HV detection circuit 111 (described later) is at the HV level, when the chip enable signal CEB is at the low level, the column address portions of these address signals A0 to Am are transferred to the bit line driver 104 and the drain. Output to the line driver 114.

The spare cell buffer 107 is used when the detection result of the HV detection circuit 111 (described later) is at the HV level.
The row address portion of the address signals A0 to Am is input.
When the chip enable signal CEB is at a low level, the row address is output to the spare cell driver 105.

The multiplexer 108 receives a selection signal from the bit line driver 104 and selects a bit line (not shown) corresponding to the selection signal.

When the chip enable signal CEB is at a low level, the sense amplifier 109 amplifies and outputs the data D0 to Dn read on the bit lines.

Output buffer 110 outputs data D0 to Dn amplified by sense amplifier 109 when output enable signal OEB is at a low level.

The HV detection circuit 111 outputs the address signal An
To detect the signal potential of the address signal An, and output the detection result as an HV detection signal AnH. Here, when the address signal An is at low level or high level, the HV detection signal AnH is at low level, and when the address signal An is at HV level, the HV detection signal An is
H goes high. The low level of the HV detection signal AnH indicates that the present memory cell 101 has been selected, and the high level of the HV detection signal AnH indicates that the spare memory cell 102 has been selected.

The control signal buffer 112 includes a chip enable signal CEB, an output enable signal OEB and Vpp
The detection signal VPPHB is input and sent to a write mode signal generation circuit 113 (described later) and the like.

The write mode signal generation circuit 113
The HV detection signal AnH is input from the V detection circuit 111, and the chip enable signal CEB, the output enable signal OEB, and the Vpp detection signal VPPHB are input from the control signal buffer 112. Then, these signals An
The mode is determined using H, CEB, OEB, and VPPHB, and the result of the determination is output as a write mode signal PGMYB. As described later, the write mode signal PG
MYB is at the low level when the mode is the write mode (that is, the program mode or the special mode of the memory cell 101), and is at the high level when the mode is another mode.

FIG. 2 shows the write mode signal generation circuit 11
FIG. 3 is a logic circuit diagram showing an internal configuration of No. 3; Also, FIG.
The mode of the OTPROM 100 and the control signals CEB, OE
B, VPPHB, and the relationship with the signal value of the HV detection signal AnH are shown.

As in the conventional OTPROM 400 (see FIG. 4), the chip enable signal CEB and the output enable signal OEB are both negative logic. The Vpp detection signal VPPHB is at a high level when the voltage is equal to or lower than Vcc, and is at a low level when the voltage is Vpp. Furthermore, H
As described above, the low level of the V detection signal AnH indicates the selection of the main memory cell 101, and the high level indicates the selection of the spare memory cell 102.

Write mode signal generating circuit 113 in FIG.
, The NOT gate 201 outputs an inverted value of the output enable signal OEB. The NOR gate 202
The output signal of the OT gate 201 is input, and the signals AnH, CEB, and VPPHB are input. Also, NOT
Gate 203 outputs an inverted value of Vpp detection signal VPPHB. NAND gate 204 is NOT gate 203
And output signals AnH, OEB,
Enter CEB. NOT gate 205 outputs the inverted value of NAND gate 204. Further, the NOR gate 206 receives the output signal of the NOR gate 202 and the NOT signal.
The output signal of the gate 205 is input, and the write mode signal PGMYB is output.

The mode employed in this embodiment is the same as that of the conventional OTPROM 400. That is,
In FIG. 3, the read mode is a read operation mode, the standby mode is a read operation standby mode, the program mode is a write operation mode for the memory cell 101, and the program inhibit mode is a write operation standby mode. The special mode is a mode of a write operation state for the spare memory cell 102, that is, a mode of a write operation test.

As can be seen from FIG. 2, the write mode signal PGMYB becomes low level when the NOR gate 20
2 is at a high level and when the NAND gate 204 is at a low level. Here, the NOR gate 202 goes high because the chip enable signal CEB is low, the output enable signal OEB is high,
This is when the Vpp detection signal VPPHB is at the low level and the HV detection signal AnH is at the low level, which corresponds to the program mode (see FIG. 3). The NAND gate 204 goes low when the chip enable signal CEB is high, the output enable signal OEB is high,
This is when the Vpp detection signal VPPHB is at the low level and the HV detection signal AnH is at the high level, and corresponds to the special mode (see FIG. 3).

That is, the OTPR according to this embodiment
In the OM 100, the logic of the control signals CEB, OEB and VPPHB when the special mode is selected is determined by the control signals CEB and CEB when the program inhibit mode is selected.
It matches the logic of OEB and VPPHB. For this reason, when the HV detection signal AnH goes low even though the address signal An is set at the HV level (when the address signal An goes high or low due to noise or the like, When an error occurs in the threshold value of the circuit 111), the OTPROM 100
Goes into the program inhibit mode. Therefore, no data is written to the memory cell 101.

In this embodiment, the present invention is applied to the OT
Although the case where the present invention is applied to the PROM has been described as an example, the present invention can be applied to other nonvolatile semiconductor memories.

In this embodiment, the control signal logic of the special mode is made to match the control signal logic of the program inhibit mode. However, the mode that matches the special mode may be any mode other than the program mode.

In this embodiment, the selected memory cell (main memory cell 101 or spare memory cell 102)
Is specified by the address signal An, but may be specified by using another signal. Further, a signal terminal for selecting a memory cell may be separately received.

[0049]

As described above in detail, according to the present invention, it is possible to provide a nonvolatile semiconductor memory which does not have a possibility of writing data to the present memory cell during a write operation test.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a nonvolatile semiconductor memory according to an embodiment;

FIG. 2 is a logic circuit diagram showing an internal configuration of a write mode signal generation circuit shown in FIG.

FIG. 3 is a diagram showing a relationship between modes of the nonvolatile semiconductor memory according to the embodiment and signal values of respective control signals.

FIG. 4 is a block diagram showing a main part configuration of a conventional nonvolatile semiconductor memory.

FIG. 5 is a logic circuit diagram showing an internal configuration of the write mode signal generation circuit shown in FIG.

FIG. 6 is a diagram showing a relationship between modes of a conventional nonvolatile semiconductor memory and signal values of respective control signals.

[Explanation of symbols]

 101 Main Memory Cell 102 Spare Memory Cell 103 Word Line Driver 104 Bit Line Driver 105 Spare Cell Driver 106 Address Buffer 107 Spare Cell Buffer 108 Multiplexer 109 Sense Amplifier 110 Output Buffer 111 HV Detection Circuit 112 Control Signal Buffer 113 Write Mode Signal Generation Circuit 114 Drain line driver 201, 203, 205 NOT gate 202 NOR gate 204 NAND gate 206 NOR gate

Claims (4)

[Claims] 1. A main memory cell for storing main data, a spare memory cell for performing a write operation test, and a memory cell selection signal being input to determine whether the main memory cell is selected or the spare memory A signal level detection unit for determining whether a cell is selected; a control signal including at least a chip enable signal and an output enable signal; and a detection result of the signal level detection unit, and a logic value of the control signal indicating a write mode. And the detection result indicates the selection of the main memory cell, and the case where the logical value of the control signal indicates a specific non-write mode and the detection result indicates the selection of the spare memory cell A write mode signal generating unit for generating a write mode signal; and And a nonvolatile semiconductor memory comprising: a, a driver unit which controls writing into the spare memory cell. 2. The nonvolatile semiconductor memory according to claim 1, wherein said control signal includes a signal indicating whether a voltage applied to a word line and a bit line is a write voltage or a read voltage. . 3. The nonvolatile semiconductor memory according to claim 1, wherein the storage elements of the main memory cell and the spare memory cell include a transistor having a floating gate. 4. The memory cell selection signal is an n-th bit address signal. When the address signal is at a first level or a second level, it is determined that the present memory cell has been selected, and the n-th bit is selected. Bit address signal is 3rd
4. The nonvolatile semiconductor memory according to claim 1, wherein it is determined that the spare memory cell is selected when the level is at the level.