JP2011154392A - Display controller, display system, and display control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display controller, a display system, and a display control method, attaining a desired gradation expression by allowing delicate gamma correction. <P>SOLUTION: The display controller 540 includes: a GCLK generation section 100 as a gradation clock generation unit which generates, within a prescribed period of time starting from a reference timing, a gradation clock having first to N-th (N is an integer of 2 or more) gradation pulses; a gradation pulse clock selection register 122 which specifies a reference clock for specifying, from a plurality of clocks having different frequencies, respective gradation pulses of the first to N-th gradation pulses; and gradation pulse setting register groups 120-1 to 120-N for setting each gradation pulse edge of the gradation pulses of the first to the N-th gradation pulses. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display controller, a display system, and a display control method.

  In recent years, display devices using EL (electroluminescence) elements have attracted attention. In particular, an organic EL panel having an EL element formed of a thin film of an organic material is a self-luminous type, so that a backlight is not required and a wide viewing angle is realized. In addition, since it has a higher response speed than a liquid crystal panel, a color moving image display can be easily realized with a simple configuration.

  Such an organic EL panel is classified into a simple matrix type and an active matrix type similarly to the liquid crystal panel. When driving a simple matrix type organic EL panel, gradation control can be performed by pulse width modulation (hereinafter abbreviated as PWM).

Japanese Patent Laid-Open No. 11-73159

  However, the manufacturing technology of the organic EL panel is not mature as compared with the manufacturing technology of the liquid crystal panel, and the manufacturing variation is large. Therefore, so-called gradation characteristics vary. Therefore, unlike the driving of the liquid crystal panel, it is often impossible to realize a desired gradation expression even by performing gradation control by PWM.

  On the other hand, there is a strong market demand for high-definition gradation expression, and it is necessary to increase the number of gradations and to set each gradation finely. When gradation control is performed by PWM, a PWM signal having a pulse width corresponding to gradation data is generated as a drive signal. However, the increase in the number of gradations increases the number of gradation clock pulses, and in order to set each gradation finely, the number of circuits required for setting the gradation clock pulses is increased.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a display controller, a display system, and a display control capable of fine gamma correction and realizing a desired gradation expression. It is to provide a method.

  Another object of the present invention is to provide a display controller, a display system, and a display control method capable of contributing to high-definition gradation expression by increasing the number of gradations while suppressing an increase in circuit scale.

  Still another object of the present invention is to provide a display controller, a display system, and a display control method capable of finely setting gradations while suppressing an increase in circuit scale.

In order to solve the above problems, the present invention
A display controller that outputs a gradation clock for specifying a changing point of a pulse width modulation signal,
A gray scale clock generating section for generating a gray scale clock having first to Nth (N is an integer of 2 or more) gray scale pulses within a predetermined period starting from a reference timing;
A grayscale pulse clock selection register for designating a reference clock for designating each grayscale pulse of the first to Nth grayscale pulses from a plurality of clocks having different frequencies;
A gradation pulse setting register group for setting an edge of each gradation pulse of the first to Nth gradation pulses;
The gradation clock generator is
Using the reference clock as a unit, the interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) th (2 ≦ i ≦ N, i is an integer) gradation pulse and the first gradation pulse. The present invention relates to a display controller that sets the interval between i and the edge of the gradation pulse based on the setting value of each register of the gradation pulse setting register group.

  According to the present invention, the timing of the edge of each gradation pulse of the gradation clock for specifying the changing point of the pulse width modulation signal can be set individually. Therefore, fine gamma correction can be realized. In addition, since the frequency of the reference clock, which is the unit for setting the edge of each gradation pulse, can be varied, when performing gamma correction with high accuracy, each gradation can be set more finely and gamma correction accuracy is required. If not, each gradation can be set with a low-frequency gold life lock.

The present invention also provides
A display controller that outputs a gradation clock for specifying a changing point of a pulse width modulation signal,
A gray scale clock generating section for generating a gray scale clock having first to Nth (N is an integer of 2 or more) gray scale pulses within a predetermined period starting from a reference timing;
One gradation pulse among pth (1 ≦ p <N, p is an integer) to qth (p <q ≦ N, q is an integer) gradation pulses of the first to Nth gradation pulses. A boundary specification register to specify,
A gradation pulse setting register group for setting an edge of each gradation pulse of the first to Nth gradation pulses;
The gradation clock generator is
The interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse Is set based on the setting value of each register of the gradation pulse setting register group,
The edge interval of each gradation pulse from the p-th gradation pulse to the gradation pulse designated by the boundary designation register is set in units of a first clock and designated by the boundary designation register. The present invention relates to a display controller that sets the interval between the edges of each gradation pulse from the gradation pulse to the qth gradation pulse in units of a second clock.

In the display controller according to the present invention,
When the boundary of the first to Nth gradation pulses is designated by the boundary designation register,
A gradation pulse clock selection register for designating the first or second clock from a plurality of clocks having different frequencies;
The gradation clock generator is
The edge interval of each gradation pulse from the first gradation pulse to the gradation pulse designated by the boundary designation register is set in units of the first clock and designated by the boundary designation register. The interval between the edges of each gradation pulse from the gradation pulse to the Nth gradation pulse can be set in units of the second clock.

  In any one of the above inventions, the interval between the grayscale pulse edges of the grayscale clock set in the horizontal display period is set in the second clock unit and then in the first clock unit. . Therefore, in the range where the pulse width of the pulse width modulation signal is small, the pulse width of the pulse width modulation signal can be determined in units of the first clock. Further, in the range where the pulse width of the pulse width modulation signal is large, the pulse width of the pulse width modulation signal can be determined in units of the second clock.

  As a result, the interval between the edges of the grayscale pulse can be set in units of reference clocks with different frequencies between the high luminance range and the low luminance range, so that the frequency of the reference clock is increased only in the luminance range that needs to be set finely. The frequency of the reference clock can be lowered in the luminance range where it is not necessary. Therefore, high-precision gamma correction according to so-called gradation characteristics can be realized while suppressing an increase in circuit scale.

The present invention also provides
A display controller that outputs a gradation clock for specifying a changing point of a pulse width modulation signal,
A gray scale clock having first to Nth (N is an integer of 2 or more) grayscale pulses or first to Mth (M> N, M is an integer) is generated within a predetermined period starting from a reference timing. A gradation clock generator to
A gradation number selection register for designating the first or second gradation number;
First to Nth gradation pulse setting registers for setting the edge of each gradation pulse of the N gradation pulses of the gradation clock;
When the first gradation number is designated by the gradation number selection register,
The gradation clock generator is
The interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse Is set based on the set value of the first to Nth gradation pulse setting registers,
When the second gradation number is designated by the gradation number selection register,
The gradation clock generator is
At least two of the interval between the reference timing and the edge of the first gradation pulse and the interval between the (j−1) th (2 ≦ j ≦ M, j is an integer) and the edge of the jth gradation pulse The present invention relates to a display controller that sets an interval based on a setting value of one gradation pulse setting register of the first to Nth gradation pulse setting registers.

  According to the present invention, when the number of gradations is changed (increased), at least two gradation pulse edges can be set by one gradation pulse setting register. Therefore, it is not necessary to provide a gradation pulse setting register for each gradation pulse in order to realize fine gamma correction, and an increase in circuit scale can be prevented.

In the display controller according to the present invention,
A boundary designation register for designating one of the first to Nth gradation pulses or one of the first to Mth gradation pulses;
The gradation clock generator is
The edge interval of each gradation pulse from the first gradation pulse to the gradation pulse designated by the boundary designation register is set in units of the first clock, and the level designated by the boundary designation register is set. The interval between the edges of each gradation pulse from the adjustment pulse to the Nth or Mth gradation pulse can be set in units of the second clock.

In the display controller according to the present invention,
When the gradation clock has gradation pulses in order from the first gradation pulse starting from the reference timing,
The frequency of the first clock may be higher than the frequency of the second clock.

In the display controller according to the present invention,
The first clock is a system clock;
The second clock may be a dot clock obtained by dividing the system clock.

  According to any one of the above inventions, the interval between gradation pulses can be set in units of the second clock having a low frequency within a high luminance range. The circuit scale can be reduced.

The present invention also provides
A plurality of scan lines;
Multiple data lines,
A display panel in which each electroluminescent element includes a plurality of electroluminescent elements specified by any one of the plurality of scanning lines and any one of the plurality of data lines;
A scan driver for scanning the plurality of scan lines;
A data driver that drives the plurality of data lines based on a pulse width modulation signal that is pulse width modulated using gradation data;
Including any of the display controllers described above,
The display controller is
Supplying the gradation clock to the data driver;
The data driver is
The present invention relates to a display system that generates the pulse width modulation signal having a pulse width corresponding to the period of the number of grayscale clocks corresponding to the grayscale data, and drives each data line based on the pulse width modulation signal. To do.

  According to the present invention, it is possible to provide a display system including a display controller that enables fine gamma correction and realizes desired gradation expression.

  According to the present invention, it is possible to provide a display system including a display controller that contributes to high-definition gradation expression by increasing the number of gradations while suppressing an increase in circuit scale.

  Furthermore, according to the present invention, it is possible to provide a display system including a display controller capable of finely setting gradations while suppressing an increase in circuit scale.

The present invention also provides
A display control method based on a pulse width modulation signal whose change point is specified by a gradation clock,
Designating a reference clock for designating each gradation pulse of the first to Nth gradation pulses within a predetermined period starting from the reference timing, from among a plurality of clocks having different frequencies,
Using the reference clock as a unit, the interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) th (2 ≦ i ≦ N, i is an integer) gradation pulse and the first gradation pulse. set the interval between the edge of the gradation pulse of i and generate the gradation clock;
Display control method for generating pulse width modulation signal having a pulse width corresponding to a period of the number of grayscale clocks corresponding to grayscale data and driving data lines of a display panel based on the pulse width modulation signal Related to.

The present invention also provides
A display control method based on a pulse width modulation signal whose change point is specified by a gradation clock,
The p-th (1 ≦ p <N, p is an integer) to q-th (g) of the grayscale clock having the first to Nth (N is an integer of 2 or more) grayscale pulses within a predetermined period starting from the reference timing. p <q ≦ N, q is an integer) and designates one gradation pulse,
The interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse To generate the gradation clock,
Generating the pulse width modulation signal having a pulse width corresponding to a period of the number of clocks of the gradation clock corresponding to the gradation data, and driving the data lines of the display panel based on the pulse width modulation signal;
The edge interval of each gradation pulse from the p-th gradation pulse to the gradation pulse designated by the boundary designation register is set in units of a first clock and designated by the boundary designation register. The present invention relates to a display control method in which the interval between the edges of each gradation pulse from the gradation pulse to the qth gradation pulse is set in units of a second clock.

In the display control method according to the present invention,
When the gradation clock has gradation pulses in order from the first gradation pulse starting from the reference timing,
The frequency of the first clock may be higher than the frequency of the second clock.

In the display control method according to the present invention,
The first clock is a system clock;
The second clock may be a dot clock obtained by dividing the system clock.

The present invention also provides
A display control method based on a pulse width modulation signal whose change point is specified by a gradation clock,
Specify the first or second number of gradations,
When the first gradation number is designated, the interval between the reference timing and the edge of the first gradation pulse, and the (i−1) th (2 ≦ i ≦ N, i is an integer, N is 2 or more) An interval between the edge of the (integer) gradation pulse and the edge of the i-th gradation pulse is set based on the setting values of the first to Nth gradation pulse setting registers, and the reference timing is the starting point. A grayscale clock having first to Nth grayscale pulses is generated within a predetermined period,
When the second number of gradations is specified, the interval between the reference timing and the edge of the first gradation pulse and the (j−1) th (2 ≦ j ≦ M, M ≧ N, j, M are integers) ) And the edge interval of the j-th gradation pulse are set based on the setting value of one gradation pulse setting register of the first to N-th gradation pulse setting registers, and Generating a grayscale clock having first to Mth grayscale pulses within a predetermined period;
Regardless of the first or second gradation number, the pulse width modulation signal having a pulse width corresponding to a period of the number of gradation clocks corresponding to gradation data is generated, and the pulse width modulation signal is generated. The display control method for driving the data lines of the display panel based on the above.

1 is a block diagram of a configuration example of a display system according to an embodiment. Explanatory drawing of the structure of an organic EL element. FIG. 2 is a block diagram of a configuration example of a data driver in FIG. 1. FIG. 2 is a block diagram of a configuration example of a scan driver in FIG. 1. The figure which shows an example of the electrical equivalent circuit of an organic EL element. Explanatory drawing of discharge operation. The block diagram of the outline | summary of a structure of the display controller in this embodiment. FIG. 8 is a block diagram of a configuration example of a driver signal generation unit in FIG. 7. The block diagram of the structural example of the GCLK production | generation part of the 1st structural example of this embodiment. Explanatory drawing of the gradation clock set by the 1st-Nth gradation pulse setting register. The figure which shows the characteristic curve of an organic electroluminescent panel. The block diagram of the structural example of the GCLK production | generation part of the 2nd structural example of this embodiment. Explanatory drawing of the boundary designation | designated register in this embodiment. Explanatory drawing of a gradation clock when the set value of the boundary designation register is valid. The block diagram of the structural example of the GCLK production | generation part of the 3rd structural example of this embodiment. Explanatory drawing when the 2nd gradation number is designated by the gradation number selection register. Explanatory drawing of a gradation clock when the 2nd gradation number is designated by the gradation number selection register. The timing diagram of the operation example of PWM performed by the display controller of this embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Display System FIG. 1 is a block diagram showing a configuration example of a display system according to this embodiment.

  The display system 500 includes an organic EL panel (display panel in a broad sense) 510, a data driver 520, a scan driver 530, and a display controller 540. Note that it is not necessary to include all these circuit blocks in the display system 500, and some of the circuit blocks may be omitted. The display system 500 may be configured to include the host 550.

  The organic EL panel 510 is a simple matrix type. FIG. 1 shows an electrical configuration of the organic EL panel 510. That is, the organic EL panel 510 includes a plurality of scanning lines (cathode in a narrow sense), a plurality of data lines (anode in a narrow sense), and an organic EL element connected to each scanning line and each data line.

  More specifically, the organic EL panel is formed on a glass substrate. A plurality of data lines DL1 to DLn (n is an integer of 2 or more) arranged in the X direction in FIG. 1 and extending in the Y direction are formed on the glass substrate. Also, a plurality of scanning lines GL1 to GLm (m is an integer of 2 or more) arranged in the Y direction in FIG. 1 and extending in the X direction are formed on the glass substrate so as to intersect the data lines. When one pixel is composed of three color components of R component, G component, and B component, the organic EL is made by combining the data line for R component, the data line for G component, and the data line for B component. A plurality of sets of data lines are arranged on the panel 510.

  An organic EL element is formed at a position corresponding to the intersection of the data line DLj (1 ≦ j ≦ n, j is an integer) and the scanning line GLk (1 ≦ k ≦ m, k is an integer).

  FIG. 2 is an explanatory diagram of the structure of the organic EL element.

  In the organic EL element, a transparent electrode (for example, ITO (Indium Thin Oxide)) serving as an anode 602 provided as a data line is formed on a glass substrate 600. A cathode 604 provided as a scanning line is formed above the anode 602. An organic layer including a light emitting layer and the like is formed between the anode 602 and the cathode 604.

  The organic layer includes a hole transport layer 606 formed on the upper surface of the anode 602, a light emitting layer 608 formed on the upper surface of the hole transport layer 606, and an electron transport formed between the light emitting layer 608 and the cathode 604. Layer 610.

  When a potential difference between the data line and the scan line is applied, that is, when a potential difference is applied between the anode 602 and the cathode 604, holes from the anode 602 and electrons from the cathode 604 are recombined in the light emitting layer 608. To do. The energy generated at this time causes the molecules of the light emitting layer 608 to be in an excited state, and the energy released when returning to the ground state becomes light. This light passes through the anode 602 formed of a transparent electrode and the glass substrate 600.

  In FIG. 1, the data driver 520 outputs to the data line based on the gradation data. At this time, the data driver 520 generates a PWM signal having a pulse width corresponding to the gradation data, and drives each data line based on the PWM signal.

  The scan driver 530 sequentially selects a plurality of scan lines. As a result, a current flows through the organic EL element connected to the data line intersecting with the selected scanning line to emit light.

  The display controller 540 controls the data driver 520 and the scan driver 530 according to the contents set by the host 550 such as a central processing unit (CPU). More specifically, the display controller 540 sets, for example, an operation mode for the data driver 520, and also generates gradations for generating a vertical synchronization signal YD, a horizontal synchronization signal LP, and a PWM signal generated internally. A clock GCLK, a dot clock DCLK, a discharge signal DIS (blanking adjustment signal in a broad sense), and gradation data D are supplied. A vertical scanning period is defined by the vertical synchronization signal YD. A horizontal scanning period is defined by the horizontal synchronization signal LP.

  Note that some or all of the data driver 520, the scan driver 530, and the display controller 540 may be formed on the organic EL panel 510.

1.1 Data Line Driver Circuit FIG. 3 shows a configuration example of the data driver 520 in FIG.

  The data driver 520 includes a shift register 522, a line latch 524, a PWM signal generation circuit 526, and a drive circuit 528.

  The shift register 522 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each data line, and the flip-flops are sequentially connected. The dot clock DCLK from the display controller 540 is input to each flip-flop in common. For example, 4-bit gradation data from the display controller 540 is input to the first flip-flop of the shift register 522 in synchronization with the dot clock DCLK. Then, the shift register 522 takes in each gradation data while shifting in synchronization with the dot clock DCLK.

  The line latch 524 latches the grayscale data of one horizontal scan taken in the shift register 522 in synchronization with the horizontal synchronization signal LP supplied from the display controller 540.

  The PWM signal generation circuit 526 generates a PWM signal for driving each data line. More specifically, the PWM signal generation circuit 526 generates a PWM signal whose change point is specified by a gradation clock based on the gradation data corresponding to the data line. This PWM signal has a pulse width corresponding to the period of the number of gradation clocks GCLK corresponding to the gradation data.

  The drive circuit 528 drives each data line based on each PWM signal generated by the PWM signal generation circuit 526. A discharge signal DIS from the display controller 540 is input to the drive circuit 528. By this discharge signal DIS, the horizontal display period within the horizontal scanning period defined by the horizontal synchronizing signal LP is specified. The horizontal display period is a period starting from the falling edge of the discharge signal DIS and starting from the rising edge of the next discharge signal DIS. The pulse of the horizontal synchronizing signal LP is output during the period when the discharge signal DIS is at the H level.

  The drive circuit 528 connects the data line to the ground potential when the discharge signal DIS is at the H level, and supplies a predetermined current to each data line only for a period corresponding to the pulse width of each PWM signal when the discharge signal DIS is at the L level. To do.

  In the data driver 520, when the discharge signal DIS is at the H level, the line data is latched by the line latch 524 in the next horizontal scanning period, thereby avoiding driving the data line with the gradation data being rewritten. it can.

1.2 Scan Driver FIG. 4 shows a configuration example of the scan driver 530 of FIG.

  The scan driver 530 includes a shift register 532 and a drive circuit 534.

  The shift register 532 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each scanning line and each flip-flop is sequentially connected. A horizontal synchronization signal LP from the display controller 540 is commonly input to each flip-flop. The vertical synchronization signal YD from the display controller 540 is input to the first flip-flop of the shift register 532. The shift register 532 shifts the pulse of the vertical synchronization signal YD in synchronization with the horizontal synchronization signal LP.

  The drive circuit 534 sequentially outputs a selection pulse to each scanning line based on the output of each flip-flop of the shift register 532. A discharge signal DIS from the display controller 540 is input to the drive circuit 534. The drive circuit 534 connects all scanning lines to the ground potential when the discharge signal DIS is at the H level, connects only the selected scanning line to the ground potential when the discharge signal DIS is at the L level, and connects the other scanning lines to the ground potential. Connect to a predetermined potential.

1.3 Discharge Operation FIG. 5 shows an example of an electrical equivalent circuit diagram of the organic EL element.

  The organic EL element can be considered equivalent to a configuration including a parasitic capacitance C1 in which a resistance component R1 and a diode D1 are connected in series and connected in parallel with the diode D1. The parasitic capacitance C1 can be considered as a capacitance component corresponding to a depletion layer formed at the junction surface when a potential difference is applied between the anode 602 and the cathode 604. Thus, the organic EL element can be considered as a capacitive load.

  Therefore, in the display system 500, the discharge operation of the organic EL element of the organic EL panel 510 can be performed using the discharge signal DIS, and the influence of the previous horizontal scanning period can be eliminated.

  FIG. 6 is an explanatory diagram for explaining the discharge operation. However, the same parts as those in the display system shown in FIG.

  When the discharge signal DIS is at the L level, the scan driver 530 sets only the selected scan line to the ground potential and connects the other scan line to the potential V-GL. Further, the data driver 520 supplies a predetermined current to the data line only for a period of a pulse width corresponding to each PWM signal. As a result, a current flows through the organic EL element connected to the selected scanning line.

  When the discharge signal DIS is at the H level, all the scanning lines are connected to the ground potential, and all the data lines are connected to the ground potential, so that the potentials at both ends of each organic EL element are equalized. Discharge is possible.

  By adjusting the length of the horizontal display period within the horizontal scanning period, it is possible to prevent flickering depending on the type of the organic EL panel and manufacturing variations, and to adjust the luminance. Thus, the blanking period can be adjusted using the discharge signal DIS, and the discharge signal DIS can be referred to as a blanking adjustment signal.

2. Display Controller FIG. 7 is a block diagram showing an outline of the configuration of the display controller 540 in this embodiment.

  The display controller 540 includes a host interface (InterFace: hereinafter abbreviated as I / F) 10, a driver I / F 20, a frame memory 30, a control unit 40, and a setting register unit 50.

  The host I / F 10 performs interface processing with the host 550. More specifically, the host I / F 10 controls transmission / reception of data and various control signals between the display controller 540 and the host 550.

  The driver I / F 20 performs interface processing with the data driver 520 and the scan driver 530. More specifically, the driver I / F 20 controls transmission / reception of data and various control signals between the display controller 540, the data driver 520, and the scanning driver 530. The driver I / F 20 includes a driver signal generation unit 22 that generates various display control signals for the data driver 520 and the scan driver 530. The driver signal generation unit 22 generates various display control signals based on the setting value of the setting register unit 50.

  The frame memory 30 stores, for example, gradation data for one frame (for one vertical scan) supplied from the host 550 via the host I / F 10. The setting value of the setting register unit 50 is set by the host 550 via the host I / F 10.

  The control unit 40 controls the host I / F 10, the driver I / F 20, the frame memory 30, and the setting register unit 50.

  In such a display controller 540, gradation data is read from the frame memory 30 at a constant reading cycle (for example, every 1/160 second), and the gradation data is transferred to the data driver 520 via the driver I / F 20. Are output. Therefore, the timing for writing gradation data from the host 550 to the frame memory 30 and the timing for reading gradation data from the frame memory 30 to the data driver 520 are asynchronous. Such access control to the frame memory 30 is performed by the memory controller 42 of the control unit 40.

  FIG. 8 shows a block diagram of a configuration example of the driver signal generation unit 22.

  Here, a case where the driver signal generation unit 22 generates the gradation clock GCLK, the dot clock DCLK, the vertical synchronization signal YD, the horizontal synchronization signal LP, and the discharge signal DIS will be described.

  The driver signal generation unit 22 includes a GCLK generation unit 100 (a gradation clock generation unit in a broad sense) and a display control signal generation unit 110. The GCLK generation unit 100 generates a gradation clock GCLK. The gradation clock GCLK has a plurality of gradation pulses within the horizontal display period. For example, the grayscale clock GCLK has N (N is an integer of 2 or more) first to Nth grayscale pulses within the horizontal display period. Alternatively, for example, the gradation clock GCLK has M first to Mth (M> N, M is an integer) gradation pulses in the horizontal display period. In the gradation clock GCLK, after the reference timing has elapsed, the first gradation pulse is output first, and then the second gradation pulse,..., The Nth gradation pulse are output in order. Shall. The display control signal generation unit 110 generates a dot clock DCLK, a vertical synchronization signal YD, a horizontal synchronization signal LP, and a discharge signal DIS.

  The setting register unit 50 of this embodiment includes first to Nth gradation pulse setting registers 120-1 to 120-N (a gradation pulse setting register group in a broad sense), a gradation pulse clock selection register 122, and boundary designation. It includes a register 124, a gradation number selection register 126, a DCLK setting register 130, a YD setting register 140, an LP setting register 150, and a DIS setting register 160.

  The gradation pulse setting registers 1201 to 120-N of the first to Nth gradation pulse setting registers 1201 to 120N, for example, specify the edge of each gradation pulse of the first to Nth gradation pulses of the gradation clock GCLK. This is a register for setting.

  The gradation pulse clock selection register 122 is for selecting a reference clock which is a unit for setting the edge interval of the gradation pulses set by the first to Nth gradation pulse setting registers 120-1 to 120-N. Register. That is, the grayscale pulse clock selection register 122 selects a reference clock from a plurality of clocks having different frequencies, and the grayscales set by the first to Nth grayscale pulse setting registers 120-1 to 120-N. An interval between pulse edges is set in units of the reference clock.

  In this embodiment, the gradation pulse clock selection register 122 is a register for selecting a reference clock from first and second clocks having different frequencies. As the first clock, the system clock SYSCLK that is the operation clock of the display controller 540 can be adopted, and as the second clock, the dot clock DCLK that operates in synchronization with the gradation data for one dot can be adopted. The dot clock DCLK is generated by dividing the system clock SYSCLK. Therefore, the frequency of the first clock is higher than the frequency of the second clock.

  Assuming that the grayscale clock GCLK has the first to Nth grayscale pulses within the horizontal display period, the boundary designation register 124 sets the pth (1 ≦ p <N, This is a register for designating one gradation pulse of the edge of the gradation pulse from p as an integer to the q-th (p <q ≦ N, M, q are integers) as a boundary. The frequency of the reference clock that is the setting unit of the edge of the grayscale pulse is made different at the boundary designated by the boundary designation register 124.

  The boundary designation register 124 may be configured so that the boundary of the gradation pulse can be designated by fixing the pth gradation pulse and designating the qth gradation pulse, or the qth gradation pulse can be designated. The boundary of the gradation pulse may be designated by specifying the p-th gradation pulse in a fixed manner. In the present embodiment, it is assumed that the boundary of the grayscale pulse can be specified by fixing the first grayscale pulse and specifying the qth grayscale pulse. In this case, the boundary designation register 124 sets the interval between the edges of the first to Nth gradation pulses set by the first to Nth gradation pulse setting registers 120-1 to 120-N as the first clock. It can be said to be a register for designating a boundary to be divided into a pulse group set in units and a pulse group set in second clock units.

  The gradation number selection register 126 is a register for selecting the number of gradations. In this embodiment, the number of gradation pulses of the gradation clock can be switched to 63 or 255 by the gradation number selection register 126. By doing so, the number of gradations per dot can be increased, so that high-definition expression can be achieved.

  The DCLK setting register 130 is a register for setting the frequency, output start timing, and output end timing of the dot clock DCLK. In FIG. 8, the display control signal generation unit 110 can include a frequency divider circuit 112. In this case, the frequency dividing circuit 112 generates a dot clock DCLK obtained by dividing the system clock SYSCLK at a frequency dividing ratio corresponding to the set value of the DCLK setting register 130. In the DCLK setting register 130, a setting value corresponding to the frequency division ratio of the system clock SYSCLK is set. Accordingly, the frequency of the dot clock DCLK can be set by the DCLK setting register 130.

  The YD setting register 140 is a register for setting the output timing of the vertical synchronization signal YD. The display control signal generation unit 110 outputs the vertical synchronization signal YD based on the setting value of the YD setting register 140.

  The LP setting register 150 is a register for setting the output timing of the horizontal synchronization signal LP. The display control signal generation unit 110 outputs the horizontal synchronization signal LP based on the set value of the LP setting register 150.

  The DIS setting register 160 is a register for setting the rising timing and falling timing of the discharge signal DIS and the output start timing thereof. The display control signal generation unit 110 (blanking adjustment signal generation unit in a broad sense) outputs the discharge signal DIS based on the set value of the DIS setting register 160.

  In FIG. 8, the setting register unit 50 may not include all these registers. In the setting register unit 50, for example, at least one of the gradation pulse clock selection register 122, the boundary designation register 124, and the gradation number selection register 126 may be omitted.

  The GCLK generation unit 100 in FIG. 8 can employ a configuration according to the type of register included in the setting register unit 50. Hereinafter, various configuration examples of the GCLK generation unit 100 in the present embodiment will be described.

2.1 First Configuration Example FIG. 9 shows a block diagram of a configuration example of the GCLK generation unit 100 in the first configuration example of the present embodiment. In FIG. 9, the same parts as those in FIG.

  In the first configuration example, the setting register unit 50 omits the boundary designation register 124 and the gradation number selection register 126 among the gradation pulse clock selection register 122, the boundary designation register 124, and the gradation number selection register 126, for example. It has been configured.

  The GCLK generation unit 100 includes a register selection circuit 200, a selection control circuit 210, a clock selection circuit 220, and a GCLK pulse setting unit 230.

  The register selection circuit 200 outputs one set value of the first to Nth gradation pulse setting registers 120-1 to 120-N based on the register selection signal RegSel. The selection control circuit 210 generates a register selection signal RegSel.

  The clock selection circuit 220 selects either the system clock SYSCLK or the dot clock DCLK based on the set value of the gradation pulse clock selection register 122 and outputs it as the reference clock SCLK.

  The GCLK pulse setting unit 230 includes an interval setting counter 232, a comparator 234, and a pulse generation circuit 236. The interval setting counter 232 is initialized by the discharge signal DIS (or an internal signal for generating the discharge signal DIS), and counts up (or counts down) the count value in synchronization with the reference clock SCLK. The comparator 234 compares the count value of the interval setting counter 232 with the output of the register selection circuit 200 and outputs a comparison result signal CmpRes. Here, the output of the register selection circuit 200 is a set value of the gradation pulse setting register selected based on the register selection signal RegSel.

  The pulse generation circuit 236 generates a pulse based on the comparison result signal CmpRes. More specifically, the pulse generation circuit 236 generates a pulse when it is detected by the comparison result signal CmpRes that the count value of the interval setting counter 232 matches the output of the register selection circuit 200. The width of this pulse is one clock cycle of the system clock SYSCLK, the dot clock DCLK, or the reference clock SCLK.

  The comparison result signal CmpRes is also supplied to the selection control circuit 210. When it is detected by the comparison result signal CmpRes that the count value of the interval setting counter 232 matches the output of the register selection circuit 200, the selection control circuit 210 selects the next gradation pulse selection register. A register selection signal RegSel is generated.

  FIG. 10 is an explanatory diagram of the gradation clock GCLK set by the first to Nth gradation pulse setting registers 120-1 to 120-N. FIG. 10 shows a case where the number of gradation pulses in the horizontal display period is 63.

  The first gradation pulse setting register 120-1 is a register for setting the interval tw1 between the reference timing that is the starting point of the horizontal display period and the edge (rising edge or falling edge) of the first gradation pulse. It is. The second gradation pulse setting register 120-2 is a register for setting an interval tw2 between the edge of the first gradation pulse and the edge of the second gradation pulse. That is, the i-th (2 ≦ i ≦ N, i is an integer) gradation pal setting register sets the interval twi between the edge of the (i−1) -th gradation pulse and the edge of the i-th gradation pulse. It is a register to do.

  When the setting value of each gradation pulse setting register is “0”, it is possible to prevent generation of subsequent gradation pulses. For example, each edge of the first to Nth gradation pulses is set by each of the first to Nth gradation pulse setting registers. In this case, when “0” is set in the tenth gradation pulse setting register, the first to ninth gradation pulses are intervals corresponding to the set values of the first to ninth gradation pulse setting registers. The tenth to Nth gradation pulses are not output. Therefore, when the grayscale clock GCLK having N grayscale pulses is generated within the horizontal display period, the first to Lth (L> N, L is an integer) grayscale pulse setting registers are provided. It is possible to set “0” in the (N + 1) gradation pulse setting register so that the (N + 1) th to Lth gradation pulses are not output.

  The GCLK generation unit 100 in FIG. 9 includes the interval between the reference timing that is the starting point of the horizontal display period and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse and the i-th gradation. A gradation clock GCLK in which the interval from the pulse edge is set based on the setting values of the first to Nth gradation pulse setting registers 120-1 to 120-N is output. Then, the edge of each gradation pulse is set in units of the system clock SYSCLK or the dot clock DCLK.

  As described above, the GCLK generating unit 100 can individually set the timing of the edge of each gradation pulse of the gradation clock GCLK for specifying the changing point of the PWM signal. Therefore, gamma correction for correcting the characteristic curve 180 of the organic EL panel 510 as shown in FIG. 11 is realized, and fine control can be performed so as to obtain a characteristic such as a gamma correction curve 182. In addition, since the gamma correction can be realized in units of the system clock SYSCLK having a higher frequency than the dot clock DCLK, each gradation can be set more finely.

2.2 Second Configuration Example FIG. 12 shows a block diagram of a configuration example of the GCLK generation unit 100 in the second configuration example of the present embodiment. In FIG. 12, the same parts as those in FIG. 8 or FIG.

  In the second configuration example, the setting register unit 50 is configured such that, for example, the gradation number selection register 126 is omitted from the gradation pulse clock selection register 122, the boundary designation register 124, and the gradation number selection register 126. Yes.

  The difference between the GCLK generator in the second configuration example and the GCLK generator in the first configuration example is that the selection control circuit 300 generates the register selection signal RegSel based on the gradation pulse clock selection register 122 and the boundary designation register 124. However, the selection control of the clock selection circuit 220 is performed.

  In the second configuration example, the setting of the boundary specification register 124 is performed on the condition that the selection control circuit 300 is specified by the gradation pulse clock selection register 122 to set the edge of the gradation pulse in units of the system clock SYSCLK. Enable the value. Therefore, when it is designated by the gradation pulse clock selection register 122 to set the edge of the gradation pulse in units of the dot clock DCLK, the selection control circuit 300 invalidates the setting value of the boundary designation register 124.

  When the gradation pulse clock selection register 122 designates the dot clock DCLK to set, the selection control circuit 300 generates the register selection signal RegSel as in the first configuration example. The selection control circuit 300 performs selection control of the clock selection circuit 220 so as to select the dot clock DCLK.

  On the other hand, when it is specified by the gradation pulse clock selection register 122 to set in units of the system clock SYSCLK, the selection control circuit 300 generates the register selection signal RegSel as in the first configuration example. The selection control circuit 300 selects the system clock SYSCLK from the first gradation pulse (pth gradation pulse) to the gradation pulse designated by the boundary designation register 124, and designates it by the boundary designation register 124. From the gradation pulse to the q-th gradation pulse, selection control of the clock selection circuit 220 is performed so as to select the dot clock DCLK.

  FIG. 13 is an explanatory diagram showing an example of the boundary designation register 124 in the present embodiment.

  FIG. 13 shows a setting example when the setting value of the boundary specification register 124 is valid. In FIG. 13, when the set value “0” is set in the boundary designation register 124, the selection control circuit 300 sets the register selection signal so as to set the first to 64th gradation pulses in units of the system clock SYSCLK. It shows that RegSel is generated and selection control of the clock selection circuit 220 is performed. For example, when the set value “1” is set in the boundary designation register 124, the selection control circuit 300 sets the first to 56th gradation pulses in units of the system clock SYSCLK, and the 57th to 5th pulses. It shows that the register selection signal RegSel is generated so that 64 gradation pulses are set in units of the dot clock DCLK, and the selection control of the clock selection circuit 220 is performed.

  Thereby, when it is specified by the gradation pulse clock selection register 122 to set in units of the system clock SYSCLK, the GCLK generation unit 100 starts from the first gradation pulse (pth gradation pulse) to the boundary designation register. The interval between the edges of each gradation pulse up to the gradation pulse specified by 124 is set in units of the system clock SYSCLK (the first clock having a higher frequency than the second clock). Then, the GCLK generating unit 100 determines the interval between the edges of each gradation pulse from the gradation pulse designated by the boundary designation register 124 to the q-th gradation pulse as a dot clock DCLK (a frequency lower than that of the first clock). 2 clocks).

  FIG. 14 is an explanatory diagram of the gradation clock GCLK when the set value of the boundary designation register 124 is valid.

  As shown in FIG. 14, the interval between the gradation pulses of the gradation clock GCLK set within the horizontal display period is set in units of the system clock SYSCLK and then set in units of the dot clock DCLK. A period from the given reference timing to the edge of the gradation pulse is the pulse width of the PWM signal. Therefore, in the range where the pulse width of the PWM signal is small, the pulse width of the PWM signal can be determined in units of the system clock SYSCLK, and in the range where the pulse width of the PWM signal is large, the pulse width of the PWM signal can be determined in units of the dot clock DCLK. Can do.

  Here, according to the characteristic diagram shown in FIG. 11, in order to obtain the luminance (gradation) specified by the discrete gradation data, the gradation pulse interval (gradation clock step size) increases as the luminance increases. Need to be larger. That is, according to the second configuration example, among the plurality of gradation pulses included in the gradation clock, the gradation pulse interval can be set finely in the range where the luminance is low, and the gradation pulse interval is set in the range where the luminance is high. Can be set coarsely.

  In this way, if the interval of the gradation pulses is set in units of the system clock SYSCLK having a high frequency in the range where the luminance is large, the number of bits of the counter for setting the interval becomes useless. Increase the scale. On the other hand, by setting the interval of the gradation pulse in units of the dot clock DCLK having a low frequency in the range where the luminance is high, the number of bits of the counter for setting the interval can be reduced, and the circuit scale can be reduced. You can contribute.

2.3 Third Configuration Example FIG. 15 shows a block diagram of a configuration example of the GCLK generating unit 100 in the third configuration example of the present embodiment. In FIG. 15, the same parts as those in FIG. 8, FIG. 9, or FIG.

  In the third configuration example, the setting register unit 50 includes a gradation pulse clock selection register 122, a boundary designation register 124, and a gradation number selection register 126.

  The GCLK generation unit in the third configuration example is different from the GCLK generation unit in the second configuration example in that the selection control circuit 310 is based on the gradation pulse clock selection register 122, the boundary designation register 124, and the gradation number selection register 126. Thus, the register selection signal RegSel is generated.

  In the third configuration example, according to the setting value of the gradation number selection register 126, the GCLK generation unit 100 has gradations having the first to Nth gradation pulses within a predetermined period starting from the reference timing. The grayscale clock GCLK having the clock GCLK or the first to Mth (M> N, M is an integer) is generated. At this time, the edge of each gradation pulse of the first to Nth gradation pulses is determined based on the set values of the first to Nth gradation pulse setting registers 120-1 to 120-N. Further, the edge of each gradation pulse of the first to Mth gradation pulses is also determined based on the set values of the first to Nth gradation pulse setting registers 120-1 to 120-N.

  Accordingly, when “64” is designated as the first gradation number by the gradation number selection register 126, the GCLK generation unit 100 determines the interval between the reference timing and the edge of the first gradation pulse, and the (i -1) The interval between the edge of the gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse is set as the first to N-th gradation pulse setting registers 120-1 to 120-120. Set based on the set value of -N. The GCLK generation unit 100 generates a grayscale clock GCLK having the first to Nth grayscale pulses set in this way.

  In addition, when “256” is designated as the second gradation number by the gradation number selection register 126, the GCLK generation unit 100 determines the interval between the reference timing and the edge of the first gradation pulse, or the (j −1) (2 ≦ j ≦ M, j is an integer) and at least two intervals among the intervals of the edges of the j-th gradation pulse, the first to N-th gradation pulse setting registers 120-1 to 120-120. It is set based on the set value of one gradation pulse setting register of −N. The GCLK generation unit 100 generates a grayscale clock GCLK having the first to Mth grayscale pulses set in this way. In this way, M gradation pulses within the horizontal display period of the gradation clock GCLK can be set by the N gradation pulse setting registers.

  FIG. 16 is an explanatory diagram when “256” is designated as the second gradation number by the gradation number selection register 126.

  For example, if the first to 64th gradation pulse setting registers 120-1 to 120-64 are provided, the setting value of each gradation pulse setting register sets the edge of four or three consecutive gradation pulses. Used to do. That is, the setting value of the first gradation pulse setting register 120-1 is commonly used to set the edges of the first to fourth gradation pulses within the horizontal display period of the gradation clock GCLK. The set value of the second gradation pulse setting register 120-2 is commonly used to set the edges of the fifth to eighth gradation pulses within the horizontal display period of the gradation clock GCLK. Similarly, the setting value of the 63rd gradation pulse setting register 120-63 is commonly used to set the edges of the 249th to 252nd gradation pulses within the horizontal display period of the gradation clock GCLK. Since the number of gradation pulses needs to be 255 in order to express 256 gradations, the setting value of the 64th gradation pulse setting register 120-64 is the value of the 253rd to 255th gradation pulses. Commonly used to set edges.

  FIG. 17 is an explanatory diagram of the gradation clock GCLK when “256” is designated as the second gradation number by the gradation number selection register 126.

  As shown in FIG. 17, among the grayscale pulses within the horizontal display period of the grayscale clock GCLK, the edges of the first to fourth grayscale pulses are set values of the first grayscale pulse setting register 120-1. Is set based on The edges of the fifth to eighth gradation pulses are set based on the setting value of the second gradation pulse setting register 120-2. Similarly, the edges of the 249th to 252nd gradation pulses are set based on the set value of the 63rd gradation pulse setting register 120-63. The edges of the 253rd to 255th gradation pulses are set based on the setting values of the 64th gradation pulse setting register 120-64.

  In this way, in the third configuration example, when the number of gradations is increased, at least two gradation pulse edges can be set by one gradation pulse setting register. Therefore, it is not necessary to provide a gradation pulse setting register for each gradation pulse, and an increase in circuit scale can be prevented. On the other hand, even when the number of gradations is increased, an effect that fine gamma correction can be realized is obtained.

  Further, since the setting unit of each gradation pulse can be made fine by the gradation pulse clock selection register 122, highly accurate gradation expression can be performed. Furthermore, since the boundary of the gradation pulse can be designated by the boundary designation register 124, even if the number of gradations is increased, the gradation pulse interval can be set in the dot clock DCLK unit having a low frequency within a high luminance range. The number of bits of the counter for setting the interval can be reduced, and the circuit scale can be reduced.

2.4 Operation Example FIG. 18 is a timing chart of an operation example of PWM performed by the display controller 540 of the present embodiment. FIG. 18 shows a timing diagram of an operation example of the data driver 520 that generates a PWM signal using the gradation clock GCLK generated by any one of the first to third configuration examples.

  When a pulse of the vertical synchronization signal YD is input from the display controller 540, one vertical scanning period is started. When the pulse of the horizontal synchronization signal LP is input from the display controller 540 during the period in which the vertical synchronization signal YD is at the H level, one horizontal scanning period is started. Further, the horizontal display period is started with the timing at which the discharge signal DIS from the display controller 540 changes from the H level to the L level as a reference timing. The horizontal display period ends when the next discharge signal DIS changes to the H level.

  In the horizontal display period, the display controller 540 outputs the dot clock DCLK and sequentially outputs gradation data in synchronization with the dot clock DCLK. In addition, the GCLK generation unit 100 outputs the grayscale clock GCLK within the horizontal display period based on the set values of the first to Nth grayscale pulse setting registers 120-1 to 120-N.

  The data driver 520 that fetches the gradation data from the display controller 540 into the shift register 522 latches the gradation data in one horizontal scanning unit in the line latch 524 by the horizontal synchronization signal LP during the period when the discharge signal DIS is at the H level. To do. Therefore, the data driver 520 generates the PWM signal PWMG corresponding to the gradation data in the horizontal scanning period next to the horizontal scanning period in which the gradation data from the display controller 540 is supplied. In FIG. 18, since the gradation data is “2”, the pulse width of the PWM signal PWMG is a period from the falling edge of the discharge signal DIS to the edge of the second gradation pulse. In this way, since the interval can be varied for each gradation pulse of the gradation clock, a PWM signal having a finely settable width can be generated.

  Further, the blanking period is adjusted by the discharge signal DIS to make the horizontal display period variable, and the interval between the grayscale pulses can be varied within the horizontal display period. Thereby, the pulse width of the PWM signal can be set as an absolute value according to the size of the organic EL panel 510 and the type of the organic EL element, so that desired gradation expression can be easily performed.

  In FIG. 18, the interval between the reference timing and the gradation pulse or the interval between the gradation pulses is set at the rising edge of each gradation pulse. However, the interval is set at the falling edge of each gradation pulse. It may be.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the organic EL panel described above, but can be applied to driving liquid crystal display devices and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

10 host I / F, 20 driver I / F, 22 driver signal generator,
30 frame memory, 40 control unit, 42 memory controller,
50 setting register unit, 100 GCLK generation unit, 110 display control signal generation unit,
112 frequency divider circuit, 120-1 to 120-N first to Nth gradation pulse setting register, 122 gradation pulse clock selection register, 124 boundary designation register,
126 gradation number selection register, 130 DCLK setting register,
140 YD setting register, 150 LP setting register,
160 DIS setting register, 200 register selection circuit,
210, 300, 310 selection control circuit, 220 clock selection circuit,
230 GCLK pulse setting unit, 232 interval setting counter, 234 comparator,
236 pulse generation circuit, 500 display system, 510 organic EL panel,
520 data driver, 522, 532 shift register,
524 line latch, 526 PWM signal generation circuit, 528, 534 drive circuit, 530 scan driver, 540 display controller, 550 host,
DCLK dot clock, DIS discharge signal,
GCLK gray scale clock, LP horizontal sync signal, SYSCLK system clock, YD vertical sync signal

Claims (13)

A display controller that outputs a gradation clock for specifying a changing point of a pulse width modulation signal,
A gray scale clock generating section for generating a gray scale clock having first to Nth (N is an integer of 2 or more) gray scale pulses within a predetermined period starting from a reference timing;
A grayscale pulse clock selection register for designating a reference clock for designating each grayscale pulse of the first to Nth grayscale pulses from a plurality of clocks having different frequencies;
A gradation pulse setting register group for setting an edge of each gradation pulse of the first to Nth gradation pulses;
The gradation clock generator is
Using the reference clock as a unit, the interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) th (2 ≦ i ≦ N, i is an integer) gradation pulse and the first gradation pulse. A display controller, wherein an interval between i and the edge of the grayscale pulse is set based on a set value of each register of the grayscale pulse setting register group. A display controller that outputs a gradation clock for specifying a changing point of a pulse width modulation signal,
A gray scale clock generating section for generating a gray scale clock having first to Nth (N is an integer of 2 or more) gray scale pulses within a predetermined period starting from a reference timing;
One gradation pulse among pth (1 ≦ p <N, p is an integer) to qth (p <q ≦ N, q is an integer) gradation pulses of the first to Nth gradation pulses. A boundary specification register to specify,
A gradation pulse setting register group for setting an edge of each gradation pulse of the first to Nth gradation pulses;
The gradation clock generator is
The interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse Is set based on the setting value of each register of the gradation pulse setting register group,
The edge interval of each gradation pulse from the p-th gradation pulse to the gradation pulse designated by the boundary designation register is set in units of a first clock and designated by the boundary designation register. A display controller, wherein an interval between edges of each gradation pulse from a gradation pulse to the qth gradation pulse is set in units of a second clock. In claim 2,
When the boundary of the first to Nth gradation pulses is designated by the boundary designation register,
A gradation pulse clock selection register for designating the first or second clock from a plurality of clocks having different frequencies;
The gradation clock generator is
The edge interval of each gradation pulse from the first gradation pulse to the gradation pulse designated by the boundary designation register is set in units of the first clock and designated by the boundary designation register. A display controller, wherein an interval between edges of each gradation pulse from a gradation pulse to the Nth gradation pulse is set in units of the second clock. A display controller that outputs a gradation clock for specifying a changing point of a pulse width modulation signal,
A gray scale clock having first to Nth (N is an integer of 2 or more) grayscale pulses or first to Mth (M> N, M is an integer) is generated within a predetermined period starting from a reference timing. A gradation clock generator to
A gradation number selection register for designating the first or second gradation number;
First to Nth gradation pulse setting registers for setting the edge of each gradation pulse of the N gradation pulses of the gradation clock;
When the first gradation number is designated by the gradation number selection register,
The gradation clock generator is
The interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse Is set based on the set value of the first to Nth gradation pulse setting registers,
When the second gradation number is designated by the gradation number selection register,
The gradation clock generator is
At least two of the interval between the reference timing and the edge of the first gradation pulse and the interval between the (j−1) th (2 ≦ j ≦ M, j is an integer) and the edge of the jth gradation pulse A display controller, wherein the interval is set based on a set value of one gradation pulse setting register of the first to Nth gradation pulse setting registers. In claim 4,
A boundary designation register for designating one of the first to Nth gradation pulses or one of the first to Mth gradation pulses;
The gradation clock generator is
The edge interval of each gradation pulse from the first gradation pulse to the gradation pulse designated by the boundary designation register is set in units of the first clock, and the level designated by the boundary designation register is set. A display controller, wherein an interval between edges of each gradation pulse from the adjustment pulse to the Nth or Mth gradation pulse is set in units of a second clock. In claim 2, 3 or 5,
When the gradation clock has gradation pulses in order from the first gradation pulse starting from the reference timing,
The display controller, wherein a frequency of the first clock is higher than a frequency of the second clock. In claim 6,
The first clock is a system clock;
The display controller, wherein the second clock is a dot clock obtained by dividing the system clock. A plurality of scan lines;
Multiple data lines,
A display panel in which each electroluminescent element includes a plurality of electroluminescent elements specified by any one of the plurality of scanning lines and any one of the plurality of data lines;
A scan driver for scanning the plurality of scan lines;
A data driver that drives the plurality of data lines based on a pulse width modulation signal that is pulse width modulated using gradation data;
A display controller according to any one of claims 1 to 7,
The display controller is
Supplying the gradation clock to the data driver;
The data driver is
Generating the pulse width modulation signal having a pulse width corresponding to a period of the number of grayscale clocks corresponding to the grayscale data, and driving each data line based on the pulse width modulation signal; Display system. A display control method based on a pulse width modulation signal whose change point is specified by a gradation clock,
Designating a reference clock for designating each gradation pulse of the first to Nth gradation pulses within a predetermined period starting from the reference timing, from among a plurality of clocks having different frequencies,
Using the reference clock as a unit, the interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) th (2 ≦ i ≦ N, i is an integer) gradation pulse and the first gradation pulse. set the interval between the edge of the gradation pulse of i and generate the gradation clock;
Generating the pulse width modulation signal having a pulse width corresponding to a period of the number of grayscale clocks corresponding to the grayscale data, and driving a data line of the display panel based on the pulse width modulation signal; Display control method. A display control method based on a pulse width modulation signal whose change point is specified by a gradation clock,
The p-th (1 ≦ p <N, p is an integer) to q-th (g) of the grayscale clock having the first to Nth (N is an integer of 2 or more) grayscale pulses within a predetermined period starting from the reference timing. p <q ≦ N, q is an integer) and designates one gradation pulse,
The interval between the reference timing and the edge of the first gradation pulse, and the edge of the (i−1) -th gradation pulse (2 ≦ i ≦ N, i is an integer) and the edge of the i-th gradation pulse To generate the gradation clock,
Generating the pulse width modulation signal having a pulse width corresponding to a period of the number of clocks of the gradation clock corresponding to the gradation data, and driving the data lines of the display panel based on the pulse width modulation signal;
The edge interval of each gradation pulse from the p-th gradation pulse to the gradation pulse designated by the boundary designation register is set in units of a first clock and designated by the boundary designation register. A display control method, wherein an interval between edges of each gradation pulse from a gradation pulse to the qth gradation pulse is set in units of a second clock. In claim 10,
When the gradation clock has gradation pulses in order from the first gradation pulse starting from the reference timing,
A display control method, wherein a frequency of the first clock is higher than a frequency of the second clock. In claim 11,
The first clock is a system clock;
The display control method, wherein the second clock is a dot clock obtained by dividing the system clock. A display control method based on a pulse width modulation signal whose change point is specified by a gradation clock,
Specify the first or second number of gradations,
When the first gradation number is designated, the interval between the reference timing and the edge of the first gradation pulse, and the (i−1) th (2 ≦ i ≦ N, i is an integer, N is 2 or more) An interval between the edge of the (integer) gradation pulse and the edge of the i-th gradation pulse is set based on the setting values of the first to Nth gradation pulse setting registers, and the reference timing is the starting point. A grayscale clock having first to Nth grayscale pulses is generated within a predetermined period,
When the second number of gradations is specified, the interval between the reference timing and the edge of the first gradation pulse and the (j−1) th (2 ≦ j ≦ M, M ≧ N, j, M are integers) ) And the edge interval of the j-th gradation pulse are set based on the setting value of one gradation pulse setting register of the first to N-th gradation pulse setting registers, and Generating a grayscale clock having first to Mth grayscale pulses within a predetermined period;
Regardless of the first or second gradation number, the pulse width modulation signal having a pulse width corresponding to a period of the number of gradation clocks corresponding to gradation data is generated, and the pulse width modulation signal is generated. A display control method for driving a data line of a display panel based on the above.

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