JP2011154097A - Semiconductor device and driving method thereof, electro-optical device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely apply a data voltage to a capacitive element via a TFT in a semiconductor device. <P>SOLUTION: The semiconductor device includes: a first transistor (31) connected between a capacitive element (70) and a data line (50); a second transistor (32) connected between the first transistor and the capacitive element; and a driving means (110) for driving the first and the second transistors so that when a data voltage is applied to the capacitive element, the first and the second transistors are both turned on, the second transistor is temporarily turned on after timing at which both are turned on, and then turned on again, and the first transistor is turned off at timing at which the second transistor is temporarily turned off or after the timing and before the timing at which the second transistor is turned on again. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technical field of a semiconductor device and a driving method thereof, an electro-optical device, and an electronic apparatus.

  As an example of this type of semiconductor device, there is an active matrix driving type liquid crystal device. In such a liquid crystal device, a pixel electrode is disposed for each pixel on the substrate, and a scanning line, a data line, and a TFT (Thin Film Transistor as a pixel switching element) for selectively driving the pixel electrode. ), And is configured to be capable of active matrix driving.

  In such a liquid crystal device, a feedthrough voltage (also referred to as “punch-through voltage”) is generated due to a parasitic capacitance between the gate and drain of the TFT as a pixel switching element or between the gate and the source. There is a technical problem that a data voltage to be applied cannot be sufficiently applied to a liquid crystal element that is a capacitive element.

  Therefore, in Patent Document 1, for example, a main TFT and a sub-TFT having a size larger than that of the main TFT are provided for each pixel, and a voltage is supplied to the pixel electrode via the sub-TFT, and then the pixel electrode is connected via the main TFT. There has been proposed a technique for reducing the parasitic capacitance of the main TFT by configuring so that a voltage is supplied to the main TFT.

Japanese Patent No. 3656179

  However, according to the technique disclosed in Patent Document 1 described above, it is difficult to reduce the variation in parasitic capacitance due to the manufacturing variation of TFTs, and there is a possibility that the variation in feedthrough voltage may not be reduced. There is a point. For this reason, there is a possibility that the data voltage cannot be sufficiently applied to the liquid crystal element which is a capacitive element.

  The present invention has been made in view of the above-described problems, for example, and a semiconductor device capable of more reliably applying a data voltage to a capacitive element via a TFT, a driving method thereof, and such a semiconductor device. It is an object to provide an electro-optical device and an electronic apparatus that are provided.

  In order to solve the above problems, a semiconductor device of the present invention has a capacitive element, a data line to which a data voltage to be applied to the capacitive element is applied, and an electric current between the capacitive element and the data line. A first transistor electrically connected, a second transistor electrically connected between the first transistor and the capacitive element, and applying the data voltage to the capacitive element, Both the first and second transistors are turned on, and the second transistor is turned on again after the second transistor is turned off after the timing when both of the transistors are turned on. In addition, the first transistor is turned off at the same time as the timing when the transistor is once turned off or after the timing when the transistor is turned on again. On purpose so that, and a driving means for driving the first and second transistors.

  According to the semiconductor device of the present invention, a capacitive element (that is, a capacitive element) such as a capacitor, a transistor, a liquid crystal element, an organic electroluminescence element (organic EL (Electro-Luminescence) element), an electrophoretic element, or the like. And the data line are provided with first and second transistors connected in series with each other. The source of the first transistor is electrically connected to the data line, the drain of the first transistor is electrically connected to the source of the second transistor, and the drain of the second transistor is the capacitive element (More specifically, it is electrically connected to one of the pair of capacitive electrodes constituting the capacitive element). The first and second transistors are driven by driving means. Typically, the gate of the first transistor is electrically connected to a first gate line that forms part of the driving means, and the gate of the second transistor forms a second part that forms part of the driving means. 2 is electrically connected to the gate line. A first gate signal is supplied to the gate of the first transistor from the gate line driving circuit (or row driving circuit) constituting a part of the driving means via the first gate line. The transistor is switched between an on state and an off state, and the second gate signal is supplied to the gate of the second transistor through the second gate line, whereby the second transistor is turned on and off. Is switched. During operation of the semiconductor device of the present invention, a data voltage to be applied to the capacitive element is applied to the data line from, for example, a data line driving circuit (or column driving circuit) constituting a part of the driving means. A data voltage is applied to the capacitive element through the first and second transistors.

  In the present invention, in particular, the driving unit applies the data voltage to the capacitive element so that both the first and second transistors are turned on and after the timing when both are turned on. The second transistor is turned on again after the second transistor is turned off, and at the same time as or after the timing when the second transistor is turned off. Before the timing when the transistor is turned on again, the first and second transistors are driven so that the first transistor is turned off. That is, in the present invention, when a data voltage is applied to the capacitive element, first, both the first and second transistors are turned on by the driving means. As a result, the data voltage is supplied from the data line to the capacitive element via the first and second transistors turned on. Next, the second transistor is once turned off by the driving means. At this time, the first transistor is maintained in the on state by the driving means or is turned off at the same time as the second transistor is once turned off. Here, once the second transistor is turned off, a feedthrough voltage is generated due to the parasitic capacitance between the gate and the drain of the second transistor, and the voltage applied to the capacitive element is reduced. The voltage applied to the capacitive element may be reduced by a feedthrough voltage with respect to the data voltage to be applied to the capacitive element. However, according to the present invention, the second transistor is once turned off by the driving means and then turned on again. Note that when the second transistor is turned on again by the driving means, the first transistor is turned off by the driving means. Therefore, the charge accumulated between the second transistor that has been turned off and the first transistor that has been turned off is supplied to the capacitive element through the second transistor that has been turned on. And the voltage applied to the capacitive element can be increased (i.e., the voltage applied to the capacitive element can be brought close to or almost or completely matched to the data voltage).

  Therefore, according to the semiconductor device of the present invention, it is possible to more reliably apply the data voltage from the data line to the capacitive element via the first and second transistors.

  In one aspect of the semiconductor device of the present invention, the driving means may be configured such that the first transistor is in an off state after the timing at which it is once turned off and before the timing at which it is turned on again. The first transistor is driven so that

  According to this aspect, the data line is connected to the data line via the first transistor that is turned on during the period in which the second transistor is once turned off by the driving unit and the first transistor is kept in the on state. The data voltage can be supplied to the source side (that is, between the first transistor and the second transistor) of the second transistor once turned off. Therefore, when the second transistor is turned on again by the driving means, the charge accumulated on the source side of the second transistor is supplied to the capacitive element through the second transistor turned on. The voltage applied to the capacitive element can be increased more reliably.

  In another aspect of the semiconductor device of the present invention, the driving unit drives the first transistor so that the first transistor is turned off simultaneously with the timing when the device is once turned off.

  According to this aspect, for example, the driving means is configured to detect the first transistor after the timing at which the second transistor is once turned off and before the timing at which the second transistor is turned on again. Compared to driving the first transistor so that the transistor is turned off, the driving sequence for driving the first and second transistors can be simplified, and the data voltage is applied to the capacitive element. It is possible to increase the speed of performing.

  In another aspect of the semiconductor device of the present invention, the data voltage is constant from a timing when both are turned on to a timing when the first transistor is turned off.

  According to this aspect, during the period from the timing when both the first and second transistors are turned on to the timing when the first transistor is turned off, the first transistor is turned on via the first transistor that is turned on. A data voltage can be supplied to the source side of the two transistors.

  In another aspect of the semiconductor device of the present invention, the capacitive element and the first and second transistors are provided in a matrix of n rows × m columns (where m and n are natural numbers) on a substrate, The data line is provided one for each column, and the driving means includes a first gate line electrically connected to a gate of the first transistor for each row, and the second line. And a second gate line electrically connected to the gate of the transistor.

  According to this aspect, it is possible to realize a matrix device that sequentially selects a plurality of capacitive elements arranged in a matrix on a substrate. Here, according to this aspect, even if the parasitic capacitance of the plurality of first and second transistors varies due to manufacturing variation, data is transferred from the data line to the capacitive element via the first and second transistors. The voltage can be applied more reliably.

  In another aspect of the semiconductor device of the present invention, the capacitive element is a capacitor, a transistor, a liquid crystal element, an organic electroluminescence element, or an electrophoretic element.

  According to this aspect, an active matrix drive type display device (that is, a liquid crystal device, an organic EL device, or an electrophoretic device) can be realized. Here, according to this aspect, even if the parasitic capacitance of the first and second transistors varies due to manufacturing variation, the data voltage is applied from the data line to the capacitive element via the first and second transistors. Since it can be applied more reliably, display spots such as so-called “burn-in” can be reduced or prevented.

  In order to solve the above problems, a driving method of a semiconductor device according to the present invention includes a capacitive element, a data line to which a data voltage to be applied to the capacitive element is applied, the capacitive element, and the data line. A semiconductor device for driving a semiconductor device comprising: a first transistor electrically connected between the first transistor; and a second transistor electrically connected between the first transistor and the capacitive element. A first driving method for driving the first and second transistors so that both the first and second transistors are turned on when the data voltage is applied to the capacitive element. And a second step of driving the first and second transistors so that the second transistor is once turned off after the timing when both are turned on. The third step of driving the first and second transistors so that the second transistor is turned on again after being turned off, and at the same time as the timing when the transistor is turned off or at the timing. And a fourth step of driving the first and second transistors so that the first transistor is turned off before the timing when the transistor is turned on again.

  According to the method for driving a semiconductor device according to the present invention, the data voltage is more reliably applied from the data line to the capacitive element via the first and second transistors, as in the semiconductor device of the present invention described above. Can do.

  Note that various aspects similar to the above-described various aspects related to the semiconductor device of the present invention can be appropriately applied to the driving method of the semiconductor device according to the present invention.

  In order to solve the above problems, an electro-optical device according to the present invention includes the above-described semiconductor device according to the present invention (including various aspects thereof).

  According to the electro-optical device of the present invention, since the above-described semiconductor device of the present invention is provided, various display devices such as a liquid crystal device, an organic EL device, and an electrophoretic device that can perform high-quality display can be realized. .

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic device of the present invention, since the electro-optical device of the present invention described above is provided, a projection display device, a television, a mobile phone, a portable audio device, an electronic notebook, capable of performing high-quality display, Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, a touch panel, a wristwatch, electronic paper, and an electronic notebook can be realized.

  The effect | action and other gain of this invention are clarified from the form for implementing invention demonstrated below.

1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment. FIG. 3 is an equivalent circuit diagram of a unit circuit of the semiconductor device according to the first embodiment. 4 is a timing chart (part 1) for explaining the operation of the semiconductor device according to the first embodiment; 4 is a timing chart (part 2) for explaining the operation of the semiconductor device according to the first embodiment; FIG. 6 is a schematic diagram (part 1) for explaining an operation of the semiconductor device according to the first embodiment. FIG. 6 is a schematic diagram (part 2) for explaining the operation of the semiconductor device according to the first embodiment. FIG. 6 is a schematic diagram (part 3) for explaining the operation of the semiconductor device according to the first embodiment; FIG. 6 is a schematic diagram (part 4) for explaining the operation of the semiconductor device according to the first embodiment; It is a block diagram which shows the unit circuit of the semiconductor device which concerns on a 1st modification. It is a block diagram which shows the unit circuit of the semiconductor device which concerns on a 2nd modification. It is a block diagram which shows the unit circuit of the semiconductor device which concerns on a 3rd modification. It is a timing chart (the 1) for explaining operation of the semiconductor device concerning a 2nd embodiment. 12 is a timing chart (part 2) for explaining the operation of the semiconductor device according to the second embodiment; FIG. 10 is a schematic diagram (part 1) for explaining an operation of the semiconductor device according to the second embodiment. FIG. 9 is a schematic diagram (part 2) for explaining the operation of the semiconductor device according to the second embodiment. It is a perspective view which shows the structure of the electronic paper to which the semiconductor device of this invention was applied. It is a perspective view which shows the structure of the electronic notebook to which the semiconductor device of this invention was applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
The semiconductor device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the semiconductor device according to the present embodiment will be described with reference to FIG.

  FIG. 1 is a block diagram showing the configuration of the semiconductor device according to the present embodiment.

  In FIG. 1, a semiconductor device 1 according to this embodiment includes a plurality of unit circuits PX (that is, PX) arranged in a matrix (two-dimensional plane) of n rows × m columns (where m and n are natural numbers). (1, 1), PX (1, 2),..., PX (n, m−1), PX (n, m)) and n first gate lines 41 (that is, first gate lines Y11, Y21,..., Yn1), n second gate lines 42 (ie, second gate lines Y12, Y22,..., Yn2), and m data lines 50 (ie, data lines X1, X2,. Xm), a row drive circuit 110, and a column drive circuit 120. The first gate line 41, the second gate line 42, the row driving circuit 110, and the column driving circuit 120 constitute an example of “driving means” according to the present invention.

  The n first gate lines 41 and the n second gate lines 42 extend in the row direction (that is, the X direction), and the m data lines 50 extend in the column direction (that is, the Y direction). Exist. Unit circuits PX are arranged corresponding to the intersections of the n first gate lines 41 and the n second gate lines 42 and the m data lines 50.

  The row driving circuit 110 supplies a first gate signal G1 (that is, a first gate signal Gi1 (where i = 1,..., N)) to the first gate line 41 and a second gate to the second gate line. The signal G2 (that is, the second gate signal Gi2 (where i = 1,..., N)) is supplied. Specifically, the row driving circuit 110 supplies the first gate signal G11 to the first gate line Y11, supplies the first gate signal G21 to the first gate line Y21,..., And supplies the first gate signal Y11 to the first gate line Yn1. The first gate signal Gn1 is supplied, the second gate signal G12 is supplied to the second gate line Y12, the second gate signal G22 is supplied to the second gate line Y22, and the second gate signal Yn2 is supplied to the second gate line Yn2. A signal Gn2 is supplied.

  The column driving circuit 120 supplies a data signal DATA (that is, a data signal DATAk (where k = 1,..., M)) to the data line 50. Specifically, the column driving circuit 120 supplies the data signal DATA1 to the data line X1, supplies the data signal DATA2 to the data line X2,..., And supplies the data signal DATAm to the data line Xm.

  Each of the plurality of unit circuits PX includes a first transistor 31 and a second transistor 32 connected in series with each other, and a capacitive element 70.

  The first transistor 31 is formed as an N-channel transistor using, for example, an amorphous semiconductor. The first transistor 31 has its gate electrically connected to the first gate line 41, its source electrically connected to the data line 50, and its drain electrically connected to the source of the second transistor 32. It is connected to the. The first transistor 31 is switched between an on state and an off state when the gate is supplied with the first gate signal G1 from the row driving circuit 110 via the first gate line 41.

  For example, the second transistor 32 is formed as an N-channel transistor using an amorphous semiconductor. The second transistor 32 has a gate electrically connected to the second gate line 42, a source electrically connected to the drain of the first transistor 31, and a drain connected to the capacitive element 70 (more Specifically, it is electrically connected to one of the pair of capacitive electrodes constituting the capacitive element 70. The second transistor 32 is switched between an on state and an off state when the gate is supplied with the second gate signal G <b> 2 from the row driving circuit 110 via the second gate line 42.

  The capacitive element 70 is a capacitor having a pair of capacitive electrodes that sandwich a dielectric. One capacitive electrode of the pair of capacitive electrodes constituting the capacitive element 70 is electrically connected to the drain of the second transistor 32. The other capacitive electrode of the pair of capacitive electrodes constituting the capacitive element 70 is electrically connected to a predetermined potential line to which a predetermined potential such as a ground potential is supplied. The capacitive element 70 is supplied with the data signal DATA from the data line 50 via the first transistor 31 that is turned on and the second transistor 32 that is turned on, so that the data voltage corresponding to the data signal DATA is supplied. Vdata is applied.

  Next, the operation of the semiconductor device according to the present embodiment will be described with reference to FIGS. 2 to 8 in addition to FIG. In the following, the operation when the data voltage Vdata is applied to the capacitive element 70 in the semiconductor device according to the present embodiment will be described.

  FIG. 2 is an equivalent circuit diagram of a unit circuit of the semiconductor device according to the present embodiment.

  2, the unit circuit PX includes the first transistor 31, the second transistor 32, and the capacitive element 70 as described above with reference to FIG. A parasitic capacitance 911 exists between the gate and source of the first transistor 31, a parasitic capacitance 912 exists between the gate and drain of the first transistor 31, and the gate and source of the second transistor 32 A parasitic capacitance 921 exists between them, and a parasitic capacitance 922 exists between the gate and drain of the second transistor 32. Here, for convenience of explanation, it is assumed that the parasitic capacitances 911, 912, 921 and 922 have the same capacitance value, and the capacitance value is Cpar. In the following description, the capacitance value of the capacitive element 70 is described as Claud.

  3 and 4 are timing charts for explaining the operation of the semiconductor device according to the present embodiment.

  In FIG. 3, the first gate signal Gi1 (in other words, the potential of the first gate line Yi1) and the second gate signal Gi2 (in other words, the potential of the second gate line Yi2), the data signal DATAk, and the unit circuit PX ( The change over time of the data signal DATA (i, k) supplied to i, k) is shown.

  In FIG. 4, the first gate signal G <b> 1 and the second gate signal G <b> 2, the voltage Vp at the point P shown in FIG. 2, and one capacitive electrode of the capacitive element 70 (that is, electrically connected to the second transistor 32). The change with time of the voltage Vc applied to the capacitor electrode) is shown. In FIG. 2, a point P is a point between the drain of the first transistor 31 and the source of the second transistor 32.

  As shown in FIGS. 3 and 4, the first gate signal G1 (ie, the first gate signals G11, G21,..., Gn1) and the second gate signal G2 (ie, the second gate signals G12, G22,..., Gn2). ) Each take either a high level potential VH or a low level potential VL lower than the high level potential.

  Particularly in the present embodiment, when the data voltage Vdata corresponding to the data signal DATA is applied to the capacitive element 70, first, the first gate signal is set so that both the first transistor 31 and the second transistor 32 are turned on. G1 and the second gate signal G2 are supplied from the row driving circuit 110 to the first transistor 31 and the second transistor 32 via the first gate line 41 and the second gate line 42.

  That is, as shown in FIG. 4, when the data voltage Vdata corresponding to the data signal DATA is applied to the capacitive element 70, first, during the period from the time point t1 to the time point t2, the first gate signal G1 and the second gate signal G1 are output. Both gate signals G2 take the high level potential VH.

  FIG. 5 is a schematic diagram for explaining the operation of the semiconductor device according to the present embodiment, and shows the operation state of the unit circuit PX during the period from the time point t1 to the time point t2.

  As shown in FIG. 5, during the period from the time point t1 to the time point t2, both the first gate signal G1 and the second gate signal G2 take the high level potential VH, so that the first transistor 31 and the second transistor Both 32 are turned on. As a result, the data signal DATA is supplied from the data line 50 to the capacitive element 70 via the first transistor 31 and the second transistor 32 that are turned on, and the potential Vc of one capacitive electrode of the capacitive element 70 is the data The voltage becomes Vdata (see FIG. 4). At this time, the point P is electrically connected to the data line 50 by the first transistor 31 turned on, so that the voltage Vp at the point P also becomes the data voltage Vdata (see FIG. 4).

  Next, in FIG. 4, during the period from time t2 to time t3, the first gate signal G1 remains at the high level potential VH, and the second gate signal G2 takes the low level potential VL. That is, at time t2, the second gate signal G2 changes from the high level potential VH to the low level potential VL, and the first gate signal G1 is maintained at the high level potential VH.

  FIG. 6 is a schematic diagram for explaining the operation of the semiconductor device according to the present embodiment, and shows the operation state of the unit circuit PX during the period from the time point t2 to the time point t3.

  As shown in FIG. 6, during the period from time t2 to time t3, the first gate signal G1 takes the high level potential VH and the second gate signal G2 takes the low level potential VL. 31 is turned on (ON) and the second transistor 32 is turned off.

  Here, when the second transistor 32 is turned off at the time point t2, a feedthrough voltage is generated due to the parasitic capacitance 922 between the gate and the drain of the second transistor 32 (in other words, the second transistor There is a possibility that the charge ΔQ moves from the drain side to the gate side of the transistor 32), and the potential Vc of one capacitive electrode of the capacitive element 70 may decrease from the data voltage Vdata to the potential V1 (see FIG. 4). ). Here, the potential V1 can be expressed by the following formula (1).

V1 = Vdata−ΔVg × Cpar / (Cpar + Cload) (1)
However, ΔVg = VH−VL
Further, when the second transistor 32 is turned off at the time t2, the voltage Vp at the point P is a feedthrough voltage (in other words, generated due to the parasitic capacitance 921 between the gate and the source of the second transistor 32). For example, due to the movement of the charge ΔQ from the source side to the gate side of the second transistor 32), the data voltage Vdata temporarily decreases from the potential V 2, but the point P is changed to the data line by the first transistor 31 turned on. Since it is electrically connected to 50, it becomes the data voltage Vdata again (see FIG. 4). Here, the potential V2 can be expressed by the following formula (2).

V2 = Vdata−ΔVg × Cpar / (2 × Cpar) (2)
Next, in FIG. 4, during the period from time t3 to time t4, both the first gate signal G1 and the second gate signal G2 take the low level potential VL. That is, at time t3, the first gate signal G1 changes from the high level potential VH to the low level potential VL, and the second gate signal G2 is maintained at the low level potential VL.

  FIG. 7 is a schematic diagram for explaining the operation of the semiconductor device according to the present embodiment, and shows the operation state of the unit circuit PX during the period from the time point t3 to the time point t4.

  As shown in FIG. 7, during the period from the time point t3 to the time point t4, both the first gate signal G1 and the second gate signal G2 take the low level potential VL, so that the first transistor 31 and the second transistor Both 32 are turned off. Accordingly, the capacitive element 70 is electrically disconnected from the data line 50 by the first transistor 31 and the second transistor 32 which are turned off, and the potential Vc of one capacitive electrode of the capacitive element 70 is the voltage V1. (See FIG. 4).

  Further, when the first transistor 31 is turned off at the time t3, the voltage Vp at the point P is a feedthrough voltage (in other words, generated due to the parasitic capacitance 912 between the gate and the drain of the first transistor 32). For example, due to the movement of the charge ΔQ from the drain side to the gate side of the first transistor 31, the voltage drops from the data voltage Vdata to the potential V2 (see FIG. 4). Since the point P is electrically disconnected from the data line 50 by the first transistor 31 in the off state, the voltage Vp at the point P remains at the potential V2 during the period from the time point t3 to the time point t4. (See FIG. 4).

  Next, in FIG. 4, after the time point t4, the first gate signal G1 remains at the low level potential VL, and the second gate signal G2 takes the high level potential VH. That is, at time t4, the second gate signal G2 changes from the low level potential VL to the high level potential VH, and the first gate signal G1 is maintained at the low level potential VL.

  FIG. 8 is a schematic diagram for explaining the operation of the semiconductor device according to the present embodiment, and shows the operation state of the unit circuit PX during the period after time t4.

  As shown in FIG. 8, after the time t4, the first gate signal G1 takes the low level potential VL and the second gate signal G2 takes the high level potential VH, so that the first transistor 31 is turned off. At the same time, the second transistor 32 is turned on.

  Here, when the second transistor 32 is turned on at the time point t4, the voltage Vp at the point P is a feedthrough voltage generated due to the parasitic capacitance 921 between the gate and the source of the second transistor 32 ( In other words, due to the movement of the charge ΔQ from the gate side to the source side of the second transistor 32), the voltage rises from the potential V2 and becomes the data voltage Vdata (see FIG. 4). Further, since one capacitive electrode of the capacitive element 70 is electrically connected to the point P by the second transistor 32 that is turned on, the potential Vc of one capacitive electrode of the capacitive element 70 is the potential V1. Rises to the data voltage Vdata (see FIG. 4). That is, the voltage applied to the capacitive element 70 once lowered by the feedthrough voltage generated due to the parasitic capacitance 922 between the gate and the drain of the second transistor 32 is increased to the data voltage Vdata to be applied. be able to.

  As described above, according to the present embodiment, when the data voltage Vdata is applied to the capacitive element 70, both the first transistor 31 and the second transistor 32 are turned on at the time t1, and The second transistor 32 is turned off at time t4 and then turned on again at time t4, and after the time t2 at which the second transistor 32 is turned off. Since the first transistor 31 and the second transistor 32 are driven by the row driving circuit 110 so that the first transistor 31 is turned off at the time t3 before the time t4 when the transistor is turned on again, the data line 50 To the capacitive element 70 via the first transistor 31 and the second transistor 32. The data voltage Vdata can be reliably applied.

<First Modification>
FIG. 9 is a block diagram showing a unit circuit of the semiconductor device according to the first modification.

  As shown in FIG. 9, the unit circuit PX may include a storage capacitor 71 and a liquid crystal element 72 instead of the capacitive element 70 in the first embodiment described above with reference to FIG. In this case, a liquid crystal display device can be realized by the semiconductor device. Here, according to this modification, even if the parasitic capacitances of the first transistor 31 and the second transistor 32 vary due to manufacturing variations, the capacitance from the data line 50 via the first transistor 31 and the second transistor 32 is increased. Since the data voltage can be reliably applied to the storage capacitor 71 and the liquid crystal element 72, which are characteristic elements, display spots such as so-called “burn-in” can be reduced or prevented.

<Second Modification>
FIG. 10 is a block diagram showing a unit circuit of a semiconductor device according to the second modification.

  As shown in FIG. 10, the unit circuit PX may include a storage capacitor 71 and an electrophoretic element 74 instead of the capacitive element 70 in the first embodiment described above with reference to FIG. In this case, an electrophoretic display device can be realized by a semiconductor device. Here, according to this modification, even if the parasitic capacitances of the first transistor 31 and the second transistor 32 vary due to manufacturing variations, the capacitance from the data line 50 via the first transistor 31 and the second transistor 32 is increased. Since the data voltage can be reliably applied to the storage capacitor 71 and the electrophoretic element 74, which are characteristic elements, display spots can be reduced or prevented.

<Third Modification>
FIG. 11 is a block diagram showing a unit circuit of a semiconductor device according to the third modification.

  As shown in FIG. 11, the unit circuit PX may include a storage capacitor 71, an organic EL element 76, and a transistor 77 instead of the capacitive element 70 in the first embodiment described above with reference to FIG. . In this case, an organic EL display device can be realized by the semiconductor device. Here, according to this modification, even if the parasitic capacitances of the first transistor 31 and the second transistor 32 vary due to manufacturing variations, the capacitance from the data line 50 via the first transistor 31 and the second transistor 32 is increased. Since the data voltage can be reliably applied to the storage capacitor 71 and the organic EL element 76, which are characteristic elements, display spots can be reduced or prevented. In FIG. 11, the transistor 77 has its gate electrically connected to the storage capacitor 71, its source electrically connected to a predetermined potential VEL, and its drain electrically connected to the organic EL element 76. Yes.

Second Embodiment
A semiconductor device according to the second embodiment will be described with reference to FIGS. 12 to 15, the same reference numerals are given to the same components as the components according to the first embodiment shown in FIGS. 1 to 8, and description thereof will be omitted as appropriate.

  The semiconductor device according to the second embodiment differs from the first embodiment described above in terms of the timing for switching the ON state and the OFF state of the second transistor 32 (in other words, the waveform of the second gate signal G2). Is configured in substantially the same manner as the semiconductor device 1 according to the first embodiment described above.

  12 and 13 are timing charts for explaining the operation of the semiconductor device according to the second embodiment.

  FIG. 12 is a timing chart having the same concept as FIG. 3 described above, and is supplied to the first gate signal Gi1, the second gate signal Gi2, the data signal DATAk, and the unit circuit PX (i, k) in the second embodiment. The change over time of the data signal DATA (i, k) to be performed is shown.

  FIG. 13 is a timing chart having the same concept as in FIG. 4 described above. In the second embodiment, the first gate signal G1 and the second gate signal G2, the voltage Vp at the point P shown in FIG. The change with time of the voltage Vc applied to one of the capacitor electrodes is shown.

  12 and 13, in the present embodiment, the first gate signal G1 changes from the high level potential VH to the low level after the time t1 when both the first gate signal G1 and the second gate signal G2 become the high level potential VH. The timing at which the level potential VL changes is the same as the timing at which the second gate signal G2 changes from the high level potential VH to the low level potential VL (both at time t3). That is, in this embodiment, both the first transistor 31 and the second transistor 32 are turned off simultaneously (time point t3) after both the first transistor 31 and the second transistor 32 are turned on (time point t1). Then, the second transistor 32 is turned on again (at time t4).

  Specifically, in this embodiment, when the data voltage Vdata corresponding to the data signal DATA is applied to the capacitive element 70, first, as in the first embodiment described above, the first transistor 31 and the second transistor 32 are first used. The first gate signal G1 and the second gate signal G2 are supplied from the row driving circuit 110 via the first gate line 41 and the second gate line 42 so that both are turned on. To be supplied.

  That is, as shown in FIG. 13, when the data voltage Vdata corresponding to the data signal DATA is applied to the capacitive element 70, first, during the period from the time point t1 to the time point t3, the first gate signal G1 and the second gate signal G1 are output. Both gate signals G2 take the high level potential VH. Thus, as in the first embodiment described above, the potential Vc of one capacitive electrode of the capacitive element 70 becomes the data voltage Vdata, and the voltage Vp at the point P also becomes the data voltage Vdata.

  Next, during the period from the time point t3 to the time point t4, both the first gate signal G1 and the second gate signal G2 take the low level potential VL. That is, at the time point t3, both the first gate signal G1 and the second gate signal G2 simultaneously change from the high level potential VH to the low level potential VL.

  FIG. 14 is a schematic diagram for explaining the operation of the semiconductor device according to the second embodiment, and shows the operation state of the unit circuit PX during the period from the time point t3 to the time point t4.

  As shown in FIG. 14, during the period from the time point t3 to the time point t4, both the first gate signal G1 and the second gate signal G2 take the low level potential VL, so that the first transistor 31 and the second transistor Both 32 are turned off.

  Here, when both the first transistor 31 and the second transistor 32 are turned off at time t3, a feedthrough voltage is generated due to the parasitic capacitance 922 between the gate and the drain of the second transistor 32. (In other words, the movement of the charge ΔQ from the drain side to the gate side of the second transistor 32 occurs), and the potential Vc of one capacitive electrode of the capacitive element 70 decreases from the data voltage Vdata to the potential V1. There is a risk (see FIG. 13). The potential V1 can be expressed by the above-described formula (1).

  Further, since both the first transistor 31 and the second transistor 32 are turned off at the time point t3, the voltage Vp at the point P is caused by the parasitic capacitance 912 between the gate and the drain of the first transistor 31. The feedthrough voltage generated (in other words, the movement of the charge ΔQ from the drain side to the gate side of the first transistor 32) and the feed generated due to the parasitic capacitance 921 between the gate and the source of the second transistor 32. Due to the through voltage (in other words, the movement of the charge ΔQ from the source side to the gate side of the second transistor 32), the voltage drops from the data voltage Vdata to the potential V3. Here, the potential V3 can be expressed by the following formula (3).

V3 = Vdata−ΔVg (3)
Next, in FIG. 13, after the time point t4, the first gate signal G1 remains at the low level potential VL, and the second gate signal G2 takes the high level potential VH. That is, at time t4, the second gate signal G2 changes from the low level potential VL to the high level potential VL, and the first gate signal G1 is maintained at the low level potential VL.

  FIG. 15 is a schematic diagram for explaining the operation of the semiconductor device according to the present embodiment, and shows the operating state of the unit circuit PX during the period after time t4.

  As shown in FIG. 15, after the time point t4, the first gate signal G1 takes the low level potential VL and the second gate signal G2 takes the high level potential VH, thereby turning off the first transistor 31. At the same time, the second transistor 32 is turned on.

Here, when the second transistor 32 is turned on at the time point t4, the voltage Vp at the point P is a feedthrough voltage generated due to the parasitic capacitance 921 between the gate and the source of the second transistor 32 ( In other words, due to the movement of the charge ΔQ from the gate side to the source side of the second transistor 32, the potential rises from the potential V3 to become the potential V4 (see FIG. 13).
Here, the potential V4 can be expressed by the following formula (4).

V4 = Vdata−ΔVg × Cpar / (3 × Cpar + Cload) (4)
Further, since one capacitive electrode of the capacitive element 70 is electrically connected to the point P by the second transistor 32 that is turned on, the potential Vc of one capacitive electrode of the capacitive element 70 is the potential V1. Rises to a potential V4 (see FIG. 13).

  As described above, according to the present embodiment, one capacitive electrode of the capacitive element 70 which has been lowered to the potential V1 by the feedthrough voltage generated due to the parasitic capacitance 922 between the gate and the drain of the second transistor 32. The potential Vc can be raised to the potential V4 (that is, the potential Vc of one capacitive electrode of the capacitive element 70 can be brought close to the data voltage Vdata to be applied).

  Further, particularly in the present embodiment, after both the first transistor 31 and the second transistor 32 are turned on at the time point t1, both the first transistor 31 and the second transistor 32 are simultaneously turned off at the time point t3. Since the first transistor 31 and the second transistor 32 are driven so that the second transistor 32 is turned on again at the time t4, the first transistor 31 and the second transistor 32 are compared with the first embodiment described above. The driving sequence for driving the transistor 32 can be simplified, and the speed at which the data voltage Vdata is applied to the capacitive element 70 can be increased.

<Electronic equipment>
Next, electronic devices to which the above-described semiconductor device is applied will be described with reference to FIGS. In the following, the case where the above-described semiconductor device is configured as an electrophoretic display device as in the above-described second modification and applied to electronic paper and an electronic notebook will be taken as an example.

  FIG. 16 is a perspective view illustrating a configuration of the electronic paper 1400.

  As illustrated in FIG. 16, the electronic paper 1400 includes the above-described semiconductor device as a display portion 1401. The electronic paper 1400 has flexibility, and includes a main body 1402 formed of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 17 is a perspective view illustrating a configuration of the electronic notebook 1500.

  As shown in FIG. 17, an electronic notebook 1500 is obtained by bundling a plurality of electronic papers 1400 shown in FIG. 16 and sandwiching them between covers 1501. The cover 1501 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

  Since the above-described electronic paper 1400 and electronic notebook 1500 include the above-described semiconductor device, high-quality image display can be performed.

  In addition to these, the semiconductor device according to the present embodiment described above can be applied to a display unit of an electronic device such as a wristwatch, a mobile phone, or a portable audio device.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and a semiconductor device with such a change, A driving method of a semiconductor device, an electro-optical device, and an electronic apparatus are also included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 31 ... 1st transistor, 32 ... 2nd transistor, 41 ... 1st gate line, 42 ... 2nd gate line, 50 ... Data line, 70 ... Capacitive element, 110 ... Row drive circuit, 120 ... Column drive circuit, 911 , 912, 921, 922 ... parasitic capacitance, PX ... unit circuit

Claims (9)

A capacitive element;
A data line to which a data voltage to be applied to the capacitive element is applied;
A first transistor electrically connected between the capacitive element and the data line;
A second transistor electrically connected between the first transistor and the capacitive element;
When the data voltage is applied to the capacitive element, both the first and second transistors are turned on, and the second transistor is turned on after the timing when both are turned on. The first state so that it is turned on again after being turned off, and at the same time as the timing when it is turned off once or after the timing when it is turned on again. And a driving means for driving the first and second transistors so that one transistor is turned off.   The driving means is configured to turn off the first transistor so that the first transistor is turned off after the timing at which it is once turned off and before the timing at which it is turned on again. The semiconductor device according to claim 1, wherein the semiconductor device is driven.   2. The semiconductor device according to claim 1, wherein the driving unit drives the first transistor so that the first transistor is turned off at the same time when the first transistor is turned off.   4. The semiconductor device according to claim 1, wherein the data voltage is constant from a timing when both are turned on to a timing when the first transistor is turned off. 5. The capacitive element and the first and second transistors are provided in a matrix of n rows × m columns (where m and n are natural numbers) on a substrate, respectively.
One data line is provided for each column,
The driving means includes, for each row, a first gate line electrically connected to a gate of the first transistor and a second gate line electrically connected to a gate of the second transistor. The semiconductor device according to claim 1, wherein the semiconductor device includes:   The semiconductor device according to claim 1, wherein the capacitive element is a capacitor, a transistor, a liquid crystal element, an organic electroluminescence element, or an electrophoretic element. A capacitive element; a data line to which a data voltage to be applied to the capacitive element is applied; a first transistor electrically connected between the capacitive element and the data line; And a second transistor electrically connected between the transistor and the capacitive element.
When applying the data voltage to the capacitive element,
A first step of driving the first and second transistors such that both the first and second transistors are in an on state;
A second step of driving the first and second transistors so that the second transistor is once turned off after the timing when both are turned on;
A third step of driving the first and second transistors so that the second transistor is turned on again after being turned off;
At the same time as the timing when the transistor is once turned off, or after the timing before the timing when the transistor is turned on again, the first and second transistors are turned on. And a fourth step of driving the transistor. A method for driving a semiconductor device, comprising:   An electro-optical device comprising the semiconductor device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 8.

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