JP2008015282A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display attaining cost reduction and having excellent performance. <P>SOLUTION: In the liquid crystal display provided with a liquid crystal layer LQ interposed between an array substrate 12 and a counter substrate 14 and having a display part 10A comprising a plurality of display pixels PX disposed in a matrix shape and a peripheral part 10B enclosing the display part 10A, the array substrate 12 has pixel electrodes PE respectively disposed in the display pixels PX, scanning lines SL disposed along columns of the display pixels PX and compensation lines W disposed to be nearly parallel to the scanning lines SL in the display part 10A and the array substrate 12 includes a scanning line driving circuit SD for outputting a scanning signal for selecting the display pixels PX for every column via the scanning lines SL and a compensation circuit D3 for outputting a compensation signal for forming such a storage capacitance C that compensates potential drop by parasitic capacitance 5 of the display pixels PX between the pixel electrodes PE and the compensation lines W to the compensation lines W in the peripheral part 10B. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device.

  Currently, liquid crystal display devices are widely used as display devices for laptop computers and notebook computers.

  As a liquid crystal display device, a liquid crystal display device (TFT-LCD) using a thin film transistor (TFT) as an active element such as a pixel switch is widely used.

  A liquid crystal display device generally has a liquid crystal display panel including a display unit including liquid crystal and display pixels arranged in a matrix. The liquid crystal display panel includes a pair of substrates facing each other, that is, an array substrate and a counter substrate, and a liquid crystal layer sandwiched between the pair of substrates. This liquid crystal display panel includes a display unit composed of display pixels arranged in a matrix. The liquid crystal display device has a drive circuit that drives the plurality of display pixels.

  When this liquid crystal display device is driven by, for example, a one-frame inversion driving method, a potential drop of the pixel electrode occurs due to the parasitic capacitance generated between the source electrode and the gate electrode of the pixel switch. A DC voltage component is applied between them.

  As a driving method that effectively compensates for such a potential drop due to parasitic capacitance, a capacitive coupling driving method has been proposed (see Patent Document 1). In this driving method, a compensation signal for compensating for a potential drop is superimposed on the scanning signal and input.

When the liquid crystal display device is driven by this capacitive coupling driving method, there is an advantage that a potential drop due to parasitic capacitance can be eliminated and sufficient contrast can be obtained even if the amplitude of the image signal is low.
Japanese Patent Laid-Open No. 2004-70367

  However, in the above capacitive coupling driving method, the potential for compensating the potential drop due to the parasitic capacitance is superimposed on the scanning signal and input to the scanning line, so that the maximum amplitude of the signal input to the scanning line increases. If it does so, it will be necessary to raise the proof pressure of the pixel switch connected to the scanning line, and it may lead to increase in chip size and cost.

  Furthermore, if a driving circuit for driving by the capacitive coupling driving method is provided outside the liquid crystal display panel, it is difficult to realize a reduction in size and cost of the liquid crystal display device.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal display device having excellent performance while realizing cost reduction of the liquid crystal display device.

  A liquid crystal display device according to an aspect of the present invention includes a liquid crystal layer sandwiched between a first substrate and a second substrate, a display unit including a plurality of display pixels arranged in a matrix, and a periphery surrounding the display unit A liquid crystal display device having a display unit, wherein the first substrate includes a pixel electrode disposed in each of the display pixels and a scanning line disposed along a row of the display pixels in the display unit, And a scanning line that outputs a scanning signal for selecting the display pixel for each row through the scanning line at a peripheral portion of the first substrate. A line drive circuit, and a compensation circuit that outputs a compensation signal to the wiring for forming a storage capacitor that compensates for a potential drop due to a parasitic capacitance of the display pixel between the pixel electrode and the wiring. .

  According to the present invention, it is possible to provide a liquid crystal display device having excellent performance while reducing the cost of the liquid crystal display device.

  Hereinafter, a liquid crystal display device according to a first embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the liquid crystal display device according to the present embodiment has a substantially rectangular liquid crystal display panel 10. The liquid crystal display panel 10 has a pair of substrates, that is, an array substrate 12 and a counter substrate 14 disposed so as to face each other. A liquid crystal layer LQ is sandwiched between the array substrate 12 and the counter substrate.

  The liquid crystal display panel 10 includes a display unit 10A including display pixels PX arranged in a matrix and a peripheral unit 10B surrounding the display unit 10A. In the case of the liquid crystal display device according to the present embodiment, the liquid crystal display panel 10 has a substantially rectangular display portion 10A. The display unit 10A has a first end side E1 and a second end side E2 facing each other.

  In the display unit 10A, each display pixel PX is provided with a pixel electrode PE and a pixel switch SW connected to the pixel electrode PE. The display unit 10A includes a plurality of scanning lines SL (SL1 to SLm) arranged along a row where the display pixels PX are arranged, and a plurality of signal lines DL arranged along a column where the display pixels PX are arranged. (DL1 to DLn) are arranged. Further, compensation wiring W (W1 to Wm) extending substantially parallel to the scanning line SL is disposed in the display unit 10A.

  In the present embodiment, the compensation wiring W is disposed, for example, below the pixel electrode PE as shown in FIG. That is, the compensation wiring W is disposed in the same layer as the signal line DL and the drain electrode of the pixel switch, or is disposed in the same layer as the gate electrode of the pixel switch SW. Further, the compensation wiring W may be arranged side by side with the pixel electrode PE, for example, as shown in FIG. That is, the compensation wiring W may be disposed in the same layer as the pixel electrode PE. The pixel switch SW includes a thin film transistor having an amorphous silicon semiconductor layer.

  The gate electrode of the pixel switch SW is connected to the corresponding scanning line SL (or formed integrally). The source electrode is connected to the corresponding signal line DL (or formed integrally). The drain electrode is connected to the pixel electrode PE.

  Further, a storage capacitor C is provided between the pixel electrode PE and the compensation wiring W. That is, the scanning line SL is connected to the pixel electrode PE through the pixel switch SW, and the compensation wiring W is connected to the pixel electrode PE through the storage capacitor C.

  On the counter substrate 14, a counter electrode CE is arranged to face the plurality of pixel electrodes PE. The liquid crystal layer LQ is sandwiched between the pixel electrode PE of the array substrate 12 and the counter electrode CE of the counter substrate 14.

  In the peripheral portion 10B, the array substrate 12 has a scanning line driving circuit SD and a compensation circuit D3. The scanning line driving circuit SD is disposed along the first end E1 of the display unit 10A. The compensation circuit D3 is disposed along the second end side E2 of the display unit 10A. That is, the scanning line driving circuit SD and the compensation circuit D3 are disposed on both sides of the display unit 10A on the array substrate 12.

  A pair of elongated printed wiring boards 16 are electrically connected to one side edge of the liquid crystal display panel 10. The signal line drive circuit DD for supplying the image signal Vs to the liquid crystal display panel 10 is disposed on the elongated rectangular flat circuit board 18 via the printed wiring board 13.

  That is, the scanning line drive circuit SD outputs a scanning signal Vg according to an external clock signal, and sequentially selects the scanning lines SL. Then, the signal line driver circuit DD sequentially outputs the image signal Vs corresponding to the signal line DL in accordance with an external clock signal. When the scanning signal Vg is output to the scanning line SL and the image signal Vs is output to the signal line DL, as shown in FIG. 1, a parasitic capacitance 5 is generated between the gate electrode and the drain electrode of the pixel switch SW.

  The image signal Vs output from the signal line drive circuit DD is applied to the pixel electrode PE via the pixel switch SW. Then, an electric field corresponding to each display pixel PX is generated between the pixel electrode PE and the counter electrode CE, and the alignment state of the liquid crystal layer LQ is controlled by the electric field.

  At this time, the compensation circuit D3 outputs the compensation signal Ve to the compensation wiring W in the holding period in which the image signal Vs applied to the pixel electrode PE is held. That is, the compensation circuit D3 outputs the compensation signal Ve having a polarity opposite to that of the image signal Vs to the compensation wiring W during the holding period in which the image signal Vs is applied to the pixel electrode PE. Accordingly, when the positive image signal Vs is applied to the pixel electrode PE, the compensation circuit D3 outputs the negative compensation signal Ve (−) to the compensation wiring W during the holding period. When the negative image signal Vs is applied to the pixel electrode PE, the compensation circuit D3 outputs the positive compensation signal Ve (+) to the compensation wiring W during the holding period.

  Then, the compensation wiring W is disposed below the pixel electrode PE as shown in FIG. 2, or is arranged side by side with the pixel electrode PE as shown in FIG. Due to the potential difference from W, a storage capacitor C is generated. This holding capacitor C can be combined with the pixel potential Vd between the pixel electrode PE and the counter electrode CE, and the potential drop of the pixel potential Vd due to the parasitic capacitance 5 can be suppressed.

  Next, a method for driving the liquid crystal display device will be described. FIG. 4 shows output waveforms of the scanning line driving circuit SD, the signal line driving circuit DD, and the compensation circuit D3 of the liquid crystal display device according to the present embodiment.

  That is, the scanning line driving circuit SD outputs the scanning signal Vg according to a predetermined timing. The pixel switch SW is on / off controlled by the scanning signal Vg. In this embodiment, the pixel switch SW is turned on when the potential of the scanning signal Vg is Vgt, and the pixel switch SW is turned off when the potential of the scanning signal Vg is Vgb.

  The signal line drive circuit DD outputs the image signal Vs according to a predetermined timing. That is, the image signal Vs for displaying the image displayed on the corresponding display pixel PX is output to the signal line DL at the timing when the pixel switch SW is turned on.

  The compensation circuit D3 outputs a compensation signal Ve composed of two potentials Ve (+) and Ve (−) for compensating for a potential drop due to the parasitic capacitance 5 to the compensation wiring W. That is, the compensation signal Ve is output to the compensation wiring W during the holding period after the potential of the scanning signal Vg becomes Vgt and the image signal Vs is applied to the pixel electrode PE, and the potential of the compensation wiring W is set to a predetermined potential.

  At this time, as shown in FIG. 2, a counter voltage Vc is applied to the counter electrode CE. As a result, a storage capacitor C generated between the pixel electrode PE and the compensation wiring W is generated.

  That is, the pixel switch SW of the display unit 10A is turned on during a period in which the scanning signal Vg applied from the scanning line driving circuit SD to the scanning line SL is on potential (Vgt). At this time, the image signal Vs transmitted from the signal line driving circuit DD to the signal line DL is applied to the pixel electrode PE via the pixel switch SW selected by the scanning line driving circuit SD.

  Subsequently, when the scanning signal Vg output from the scanning line driving circuit SD changes to the off potential (Vgb), the pixel switch SW is turned off. Then, the pixel potential Vd is held by the liquid crystal capacitor and the holding capacitor C. At this time, the pixel potential Vd shifts according to the potential of the compensation signal Ve supplied from the compensation circuit D3 via the storage capacitor C and the compensation wiring W. That is, the pixel potential Vd is compensated by the storage capacitor C as shown in FIG.

  In this embodiment, when one frame period ends and the next frame is reached, the polarity of the image signal Vs is inverted with respect to the center potential, and the same operation is repeated.

  As described above, according to the liquid crystal display device and the driving method thereof according to the present invention, the scanning signal in the conventional capacitive coupling driving method is converted into the scanning signal Vg composed of the ON potential (Vgt) and the OFF potential (Vgb) of the switching element. The compensation signal Ve, that is, two potentials (Ve (+), Ve (−)) for compensating for the potential drop due to the parasitic capacitance 5 can be supplied separately.

  That is, conventionally, in the capacitive coupling driving method, a voltage pulse for compensating for a potential drop is superimposed on the scanning signal. For this reason, the maximum amplitude of the scanning signal Vg is increased, and as a result, it may be necessary to increase the breakdown voltage of the switching element. In this case, the chip size is increased and the cost is increased.

  On the other hand, according to the liquid crystal display device and the driving method thereof of the present invention, the original scanning signals (Vgt and Vgb) for on / off control of the switching element and the potential drop due to the parasitic capacitance 5 are compensated. The bias potential Ve is applied separately through another circuit and wiring.

  Therefore, the maximum amplitude of the scanning signal can be significantly reduced as compared with the conventional case. As a result, the breakdown voltage of the switching element can be lowered without impairing the advantages of the capacitive coupling driving method, and the chip size and cost can be reduced.

  That is, according to the liquid crystal display device according to the present embodiment, it is possible to reduce the cost of the liquid crystal display device and provide a liquid crystal display device having excellent performance and a driving method thereof.

  Further, since the compensation circuit D3 is operated at a frequency for driving the circuit on the scanning side, a thin film transistor using amorphous silicon having low mobility can be realized as an active element. That is, according to the liquid crystal display device according to the above-described embodiment, it is possible to realize a liquid crystal display panel at a lower price than the case where a thin film transistor using polycrystalline silicon is employed as an active element.

  Further, in the liquid crystal display panel 10 of the liquid crystal display device according to the above embodiment, since the scanning line driving circuit SD and the compensation circuit D3 are arranged on both sides of the display unit 10A, compared with the case of arranging on one side. The area of the peripheral portion 10B of the liquid crystal display panel 10 can be reduced. Therefore, according to the liquid crystal display device according to the present embodiment, it is possible to reduce the size of the liquid crystal display device.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

The figure which shows schematically the structural example of the liquid crystal display panel of the liquid crystal display device which concerns on one Embodiment of this invention. Sectional drawing for demonstrating the example of arrangement | positioning of the pixel electrode and compensation wiring of the liquid crystal display device shown in FIG. Sectional drawing for demonstrating the other example of arrangement | positioning of the pixel electrode and compensation wiring of the liquid crystal display device shown in FIG. FIG. 3 is a diagram illustrating an example of a driving waveform of the liquid crystal display device illustrated in FIG. 1.

Explanation of symbols

  C: Retention capacitance, SL: Scanning line, W: Compensation wiring, SD: Scanning line drive circuit, D3: Compensation circuit, LQ ... Liquid crystal layer, PX ... Display pixel, PE ... Pixel electrode, 5 ... Parasitic capacitance, 10A ... Display Part, 10B, peripheral part, 12 ... array substrate, 14 ... counter substrate

Claims (3)

A liquid crystal display device having a liquid crystal layer sandwiched between a first substrate and a second substrate, and having a display portion composed of a plurality of display pixels arranged in a matrix and a peripheral portion surrounding the display portion. ,
The first substrate includes a pixel electrode disposed in each of the display pixels, a scanning line disposed along a row of the display pixels, and a wiring disposed substantially parallel to the scanning line in the display unit. And having
The first substrate compensates for a potential drop due to a parasitic capacitance of the display pixel, and a scanning line driving circuit that outputs a scanning signal for selecting the display pixel for each row via the scanning line in the peripheral portion. A liquid crystal display device comprising: a compensation circuit that outputs a compensation signal for forming such a storage capacitor between the pixel electrode and the wiring to the wiring. The display unit has a first end side and a second end side facing the first end side,
The scanning line driving circuit is disposed along a first end side of the display unit,
The liquid crystal display device according to claim 1, wherein the compensation circuit is disposed along the second end side.   The liquid crystal display device according to claim 1, wherein the compensation circuit includes an active element using amorphous silicon.

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