JP2011151056A - Semiconductor device, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for maximally reducing the inclination of a semiconductor chip, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device is constituted in such a way that a region with a plurality of source electrodes formed therein and a region with a drain electrode formed therein are formed at substantially symmetrical positions via a semiconductor element. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Flip chip (face-down) mounting in which the surface of the semiconductor chip on which the active region is formed faces the module substrate and the semiconductor chip is mounted on the module substrate with a solder layer is disclosed in, for example, Japanese Patent Laid-Open No. 2002-110871 .
JP 2002-110871 A

  In the configuration in which the front and back surfaces of the semiconductor chip are connected to the module substrate as in Document 1, the semiconductor chip is likely to be inclined in the flip chip mounting process. When the inclination occurs, stress (strain) concentrates on the solder layer of the connection portion. Such stress concentration affects the reliability of the semiconductor device. In particular, in a bare chip smaller than 5 mm square, the inclination of the semiconductor chip is likely to occur. Therefore, in a semiconductor device using such a bare chip, the influence on reliability becomes more remarkable.

  The inventor of the present invention paid attention to a problem that has not been noticed in the past, and made an invention described later to solve it. An object of the present invention is to provide a semiconductor device capable of reducing the tilt of a semiconductor chip to the maximum and a method for manufacturing the semiconductor device.

In order to achieve the above object, a semiconductor device according to a representative invention of the present application is:
A first wiring board;
A plurality of sources having a first surface and a second surface opposite to the first surface, the first surface being connected to the first wiring board via a first solder layer A semiconductor element having an electrode formed thereon and a drain electrode formed on the second surface;
A second wiring board connected to the drain electrode via a second solder layer;
The region in which the plurality of source electrodes are formed and the region in which the drain electrode is formed are arranged at substantially symmetrical positions with the semiconductor element interposed therebetween.

In addition, a method for manufacturing a semiconductor device according to another invention of the present application is as follows:
Preparing a first wiring board;
Connecting a plurality of source electrodes of a semiconductor element and the first wiring board via a first solder layer by a first reflow;
Thereafter, a second wiring board is connected via a second solder layer to the drain electrode of the semiconductor element formed on the surface opposite to the surface on which the plurality of source electrodes are formed by a second reflow. A process,
The region in which the plurality of source electrodes are formed and the region in which the drain electrode is formed are arranged at substantially symmetrical positions with the semiconductor element interposed therebetween.

According to the representative invention of the present application, a semiconductor device in which the inclination of the semiconductor element is reduced to the maximum can be realized. As a result, the reliability against thermal fatigue of the solder layer as the connection portion can be improved.

Sectional schematic diagram of the mounting structure of the semiconductor device according to the embodiment of the present invention FIG. 1 is a schematic top view (drain electrode side) of the semiconductor device of FIG. 1 is a schematic top view (source electrode side) of the semiconductor device of FIG. Another layout of the gate electrode according to the embodiment Schematic top view of semiconductor devices used in the embodiments and comparative examples Comparison results between the embodiment and the comparative example Partial sectional schematic view according to another embodiment Schematic top view according to another embodiment

  Embodiments of the present invention will be described below with reference to the drawings. The drawings according to the present embodiment are schematically shown for easy understanding. In this embodiment, the example which applied this invention to the semiconductor device used for a power converter device etc. is shown as an example, However, It is not limited to this. FIG. 1 shows a schematic cross-sectional view of the mounting structure of the semiconductor device according to the present embodiment, and FIG. 2 shows a schematic top view on the drain electrode side in the AA ′ cross-section of the semiconductor device of FIG. FIG. 3 is a schematic top view on the source electrode side in the section AA ′ of the semiconductor device of FIG. In this embodiment, a semiconductor chip in which an active region or a circuit region is formed may be referred to as a semiconductor element. In particular, a semiconductor chip or a semiconductor element whose surface is not sealed with a resin is a resin-sealed type. It is called a bare chip to distinguish it from those.

  FIG. 1 shows a semiconductor device 100 of this embodiment. The semiconductor device 100 includes a semiconductor chip 1. The semiconductor chip 1 is a MOS transistor and is formed by a known semiconductor process. In the circuit region formed on the first surface side of the semiconductor chip 1, a plurality of source electrodes 2 and gate electrodes 3 are formed of a conductive material as shown in FIG. In the present embodiment, as shown in FIG. 3, 16 source electrodes 2 are arranged in a matrix, and a region where the plurality of source electrodes 2 are arranged is defined as a source electrode formation region 20. That is, the inner side of the region arranged on the outermost side and connecting the outermost portions of adjacent source electrodes with a straight line is referred to as a source electrode formation region in this embodiment. The matrix arrangement of the source electrodes can be appropriately changed depending on the design. That is, the number of rows and columns can be changed as appropriate, and is not limited to the four rows and four columns of the present embodiment. In the configuration shown in FIG. 3, the gate electrode 3 is formed outside the source electrode formation region 20, but the gate electrode 3 is formed inside the source electrode formation region 20 as shown in FIG. There is also a case.

  The source electrode 2 and the gate electrode 3 are connected to the electrode 6 formed on the first wiring board 5 via the solder balls 4, respectively. A circuit pattern is formed on the first wiring board 5, and the plurality of electrodes 6 are electrically connected to a predetermined circuit.

  A drain electrode 7 is formed on the second surface opposite to the first surface of the semiconductor chip 1. The drain electrode 7 is made of a conductive material, and is formed in a region that is substantially symmetrical with the source electrode formation region 20. That is, the region where the drain electrode 7 is formed and the source electrode forming region 20 are opposed to each other with the semiconductor chip 1 interposed therebetween. The drain electrode 7 is connected to an electrode 9 formed on the second wiring board 8 through a solder layer 10.

  Next, a mounting process of the semiconductor device 100 will be described. The mounting method performed here is called flip-chip (face-down) mounting. When mounting the semiconductor chip 1, first, solder balls 4 are formed on the source electrode 2 and the gate electrode 3 on the circuit surface, and the electrodes 6 of the first wiring board 5 formed in advance at positions corresponding to these electrodes. After aligning to, join by reflow.

  Next, in order to join the drain electrode 7 of the semiconductor chip 1, solder is disposed on the first wiring board 5 on which the semiconductor chip 1 is mounted and formed in advance at a position corresponding to the drain electrode of the semiconductor chip 1. The second wiring board 8 is aligned with the electrode 9 and reflowed again to be joined via the solder layer 10. In this way, the mounting of the semiconductor device 100 is completed.

  In a general semiconductor device mounting process, since reflow is performed twice, there is a possibility that the semiconductor chip 1 may be inclined during the second reflow. In other words, the surface tension of the solder generated during the second reflow may cause a force in the direction of crushing the solder balls formed in the first reflow on the semiconductor chip. In particular, when the source electrode and the gate electrode are not formed uniformly over the entire circuit surface of the semiconductor chip, the area of the solder ball that receives the surface tension generated on the drain electrode side differs depending on the location, and the second time During the reflow process, the semiconductor chip may be tilted.

  On the other hand, in the present embodiment, the drain electrode 7 is formed in a region that is substantially symmetrical with the source electrode formation region 20. That is, the region where the drain electrode 7 is formed and the source electrode forming region 20 are opposed to each other with the semiconductor chip 1 interposed therebetween. The electrode 9 of the second wiring board 8 joined to the drain electrode 7 is formed in a region equal to the source electrode formation region 21. That is, the drain electrode formation region 21 and the source electrode formation region 20 are formed symmetrically with respect to the neutral plane in the thickness direction of the semiconductor chip 1. Accordingly, the surface tension generated on the drain electrode side can be substantially equally applied to the plurality of source electrode sides, so that the inclination of the semiconductor chip can be reduced to the maximum during the second reflow.

  In this case, an area equal to the area corresponding to the source electrode forming area 20 surrounded by the broken line shown in FIG. 3 is used as the drain electrode forming area 21, and the drain electrode 7 of the semiconductor element 1 and the second wiring board 8 joined thereto. In this case, the drain electrode 7 of the semiconductor element 1 was subjected to a resist treatment so that the solder did not spread. Since this resist treatment is intended to prevent the solder from spreading, a metal such as Al having low solder wettability may be deposited in advance, or a resist treatment formed on a wiring board may be applied.

  Here, a result of comparison between the semiconductor device of the present embodiment and a general semiconductor device in which the drain electrode is formed on the entire second surface of the semiconductor chip will be described with reference to FIGS. In this comparison, a semiconductor electrode having a long side: 3.9 mm, a short side: 2.8 mm, and a thickness: 0.28 mm is arranged with a source electrode having a diameter of 0.2 mm arranged in a matrix at a pitch shown in FIG. In this embodiment, the drain electrode is formed in a region (drain electrode formation region 21) symmetrical to the source electrode formation region 20 through the chip 1, and the entire surface on the second surface of the semiconductor chip (two points in FIG. 5). A comparative example is one in which a drain electrode is formed in a drain electrode forming region 21 ′) indicated by a chain line.

  After manufacturing the semiconductor devices of this embodiment and the comparative example, the resin was cured after sealing with an embedded resin in a state where the semiconductor device was erected. Then, it grind | polished to the observation position with the water resistant abrasive paper, and observed the cross section. From one end to the other end of the drain electrode, the height of the semiconductor chip is observed, and the height (H ′) of the semiconductor chip in the comparative example when the height (H) of the semiconductor chip in this embodiment is 1. The ratio is shown in FIG.

  According to FIG. 6, it can be seen that the configuration of this embodiment has a significantly reduced inclination of the semiconductor chip compared to the configuration of the comparative example. That is, according to this embodiment, a semiconductor device in which the inclination of the semiconductor chip is reduced to the maximum can be realized. As a result, an improvement in reliability against thermal fatigue of the solder layer that is the connecting portion can be expected. In particular, if the configuration of this embodiment is applied to a part that generates a large amount of heat, such as an inverter circuit for driving a motor, thermal fatigue of the solder joint can be reduced, and a highly reliable motor drive device can be realized. it can.

  Furthermore, another embodiment will be described with reference to FIG. The electrode 9 ′ and the solder layer 10 ′ in this embodiment correspond to the electrode 9 and the solder layer 10 described above, respectively, and spread outwardly by the extended portion E on the second wiring board 8 side rather than the drain electrode 7 side. Is formed. The extended portion E is called a solder fillet, and in this embodiment, the solder fillet is formed outside the drain electrode, so that a downward force is hardly generated in the drain electrode. Thereby, the inclination of the semiconductor chip can be further reduced. According to the inventor's knowledge, it is preferable that the electrode 9 ′ is about 10% larger than the drain electrode 7. Also, as shown in FIG. 8, the same effect can be obtained by providing an extended portion of the electrode at a location corresponding to the corner of the semiconductor chip 1.

  The present invention can be applied to a flip-chip mounting type semiconductor device.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Source electrode 3 Gate electrode 4 Solder ball 5 First wiring board 6 Electrode 7 Drain electrode 8 Second wiring board 9 Electrode 10 Solder layer 20 Source electrode formation area 21 Drain electrode formation area

Claims (6)

A first wiring board;
A plurality of sources having a first surface and a second surface opposite to the first surface, wherein the first surface is connected to the first wiring board via a first solder layer on the first surface. A semiconductor element having an electrode formed thereon and a drain electrode formed on the second surface;
A second wiring board connected to the drain electrode via a second solder layer;
The region where the plurality of source electrodes are formed and the region where the drain electrodes are formed are arranged at substantially symmetrical positions with the semiconductor element interposed therebetween.   The semiconductor device according to claim 1, wherein the second solder layer extends outward on the second wiring board side than on the drain electrode side.   The semiconductor device according to claim 1, wherein the semiconductor element is a bare chip.   A motor drive device, wherein a motor is driven using an inverter device configured by the semiconductor device according to claim 1. Preparing a first wiring board;
Connecting a plurality of source electrodes of a semiconductor element and the first wiring board via a first solder layer by a first reflow;
Thereafter, a second wiring board is connected via a second solder layer to the drain electrode of the semiconductor element formed on the surface opposite to the surface on which the plurality of source electrodes are formed by a second reflow. A process,
The method for manufacturing a semiconductor device, wherein the region in which the plurality of source electrodes are formed and the region in which the drain electrode is formed are disposed at substantially symmetrical positions with the semiconductor element interposed therebetween. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the second solder layer extends outward on the second wiring board side than on the drain electrode side.

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