JP2011146620A - Display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device of low power consumption that is unlikely to increase in off-leakage current due to a pixel electrode potential. <P>SOLUTION: The display device includes a first substrate and a second substrate arranged opposite each other, a display element disposed between the first substrate and second substrate, a thin-film transistor 24 formed on the display element side of the first substrate, a pixel electrode 21 formed on the display element side of the thin-film transistor 24 so as to overlap with the thin-film transistor 24 in plane view, and a shield electrode 26 formed in a layer between the thin-film transistor 24 and pixel electrode 21. The shield electrode 26 is arranged at a position where it overlaps with at least a lightly doped region of the thin-film transistor 24 in plane view. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device and an electronic device using a thin film transistor.

  The pixel circuit of the active matrix substrate includes at least a pixel switching thin film transistor (TFT). As a method for forming a TFT, there is a self-aligned structure in which impurities are implanted using a gate electrode as a mask. A TFT formed with this structure has a small parasitic capacitance and can make the characteristics of the TFT uniform, but has a problem that an off-leakage current is large. If such a TFT having a large off-leakage current is used in the pixel circuit, it causes an increase in current consumption, display unevenness, malfunction, and the like.

  Therefore, an active matrix substrate uses an LDD (Lightly Doped Drain) structure in which regions with low impurity concentration are formed at both ends of a channel region, or an offset structure TFT in which regions where impurities are not implanted are formed. In this type of TFT, since the electric field at the drain end is relaxed, off-leakage current can be reduced. Therefore, by using a TFT with an LDD structure or an offset structure in the pixel circuit, current consumption can be reduced and display unevenness, malfunction, and the like can be prevented (see, for example, Patent Document 1).

JP-A-6-102531

  As described above, off-leakage current can be reduced by using a TFT having an LDD structure or an offset structure. However, when the pixel pitch is shortened and a high-resolution pixel is to be formed, the pixel electrode may have to be formed so as to cover the TFT through the insulating film. In the case of this structure, it has been found that the leakage electric field from the pixel electrode acts on the TFT through the insulating film to induce carriers. As a result, it has been found that the threshold voltage (Vth) of the TFT shifts and the off-leakage current increases.

  FIG. 9 is a diagram showing the relationship between the electrical characteristics of the N-type TFT and the pixel electrode potential. Compared with the case where there is no pixel electrode covering the TFT (None Pixel), when the pixel electrode has a potential, the electrical characteristics of the TFT change. In particular, when the pixel electrode potential (Vpixel) has a polarity potential to turn on the TFT, Vth shifts so that the electrical characteristics of the TFT become a depletion type, so that the leakage current at Vgs = 0V increases. End up.

  The present invention is realized as the following forms or application examples so as to solve at least a part of the problems described above.

  Application Example 1 A first substrate, a second substrate disposed opposite to the first substrate, a display element disposed between the first substrate and the second substrate, A thin film transistor formed on the display element side of the first substrate, a pixel electrode formed on the display element side of the thin film transistor so as to overlap the thin film transistor in plan view, the thin film transistor, and the pixel A thin film transistor including a gate electrode, a channel region facing the gate electrode through a gate insulating film, and the same layer as the channel region A low-concentration impurity region located outside the end portion of the gate electrode in plan view, and the channel region and the low-concentration impurity region in the same layer. It has a high concentration impurity region located outside of the doped region, wherein the shield electrode, a display device, characterized in that disposed on at least the overlapping in the low concentration impurity regions located in a plan view.

  The inventor has found that when the pixel electrode is formed so as to cover the TFT through the insulating film, the off-leakage current increases. The leakage electric field from the pixel electrode acts on the channel region or the LDD region through the insulating film. It was found that Vth is shifted by the induction of carriers. Therefore, according to the display device, a leakage electric field from the pixel electrode can be shielded by the shield electrode, carriers are not induced in the channel region or the LDD region, and an increase in off-leakage current can be suppressed. .

  Application Example 2 In the application example described above, the thin film transistor is a staggered transistor, and the shield electrode does not overlap all or part of a region where the gate electrode and the channel region overlap in plan view. Display device placed in the.

  In the case of a staggered TFT, since the gate electrode acts as a shield electrode with respect to the channel region, an increase in off-leakage current can be suppressed by covering at least the LDD region with the shield electrode.

  Application Example 3 In the application example described above, the thin film transistor is an inverted staggered transistor, and the shield electrode is disposed at a position overlapping the channel region and the low-concentration impurity region in plan view.

  In the case of an inverted stagger type TFT, the pixel electrode potential affects the channel region and the LDD region. Therefore, an increase in off-leakage current can be suppressed by covering the channel region and the LDD region with the shield electrode.

  Application Example 4 A first substrate, a second substrate disposed opposite to the first substrate, a display element disposed between the first substrate and the second substrate, A thin film transistor formed on the display element side of the first substrate, a pixel electrode formed on the display element side of the thin film transistor so as to overlap the thin film transistor in plan view, the thin film transistor, and the pixel A thin film transistor including a gate electrode, a channel region facing the gate electrode through a gate insulating film, and the same layer as the channel region An offset region located outside the end of the gate electrode in plan view, and formed in the same layer as the channel region and the offset region in plan view. Has a high concentration impurity region located outside of Tsu DOO region, wherein the shield electrode, a display device disposed at a position overlapping at least in the offset region in a plan view.

  The inventor found that when the pixel electrode is formed so as to cover the TFT through the insulating film, the off-leakage current increases. The leakage electric field from the pixel electrode acts on the channel region or the offset region through the insulating film. It was found that Vth is shifted by the induction of carriers. Therefore, according to the display device, a leakage electric field from the pixel electrode can be shielded by the shield electrode, carriers are not induced in the channel region or the offset region, and an increase in off-leakage current can be suppressed.

  Application Example 5 In the application example described above, the thin film transistor is a staggered transistor, and the shield electrode does not overlap all or part of a region where the gate electrode and the channel region overlap in plan view. Display device placed in the.

  In the case of a staggered TFT, since the gate electrode acts as a shield electrode with respect to the channel region, an increase in off-leakage current can be suppressed by covering at least the offset region with the shield electrode.

  Application Example 6 In the application example described above, the thin film transistor is an inverted staggered transistor, and the shield electrode is disposed at a position overlapping the channel region and the offset region in plan view.

  In the case of an inverted stagger type TFT, the pixel electrode potential affects the channel region and the offset region. Therefore, an increase in off-leakage current can be suppressed by covering the channel region and the offset region with the shield electrode.

  Application Example 7 A first substrate, a second substrate disposed opposite to the first substrate, a display element disposed between the first substrate and the second substrate, An inverted staggered thin film transistor formed on the display element side of the first substrate; a pixel electrode formed on the display element side of the thin film transistor so as to overlap the thin film transistor in plan view; and the thin film A shield electrode formed in a layer between a transistor and the pixel electrode, wherein the thin film transistor includes a gate electrode, a channel region facing the gate electrode through a gate insulating film, and the channel A source electrode disposed so as to overlap a part of the region, and a drain electrode disposed so as to overlap a part of the channel region and having a gap between the source electrode and It has the shield electrode, a display device disposed at a position overlapping at least in the gap in a plan view.

  According to the TFT having the above-described structure, since the source / drain electrode functions as a shield electrode, an increase in off-leakage current can be suppressed by covering at least the gap between the source / drain electrodes with the shield electrode.

  Application Example 8 In the application example described above, the thin film transistor is an N type, and the shield electrode is connected to a wiring having a potential equal to or lower than the potential applied to the source of the thin film transistor.

  According to such a configuration, since no carriers are induced in the LDD region or the offset region by the potential of the shield electrode, an increase in off-leakage current can be effectively suppressed.

  Application Example 9 In the application example described above, the thin film transistor is P-type, and the shield electrode is connected to a wiring having a potential equal to or higher than the potential applied to the source of the thin film transistor.

  According to such a configuration, since no carriers are induced in the LDD region or the offset region by the potential of the shield electrode, an increase in off-leakage current can be effectively suppressed.

  Application Example 10 In the application example described above, the display element is an electrophoretic display element.

  Application Example 11 Electronic equipment including the display unit according to the application example described above in a display unit.

The block diagram which shows the whole structure of the display apparatus which concerns on 1st Embodiment. FIG. 3 is an equivalent circuit diagram illustrating a configuration of a pixel of the display device according to the first embodiment. The fragmentary sectional view of the display part of the display apparatus which concerns on 1st Embodiment. The top view which shows the structure of a pixel concretely. Sectional drawing of the pixel switching element in FIG. Sectional drawing which shows the relationship between the LDD area | region of TFT of the display apparatus which concerns on 2nd Embodiment, and a shield electrode. Sectional drawing which shows the relationship between the semiconductor layer and shield electrode in TFT of the display apparatus which concerns on 3rd Embodiment. Sectional drawing which shows the relationship between the semiconductor layer and shield electrode in TFT of the display apparatus which concerns on 4th Embodiment. The gate voltage-drain current characteristic view showing the change of the electric characteristic of TFT by the pixel electrode potential. FIG. 10 is a front view showing a configuration of a wrist watch as an example of an electronic apparatus to which the display device is applied. The perspective view which shows the structure of the electronic paper which is an example of the electronic device to which the display apparatus is applied.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, in order to make each configuration easy to understand, the actual structure and the scale and number of each structure are different.

(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of the display device 1 according to the present embodiment. The display device 1 includes a display unit 3 in which a plurality of pixels 20 are arranged, a scanning line driving circuit 60, and a data line driving circuit 70. The display unit 3 includes a plurality of scanning lines 40 (Y1, Y2,..., Ym) extending from the scanning line driving circuit 60 and a plurality of data lines 50 (X1, X2,..., Xn) extending from the data line driving circuit 70. And are formed. The pixels 20 are arranged corresponding to the intersections between the scanning lines 40 and the data lines 50. Each pixel 20 is connected to a scanning line 40 and a data line 50, respectively.

  FIG. 2 is an equivalent circuit diagram showing the configuration of the pixel 20. As illustrated in FIG. 2, the pixel 20 includes a pixel switching element 24, a storage capacitor 25, a pixel electrode 21, a common electrode 22, and an electrophoretic element 51 as a display element. The pixel switching element 24 is a field effect N-type transistor. The scanning line 40 is connected to the gate terminal of the pixel switching element 24, the data line 50 is connected to the source terminal, and one end of the storage capacitor 25 and the pixel electrode 21 are connected to the drain terminal. The other end of the storage capacitor 25 is connected to the capacitor line 80. The capacitor line 80 is disposed along the extending direction of the scanning line 40 and is disposed so as to intersect the data line 50 in plan view.

  FIG. 3 is a partial cross-sectional view of the display unit 3 of the display device 1 according to the present embodiment. As shown in FIG. 3, the display unit 3 has a configuration in which an electrophoretic element 51 is sandwiched between a substrate 41 and a counter substrate 46. In the present embodiment, description will be made on the assumption that an image is displayed on the counter substrate 46 side.

  The substrate 41 is a substrate made of, for example, glass or plastic. Although not shown, a stacked structure in which the pixel switching element 24, the storage capacitor 25, the scanning line 40, the data line 50, the capacitor line 80, and the like are formed is formed on the substrate 41. A plurality of pixel electrodes 21 are provided in a matrix on the upper layer side of the stacked structure.

  The counter substrate 46 is a transparent substrate made of, for example, glass or plastic. On the surface of the counter substrate 46 facing the substrate 41, the common electrode 22 is formed so as to face the plurality of pixel electrodes 21. The common electrode 22 is formed of a transparent conductive material such as magnesium silver (MgAg), indium / tin oxide (ITO), indium / zinc oxide (IZO), or the like.

  The electrophoretic element 51 includes a plurality of microcapsules 49 containing electrophoretic particles, a binder 47 made of, for example, a resin, and an adhesive layer 48. The plurality of microcapsules 49 are fixed to each other by a binder 47. The microcapsule 49 and the binder 47 are fixed to the substrate 41 by an adhesive layer 48.

  FIG. 4 is a plan view specifically showing the configuration of one pixel 20 in the display device 1 according to the present embodiment. FIG. 5 is a diagram showing a cross section taken along the dashed line (1) in FIG. 4, and mainly shows the cross-sectional structure of the pixel switching element 24. In addition, the figure has described the principal part for description, The structure of a counter substrate is abbreviate | omitted.

  As shown in FIG. 5, the cross-sectional structure of the pixel 20 includes a semiconductor layer 30 as a first layer, a first wiring layer including a gate electrode 27 as a second layer, a data line 50 and a shield as a third layer. It has a four-layer structure of a pixel electrode layer including the pixel electrode 21 as a second wiring layer including the electrode 26 and a fourth layer. As shown in FIG. 4, the pixel switching element 24 is formed corresponding to the intersection of the data line 50 and the scanning line 40, and the electrode provided in the semiconductor layer 30 and the second layer electrode connected to the capacitor line 80 Thus, the holding capacitor 25 is formed. The capacitor line 80 is formed by the second layer.

  In FIG. 5, a base insulating film made of silicon nitride and silicon dioxide (not shown) is formed on a substrate 41. The base insulating film has a role of preventing diffusion of impurities from the substrate 41. A first semiconductor layer 30 is disposed on the base insulating film. The semiconductor layer 30 has at least one channel region 33, an LDD region 32 located outside the channel region 33, and a high concentration impurity region 31 located outside the LDD region 32. Thus, the TFT having the LDD region 32 can reduce the off-leak current because the electric field between the drain and the source is relaxed at the drain end.

  A data line 50 for supplying a pixel potential is connected to the high concentration impurity region 31. A gate insulating film 42 is formed on the semiconductor layer 30, and a gate electrode 27 is formed in the second layer at a position facing the channel region 33 through the gate insulating film 42. Here, after forming the gate electrode 27, ion implantation into the LDD region 32 is performed using the gate electrode 27 as a mask. Therefore, in the cross section of FIG. 5, the end of the channel region 33 and the end of the gate electrode 72 coincide with each other in plan view.

  The pixel switching element 24 is formed by the above configuration. More specifically, the pixel switching element 24 includes a channel region 33, an LDD region 32, a portion of the high concentration impurity region 31 adjacent to the LDD region 32, a gate insulating film 42, and a channel region 33 of the gate electrode 27. It is comprised by the part which overlaps. An interlayer insulating film 43 is formed so as to cover the pixel switching element 24, and a data line 50 and a shield electrode 26 constituting a third layer are formed on the interlayer insulating film 43. The shield electrode 26 is electrically connected to the capacitor line 80 and overlaps at least the LDD region 32 in plan view.

  A planarization insulating film 44 made of acrylic resin having a protective film made of silicon nitride (not shown) is formed on the third layer, and the pixel electrode 21 is formed on the upper layer. The pixel electrode 21 overlaps at least the LDD region 32 of the pixel switching element 24 in plan view. The pixel electrode 21 may overlap the entire pixel switching element 24 in plan view.

  According to the present embodiment, the shield electrode 26 connected to the capacitor line 80 is formed between the semiconductor layer 30 and the pixel electrode 21. According to such a configuration, the leakage electric field generated in the direction of the pixel switching element 24 by the potential applied to the pixel electrode 21 is blocked by the shield electrode 26, so that the leakage electric field is generated with respect to the semiconductor layer 30, particularly the LDD region 32. There is no influence, and unnecessary carriers are not induced in the LDD region 32. Therefore, an increase in off-leakage current of the pixel switching element 24 due to the potential of the pixel electrode 21 can be prevented without shifting the Vth of the TFT.

  Further, in the present embodiment, the shield electrode 26 is connected to the capacitor line 80 connected to the ground potential. Since a ground potential is normally applied to the capacitor line 80, according to such an embodiment, the potential of the shield electrode 26 is equal to or lower than the potential of the source line in the pixel switching element 24. Accordingly, carriers are not induced in the LDD region 32 due to the influence of the potential of the shield electrode 26, and the Vth of the TFT does not shift.

  In the present embodiment, the shield electrode 26 is connected to the capacitor line 80. However, it may be connected to a shield electrode wiring prepared separately. In this case, since the potential of the shield electrode 26 can be controlled independently, the potential of the shield electrode 26 is fixed below the source potential of the pixel switching element 24 even when driving such as changing the potential of the capacitor line 80 is performed. can do.

  When the pixel switching element 24 is P-type, the potential of the shield electrode 26 needs to be equal to or higher than the source potential of the pixel switching element 24. When the shield electrode 26 is connected to the capacitor line 80, the potential of the capacitor line 80 is set to a high potential, or the potential of the capacitor line 80 is set to the ground potential and data input to the pixel is set to a negative potential. In this case, the potential of the shield electrode 26 is equal to or higher than the source potential of the pixel switching element 24. Accordingly, carriers are not induced in the LDD region 32 due to the influence of the potential of the shield electrode 26, and the Vth of the TFT does not shift. Therefore, an increase in the off-leakage current of the pixel switching element 24 due to the potential of the pixel electrode 21 can be suitably prevented.

(Second Embodiment)
FIG. 6 is a cross-sectional view when the shield electrode 26 in the cross-sectional view of FIG. 5 is formed so as to cover the LDD region 32 and not to cover all or part of the gate electrode 27. That is, the shield electrode 26 is disposed so as not to overlap all or part of the region where the gate electrode 27 and the channel region overlap in plan view. The gate electrode 27 is connected to the ground potential during a period in which the pixel switching element 24 is turned off. Therefore, on the gate electrode 27, the leakage electric field due to the potential of the pixel electrode 21 is blocked by the gate electrode 27 and does not affect the semiconductor layer 30. Therefore, by covering the LDD region 32 with the shield electrode 26, it is possible to prevent an increase in off-leakage current due to the leakage electric field of the pixel electrode 21. By reducing the area of the shield electrode 26 in this way, the parasitic capacitance generated between the shield electrode 26 and the gate electrode 27 and between the shield electrode 26 and the pixel electrode 21 can be reduced. Therefore, the charge / discharge current of the parasitic capacitance generated when the scanning line is driven can be reduced, and a TFT panel with low power consumption can be manufactured.

(Third embodiment)
FIG. 7 is a cross-sectional view of the pixel switching element 24 in which an inverted staggered TFT having an LDD structure is used. In a TFT having an inverted stagger structure, a base insulating film (not shown) is formed on a substrate 41, and a gate electrode 27 is first formed thereon. The semiconductor layer 30 is formed on the upper layer via the gate insulating film 42, and the pixel switching element 24 is formed. In this embodiment, the first layer includes the gate electrode 27, the second layer includes the semiconductor layer 30, the third layer includes the source / drain electrode 39, and the fourth layer includes the shield electrode 26. The fifth layer is a layer including the pixel electrode 21.

  The semiconductor layer 30 is formed by a channel region 33 facing the gate electrode 27 and the gate insulating film 42, an LDD region 32 positioned outside the channel region 33, and an intrinsic region 34 positioned outside the LDD region 32. . The pixel switching element 24 is configured by a portion of the channel region 33, the LDD region 32, the gate insulating film 42, and the gate electrode 27 that overlaps the channel region 33. Thus, the TFT having the LDD region 32 can reduce the off-leak current because the electric field between the drain and the source is relaxed at the drain end.

  A source / drain electrode of the third layer is connected to the semiconductor layer 30 of the pixel switching element 24. A protective insulating film 45 is formed so as to cover them, and a shield electrode 26 of a fourth layer is formed on the protective insulating film 45. The shield electrode 26 is electrically connected to the capacitor line 80 and overlaps at least the channel region 33 and the LDD region 32 in plan view. A planarization insulating film 44 made of an acrylic resin including a protective film made of silicon nitride (not shown) is formed on the upper layer, and the pixel electrode 21 is formed on the upper layer. The pixel electrode 21 overlaps at least the LDD region 32 of the pixel switching element 24 in plan view. The pixel electrode 21 may overlap the entire pixel switching element 24 in plan view.

  According to the present embodiment, the shield electrode 26 connected to the capacitor line 80 is formed between the semiconductor layer 30 and the pixel electrode 21. According to such a configuration, the leakage electric field due to the potential applied to the pixel electrode 21 is blocked by the shield electrode 26, and therefore, the leakage electric field does not affect the semiconductor layer 30, particularly the channel region 33 and the LDD region 32. Is not induced. Therefore, an increase in off-leakage current of the pixel switching element 24 due to the potential of the pixel electrode 21 can be prevented without shifting the Vth of the TFT.

(Fourth embodiment)
FIG. 8 is a cross-sectional view of the pixel switching element 24 using a reverse staggered TFT having no LDD structure. Below, it demonstrates centering on difference with FIG. A base insulating film (not shown) is formed on the substrate 41, and a gate electrode 27 is first formed on the base insulating film. The semiconductor layer 30 is formed on the upper layer via the gate insulating film 42, and the pixel switching element 24 is formed. The semiconductor layer 30 is formed by a channel region 33 that faces the gate electrode 27 and the gate insulating film 42 and an intrinsic region 34 that is located outside the channel region 33.

  A source / drain electrode of the third layer is connected to the semiconductor layer 30 of the pixel switching element 24. The source / drain electrodes both overlap part of the channel region 33 in plan view. Further, the source / drain electrodes are formed with a gap that becomes a channel length. In other words, the width of the gap between the source electrode and the drain electrode corresponds to the channel length. A protective insulating film 45 is formed so as to cover them, and a shield electrode 26 of a fourth layer is formed on the protective insulating film 45. The shield electrode 26 is electrically connected to the capacitor line 80 and overlaps at least the gap between the source electrode and the drain electrode in plan view. The pixel switching element 24 is configured by a portion of the channel region 33, the gate insulating film 42, and the gate electrode 27 that overlaps the channel region 33.

  According to the present embodiment, the shield electrode 26 connected to the capacitor line 80 is formed between the semiconductor layer 30 and the pixel electrode 21. According to such a configuration, the leakage electric field due to the potential applied to the pixel electrode 21 is blocked by the shield electrode 26, and therefore, the leakage electric field does not affect the semiconductor layer 30, particularly the channel region 33 and the LDD region 32. Is not induced. Therefore, an increase in off-leakage current of the pixel switching element 24 due to the potential of the pixel electrode 21 can be prevented without shifting the Vth of the TFT.

(Modification)
As a method for reducing the off-leakage current of the TFT, there is an offset structure in addition to the LDD structure. The offset structure is a structure in which an intrinsic region is provided between the channel region 33 and the high concentration impurity region 31. In other words, the low-concentration impurity region 32 in the first to third embodiments is replaced with an intrinsic region.

  Each of the above embodiments is also applicable to an offset structure instead of the LDD structure. Therefore, if the TFT has an offset structure, the LDD structure may be replaced with the offset structure and the LDD region may be replaced with the offset region in the above description.

(Application examples)
The effect of the shield electrode of the present invention is not limited to the pixel switching element. When the pixel circuit is composed of a plurality of TFTs, it can be applied to all TFTs. Further, the connection destination of the shield electrode is not limited to the capacitor line or the dedicated independent wiring. As an example, in the case of a pixel circuit that employs a latch circuit as a memory circuit, the shield electrode that covers the P-type TFT may be connected to the high potential power line, and the shield electrode that covers the N-type TFT may be connected to the ground power line.

(Electronics)
Next, electronic devices to which the above-described display device is applied will be described with reference to FIGS. FIG. 11 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.

  On the front surface of the watch case 1002, a display unit 1005 including the display device of the above embodiment, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided. On the side surface of the watch case 1002, a crown 1010 and an operation button 1011 are provided as operation elements. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

  FIG. 14 is a perspective view illustrating a configuration of the electronic paper 1100. The electronic paper 1100 includes the display device of the above embodiment in the display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  According to the wristwatch 1000 and the electronic paper 1100 described above, the display device according to the present invention is employed, so that power consumption is small and high-quality image display can be performed.

  In addition, said electronic device illustrates the electronic device which concerns on this invention, Comprising: The technical scope of this invention is not limited. For example, the display device according to the present invention can be suitably used for a display unit of an electronic device such as a mobile phone or a portable audio device.

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 3 ... Display part, 20 ... Pixel, 21 ... Pixel electrode, 22 ... Common electrode, 23 ... Display element, 24 ... Pixel switching element, 25 ... Retention capacity, 26 ... Shield electrode, 27 ... Gate electrode, DESCRIPTION OF SYMBOLS 30 ... Semiconductor layer, 31 ... High concentration impurity region, 32 ... LDD region, 33 ... Channel region, 34 ... Intrinsic region, 40 ... Scanning line, 41 ... Substrate, 42 ... Gate insulating film, 43 ... Interlayer insulating film, 44 Planarization insulating film 45 ... Protective insulating film 46 ... Counter substrate 47 ... Binder 48 ... Adhesive layer 49 ... Microcapsule 50 ... Data line 51 ... Electrophoretic element 60 ... Scanning line driving circuit 70 DESCRIPTION OF SYMBOLS ... Data line drive circuit, 80 ... Capacity line, 1000 ... Wristwatch, 1002 ... Watch case, 1003 ... Band, 1005 ... Display part, 1010 ... Crown, 1011 ... Operation button, 1021 ... Second hand, 1 22 ... the minute hand, 1023 ... the hour hand, 1100 ... electronic paper, 1101 ... display area, 1102 ... body.

Claims (11)

A first substrate;
A second substrate disposed opposite to the first substrate;
A display element disposed between the first substrate and the second substrate;
A thin film transistor formed on the display element side of the first substrate;
A pixel electrode formed on the display element side of the thin film transistor so as to overlap the thin film transistor in a plan view;
A shield electrode formed in a layer between the thin film transistor and the pixel electrode,
The thin film transistor
A gate electrode;
A channel region facing the gate electrode through a gate insulating film;
A low-concentration impurity region formed in the same layer as the channel region and located outside the end of the gate electrode in plan view;
A high concentration impurity region formed in the same layer as the channel region and the low concentration impurity region, and located outside the low concentration impurity region in plan view,
The shield electrode is disposed at a position overlapping at least the low-concentration impurity region in plan view.
A display device characterized by that. The thin film transistor is a staggered transistor, and the shield electrode is disposed so as not to overlap all or part of a region where the gate electrode and the channel region overlap in a plan view.
The display device according to claim 1.   2. The display device according to claim 1, wherein the thin film transistor is an inverted staggered transistor, and the shield electrode is disposed at a position overlapping the channel region and the low-concentration impurity region in a plan view. A first substrate;
A second substrate disposed opposite to the first substrate;
A display element disposed between the first substrate and the second substrate;
A thin film transistor formed on the display element side of the first substrate;
A pixel electrode formed on the display element side of the thin film transistor so as to overlap the thin film transistor in a plan view;
A shield electrode formed in a layer between the thin film transistor and the pixel electrode,
The thin film transistor
A gate electrode;
A channel region facing the gate electrode through a gate insulating film;
An offset region formed in the same layer as the channel region, and located outside the end of the gate electrode in plan view;
A high-concentration impurity region formed in the same layer as the channel region and the offset region, and located outside the offset region in plan view,
The shield electrode is disposed at a position overlapping at least the offset region in plan view;
A display device characterized by that. The thin film transistor is a staggered transistor, and the shield electrode is disposed so as not to overlap all or part of a region where the gate electrode and the channel region overlap in a plan view.
The display device according to claim 4.   5. The display device according to claim 4, wherein the thin film transistor is an inverted staggered transistor, and the shield electrode is disposed at a position overlapping the channel region and the offset region in plan view. A first substrate;
A second substrate disposed opposite to the first substrate;
A display element disposed between the first substrate and the second substrate;
An inverted staggered thin film transistor formed on the display element side of the first substrate;
A pixel electrode formed on the display element side of the thin film transistor so as to overlap the thin film transistor in a plan view;
A shield electrode formed in a layer between the thin film transistor and the pixel electrode,
The thin film transistor
A gate electrode;
A channel region facing the gate electrode through a gate insulating film;
A source electrode arranged to overlap a part of the channel region;
A drain electrode disposed so as to overlap a part of the channel region and having a gap between the source electrode, and
The shield electrode is disposed at a position overlapping at least the gap in plan view.
A display device characterized by that. The thin film transistor is N-type, and the shield electrode is connected to a wiring having a potential equal to or lower than the potential applied to the source of the thin film transistor.
The display device according to claim 1, wherein the display device is a display device. The thin film transistor is P-type, and the shield electrode is connected to a wiring having a potential equal to or higher than the potential applied to the source of the thin film transistor.
The display device according to claim 1, wherein the display device is a display device.   The display device according to claim 1, wherein the display element is an electrophoretic display element.   An electronic apparatus comprising the display device according to claim 1 in a display unit.

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