JP2015170642A - display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device that can suppress off-state current of a semiconductor device and operate stably.SOLUTION: A thin film transistor has a semiconductor layer SC having a first channel region SCC, a source region SCS, a drain region SCD, a first boundary region SD1 between the channel region and the source region, and a second boundary region S between the channel region and the drain region, a light shielding layer SL2 confronting the semiconductor layer through a first insulating layer 11, a gate electrode GE confronting the channel region through a second insulating layer 12, a source electrode SE and a drain electrode DE. The light shielding layer is disposed to confront the channel region, the first boundary region, the second boundary region, the end portion at the first boundary region side of the source region and the end portion at the second boundary region side of the drain region. In the light shielding layer, a first area of a first overlap region which is overlapped with the first boundary region and the end portion of the source region is larger than a second area of a second overlap region which is overlapped with the second boundary region and the end portion of the drain region.

Description

  Embodiments described herein relate generally to a display device having a semiconductor device.

  In recent years, display devices including thin film transistors as semiconductor devices have been put into practical use. Examples of the display device include a liquid crystal display device and an organic electroluminescence display device.

A general thin film transistor includes a semiconductor layer made of amorphous silicon, polysilicon, or the like. In recent years, as a thin film transistor, a structure including an oxide semiconductor layer typified by indium gallium zinc oxide (IGZO) has been actively studied.
In such a thin film transistor, it is known that off-current is generated when light irradiated from the back side of the semiconductor layer is incident on the semiconductor layer, and display performance is deteriorated. In order to suppress such an off-current, a technique for arranging a light shielding film directly under a semiconductor layer has been proposed.

JP 2001-284594 A JP 2012-047840 A

  The above-described light shielding film is usually installed in a floating state in which the potential is not fixed. When a high voltage is applied to the drain of the thin film transistor, the potential of the light shielding film in the floating state fluctuates, and the off-current increases.

  An object of an embodiment of the present invention is to provide a display device capable of reducing light leakage current of a semiconductor device and suppressing light deterioration of a semiconductor layer. Alternatively, an object of an embodiment of the present invention is to provide a display device that can suppress driving with a stable off current.

  The display device according to the embodiment includes an insulating substrate and a plurality of thin film transistors provided on the insulating substrate. At least one thin film transistor includes a channel region, a source region and a drain region respectively provided on both sides of the channel region, a first boundary region located between the channel region and the source region, and the channel region A semiconductor layer having a second boundary region located between the first insulating layer and the drain region; and a light-shielding layer provided between the insulating substrate and the semiconductor layer and facing the semiconductor layer with the first insulating layer interposed therebetween A gate electrode facing the channel region across the second insulating layer on the opposite side of the light shielding layer, a source electrode in contact with the source region, and a drain electrode in contact with the drain region Yes. The light shielding layer is disposed to face the channel region, the first boundary region, the second boundary region, the end portion of the source region on the first boundary region side, and the end portion of the drain region on the second boundary region side, In the light shielding layer, the first area of the first overlapping region that overlaps the end portions of the first boundary region and the source region is larger than the second area of the second overlapping region that overlaps the end portions of the second boundary region and the drain region. large.

FIG. 1 is a diagram schematically illustrating a configuration example of a display device according to a first embodiment. FIG. 2 is a cross-sectional view schematically showing a configuration example of an array substrate applicable to the liquid crystal display device shown in FIG. 3 is a cross-sectional view illustrating a configuration example of the thin film transistor illustrated in FIG. 4 is a plan view schematically showing a configuration example of the thin film transistor shown in FIG. FIG. 5 is a diagram showing a comparison of the relationship between the channel length L, linear Id, saturation Id, and threshold voltage difference ΔV for the thin film transistor according to the present embodiment and the thin film transistor according to the comparative example. FIG. 6 is a cross-sectional view illustrating a configuration example of a thin film transistor in the display device according to the second embodiment. 7 is a plan view schematically showing a configuration example of the thin film transistor shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
It should be noted that the disclosure is merely an example, and those skilled in the art can appropriately modify the gist of the invention and can be easily conceived, and are naturally included in the scope of the present invention. In addition, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part in comparison with actual aspects for the sake of clarity of explanation, but are merely examples, and the interpretation of the present invention is not limited. It is not limited. In addition, in the present specification and each drawing, elements similar to those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description may be omitted as appropriate.

  FIG. 1 is a diagram schematically illustrating a configuration example of a display device according to the present embodiment. Here, a liquid crystal display device will be described as an example of a display device having a semiconductor device. The liquid crystal display device 1 can be used by being incorporated into various electronic devices such as a smartphone, a tablet terminal, a mobile phone, a notebook type PC, a portable game machine, an electronic dictionary, or a television device.

  As shown in FIG. 1, the liquid crystal display device 1 includes a display unit (active area) ACT that displays an image, and drive circuits GD and SD that drive the display unit ACT. The display unit ACT includes a plurality of display pixels PX arranged in a matrix.

  In the display portion ACT, gate lines G (G1 to Gn), capacitor lines C (C1 to Cn), source lines S (S1 to Sm), and the like are formed. Each gate line G is drawn to the outside of the display unit ACT and connected to the gate drive circuit GD. Each source line S is drawn to the outside of the display unit ACT and connected to the source drive circuit SD. The capacitance line C is electrically connected to the voltage application unit VCS to which the auxiliary capacitance voltage is applied.

Each display pixel PX includes a liquid crystal capacitor CLC, a thin film transistor (TFT) TR1, a storage capacitor CS in parallel with the liquid crystal capacitor CLC, and the like. The liquid crystal capacitor CLC includes a pixel electrode PE connected to the thin film transistor TR, a common electrode CE electrically connected to the common potential power supply unit VCOM, and a liquid crystal layer interposed between the pixel electrode PE and the common electrode CE. It has.
The thin film transistor TR1 is electrically connected to the gate line G and the source line S. A control signal for ON / OFF control of the thin film transistor TR1 is supplied to the gate wiring G from the gate drive circuit GD. A video signal is supplied to the source line S from the source drive circuit SD. When the thin film transistor TR1 is turned on based on the control signal supplied to the gate line G, the thin film transistor TR1 writes the pixel potential corresponding to the video signal supplied to the source line S to the pixel electrode PE. The voltage applied to the liquid crystal layer is controlled by the potential difference between the common electrode CE having the common potential and the pixel electrode PE having the pixel potential.

The storage capacitor CS holds a voltage applied to the liquid crystal layer for a certain period, and is composed of a pair of electrodes opposed via an insulating layer. For example, the storage capacitor CS includes a first electrode having the same potential as the pixel electrode, a second electrode electrically connected to a part of the capacitor line C or the capacitor line C, and the first electrode and the second electrode. And an insulating layer interposed therebetween.
Each of the gate drive circuit GD and the source drive circuit SD includes a plurality of thin film transistors (TFTs) TR2 that function as switching elements.

FIG. 2 is a cross-sectional view schematically showing a configuration example of an array substrate applicable to the liquid crystal display device 1 shown in FIG.
The array substrate SUB1 is formed using an insulating substrate 10 having optical transparency such as a glass substrate or a resin substrate. The array substrate SUB1 includes, on the insulating substrate 10, a thin film transistor TR1 and a storage capacitor CS that form each display pixel PX, and a plurality of thin film transistors TR2 that form a gate drive circuit GD and a source drive circuit SD. Here, the thin film transistors TR1 and TR2 functioning as semiconductor devices will be described in detail.

In the configuration example shown in FIG. 2, the inner surface 10 </ b> A of the insulating substrate 10 is covered with a first insulating layer (undercoat layer) 11. The first insulating layer 11 is made of silicon oxide (SiO), silicon oxynitride (SiON), or the like.
The thin film transistors TR1 and TR2 include a semiconductor layer SC provided on the first insulating layer 11, a gate electrode GE provided on the semiconductor layer SC across the second insulating layer 12, and a third insulating layer covering the gate electrode GE. 13 has a source electrode SE and a drain electrode DE provided on 13 and constitutes a top gate type transistor. In addition, a first light shielding layer SL1 and a second light shielding layer SL2 are provided in the first insulating layer 11. The first light shielding layer SL1 is opposite to the gate electrode GE and faces the semiconductor layer SC of the thin film transistor TR1 with the first insulating layer 11 interposed therebetween. The second light shielding layer SL2 is opposite to the gate electrode GE and faces the semiconductor layer SC of the thin film transistor TR2 with the first insulating layer 11 interposed therebetween. The light shielding layer is used as a concept including a light shielding film or a light shielding film.

  The first light shielding layer SL1 and the second light shielding layer SL2 are formed of a conductive light shielding material, for example, a metal material such as molybdenum, tungsten, aluminum, or titanium, or an alloy containing these metal materials. The first light shielding layer SL1 and the second light shielding layer SL2 are patterned, for example, in a rectangular shape with a predetermined dimension. Further, the first light shielding layer SL1 and the second light shielding layer SL2 are covered with the first insulating layer 11, and the potential thereof is in a floating state.

  On the first insulating layer 11, for example, an oxide semiconductor layer SC is formed as the semiconductor layer SC. For example, the oxide semiconductor layer SC is patterned in a substantially rectangular shape. The oxide semiconductor layer SC is formed of an oxide containing at least one of indium (In), gallium (Ga), zinc (Zn), and tin (Sn). As a typical example of forming the oxide semiconductor layer SC, for example, indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), zinc oxide tin (ZnSnO), zinc oxide (ZnO) is used. ) And the like. Such an oxide semiconductor layer SC can achieve higher mobility than a semiconductor layer made of amorphous silicon, and can be uniformly distributed over a large area at a lower temperature than a semiconductor layer made of polysilicon. It has the characteristic that it can form into a film.

  The oxide semiconductor layer SC includes a channel region (first region) SCC located above the first light shielding layer SL1, and a source region (first low resistance region) SCS located on both sides of the channel region SCC. It has a drain region (second low resistance region) SCD. The source region SCS and the drain region SCD have a lower resistance than the channel region SCC.

  A first boundary region (first depletion layer) SD1 is formed between the channel region SCC and the source region SCS, and a second boundary region (second depletion layer) SD2 is formed between the channel region SCC and the drain region SCD. Has been.

  A second insulating layer (gate insulating layer) 12 is formed on the channel region SCC of the oxide semiconductor layer SC. The gate electrode GE constituting the thin film transistors TR1 and TR2 is formed on the second insulating layer 12. That is, the channel region SCC and the gate electrode GE are opposed to each other with the second insulating layer 12 interposed therebetween.

  The gate electrode GE is formed of a wiring material, for example, a metal material such as molybdenum, tungsten, aluminum, or titanium, or an alloy containing these metal materials. The gate electrode GE is electrically connected to a gate wiring G provided in the same layer as the gate electrode GE, for example.

  The source region SCS, the drain region SCD, and the gate electrode GE of the oxide semiconductor layer SC are covered with the third insulating layer 13. The third insulating layer 13 also covers the side surfaces of the second insulating layer 12 and the surface of the first insulating layer 11. As a material for forming the third insulating layer 13, silicon oxide (SiO), silicon oxynitride (SiON), or the like can be used.

  The source electrode SE and the drain electrode DE constituting the thin film transistors TR1 and TR2 are formed on the third insulating layer 13. The source electrode SE is in contact with the source region SCS of the oxide semiconductor layer SC through a contact hole CH1 that penetrates the third insulating layer 13. The source electrode SE is connected to the source line S. The drain electrode DE is in contact with the drain region SCD of the oxide semiconductor layer SC through a contact hole CH2 that penetrates the third insulating layer 13. The source electrode SE and the drain electrode DE are formed of the same wiring material.

  The source electrode SE and the drain electrode DE of the thin film transistor TR1 constituting the display pixel PX are connected to the source line S and the pixel electrode PE, respectively. The source electrode SE and the drain electrode DE of the thin film transistor TR2 constituting the drive circuit are each connected to a control wiring of the drive circuit.

  Next, the light shielding layer will be described in detail. FIG. 3 is an enlarged cross-sectional view showing one thin film transistor, for example, the thin film transistor TR2, and FIG. 4 is a plan view schematically showing the thin film transistor TR2.

  As shown in FIGS. 3 and 4, the oxide semiconductor layer SC is patterned in a rectangular shape and has a constant channel width W. The channel region SCC has a channel length L along the longitudinal direction of the oxide semiconductor layer SC. The channel length L substantially matches the width of the gate electrode GE. The first boundary region SD1 and the second boundary region SD2 located on both sides of the channel region SCC have a width in the channel length direction of about 0.5 μm, for example.

  The second light shielding layer SL2 is formed in a substantially rectangular shape, and is provided between the inner surface 10A of the insulating substrate 10 and the oxide semiconductor layer SC so as to be substantially parallel thereto. The second light shielding layer SL2 includes the entire channel region SCC, the entire first boundary region SD1, the entire second boundary region SD2, the end of the source region SCS adjacent to the channel region SCC, and the drain region SCD adjacent to the channel region SCC. It arrange | positions so that an edge part may be opposed, ie, covered.

  The second light shielding layer SL2 has a width larger than the channel width W, and both ends in the width direction extend beyond both side edges of the oxide semiconductor layer SC. The second light shielding layer SL2 has two side edges extending in the channel width W direction, that is, two side edges extending in a direction orthogonal to the channel length L. Of the two side edges, the first side edge SLS is positioned so as to overlap the source region SCS, and is separated from the source region side end of the channel region SCC by a length (first length) Lss along the channel length direction. Is located. This length Lss is set longer than the width of the first boundary region SD1. Further, the second side edge SLD of the second light shielding layer SL2 is positioned so as to overlap the drain region SCD, and is separated from the drain region side end of the channel region SCC by a length (second length) Lsd along the channel length direction. Is located. This length Lsd is set longer than the width of the second boundary region SD1.

  In the present embodiment, the length Lsd is shorter than the length Lss (Lss> Lsd). Since the channel width W of the oxide semiconductor layer SC is constant, by setting (Lss> Lsd), the second light shielding layer SL2 is opposed to the first boundary region SD1 and the source region SCS of the oxide semiconductor layer SC. The first area S1 of the first overlapping region (overlapping in the direction perpendicular to the inner surface 10A of the insulating substrate 10) faces the second boundary region SD2 and the drain region SCD of the oxide semiconductor layer SC (the inner surface of the insulating substrate 10). It is larger than the second area S2 of the second overlapping region (which overlaps in a direction perpendicular to 10A). That is, the second light shielding layer SL2 is formed and arranged so that S1> S2 and (Lss> Lsd).

  In the present embodiment, the second light shielding layer SL2 is formed so that the ratio (S2 / S1) = (Lsd / Lss) of the second area S2 to the first area S1 is 0.8 or less. desirable. Further, it is desirable that the second light shielding layer SL2 completely covers the first boundary region SD1 and the second boundary region SD2. On the other hand, when the area of the overlapping region is increased, potential fluctuation due to capacitive coupling between the source region and the drain region and the second light-shielding layer SL2 is likely to occur. Therefore, it is desirable to form the overlapping region as small as possible. In the present embodiment, the length Lsd is set to 0.5 μm or more in consideration of the width of the first and second boundary regions, the mask displacement at the time of manufacturing, etc., and preferably is set to 1 to 2 μm. Is done.

  Although the second thin film transistor TR2 has been described in detail above, the oxide semiconductor layer SC and the first light shielding layer SL1 of the first thin film transistor TR1 are configured in the same manner as the second thin film transistor TR2. However, the present invention is not necessarily limited to this, and the first light shielding layer SL1 of the first thin film transistor TR1 may be formed to satisfy Lsd = Lss.

The array substrate SUB1 having such a configuration is manufactured, for example, as follows.
First, the first insulating layer 11 is formed on the insulating substrate 10. A conductive light shielding material is formed on the first insulating layer 11 and then patterned into islands to form a first light shielding layer SL1 and a second light shielding layer SL2. Subsequently, another first insulating layer 11 is formed on the first insulating layer 11 so as to overlap the first light shielding layer SL1 and the second light shielding layer SL2. Thereafter, an oxide semiconductor material is deposited on the first insulating layer 11, and then patterned into islands to form a plurality of oxide semiconductor layers SC.

  Next, after forming the second insulating layer 12 and further forming the wiring material, patterning is performed to form the island-shaped first insulating layer 12 and the gate electrode GE. Thereafter, the resistance of both ends of the oxide semiconductor layer SC is reduced to form the source region SCS and the drain region SCD. Thereafter, the third insulating layer 13 is formed over the gate electrode GE and the oxide semiconductor layer SC, and then the contact holes CH1 and CH2 are patterned. Subsequently, after forming a wiring material on the third insulating layer 13, patterning is performed to form the source electrode SE and the drain electrode DE.

  In the illustrated configuration example, the first insulating layer 11 of the first layer is formed on the insulating substrate 10, and then the light shielding layers SL1 and SL2 are formed on the first insulating layer 11. When the first insulating layer 11 of the first layer is not necessarily useful for the thin film transistor, the first insulating layer 11 of the first layer may be omitted. The second insulating layer 12 may be an insulating layer that covers the entire surface of the oxide semiconductor layer SC without patterning into an island shape. In this case, after the gate electrode is formed over the second insulating layer, the oxide semiconductor layer is irradiated with laser light through the second insulating layer, thereby reducing the resistance of the source region and the drain region of the oxide semiconductor layer. Can do.

  According to the illustrated configuration example, in the thin film transistors TR1 and TR2, the first light shielding layer SL1 and the second light shielding layer SL2 are on the back side of the channel region SCC, the first and second boundary regions SD1 and SD2 of the oxide semiconductor layer SC. And functions as a light-shielding film that blocks irradiation of light incident through the insulating substrate 10 to the channel region SCC and the first and second boundary regions SD1 and SD2.

  According to such a structure, it is possible to form a thin film transistor using the oxide semiconductor layer SC as a semiconductor layer and employing a top gate structure. Also in the liquid crystal display device in which the backlight unit is disposed on the back surface of the array substrate SUB1 including the thin film transistors TR1 and TR2, the channel region SCC and the first and second boundary regions SD1 and SD2 of the oxide semiconductor layer SC are also provided. Thus, it is possible to suppress the irradiation of light such as backlight light to the TFT, and it is possible to suppress an increase in off current of the thin film transistors TR1 and TR2 due to the light irradiation and deterioration of transistor characteristics.

  Further, according to the present embodiment, the second area S2 of the second overlapping region overlapping the second boundary region SD2 and the drain region SCD of the oxide semiconductor layer SC in the first and second light shielding layers SL1 and SL2 is oxidized. The physical semiconductor layer SC is formed smaller than the first area S1 of the first overlapping region overlapping the first boundary region SD1 and the source region SCS. That is, the first and second light shielding layers SL1 and SL2 are formed and arranged so that S1> S2 and (Lss> Lsd). Therefore, even when a high voltage is applied to the drain region SCD of the thin film transistor, the potential of the first and second light shielding layers SL1 and SL2 in the floating state can be suppressed from being pulled and fluctuated by the drain voltage. Thereby, fluctuations in the threshold voltage of the thin film transistors TR1 and TR2 can be suppressed, and an increase in off-current (Ioff (Id at Vg = 0V)) can be suppressed.

  FIG. 5 shows a thin film transistor according to the present embodiment (Lsd / Lss = S2 / S1 = 0.8) and a thin film transistor according to a comparative example (Lsd / Lss = S2 / S1 = 1.2) (source side rather than drain side). The variation of the threshold voltage is shown in comparison. In FIG. 5, the horizontal axis represents the channel length of the semiconductor layer, and the vertical axis represents the threshold voltage and saturation Id (linear Id (Vd = 0.1 V) when the gate voltage when 100 pA flows is the threshold voltage. The difference ΔV from the threshold voltage at Vd = 15.1 V) is shown. Further, the ratio (W / L) between the channel width and the channel length of the oxide semiconductor layer is, for example, 5/3.

  From FIG. 5, the threshold voltage of the thin film transistor (Lsd / Lss = 0.8) according to the present embodiment is higher than that of the thin film transistor according to the comparative example (Lsd / Lss = 1.2) at any channel length L. It can be seen that the difference (ΔV) is small. That is, it can be seen that the thin film transistor according to this embodiment has a small variation in threshold voltage even when a high voltage is applied.

From the above, according to the present embodiment, it is possible to provide a display device capable of reducing the light leakage current of the semiconductor device, suppressing the light deterioration of the semiconductor layer, and suppressing the off current. The above-described structure of the thin film transistor is particularly suitable for the thin film transistor TR2 of the driving circuit in which the source and drain are determined by the power supply, rather than the thin film transistor TR1 of the display pixel in which the source and drain are driven in an inverted manner.
In the first embodiment described above, the light shielding layer has a floating potential. However, the present invention is not limited to this. For example, the light shielding layer may be connected to the ground.

  Next, a thin film transistor of a display device according to another embodiment will be described. In other embodiments described below, the same parts as those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted, and the parts different from those in the first embodiment. Will be described in detail.

FIG. 6 is a cross-sectional view showing a thin film transistor of a display device according to the second embodiment, and FIG. 7 is a plan view schematically showing the thin film transistor.
As shown in FIGS. 6 and 7, the inner surface 10 </ b> A of the insulating substrate 10 constituting the array substrate SUB <b> 1 is covered with a first insulating layer (undercoat layer) 11. The first insulating layer 11 is made of silicon oxide (SiO), silicon oxynitride (SiON), or the like.
The thin film transistor TR includes a semiconductor layer SC provided on the first insulating layer 11, a gate electrode GE provided on the semiconductor layer SC across the second insulating layer 12, and a third insulating layer 13 covering the gate electrode GE. And a source electrode SE and a drain electrode DE provided on the top, and constitutes a top-gate transistor. The thin film transistor TR has a light shielding layer SL provided in the first insulating layer 11. The light shielding layer SL is opposite to the gate electrode GE and faces the semiconductor layer SC of the thin film transistor TR with the first insulating layer 11 interposed therebetween. The light shielding layer is used as a concept including a light shielding film or a light shielding film.

  In the second embodiment, a polysilicon (p-Si) semiconductor layer SC is provided as the semiconductor layer SC of the thin film transistor TR. The p-Si semiconductor layer SC is patterned in a rectangular shape and has a certain channel width W. The p-Si semiconductor layer SC includes a channel region (first region) SCC located above the light shielding layer SL, a source region (first low resistance region) SCS and a drain region (on both sides of the channel region SCC). (Second low resistance region) SCD, first lightly doped impurity (LDD) region LDD1 located between source region SCS and channel region SCC, and between drain region SCD and channel region SCC A second low-concentration impurity (LDD (Light 1y Doped Drain) region LDD2 is included. The source region SCS and the drain region SCD have a lower resistance than the channel region SCC.

  A first boundary region (first depletion layer) SD1 is formed between the first LDD region LDD1 and the source region SCS, and a second boundary region (second depletion layer) SD2 is formed between the second LDD region LDD2 and the drain region SCD. Is formed.

  The channel region SCC has a channel length L along the longitudinal direction of the p-Si semiconductor layer SC. The channel length L substantially matches the width of the gate electrode GE. Each of the first boundary region SD1 and the second boundary region SD2 has a width in the channel length direction of about 0.5 μm, for example.

  A second insulating layer (gate insulating layer) 12 is formed on the channel region SCC of the p-Si semiconductor layer SC. The gate electrode GE constituting the thin film transistor TR is formed on the second insulating layer 12. That is, the channel region SCC and the gate electrode GE are opposed to each other with the second insulating layer 12 interposed therebetween.

  The gate electrode GE is formed of a wiring material, for example, a metal material such as molybdenum, tungsten, aluminum, or titanium, or an alloy containing these metal materials. The gate electrode GE is electrically connected to a gate wiring G provided in the same layer as the gate electrode GE, for example.

  The first and second LDD regions LDD1, LDD2, the source region SCS, the drain region SCD, and the gate electrode GE of the p-Si semiconductor layer SC are covered with the third insulating layer 13. The third insulating layer 13 also covers the side surfaces of the second insulating layer 12 and the surface of the first insulating layer 11. As a material for forming the third insulating layer 13, silicon oxide (SiO), silicon oxynitride (SiON), or the like can be used.

  The source electrode SE and the drain electrode DE constituting the thin film transistor TR are formed on the third insulating layer 13. The source electrode SE is in contact with the source region SCS of the p-Si semiconductor layer SC through a contact hole CH1 that penetrates the third insulating layer 13. The source electrode SE is connected to the source line S. The drain electrode DE is in contact with the drain region SCD of the oxide semiconductor layer SC through a contact hole CH2 that penetrates the third insulating layer 13. The source electrode SE and the drain electrode DE are formed of the same wiring material.

  When the thin film transistor TR constitutes the display pixel PX, the source electrode SE and the drain electrode DE are connected to the source wiring and the pixel electrode, respectively. When the thin film transistor TR constitutes a drive circuit, the source electrode SE and the drain electrode DE are each connected to a control wiring of the drive circuit.

  The light shielding layer SL is formed of a conductive light shielding material, and is formed of, for example, a metal material such as molybdenum, tungsten, aluminum, or titanium, or an alloy containing these metal materials. For example, the light shielding layer SL is patterned into a rectangular shape having a predetermined size. Further, the light shielding layer SL is covered with the first insulating layer 11, and the potential thereof is in a floating state.

  The light shielding layer SL is provided between the inner surface 10A of the insulating substrate 10 and the p-Si semiconductor layer SC substantially in parallel with them. The light shielding layer SL includes the entire channel region SCC, the first and second LDD regions LDD1, LDD2, the entire first boundary region SD1, the entire second boundary region SD2, the end of the source region SCS adjacent to the channel region SCC, and It is arranged so as to face the end of the drain region SCD adjacent to the channel region SCC, that is, to cover it.

  The light shielding layer SL has a width larger than the channel width W, and both ends in the width direction extend beyond both side edges of the p-Si semiconductor layer SC. The light shielding layer SL has two side edges extending in the channel width W direction, that is, two side edges extending in a direction orthogonal to the channel length L. Of these two side edges, the first side edge SLS on the source region SCS side is positioned so as to overlap the source region SCS and has a length (first length) along the channel length direction from the source region side end of the first LDD region LDD1. A) Lss is spaced apart. This length Lss is set longer than the width of the first boundary region SD1. The second side edge SLD on the drain region SCD side of the light shielding layer SL2 is positioned so as to overlap the drain region SCD and has a length (second length) Lsd along the channel length direction from the drain region side end of the second LDD region LDD2. Are located only apart. This length Lsd is set longer than the width of the second boundary region SD1.

  In the present embodiment, the length Lsd is shorter than the length Lss (Lss> Lsd). Since the channel width W of the p-Si semiconductor layer SC is constant, by setting (Lss> Lsd), the light shielding layer SL is opposed to the first boundary region SD1 and the source region SCS of the p-Si semiconductor layer SC. The first area S1 of the first overlapping region (overlapping in the direction perpendicular to the inner surface 10A of the insulating substrate 10) faces the second boundary region SD2 and the drain region SCD of the oxide semiconductor layer SC (the inner surface of the insulating substrate 10). It is larger than the second area S2 of the second overlapping region (which overlaps in a direction perpendicular to 10A). That is, the second light shielding layer SL2 is formed and arranged so that S1> S2 and (Lss> Lsd).

  In the present embodiment, the light shielding layer SL is preferably formed such that the ratio (S2 / S1) = (Lsd / Lss) of the second area S2 to the first area S1 is 0.8 or less. Further, it is desirable that the light shielding layer SL2 completely covers the first boundary region SD1 and the second boundary region SD2. On the other hand, when the area of the overlapping region is increased, potential fluctuation due to capacitive coupling between the source region and the drain region and the second light-shielding layer SL2 is likely to occur. In the present embodiment, the length Lsd is set to 0.5 μm or more in consideration of the width of the first and second boundary regions, the mask displacement at the time of manufacturing, etc., and preferably is set to 1 to 2 μm. Is done.

In the second embodiment, other configurations of the array substrate and the liquid crystal display device other than the configuration described above are configured in the same manner as in the first embodiment described above.
According to 2nd Embodiment comprised as mentioned above, the effect similar to 1st Embodiment mentioned above can be acquired. That is, according to the second embodiment, the light shielding layer SL includes the channel region SCC of the p-Si semiconductor layer SC, the first and second LDD regions LDD1, LDD2, the first and second boundary regions SD1, A light-shielding film that is located on the back side of SD2 and blocks irradiation of light incident through insulating substrate 10 onto channel region SCC, first and second LDD regions LDD1, LDD2, and first and second boundary regions SD1, SD2. Function as.

  According to such a configuration, it is possible to form the thin film transistor TR that employs the p-Si semiconductor layer SC as the semiconductor layer and adopts a top gate structure. Also in the liquid crystal display device in which the backlight unit is arranged on the back surface of the array substrate SUB1 having such a thin film transistor TR, the channel region SCC of the p-Si semiconductor layer SC, the first and second LDD regions LDD1, LDD2, Irradiation of light such as backlight light to the first and second boundary regions SD1 and SD2 can be suppressed, and increase in off current of the thin film transistor TR and deterioration of transistor characteristics due to light irradiation can be suppressed. .

Further, according to the present embodiment, in the light shielding layer SL, the second area S2 of the second overlapping region overlapping the second boundary region SD2 and the drain region SCD of the p-Si semiconductor layer SC is equal to that of the p-Si semiconductor layer SC. It is formed smaller than the first area S1 of the first overlapping region that overlaps the first boundary region SD1 and the source region SCS. That is, the light shielding layer SL is formed and arranged so that S1> S2 and (Lss> Lsd). Therefore, even when a high voltage is applied to the drain region SCD of the thin film transistor, the potential of the floating light-shielding layer SL can be suppressed from being pulled and fluctuated by the drain voltage. As a result, it is possible to suppress fluctuations in the threshold voltage of the thin film transistor TR and suppress an increase in off current (Ioff (Id at Vg = 0 V)).
From the above, according to the second embodiment, it is possible to provide a display device capable of reducing light leakage current of a semiconductor device, suppressing light deterioration of a semiconductor layer, and suppressing off-current. it can.

  In the above embodiment, a liquid crystal display device is shown as an example of disclosure of a display device including a thin film transistor. However, as another application example, an organic EL display device, another self-luminous display device, or an electronic device having an electrophoretic element or the like. Any flat panel display device such as a paper display device can be used. Further, it goes without saying that the same configuration or manufacturing process as that of the above embodiment can be applied without any particular limitation from a small-sized display device to a large-sized display device.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  All configurations and manufacturing steps that can be implemented by those skilled in the art based on the configurations and manufacturing steps described above as the embodiments of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belonging to. In addition, it is understood that other functions and effects brought about by the above-described embodiment are apparent from the description of the present specification or can be appropriately conceived by those skilled in the art to be brought about by the present invention.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 10 ... Insulating substrate, 11 ... 1st insulating layer, 12 ... 2nd insulating layer,
13 ... 3rd insulating layer, SUB1 ... Array substrate,
TR, TR1, TR2 ... Thin film transistor, GE ... Gate electrode, SC ... Semiconductor layer,
SE ... Source electrode, DE ... Drain electrode, SCC ... Channel region,
SCS ... source region, SCD ... drain region, SL ... light shielding layer, SL1 ... first light shielding layer,
SL2 ... second light shielding layer, CH1, CH2 ... contact hole,
SD1 ... 1st boundary region (depletion layer), SD2 ... 2nd boundary region (depletion layer),
LDD1 ... first low concentration impurity region, LDD2 ... second low concentration impurity region

Claims (14)

An insulating substrate, and a plurality of thin film transistors provided on the insulating substrate,
At least one thin film transistor is
A channel region, a source region and a drain region respectively provided on both sides of the channel region, a first boundary region located between the channel region and the source region, and between the channel region and the drain region A semiconductor layer having a second boundary region located at
A light-shielding layer provided between the insulating substrate and the semiconductor layer and facing the semiconductor layer with the first insulating layer interposed therebetween;
A gate electrode facing the channel region across the second insulating layer on the opposite side of the light shielding layer;
A source electrode in contact with the source region;
A drain electrode in contact with the drain region,
The light shielding layer is disposed to face the channel region, the first boundary region, the second boundary region, the end portion of the source region on the first boundary region side, and the end portion of the drain region on the second boundary region side,
In the light shielding layer, the first area of the first overlapping region that overlaps the end portions of the first boundary region and the source region is larger than the second area of the second overlapping region that overlaps the end portions of the second boundary region and the drain region. Large display device.   The display device according to claim 1, wherein a ratio of the second area to the first area is 0.8 or less.   The light shielding layer extends in the channel width direction of the channel region and overlaps with the source region, and the second side edge extends in the channel width direction of the channel region and overlaps with the drain region. And the first length between the first side edge and the source region side end of the channel region along the channel length direction of the channel region is the second side edge and the drain of the channel region The display device according to claim 1, wherein the display device is longer than a second length between the region side ends.   The display device according to claim 3, wherein the second length is greater than or equal to a width of the second boundary region.   The display device according to claim 1, wherein the light shielding layer has a floating potential.   6. The semiconductor layer according to claim 1, wherein the semiconductor layer is an oxide semiconductor layer formed of an oxide containing at least one of indium (In), gallium (Ga), and zinc (Zn). Display device.   A plurality of display pixels provided on the insulating substrate, and a driving circuit provided on the insulating substrate and driving the display pixels, wherein the at least one thin film transistor is provided in the driving circuit. The display device according to any one of 1 to 6. An insulating substrate, and a plurality of thin film transistors provided on the insulating substrate,
At least one thin film transistor is
A channel region, a source region and a drain region respectively provided on both sides of the channel region, a first low-concentration impurity region provided between the channel region and the source region, and the channel region and the drain region A second low concentration impurity region provided between the first low concentration impurity region, a first boundary region located between the first low concentration impurity region and the source region, and between the second low concentration impurity region and the drain region. A semiconductor layer having a second boundary region located at
A light-shielding layer provided between the insulating substrate and the semiconductor layer and facing the semiconductor layer with the first insulating layer interposed therebetween;
A gate electrode facing the channel region across the second insulating layer on the opposite side of the light shielding layer;
A source electrode in contact with the source region;
A drain electrode in contact with the drain region,
The light shielding layer includes the channel region, the first low-concentration impurity region, the second low-concentration impurity region, the first boundary region, the second boundary region, the end of the source region on the first boundary region side, and the drain region first. 2 is arranged opposite to the end on the boundary area side,
In the light shielding layer, the first area of the first overlapping region that overlaps the end portions of the first boundary region and the source region is larger than the second area of the second overlapping region that overlaps the end portions of the second boundary region and the drain region. Large display device.   The display device according to claim 8, wherein a ratio of the second area to the first area is 0.8 or less.   The light shielding layer extends in the channel width direction of the channel region and overlaps with the source region, and the second side edge extends in the channel width direction of the channel region and overlaps with the drain region. And the first length between the first side edge and the source region side end of the first low-concentration impurity region along the channel length direction of the channel region is the second side edge and the 10. The display device according to claim 8, wherein the display device is longer than a second length between the second low-concentration impurity region and a drain region side end.   The display device according to claim 10, wherein the second length is formed to be greater than or equal to a width of the second boundary region.   The display device according to claim 8, wherein the light shielding layer has a floating potential.   The display device according to claim 8, wherein the semiconductor layer is a polysilicon semiconductor layer formed of polysilicon.   A plurality of display pixels provided on the insulating substrate, and a driving circuit provided on the insulating substrate and driving the display pixels, wherein the at least one thin film transistor is provided in the driving circuit. The display device according to any one of 8 to 13.

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