KR102428434B1 - Backplane Substrate and Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a backplane substrate having a structure capable of reducing off-state current and preventing in-plane off-current deviation even during low-frequency driving in order to reduce power consumption and a liquid crystal display device using the same. The backplane substrate of the present invention has a triple gate structure and By providing a blocking pattern that selectively overlaps with this, the off current is reduced during low-frequency driving, and the separation of the blocking pattern between pixel areas prevents the parasitic cap generated at the overlapping portion of the light blocking pattern and the electrode from affecting the adjacent pixel area. can be prevented

Description

Backplane Substrate and Liquid Crystal Display Device Using Same

The present invention relates to a display device, and more particularly, to a backplane substrate having a structure capable of reducing an off current and preventing an in-plane off current deviation during low-frequency driving to reduce power consumption, and a liquid crystal display using the same.

Specific examples of the flat panel display include a liquid crystal display device (LCD), an organic light emitting display device (organic emitting display device), a plasma display panel device (PDP), and a quantum dot display device (Quantum Dot Display Device). ), a field emission display device (FED), an electrophoretic display device (EPD), etc., which in common use a flat panel display panel that implements an image as an essential component, A flat panel display panel has a structure in which a pair of transparent insulating substrates are bonded to each other with a unique light emitting or polarized light or other optical material layer interposed therebetween.

As a basic configuration of these various types of flat panel display devices, a backplane substrate including a plurality of pixels and a plurality of gate lines and data lines dividing the pixels, and a thin film transistor in each pixel may be included. In the sense that such a backplane substrate can selectively drive each pixel, it is also referred to as an active matrix driving substrate.

On the other hand, the aforementioned flat panel display device is generally driven at a specific frequency such as 60 Hz for display. Recently, there is a demand for reducing power consumption by including some low-frequency driving regions by changing the driving frequency according to the type of image. is being raised This is called a Low Refresh Rate (LRR) method.

However, in the case of using the LRR method, since the pulse period for each gate line becomes longer when driving at a low frequency, the discharge time between frames inverted with different polarities is long, the charge leakage value in the pixel is large, and the residual DC value is large. , there is a phenomenon in which flicker on the screen is generated accordingly. In addition, since such a flicker is proportional to ΔVp, there is a problem in that the longer the discharge time, that is, the longer the period, the more pronounced the flicker phenomenon.

As described above, although low-frequency driving has the advantage of reducing power consumption, there is a problem in that it is difficult to apply the flicker phenomenon because it is difficult to solve.

In addition, in a polysilicon type thin film transistor generally used for mobility above a certain level, defects including a grain boundary region in the active layer are under a strong drain field, There is also a structural problem of increasing the off current by acting as a detrap state of electrons.

Hereinafter, problems of the conventional thin film transistor structure will be described.

1 is a view showing a cross-sectional view of a conventional thin film transistor and a detrap phenomenon thereof.

As shown in FIG. 1 , the conventional thin film transistor includes an active layer 12 on a substrate 10 with a buffer layer 11 interposed therebetween, overlapping the channel region 12a of the active layer 12 and having a gate An electrode 14 is provided. In addition, a gate insulating layer 13 is provided between the active layer 12 and the gate electrode 14 .

The active layer 12 has a central channel region 12a, a high-concentration impurity region 12c at both ends, and a lightly doped drain (LDD) region between the channel region 12a and the high-concentration impurity region 12c. (12b) is provided.

In addition, the high-concentration impurity regions 12c at both ends of the active layer 12 are respectively connected to the source electrode 15a and the drain electrode 15b. A region connected to the source electrode 15a is a source region, and a region connected to the drain electrode 15b is a drain region. In addition, an interlayer insulating layer 16 is further provided between the active layer 12 and the layers of the source electrode 15a and the drain electrode 15b except for the connection portion.

In such a conventional thin film transistor, a current is generated by a potential difference between the gate electrode 14 and the drain electrode 15b, and electrons move from the channel region 12a to the drain region 12c, in particular, by the lower backlight unit. The generated photoelectrons in the channel region 12a are annihilated and disappear due to a short mean free path while moving to the drain region 12c, but the photoelectrons generated in the LDD region 12b are generated in the LDD region ( 12b) caused the off current value to rise.

The present invention has been devised to solve the above problems, and to provide a backplane substrate having a structure capable of reducing off current and preventing in-plane off current deviation even during low-frequency driving to reduce power consumption and a liquid crystal display using the same , there is a purpose.

In order to achieve the above object, the backplane substrate and the liquid crystal display using the same of the present invention have a triple gate structure and a light blocking pattern selectively overlapping the same, thereby reducing an off current during low-frequency driving, and a light blocking pattern between pixel regions. separation, it is possible to prevent the parasitic cap generated at the overlapping portion of the light blocking pattern and the electrode from affecting the adjacent pixel area.

For this purpose, the backplane substrate of the present invention has a display area including a pixel area on a matrix in the center, a substrate having a non-display area on the outside, a gate line and a data line crossing each other on the substrate, and each of the pixel areas An active layer integrally provided with a bent portion between the overlapping portions by having three or more overlapping portions with the gate line, a source electrode and a drain electrode connected to both ends of the active layer, and a lower portion of the active layer, and a light-blocking pattern covering the closest overlapping portions from both edges of the active layer.

The active layer may include a channel region corresponding to an overlapping portion with the gate line, a low concentration impurity region in contact with the channel region, and a high concentration impurity region in contact with the low concentration impurity region. In this case, the bent portions of the active layer protrude from the gate line, and may include a low concentration impurity region and a high concentration impurity region. In the bent portion, the high-concentration impurity region may be positioned between the low-concentration impurity regions.

In addition, the light blocking pattern is spaced apart from each other at both sides by a boundary between the active layer and the most central overlapping portion of the gate line in each pixel area. In this case, the light blocking pattern may not overlap the channel region at the center of the active layer and the low concentration impurity region in contact therewith in each of the pixel regions.

As another example, the light blocking pattern overlaps the gate line, covers both the overlapping portions of the active layer and the gate line, and is grounded. And, in this case, the light blocking pattern may extend to the non-display area and be grounded.

On the other hand, the light blocking pattern is in direct contact with the substrate, a buffer layer between the light blocking pattern and the active layer, a gate insulating layer between the active layer and the gate line, the gate line and the data including the source electrode An interlayer insulating layer may be further included between the layers of the line and drain electrodes.

In the non-display area, a gate driver is provided at both ends of the gate line, and electrodes and an active pattern constituting the thin film transistors included in the gate driver include the gate line, the data line and the active layer provided in the display area. is on the same layer as any one of the electrodes, and in this case, the electrodes of the thin film transistor included in the gate driver include a driver gate electrode, a driver source electrode, and a driver drain electrode, wherein the driver gate electrode is the active It is desirable to have two overlapping portions with the pattern.

A liquid crystal display device of the present invention for the same purpose includes a substrate having a display area including a pixel area on a matrix in the center and a non-display area on the outside, a gate line and a data line crossing each other on the substrate, and the pixel An active layer integrally provided with at least three overlapping portions with the gate line in each region, a bent portion between the overlapping portions, a source electrode and a drain electrode connected to both ends of the active layer, and the active layer On the lower side, a light-shielding pattern covering adjacent overlapping portions from both edges of the active layer, a pixel electrode connected to the drain electrode in the pixel region, a counter substrate facing the substrate, and liquid crystal between the substrate and the opposite substrate layers may be included.

In addition, the substrate may further include a common electrode covering the plurality of pixel areas and a metal line connected to each of the common electrodes. In this case, the pixel electrode may be positioned above the common electrode, and may be connected to the drain electrode at a portion that does not overlap the common electrode.

The backplane substrate of the present invention and a liquid crystal display using the same have the following effects.

First, by applying a gate electrode structure overlapping the active layer by three or more, the drain field is divided by the number of the provided gate electrodes to buffer the drain current, thereby reducing the off-state current.

Second, in the light blocking pattern provided below the active layer to prevent photocurrent generation in the active layer, separate areas are provided for each pixel area, so even if a parasitic capacitance between the light blocking pattern and the overlapping electrodes occurs, the effect of this is adjacent It can be prevented from being transmitted to the pixel regions, so that the in-plane off-current characteristic can be stabilized without deviation.

Third, when both the channel region of the active layer and the light blocking pattern overlap, the light blocking pattern is grounded outside to prevent parasitic capacitance caused by the light blocking pattern.

Fourth, by applying different gate electrode structures to the display area and the non-display area, the off current may be lowered in the display area and mobility characteristics may be improved in the non-display area.

1 is a cross-sectional view of a conventional thin film transistor and a view showing an electron detrap phenomenon thereof;
2 is a plan view showing a thin film transistor of the present invention;
3 is a cross-sectional view taken along line I to I' of FIG. 2;
FIG. 4 is a diagram illustrating electron movement from a source region to a drain region in the thin film transistor of FIG. 2 ;
5 is a plan view of a backplane substrate according to a first embodiment of the present invention;
6 is a cross-sectional view taken along line II to II' of FIG.
7 is a cross-sectional view showing a liquid crystal display device of the present invention;
8 is a plan view of a backplane substrate according to a second embodiment of the present invention;
9 is a cross-sectional view taken along line III-III' of FIG.
10A and 10B are graphs showing Vgs-Ids characteristics of thin film transistors having dual gate and triple gate structures;
11 is a plan view showing the backplane substrate of the present invention;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the part names of the actual product.

2 is a plan view showing the thin film transistor of the present invention, FIG. 3 is a cross-sectional view taken along line I to I' of FIG. 2, and FIG. 4 is a view showing electron movement from the source region to the drain region in the thin film transistor of FIG. .

2 to 4 , the thin film transistor of the present invention has a triple gate structure, and has a total of three overlapping portions with the active layer 110 and the gate line 120 . In addition, both ends of the active layer 110 are connected to the source electrode 131 and the drain electrode 132 .

In addition, the active layer 110 is provided on the substrate 100 , and in order to prevent contamination by components included in the substrate 100 during crystallization, a buffer layer is disposed between the substrate 100 and the active layer 110 . (103) is provided. In addition, a gate insulating layer 115 is disposed between the active layer 110 and the gate line 120 , and an interlayer insulating layer 125 is disposed between the gate line 120 and the source electrode 131/drain electrode 132 . ) is provided.

In addition, in the overlapping portion of the gate line 120 and the active layer 110 , the gate line 120 is provided with a total of three gate electrodes 120a of the thin film transistor. ) is called a structure. In addition, the active layer 110 at a portion overlapping the gate electrode 120a functions as the channel regions C1 , C2 , and C3 . In the active layer 110 , low-concentration impurity regions LDD1 , LDD2 , LDD3 , LDD4 , LDD5 and LDD6 are provided in a region adjacent to the channel region 110a to reduce an off-state current, and second and third low-concentration dopant regions are provided. A high-concentration impurity is located between the impurity regions LDD2 and LDD3 and the fourth and fifth low-concentration impurity regions LDD4 and LDD5 and in the region of the active layer 110 connected to the source electrode 131 and the drain electrode 132 . Areas SD1, SD2, SD3, and SD4 are defined.

Here, the low-concentration impurity regions are sequentially referred to as first to sixth regions LDD1 , LDD2 , LDD3 , LDD4 , LDD5 , and LDD6 from left to right of the cross-sectional view.

In the thin film transistor of the present invention, even if a drain field occurs due to a potential difference between the gate electrode (the overlapping portion of the gate line 120 and the active layer 110 ) and the drain electrode 132 . , an effective drain field applied to each channel by photoelectrons is reduced by three-division buffering, thereby reducing off-current generation due to electron detrap. In addition, as the number of LDD regions increases to six, the off-current suppression effect increases and the off-current generation is further reduced. Accordingly, the drain current Ids is prevented from rising, thereby stably lowering the off current.

Accordingly, the backplane substrate structure having the thin film transistor of the present invention can maintain a low off-current characteristic without in-plane deviation even in low-frequency driving, thereby minimizing fluctuation of Vp to prevent flicker.

Specifically, an example in which the above-described thin film transistor of the present invention is applied will be described.

5 is a plan view of a backplane substrate according to a first embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line II to II′ of FIG. 5 .

5 and 6, in the backplane substrate according to the first embodiment of the present invention, in the thin film transistor of FIGS. 2 to 4, a channel region C1 by a light source provided below the active layer 110; In order to prevent the generation of photocurrent in C2 and C3, a state in which the light-blocking pattern 105 is provided on the substrate 100 is illustrated.

Here, the light blocking pattern 105 may cover all of the channel regions C1 , C2 , and C3 of the active layer 110 from the lower side, but in the first embodiment of the present invention, the second channel region ( It may also be formed by exposing a portion of the central gate electrode (gate line and active layer overlapping region) corresponding to C2). With the actual electrode, the portion to which a strong field is applied is the first and second low concentration impurity regions LDD1 and LDD2 adjacent to the connection portions of the source electrode 131 and the drain electrode 132 , and the fifth and sixth regions. As the low-concentration impurity regions LDD5 and LDD6, the central channel region having a relatively small field or the third and fourth low-concentration impurity regions LDD3 and LDD4 adjacent thereto have little effect on the increase of the drain current. The pattern 105 may be omitted. This is due to the bidirectional driving characteristics of the backplane substrate for the liquid crystal display, and the function of the source electrode 131 and the drain electrode 132 is crossed and repeatedly changed. When applied to a thin film transistor having a one-way driving characteristic of a circuit structure of an organic light emitting diode display, the highest photocurrent is generated in the impurity region adjacent to the connection portion of the drain electrode, and the photocurrent is rapidly decreased as it moves away from the drain electrode. .

An advantage of this structure is that the aperture ratio is improved by omitting a portion of the light blocking pattern 105 formed by increasing the width compared to the gate line 120 for a process margin. As shown in FIG. 5 , the actual light-blocking pattern 105 is formed to have a relatively larger width than the gate line 120 in consideration of the margin with the black matrix layer. Accordingly, when the light blocking pattern 105 is provided outside of the gate line 120 , there is a problem in that the aperture ratio is lowered. The backplane substrate of the present invention selectively covers the region of the active layer 110 where the field is strong, thereby preventing the generation of photocurrent and improving the aperture ratio at the same time.

The plan view of FIG. 5 further illustrates a data line 130 that intersects the gate line and defines a pixel. In this case, the data line 130 is integrally formed with the source electrode 131 of the thin film transistor. In addition, the drain electrode 132 is formed on the same layer as the data line 130 .

A pixel electrode (refer to 147 of FIG. 7 ) connected to the drain electrode may be further included in the pixel, and the pixel electrode 147 may be branched into two or more within the pixel region to induce a transverse electric field. .

When the pixel electrode 147 is branched, it may further include a common electrode (see 144 of FIG. 7 ) that occupies most of the area of the pixel and overlaps the pixel electrode 147 .

More specifically, the backplane substrate of the present invention includes a substrate 100 (refer to FIG. 11 ) having a display area AA including a pixel area on a matrix in the center and a non-display area on the outside, and a substrate 100 (refer to FIG. 11 ) intersecting each other on the substrate. The gate line 120 and the data line 130 and three or more overlapping portions of the gate line 120 are provided in each of the pixel regions, and are integrally provided with curved portions B1 and B2 between the overlapping portions the active layer 110 , the source electrode 131 and the drain electrode 132 connected to both ends of the active layer 110 , and the active layer 110 on the lower side of the active layer 110 . and a light-shielding pattern 105 covering the closest overlapping portions from both edges.

Although the number of pixel areas included in the display area is gradually increasing and the degree of integration tends to increase, the curved portions B1 and B2 may prevent the length of the gate line 120 included in the single pixel area from being increased. That is, in the pixel area, the horizontal width occupied by the active layer 110 is not increased, and thus the degree of pixel integration is not reduced.

The active layer 110 includes the channel regions C1 , C2 and C3 corresponding to the overlapping portion with the gate line 120 , and the low concentration impurity region LDD1 in contact with both sides of the channel regions C1 , C2 and C3 . , LDD2, LDD3, LDD4, LDD5, and LDD6) and high-concentration impurity regions SD1, SD2, SD3, and SD4 in contact with the low-concentration impurity regions. In this case, the bent portions of the active layer 110 protrude from the gate line 120 , and include second to fifth lightly doped impurity regions LDD2 , LDD3 , LDD4 , and LDD5 and second and third highly doped impurity regions. (SD2, SD3).

In the active layer 110 , a first high-concentration impurity region SD1 positioned at both ends is integrally connected to the data line 130 and a partially protruding source electrode 131 , and the fourth high-concentration impurity region SD4 is integrally formed with the source electrode 131 . ) is connected to the drain electrode 132 of the same layer as the data line 130 .

The source electrode 131 and the drain electrode 132 on the cross-sectional view were side-connected by over-etching the first and fourth high-concentration impurity regions SD1 and SD4 of the active layer 110, which is only an example, and It may be connected to upper portions of the first and fourth high-concentration impurity regions SD1 and SD4.

And, in the bent portions B1 and B2, the second and third low-concentration impurity regions LDD2 and LDD3 of the second and third high-concentration impurity regions SD2 and SD3, respectively, and fourth and fifth impurity regions ( It may be located between LDD4 and LDD5).

In addition, the light blocking pattern 105 of the present invention borders the central overlapping portion (corresponding to the second channel region C2 ) between the active layer 110 and the gate line 120 in each pixel region. are spaced apart on both sides. In this case, the light blocking pattern 105 may not overlap the second channel region C2 at the center of the active layer and the third and fourth low concentration impurity regions LDD3 and LDD4 in contact therewith in each pixel region. can In this case, the light blocking pattern 105 has a separation area in each pixel area, and each pixel area is divided periodically, and is generated between the gate line 120 or the source electrode 131 overlapping the light blocking pattern 105 . It is possible to reduce the effect of the parasitic capacitance on other pixel areas.

In addition, in the light blocking pattern 105 , the first and fourth heavily doped impurity regions SD1 and SD4 to which a voltage is applied, and the first and third channel regions C1 and C3 adjacent thereto are formed. By blocking, the region where the drain field is strongly applied is covered, thereby preventing photoelectrons from increasing the photocurrent in the adjacent first, second, fifth, and sixth low-concentration impurity regions LDD1, LDD2, LDD5, and LDD6. In this case, even though the light blocking pattern 105 is divided and the second channel region C2 is exposed to the lower light source, the first high concentration impurity region SD1 and the fourth high concentration impurity region SD1 to which a voltage is already directly applied SD4) and adjacent areas of the first and third channel regions C1 and C3 are shielded from light to reduce photoelectron generation, and also the innermost region among the plurality of channel regions C1, C2, and C3. The generation of drain current is not large, and the influence on the off current is small even during exposure. In addition, the opening ratio can be improved by exposing this portion, so that when the structure of the backplane substrate according to the first embodiment of the present invention is applied, the advantage of improving the opening ratio is great.

Meanwhile, the light blocking pattern 105 is in direct contact with the substrate 100 , and a buffer layer 103 is further provided between the light blocking pattern 105 and the active layer 110 , and the active layer 110 . A gate insulating layer 115 between the layers of the gate line 120 and the gate line 120 , the gate line 120 , the data line 130 including the source electrode 131 , and an interlayer insulating layer 125 between the layers of the drain electrode 132 . ) is further included.

In the constant backplane substrate of the first embodiment of the present invention, the substrate 100 has been described based on a triple gate structure in which the gate line 120 and the active layer 110 have three overlapping portions, but in terms of reducing the off current, the gate An overlapping portion of the line 120 and the active layer 110 may be further provided.

In addition, the backplane substrate may be applied to a liquid crystal display device, an organic light emitting display panel, an electrophoretic display panel, a quantum dot display panel, and the like, but an example applied to a liquid crystal display will be described below as an example.

Hereinafter, an example in which the above-described backplane substrate of the present invention is applied to a liquid crystal display will be described.

7 is a cross-sectional view illustrating a liquid crystal display device of the present invention.

As shown in FIG. 7, the liquid crystal display of the present invention has the structure of FIGS. 5 and 6, a pixel electrode 147 connected to the drain electrode 132 in the pixel region, and a counter substrate facing the substrate ( 200 ) and a liquid crystal layer 300 between the substrate 100 and the opposite substrate 200 .

A color filter layer 210 may be further provided on either the opposite substrate 200 or the substrate 100 . In the illustrated drawings, the color filter layer 210 is illustrated on the opposite substrate 200 side, and a black matrix layer may be provided on the same layer as the color filter layer 210 at the boundary between the pixel regions.

On the other hand, the position of the color filter layer 210 is not limited to the illustrated bar, and the color filter layer may be located on the substrate 100 side. When the color filter layer is positioned on the substrate 100 , the black matrix layer may be omitted.

In addition, a common electrode 144 covering a plurality of pixel areas and a metal line (not shown) connected to each of the common electrodes 144 are further included on the substrate 100 . Here, the pixel electrode 147 may be branched into a plurality of pixels in the pixel area, thereby inducing a transverse electric field between the pixel electrode 144 and the common electrode 144 to horizontally adjust the alignment direction of the liquid crystal layer 300 . .

The common electrode 144 is provided one by one for each of the plurality of pixel areas, and can perform a touch sensing function by changing the capacitance depending on whether a corresponding part is touched. It is possible to detect whether the electrode 144 is touched.

Meanwhile, in the liquid crystal display of the present invention, the pixel electrode 147 provided in each pixel area is located above the common electrode 144 , and does not overlap the common electrode 144 to prevent an electric short. may be connected to the drain electrode 132 of each pixel area. In this case, the common electrode 144 does not cover all of the plurality of pixel areas, but has some openings at the connection portion between the pixel electrode 147 and the drain electrode 132 in the included pixel areas and at the edge thereof. .

The above-described example merely shows an example in which a liquid crystal display is applied as a display panel to be used, but is not limited thereto. It may also be applied to an electrophoretic display device or a quantum dot display device.

Meanwhile, in the above example, although the triple gate structure has been described as a basis, the number of gate electrodes overlapping the active layer can be increased to the maximum that can be integrated in the pixel region of the backplane substrate. Currently, in small models such as smartphones, high integration is progressing, and in the QHD model with a resolution of 2560x1440, triple gate is the best at the current level of technology that can be integrated, but with improvements such as exposure equipment for patterning each pattern When the degree of integration is further improved, the number of overlapping of the active layer and the gate line may be further increased. In addition, since the QHD model or less includes a spatial margin in the pixel area, the number of overlapping between the active layer and the gate line may be greater than three. And, the more the active layer and the gate line overlap, the more the off current is reduced.

8 is a plan view of a backplane substrate according to a second embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line III to III' of FIG. 8 .

Meanwhile, as shown in FIGS. 8 and 9 , in the backplane substrate according to the second embodiment of the present invention, only the configuration of the light blocking pattern 405 is different from that of the first embodiment, and the light blocking pattern 405 is the gate line. It overlaps with 120 , covers both the overlapping portions of the active layer 110 and the gate line 120 , and is connected to and grounded with a ground wire 415 in a non-display area outside the substrate 100 . .

And, in this case, the light blocking pattern 405 extends along the direction of the gate line 120 to the non-display area and is grounded.

Since the light blocking pattern 405 overlaps the gate line 120 , it overlaps the gate line 120 extending to the gate driver of the non-display area, and the light blocking pattern 405 up to the edge of the substrate 100 is It extends and is connected to the ground wiring 415 in a portion of the non-display area of the substrate 100 to receive a ground signal.

The effect of the structure of the backplane substrate according to the second embodiment of the present invention is to prevent the parasitic capacitance and prevent the generation of the floating capacitance in the light blocking pattern, so that the adjacent pixel areas are caused by the parasitic capacitance or the floating capacitance due to the light blocking pattern. can be prevented from affecting the picture quality.

Hereinafter, the reason why the triple gate structure applied to the backplane substrate of the present invention is superior to that of the dual gate structure will be described.

10A and 10B are graphs showing Vgs-Ids characteristics of thin film transistors having dual gate and triple gate structures.

10A and 10B show the Vgs-Ids characteristics of thin film transistors of dual-gate and triple-gate structures, respectively. In both structures, when Vds is set to 0.1V, low Ids (drain current) is uniformly lower than 0V, When the Vds voltage is 10V, as shown in FIG. 10B, when the Vgs voltage is -10V or higher, it can be confirmed that a low value of about 100fA is maintained. There is a large trend of variation between to 300 fA, and it can be confirmed that the off current value is reduced when a relatively more gates are provided in FIG. 10B , and the in-plane deviation is also reduced.

Therefore, in the portion of the pixel region to which a signal according to the low frequency driving is applied, the structure of three or more gate electrodes (the overlapping portion of the active layer and the gate line) is relatively higher than that of a double gate or a single gate in terms of lowering off current and reducing flicker. advantage can be found.

11 is a plan view showing a backplane substrate of the present invention.

11 , the backplane substrate of the present invention includes gate drivers 320 at both ends of the gate line in the non-display area of the substrate 100 .

In addition, the thin film transistor provided in the gate driver 320 applies a dual gate excellent in mobility, and a triple gate is applied to the pixel region, and a selective gate electrode structure is applied, thereby providing circuit advantages and low frequency off. It indicates that current reduction is attempted at the same time.

Here, a plurality of pixels are included in a matrix in the display area AA, and each pixel has R, G, and B pixel areas.

In addition, each of the thin film transistors in the pixel area includes three or more gate electrodes, while electrodes and active patterns constituting the thin film transistors included in the gate driver 320 are formed between the gate line and the gate line provided in the display area. It is on the same layer as any one of the data line and the active layer. In this case, the electrodes of the thin film transistor included in the gate driver include a driver gate electrode, a driver source electrode, and a driver drain electrode, and the driver part The gate electrode has two overlapping portions with the active pattern.

In addition, the ground wiring 415 of the backplane substrate according to the second embodiment may be located outside the gate driver 320 .

Meanwhile, reference numeral 350 (not described) denotes a driver IC, which applies an image signal to a data line, and transmits a gate low voltage signal, a gate high voltage signal, and various clock signals to the gate driver 320 with the gate driver 320 . It functions to transmit to the data line 130 .

Table 1 shows that the off current when the Vgs voltage shown in FIGS. 10A and 10B is -10V in the dual gate, 1.28e ^-13 A, in the triple gate, 7.58e ^-14 A, in the triple gate, in the dual gate It can be seen that it is reduced by ⁵⁹ % compared to ^the off current at It can be confirmed that the use of the dual gate is more advantageous when used in the display, and thus, it can be expected that different gate structures in the circuit area within the display area and the non-display area are excellent both in terms of movement speed improvement and off current.

[Table 1]

In the above experiment, in the dual gate structure and the triple gate structure, the low concentration impurity region LDD had a concentration of 0.8e ¹³ /cm ² and the high concentration impurity region SD had a concentration of 3.0e ¹⁵ /cm ² .

The backplane substrate of the present invention can implement a 30Hz driving QHD smartphone product, and power consumption is expected to be reduced by about 20%. All smart phones that are currently commercialized operate at 60Hz. If the off current (leakage current) of the backplane substrate is lowered, it is possible to drive at 30Hz without the issue of flickering.

The backplane substrate of the present invention and the display device using the same apply a gate electrode structure overlapping the active layer and three or more, thereby dividing the drain field by the number of gate electrodes provided to buffer the drain current, thereby reducing the off current. .

In addition, in the light blocking pattern provided under the active layer to prevent photocurrent generation in the active layer, separate areas are provided for each pixel area, so even if a parasitic capacitance between the light blocking pattern and the overlapping electrodes occurs, the effect of this is adjacent It can be prevented from being transmitted to the pixel regions, so that the in-plane off-current characteristic can be stabilized without deviation.

In addition, when both the channel region of the active layer and the light blocking pattern overlap, the light blocking pattern is grounded outside to prevent parasitic capacitance caused by the light blocking pattern.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those of ordinary skill in the art.

100: substrate 103: buffer layer
105: light blocking pattern 110: active layer
C1, C2, C3: Channel area
LDD1, LDD2, LDD3, LDD4, LDD5, LDD6: low concentration impurity regions
SD1, SD2, SD3, SD4: high concentration impurity regions
115: gate insulating film 120: gate line
125: interlayer insulating film 130: data line
131: source electrode 132: drain electrode
137: protective film 140: transparent electrode pattern
144: common electrode 415: ground wiring
145: fourth passivation layer 147: pixel electrode
200: counter substrate 210: color filter layer
300: liquid crystal layer 320: gate driver
350: driver IC 405: light blocking pattern

Claims (16)

a substrate having a display area including a pixel area on a matrix at a center and a non-display area at an outer side;
a gate line and a data line crossing each other on the substrate;
an active layer having three or more overlapping portions with the gate line in each of the pixel regions, the active layer having a curved portion between the overlapping portions and integrally formed;
a source electrode and a drain electrode connected to both ends of the active layer; and
A light blocking pattern covering a first overlapping portion closest to a first end portion of the active layer connected to the source electrode and a second overlapping portion closest to a second end portion of the active layer connected to the drain electrode under the active layer including,
the active layer includes a channel region corresponding to the overlapping portions with the gate line, a low-concentration impurity region in lateral contact with each of the channel region, and a high-concentration impurity region in lateral contact with the low-concentration impurity region;
In the active layer, at least one third overlapping portion between the first overlapping portion and the second overlapping portion and a low concentration impurity region in contact with a side of the third overlapping portion do not overlap the light blocking pattern.
delete The method of claim 1,
The bent portions of the active layer protrude from the gate line, and the backplane substrate includes the low-concentration impurity region and the high-concentration impurity region. 4. The method of claim 3,
In the curved portion, the high-concentration impurity region is located between the low-concentration impurity regions. The method of claim 1,
The light blocking pattern is spaced apart from each other on both sides by a boundary between the active layer and the most central overlapping portion of the gate line in each pixel area;
The spaced portion of the light blocking pattern is positioned with respect to the central channel region of the active layer and the low-concentration impurity region adjacent thereto.
delete The method of claim 1,
The light blocking pattern is a backplane substrate connected to a ground wiring. 8. The method of claim 7,
A light blocking pattern positioned at an edge of the display area extends to the non-display area and is grounded. The method of claim 1,
The light blocking pattern is in direct contact with the substrate,
a buffer layer between the light blocking pattern and the active layer;
A backplane substrate further comprising: a gate insulating layer between the active layer and the gate line; and an interlayer insulating layer between the gate line, the data line including the source electrode, and the drain electrode. The method of claim 1,
a gate driver at both ends of the gate line in the non-display area;
The electrodes and the active pattern constituting the thin film transistors included in the gate driver are on the same layer as any one of the gate line, the data line, and the active layer provided in the display area. 11. The method of claim 10,
The electrodes of the thin film transistor included in the gate driver include a driver part gate electrode, a driver part source electrode, and a driver part drain electrode,
The driver part gate electrode is a backplane substrate having two overlapping parts with the active pattern. a substrate having a display area including a pixel area on a matrix at a center and a non-display area at an outer side;
a gate line and a data line crossing each other on the substrate;
an active layer having three or more overlapping portions with the gate line in each of the pixel regions, the active layer having a curved portion between the overlapping portions and integrally formed;
a source electrode and a drain electrode connected to both ends of the active layer;
A light blocking pattern covering a first overlapping portion closest to a first end portion of the active layer connected to the source electrode and a second overlapping portion closest to a second end portion of the active layer connected to the drain electrode under the active layer ;
a pixel electrode connected to the drain electrode in the pixel region;
an opposing substrate facing the substrate; and
a liquid crystal layer between the substrate and the opposite substrate;
the active layer includes a channel region corresponding to the overlapping portions with the gate line, a low-concentration impurity region in lateral contact with each of the channel region, and a high-concentration impurity region in lateral contact with the low-concentration impurity region;
In the active layer, at least one third overlapping portion between the first overlapping portion and the second overlapping portion and a low concentration impurity region in contact with a side of the third overlapping portion do not overlap the light blocking pattern. 13. The method of claim 12,
a common electrode covering a plurality of pixel areas on the substrate; and
The liquid crystal display device further comprising a metal line connected to each of the common electrodes. 14. The method of claim 13,
The pixel electrode is located above the common electrode,
A liquid crystal display connected to the drain electrode at a portion that does not overlap the common electrode. 11. The method of claim 10,
The gate driver is a backplane substrate including a frequency signal of 30 Hz or less. The method of claim 1,
a backplane substrate in which the first and second overlapping portions and the low concentration impurity regions in lateral contact with the first and second overlapping portions, respectively, overlap the light blocking pattern.

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