JP2011142227A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which has superior writing characteristics and data holding characteristics. <P>SOLUTION: The semiconductor storage device includes: a substrate 101; and a memory cell transistor 201 including a gate insulating film 111 functioning as an FN (Fowler-Nordheim) tunnel film, a floating gate 112, an inter-gate insulating film 113 functioning as a charge block film, and a control gate 114, those being formed in order on the substrate 101. Further, the memory cell transistor includes a charge trap layer 121 sandwiched between the floating gates from above and below and functioning to trap electric charges, and the floating gate 112 covers an upper surface and a lower surface, and a pair of mutually opposite side surfaces, of the charge trap layer 121. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  A memory cell of a NAND flash memory is generally composed of a gate insulating film, a floating gate, an inter-gate insulating film, and a control gate that are sequentially formed on a substrate. In such a memory cell, characteristics such as a threshold voltage (Vth) per charge increase as the memory cell shrinks, and deterioration of charge retention characteristics (retention characteristics) becomes a serious problem.

  In the memory cell as described above, the capacity coupling ratio (Cr) between the floating gate and the control gate is further reduced as the cell size is reduced. As a result, the electric field strength applied to the inter-gate insulating film at the time of writing into the memory cell increases, and carriers escape from the floating gate through the inter-gate insulating film. As a result, there is a problem that sufficient writing to the memory cell cannot be performed.

  Therefore, in the memory cell of the NAND flash memory, it is necessary to stabilize carrier retention in the floating gate and capture a large number of carriers in the floating gate.

  Patent Documents 1 and 2 describe examples of a semiconductor memory device including a plurality of floating gates and an insulating film formed between these floating gates. Patent Document 3 describes an example of a semiconductor memory device including a floating gate including an insulating film.

JP 2009-141354 A JP 2007-250974 A JP 2009-1135 A

  An object of the present invention is to provide a semiconductor memory device having excellent writing characteristics and data retention characteristics.

  One embodiment of the present invention includes, for example, a substrate, a gate insulating film functioning as an FN (Fowler-Nordheim) tunnel film, a floating gate, and a gate functioning as a charge blocking film, which are sequentially formed on the substrate. A memory cell transistor including an insulating film and a control gate, wherein the memory cell transistor further includes a charge trap layer formed to be sandwiched between the floating gate and having a function of trapping charges; In the semiconductor memory device, the gate covers an upper surface and a lower surface of the charge trap layer and a set of side surfaces facing each other.

  Another aspect of the present invention includes, for example, a substrate, a gate insulating film sequentially formed on the substrate, and a selection or peripheral transistor including a gate electrode, and the gate insulating film is formed on the substrate. The gate electrode includes a first electrode layer, a second insulating film, and a second electrode layer formed in order on the first insulating film, and the first electrode layer And the second electrode layer is electrically connected through an opening provided in the second insulating film, and the selection or peripheral transistor is further formed to be sandwiched between the first electrode layer and the first electrode layer, A semiconductor memory including a charge trap layer having a function of trapping charges, wherein the first electrode layer covers an upper surface, a lower surface, and a pair of side surfaces facing each other. Device.

  According to the present invention, it is possible to provide a semiconductor memory device having excellent write characteristics and data retention characteristics.

1 is a plan view schematically showing a configuration of a semiconductor memory device according to a first embodiment. 1A and 1B are a plan view and a side sectional view showing a configuration of a semiconductor memory device according to a first embodiment. It is a conceptual diagram for demonstrating a direct tunnel film | membrane and a FN tunnel film | membrane. It is the graph which showed the actual value of the direct tunnel current and the FN tunnel current. It is the top view and side sectional view which show the structure of the semiconductor memory device of 2nd Embodiment. It is the top view and side sectional view which show the structure of the semiconductor memory device of 3rd Embodiment. It is the top view and side sectional view which show the structure of the semiconductor memory device of 4th Embodiment. It is a sectional side view (1/2) which shows the manufacturing method of the semiconductor memory device of 5th Embodiment. FIG. 25 is a side cross-sectional view (2/2) showing the method for manufacturing the semiconductor memory device of the fifth embodiment. It is a side sectional view (1/2) showing a method for manufacturing a semiconductor memory device of a sixth embodiment. It is a side sectional view (2/2) showing the method for manufacturing the semiconductor memory device of the sixth embodiment. It is a sectional side view (1/2) which shows the manufacturing method of the semiconductor memory device of 7th Embodiment. FIG. 25 is a side cross-sectional view (2/2) illustrating the method for manufacturing the semiconductor memory device according to the seventh embodiment. It is a sectional side view (1/4) which shows the manufacturing method of the semiconductor memory device of 8th Embodiment. It is a sectional side view (2/4) which shows the manufacturing method of the semiconductor memory device of 8th Embodiment. It is a sectional side view (3/4) which shows the manufacturing method of the semiconductor memory device of 8th Embodiment. It is a sectional side view (4/4) which shows the manufacturing method of the semiconductor memory device of 8th Embodiment. It is a sectional side view showing the composition of the semiconductor memory device of a 9th embodiment. It is a sectional side view which shows the structure of the semiconductor memory device of 10th Embodiment. It is a side sectional view showing the composition of the semiconductor memory device of an 11th embodiment. It is a sectional side view which shows the structure of the semiconductor memory device of 12th Embodiment. It is a sectional side view which shows the structure of the semiconductor memory device of 13th Embodiment.

  Embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view schematically showing the configuration of the semiconductor memory device of the first embodiment. The semiconductor memory device of FIG. 1 is a NAND flash memory.

In FIG. 1, the memory cell array region is indicated by R _C and the select transistor region is indicated by R _S. 1 further shows a bit line BL extending in a first direction parallel to the surface of the substrate, and a word line WL and a selection line SG extending in a second direction parallel to the surface of the substrate. The first and second directions are indicated by arrows X and Y, respectively, and are orthogonal to each other.

In the memory cell array region R _C, at each intersection P _C between the bit line BL and a word line WL, the memory cell transistor (memory cell) is provided. On the other hand, in the selection transistor region R _S , a selection transistor is provided at each intersection P _S between the bit line BL and the selection line SG. The memory cell transistor is electrically connected to the bit line BL and the word line WL, and the selection transistor is electrically connected to the bit line BL and the selection line SG.

FIG. 1 further shows an element isolation region R ₁ and an active region (element region) R ₂ . Both the element isolation region R ₁ and the active region R ₂ extend in the X direction, and are alternately provided on the surface of the substrate along the Y direction. Select transistor and the memory cell transistors are both formed on the active region R _2.

  Hereinafter, the memory cell transistor is simply referred to as a cell transistor.

  FIG. 2 is a plan view and a side sectional view showing the configuration of the semiconductor memory device of the first embodiment.

FIG. 2A is a plan view showing a part of the memory cell array region _RC shown in FIG. 2 (B) and 2 (C) are GC (Gate Conductor) cross-sectional views taken along lines X ₁ and X ₂ shown in FIG. 2 (A). The former is a cross-section at the center of GC, and the latter is The cross section of GC end part is represented. 2 (D) and 2 (E) are AA (Active Area) cross-sectional views along line Y _{1 and} line Y ₂ shown in FIG. 2 (A). The former is a cross-section at the center of AA, and the latter is The cross section of an AA edge part is represented.

  2B to 2E show a plurality of cell transistors 201 formed on the substrate 101. FIG. The substrate 101 is a semiconductor substrate such as a silicon substrate, for example. The substrate 101 may be a p-type substrate or an n-type substrate, but is a p-type substrate in this embodiment.

  As shown in FIGS. 2B to 2E, each cell transistor 201 includes a gate insulating film 111, a floating gate 112, an inter-gate insulating film 113, a control gate 114, and a control gate 114, which are sequentially formed on the substrate 101. Is included.

  The gate insulating film 111 is a tunnel insulating film that functions as an FN (Fowler-Nordheim) tunnel film. The FN tunnel film is an insulating film having a thickness in which charge transmission by FN tunneling is dominant. The thickness of the gate insulating film 111 is an effective thickness in terms of EOT (Equivalent Oxide Thickness), that is, in terms of silicon oxide thickness, and is, for example, 3 nm or more, preferably 3 to 5 nm. The gate insulating film 111 is appropriately referred to as a TOX film.

The floating gate 112 functions as a charge storage film for storing charges. The floating gate 112 is, for example, a polysilicon layer doped with impurities. The impurity is, for example, an n-type impurity such as phosphorus, and the impurity concentration is, for example, 1 × 10 ²⁰ cm ⁻³ . However, the conductivity type, type, and concentration of the impurities to be employed are not limited to these. The floating gate 112 may be a semiconductor layer such as a polysilicon layer or a conductive layer such as a metal layer. The floating gate 112 is appropriately referred to as an FG layer.

  The inter-gate insulating film 113 functions as a charge blocking film that blocks charges injected from the substrate 101 to the floating gate 112 from passing to the control gate 114. The thickness of the inter-gate insulating film 113 of this embodiment is an effective film thickness in terms of EOT, and is thicker than the thickness of the gate insulating film 111. The inter-gate insulating film 113 is appropriately expressed as an IPD (Inter Poly-Si Dielectric) film.

  The control gate 114 functions as a control electrode for controlling the potential of the cell transistor 201. The control gate 114 is, for example, a polysilicon layer. The control gate 114 is shown as a word line WL in FIG. The control gate 114 is appropriately expressed as a CG layer.

  Note that the inter-gate insulating film 113 and the control gate 114 are formed so as to straddle between the cell transistors 201 arranged in the Y direction, as shown in FIGS.

  Further, as shown in FIGS. 2B to 2E, each cell transistor 201 is formed so as to be surrounded by the floating gate 112 so as to surround the periphery, and has a charge trap layer 121 having a function of trapping charges. Is included.

  Therefore, in this embodiment, when charge is injected from the substrate 101 to the floating gate 112, a part of the charge is trapped in the charge trap layer 121. In other words, it can be said that the charge storage layer of each cell transistor 201 includes the floating gate 112 and the charge trap layer 121.

  Thereby, in the present embodiment, carrier retention in the charge storage layer is stabilized as compared with the case where the charge storage layer is configured by only the floating gate 112. Therefore, according to the present embodiment, the charge retention characteristic (retention characteristic) of the cell transistor 201 is improved.

  Further, in the present embodiment, it is possible to increase the carrier concentration in the charge storage layer as compared with the case where the charge storage layer is composed of only the floating gate 112, and as a result, more carriers are captured in the charge storage layer. It becomes possible to do. Therefore, according to the present embodiment, the write characteristics of the cell transistor 201 are improved.

  As described above, in this embodiment, a fine semiconductor memory excellent in writing characteristics and data retention characteristics is provided by providing the charge trap layer 121 in each cell transistor 201 so that the floating gate 112 is sandwiched between the upper and lower sides. An apparatus can be realized.

Examples of the charge trap layer 121 include an insulating film such as a silicon nitride film (Si ₃ N ₄ ), a hafnium oxide film (HfO ₂ ), and an aluminum oxide film (Al ₂ O ₃ ). The charge trap layer 121 is appropriately referred to as a CT layer.

  2B to 2C, a diffusion layer 131 formed so as to sandwich the cell transistor 201 in the substrate 101, an interlayer insulating film 132 formed on the substrate 101 so as to cover the cell transistor 201, An element isolation insulating film 133 formed on the substrate 101 and interposed between the cell transistors 201 is shown. The diffusion layer 131 functions as a source / drain diffusion layer of the cell transistor 201. On the element isolation insulating film 133, as shown in FIGS. 2D and 2E, an intergate insulating film 113 and a control gate 114 formed so as to straddle between the cell transistors 201 are stacked.

  Here, the shapes of the floating gate 112 and the charge trap layer 121 will be described.

  In this embodiment, as shown in FIGS. 2B to 2E, the charge trap layer 121 has a rod shape extending in the X direction, and the floating gate 112 surrounds the charge trap layer 121. It has a cylindrical shape extending in the X direction so as to surround it. 2D and 2E show the cross-sectional shapes of these rods and cylinders.

  Therefore, although the floating gate 112 of each cell transistor 201 appears to be divided into an upper layer portion and a lower layer portion when viewed in FIG. 2B, in reality, the side wall portion illustrated in FIG. The upper layer part and the lower layer part are connected. Therefore, the entire floating gate 112 of each cell transistor 201 is formed of a continuous member. Thereby, the potential of the floating gate 112 of each cell transistor 201 becomes substantially uniform as a whole if the influence of the depletion layer or the like is ignored.

In FIG. 2B, a pair of side surfaces of the charge trap layer 121 facing each other are indicated by S ₁ and S ₂ . On the other hand, in FIG. 2D and FIG. 2E, another set of side surfaces of the charge trap layer 121 facing each other are indicated by S ₃ and S ₄ . The side surfaces S ₁ and S ₂ are side surfaces perpendicular to the X direction and face the X direction, and the side surfaces S ₃ and S ₄ are side surfaces perpendicular to the Y direction and face the Y direction. Yes.

In the present embodiment, as described above, the charge trap layer 121 has a rod shape extending in the X direction, and the floating gate 112 extends in the X direction so as to surround the charge trap layer 121. It has the shape of As a result, as shown in FIGS. 2B to 2E, the floating gate 112 covers the upper and lower surfaces of the charge trap layer 121 and a pair of side surfaces S ₃ and S ₄ perpendicular to the Y direction. . On the other hand, as shown in FIG. 2B, the side surfaces S ₁ and S ₂ are not covered with the floating gate 112 and are formed on the insulating film (interlayer insulating film 132) provided on the side of the cell transistor 201. It touches.

  Here, the direct tunnel film and the FN tunnel film will be described.

  FIG. 3 is a conceptual diagram for explaining the direct tunnel film and the FN tunnel film. The horizontal direction in FIG. 3 represents the thickness direction of the insulating film, and the vertical direction in FIG. 3 represents the height direction of the potential inside and outside the insulating film.

  FIG. 3A shows a thin insulating film. The insulating film illustrated in FIG. 3A directly corresponds to a tunnel film. The direct tunnel film is an insulating film having a thickness in which charge transmission by direct tunneling is dominant. As indicated by an arrow A, the charges located in the vicinity of the direct tunnel film cause direct tunneling with a certain probability and directly pass through the tunnel film.

  On the other hand, FIG. 3B shows a thick insulating film. The insulating film illustrated in FIG. 3B corresponds to an FN tunnel film. As described above, the FN tunnel film is an insulating film having a thickness in which charge transmission by FN tunneling is dominant. There is a low probability that charges located in the vicinity of the FN tunnel film pass through the FN tunnel film by direct tunneling. However, when an electric field is applied to the FN tunnel film, the potential barrier of the FN tunnel film is inclined and the barrier becomes thin. As a result, the charges located near the FN tunnel film cause FN tunneling and pass through the FN tunnel film as indicated by an arrow B.

FIG. 4 is a graph showing measured values of the direct tunnel current and the FN tunnel current. The horizontal axis in FIG. 4 represents the gate voltage [V] applied to the nMOSFET by n + poly, and the vertical axis in FIG. 4 represents the current density [μA / cm ² ] of the gate current in the nMOSFET.

  FIG. 4 shows the direct tunnel current and the FN tunnel current when the effective thickness of the gate insulating film (TOX film (tunnel insulating film)) of the nMOSFET is 2.58 nm, 3.65 nm, 4.55 nm, and 5.70 nm. And the theoretical value of the FN tunnel current is shown.

  According to FIG. 4, when the effective film thickness of the TOX film is 3.65 nm, 4.55 nm, and 5.70 nm, the gate current is almost equal to the FN in the entire gate voltage region above the gate voltage at which the gate current starts to flow. It almost matches the tunnel current. On the other hand, when the effective film thickness of the TOX film is 2.58 nm, the gate current coincides with the FN tunnel current only in a region having a predetermined voltage or higher in the gate voltage region.

  From this, it can be seen that in an insulating film having an effective film thickness of about 3 nm or more, charge transmission by FN tunneling is dominant. Therefore, an insulating film having an effective film thickness of 3 nm or more can be regarded as an FN tunnel film. Therefore, in this embodiment, the effective film thickness of the gate insulating film 111 is set to 3 nm or more. Thereby, the gate insulating film 111 becomes an FN tunnel film.

  For details of the graph shown in FIG. 4, refer to “A. Gupta et al., IEEE Trans. Electron Device Lett. 18 (1977) 580.”.

  As described above, in this embodiment, the charge trap layer 121 is provided in each cell transistor 201 so that the floating gate 112 is sandwiched and surrounded by the upper and lower sides. As a result, the charge storage layer of each cell transistor 201 includes the floating gate 112 and the charge trap layer 121. As a result, as compared with the case where the charge storage layer of each cell transistor 201 is composed of only the floating gate 112, carrier retention in the charge storage layer is stabilized, and the charge retention characteristics (retention characteristics) of the cell transistor 201 are improved. . Furthermore, more carriers can be captured in the charge storage layer, and the writing characteristics of the cell transistor 201 are improved.

  Therefore, according to the present embodiment, it is possible to realize a semiconductor memory device having excellent writing characteristics and data retention characteristics.

  Hereinafter, second to thirteenth embodiments of the present invention will be described. These embodiments are modifications of the first embodiment, and these embodiments will be described with a focus on differences from the first embodiment.

(Second Embodiment)
FIG. 5 is a plan view and a side sectional view showing the configuration of the semiconductor memory device of the second embodiment.

  In the first embodiment, as shown in FIGS. 2D and 2E, the height of the upper surface of the element isolation insulating film 133 is equal to the height of the upper surface of the floating gate 112. As a result, the heights of the lower surfaces of the intergate insulating film 113 and the control gate 114 on the element isolation insulating film 133 are equal to the heights of the lower surfaces of the intergate insulating film 113 and the control gate 114 on the floating gate 112, respectively. .

  On the other hand, in the second embodiment, as shown in FIGS. 5D and 5E, the height of the upper surface of the element isolation insulating film 133 is lower than the height of the upper surface of the floating gate 112. As a result, the heights of the lower surfaces of the intergate insulating film 113 and the control gate 114 on the element isolation insulating film 133 are lower than the heights of the lower surfaces of the intergate insulating film 113 and the control gate 114 on the floating gate 112, respectively. In addition, the inter-gate insulating film 113 and the control gate 114 are dropped between the cell transistors 201 adjacent in the Y direction. Thereby, in the second embodiment, capacitive coupling between the floating gate 112 and the control gate 114 is larger than that in the first embodiment.

  According to the second embodiment, similarly to the first embodiment, it is possible to realize a semiconductor memory device having excellent write characteristics and data retention characteristics.

  Further, according to the second embodiment, the capacitive coupling between the floating gate 112 and the control gate 114 can be increased by dropping the inter-gate insulating film 113 and the control gate 114 between the cell transistors 201.

  Note that the dropping structure of the second embodiment can also be applied to third and fourth embodiments described later.

(Third embodiment)
FIG. 6 is a plan view and a side sectional view showing the configuration of the semiconductor memory device of the third embodiment.

In the first embodiment, as shown in FIGS. 2B to 2E, the floating gate 112 has a pair of side surfaces S ₃ and S ₄ perpendicular to the upper and lower surfaces of the charge trap layer 121 and the Y direction. Covering.

In contrast, in the third embodiment, as shown in FIGS. 6B to 6E, the floating gate 112 includes a pair of side surfaces S perpendicular to the upper and lower surfaces of the charge trap layer 121 and the X direction. _1, and S _2, and covers the Y direction perpendicular to a pair of side surfaces S _3, S _4. That is, the floating gate 112 covers the entire surface of the charge trap layer 121. Thereby, in the third embodiment, the charge retention characteristic and the write characteristic of the cell transistor 201 are improved as in the first embodiment.

  Therefore, according to the third embodiment, similarly to the first embodiment, it is possible to realize a semiconductor memory device having excellent write characteristics and data retention characteristics.

  When comparing the first embodiment and the third embodiment, the cell transistor 201 of the first embodiment has an advantage that it is easier to manufacture than the cell transistor 201 of the third embodiment, as will be described later.

(Fourth embodiment)
FIG. 7 is a plan view and a side sectional view showing the configuration of the semiconductor memory device of the fourth embodiment.

  In the first embodiment, as shown in FIGS. 2B to 2E, the charge trap layer 121 has a rod-like shape extending in the X direction, and the floating gate 112 is formed around the charge trap layer 121. Has a cylindrical shape extending in the X direction.

On the other hand, in the fourth embodiment, as shown in FIGS. 7B to 7E, the charge trap layer 121 has a rod shape extending in the Y direction, and the floating gate 112 has a charge trap. It has a cylindrical shape extending in the Y direction so as to surround the periphery of the layer 121. As a result, as shown in FIGS. 7B to 7E, the floating gate 112 covers the upper and lower surfaces of the charge trap layer 121 and a pair of side surfaces S ₁ and S ₂ perpendicular to the X direction. . On the other hand, as shown in FIG. 7D, the side surfaces S ₃ and S ₄ are not covered with the floating gate 112 and are provided on the side of the cell transistor 201 (element isolation insulating film 133). Is in contact with Thereby, in the fourth embodiment, the charge retention characteristic and the write characteristic of the cell transistor 201 are improved as in the first embodiment.

  Therefore, according to the fourth embodiment, similarly to the first embodiment, it is possible to realize a semiconductor memory device having excellent write characteristics and data retention characteristics.

  When comparing the first, third, and fourth embodiments, the cell transistor 201 of the first and fourth embodiments is easier to manufacture than the cell transistor 201 of the third embodiment, as will be described later. There is. Further, the cell transistor 201 of the first embodiment has an advantage that it is easier to manufacture than the cell transistor 201 of the fourth embodiment, as will be described later.

(Fifth embodiment)
8 and 9 are side sectional views showing the method for manufacturing the semiconductor memory device of the fifth embodiment. In the fifth embodiment, an example of a method for manufacturing the semiconductor memory device shown in FIG. 2 will be described.

  First, as illustrated in FIG. 8A, a gate insulating material 301 which is a material of the gate insulating film 111 of the cell transistor 201 is formed over the substrate 101. Next, a first floating gate material 302A, which is a material of the floating gate 112 of the cell transistor 201, is formed over the gate insulating material 301 (FIG. 8A).

  Next, a charge trap material 311 to be a material of the charge trap layer 121 of the cell transistor 201 is formed over the first floating gate material 302A (FIG. 8A). Next, a second floating gate material 302B, which is a material of the floating gate 112 of the cell transistor 201, is formed over the charge trap material 311 (FIG. 8A).

  In the present embodiment, the first and second floating gate materials 302A and B are made of polysilicon doped with phosphorus, but may be other semiconductors or conductors. In addition, as the charge trapping material 311, any substance that has an effect of capturing electrons and holes, such as a silicon nitride film containing excessive silicon, can be used.

  Next, as shown in FIG. 8A, a mask layer 321 is deposited over the second floating gate material 302B.

  The material of the mask layer 321 needs to be a substance that is difficult to be peeled off during the etching process of the first floating gate material 302A, the charge trapping material 311, and the second floating gate material 302B. Appropriate materials should be selected in consideration of RIE (Reactive Ion Etching) conditions. In this embodiment, the material of the mask layer 321 is a silicon oxide film.

  Next, a resist film is deposited on the mask layer 321 and the resist film is patterned by lithography. Next, the mask layer 321, the second floating gate material 302B, the charge trap material 311, and the first floating gate material 302A are etched by RIE using the resist film (FIG. 8B). Next, the resist film is removed.

By the etching process, a plurality of trenches T ₁ extending in the X direction through the mask layer 321, the second floating gate material 302B, the charge trap material 311 and the first floating gate material 302A are formed (FIG. 8). (B)). In the groove T _1, the mask layer 321, a second floating gate material 302B, the charge trapping material 311, and the side surfaces of the first floating gate material 302A is exposed (FIG. 8 (B)).

Next, as shown in FIG. 8C, the charge trapping material 311 is etched from the side surface of the charge trapping material 311 by isotropic etching. Thereby, a part of the charge trap material 311 is removed, and a cavity C ₁ is formed on the side surface of the charge trap material 311.

Next, as shown in FIG. 9 (A), it performs a selective deposition of the third floating gate material 302C which is a material of the floating gate 112, the cavity C _1, embedding the third floating gate material 302C. As a result, the first floating gate material 302A and the second floating gate material 302B are connected by the third floating gate material 302C.

  In this embodiment, the third floating gate material 302C is made of polysilicon doped with phosphorus in order to electrically connect the first floating gate material 302A and the second floating gate material 302B. It may be a semiconductor or a conductor. The third floating gate material 302C is, for example, polysilicon that is not doped with impurities, and the third floating gate material 302C is diffused from the first and second floating gate materials 302A and 302B to the third floating gate material 302C, so that the third floating gate material 302C is formed. The gate material 302C may be doped with impurities.

Next, as shown in FIG. 9B, the gate insulating material 301 at the bottom of the trench T _{1 and} a part of the substrate 101 are etched by RIE using the mask layer 321. Thus, the trench T ₁ is processed into an element isolation groove for forming the element isolation insulating film 133 (FIG. 2). Also, this etching process, as shown in FIG. 9 (B), in the third floating gate material 302C, protruding part in the groove T ₁ is removed, the shape of the third floating gate material 302C is trimmed.

Next, as shown in FIG. 9C, the trench T ₁ is filled with an appropriate insulating film such as a silicon oxide film. Thus, an element isolation insulating film 133 is formed over the substrate 101 (FIG. 9C).

  In this embodiment, thereafter, the mask layer 321 is removed, and the height of the upper surface of the element isolation insulating film 133 is adjusted as necessary. Furthermore, an inter-gate insulating material that is a material of the inter-gate insulating film 113 (FIG. 2) of the cell transistor 201 and the control gate 114 (see FIG. 2) on the second floating gate material 302B and the element isolation insulating film 133. A control gate material as a material of FIG. 2) is formed in order. Further, the control gate material, the inter-gate insulating material, the second floating gate material 302B, the charge trap material 311, the first floating gate material 302A, and the gate electrode material 301 are etched to form a cell transistor on the substrate 101. 201 is formed. In this way, the semiconductor memory device shown in FIG. 2 is manufactured.

As described above, in the present embodiment, the first floating gate material 302A, the charge trap material 311, and the second floating gate material 302B are sequentially formed on the substrate 101, and the cavity C ₁ is formed on the side surface of the charge trap material 311. forming a buried a third floating gate material 302C in the cavity C _1. As a result, a structure in which the floating gate 112 surrounds the charge trap layer 121 with the upper and lower sides interposed therebetween is realized. Therefore, according to the present embodiment, it is possible to realize a semiconductor memory device having excellent writing characteristics and data retention characteristics.

(Sixth embodiment)
10 and 11 are side sectional views showing a method for manufacturing a semiconductor memory device according to the sixth embodiment. In the sixth embodiment, another example of a method for manufacturing the semiconductor memory device shown in FIG. 2 will be described.

  The processes shown in FIGS. 10A to 11C of the sixth embodiment are performed in the same manner as the processes shown in FIGS. 8A to 9C of the fifth embodiment, respectively. However, in the process of FIG. 9A of the fifth embodiment, the third floating gate material 302C is formed by selective deposition, whereas in the process of FIG. 11A of the sixth embodiment, the third floating gate material 302C is formed. The floating gate material 302C is formed by isotropic deposition. Therefore, in the fifth embodiment, the third floating gate material 302C is formed only on the surfaces of the first and second floating gate materials 302A and B, whereas in the sixth embodiment, the third floating gate material 302C is formed. The gate material 302C is formed so as to cover the entire surface of the substrate 101.

In the sixth embodiment, by the etching process in the step of FIG. 11B, an extra portion outside the cavity C ₁ in the third floating gate material 302C is removed, and the third floating gate material 302C is removed. Arrange the shape.

As described above, in this embodiment, as in the fifth embodiment, the first floating gate material 302A, the charge trap material 311, and the second floating gate material 302B are sequentially formed on the substrate 101, and the charge trap material. A cavity C ₁ is formed on the side surface of 311, and a third floating gate material 302 C is embedded in the cavity C ₁ . As a result, a structure in which the floating gate 112 surrounds the charge trap layer 121 with the upper and lower sides interposed therebetween is realized. Therefore, according to the present embodiment, it is possible to realize a semiconductor memory device having excellent writing characteristics and data retention characteristics.

  The selective deposition of the fifth embodiment has an advantage that the shape of the floating gate 112 can be easily controlled. On the other hand, the isotropic deposition of the sixth embodiment has an advantage that the third floating gate material 302C can be easily doped with impurities.

(Seventh embodiment)
12 and 13 are side sectional views showing the method for manufacturing the semiconductor memory device of the seventh embodiment. In the seventh embodiment, an example of a method for manufacturing the semiconductor memory device shown in FIG. 5 will be described. In FIG. 5, the inter-gate insulation 113 and the control gate 114 are dropped between the cell transistors 201.

  In this embodiment, first, the processes of FIGS. 12A and 12B are the same as the processes of FIGS. 8A to 9C (or the processes of FIGS. 10A to 11C). To do.

Next, as shown in FIG. 12C, the mask layer 321 is removed and the element isolation insulating film 133 is dropped. Accordingly, the height of the upper surface S _A of the element isolation insulating film 133 is lower than the upper surface height of the S _B of the second floating gate material 302B.

  Next, as shown in FIG. 13A, an inter-gate insulating material 303 which is a material of the inter-gate insulating film 113 of the cell transistor 201 is formed over the second floating gate material 302B and the element isolation insulating film 133. . As a result, the inter-gate insulating material 303 is dropped between the cell transistors 201.

  Next, as illustrated in FIG. 13B, a control gate material 304 that is a material of the control gate 114 of the cell transistor 201 is formed over the inter-gate insulating material 303. As a result, the control gate material 304 is dropped between the cell transistors 201.

  In this embodiment, thereafter, the control gate material 304, the inter-gate insulating material 303, the second floating gate material 302B, the charge trap material 311, the first floating gate material 302A, and the gate electrode material 301 are etched to form a substrate. A cell transistor 201 is formed on 101. In this way, the semiconductor memory device shown in FIG. 5 is manufactured.

As described above, in this embodiment, as in the fifth embodiment, the first floating gate material 302A, the charge trap material 311, and the second floating gate material 302B are sequentially formed on the substrate 101, and the charge trap material. A cavity C ₁ is formed on the side surface of 311, and a third floating gate material 302 C is embedded in the cavity C ₁ . As a result, a structure in which the floating gate 112 surrounds the charge trap layer 121 with the upper and lower sides interposed therebetween is realized. Therefore, according to the present embodiment, it is possible to realize a semiconductor memory device having excellent writing characteristics and data retention characteristics.

  Further, according to the present embodiment, the capacitive coupling between the floating gate 112 and the control gate 114 can be increased by dropping the inter-gate insulating film 113 and the control gate 114 between the cell transistors 201.

(Eighth embodiment)
14 to 17 are side sectional views showing the method for manufacturing the semiconductor memory device according to the eighth embodiment. In the eighth embodiment, an example of a method for manufacturing the semiconductor memory device shown in FIG. 6 will be described.

  In the present embodiment, first, similarly to the seventh embodiment, the processes of FIGS. 12A to 13B are performed. FIG. 14A shows an AA cross section of the semiconductor memory device in which the step of FIG. 13B is performed. FIG. 14B shows a GC cross section of the semiconductor memory device on the Q line shown in FIG.

  In the present embodiment, next, as shown in FIG. 14C, a mask layer 322 is deposited on the control gate material 304.

  Next, a resist film is deposited on the mask layer 322, and the resist film is patterned by lithography. Next, the mask layer 322 and the control gate material 304 are etched by RIE using the resist film (FIG. 14C). At this time, if the second floating gate material 302B is not exposed, a part of the inter-gate insulating material 303 may be removed.

By the etching process, a plurality of trenches T ₂ that penetrate the mask layer 322 and the control gate material 304 and extend in the Y direction are formed (FIG. 14C). The side surfaces of the mask layer 322 and the control gate material 304 are exposed in the trench T ₂ (FIG. 14C).

  Next, as shown in FIG. 15A, a sidewall film 331 is formed on the side surfaces of the mask layer 322 and the control gate material 304.

  Any material can be used for the mask layer 322 and the sidewall film 331 as long as the material is resistant to the etching processing of the control gate material 304, the intergate insulating material 303, and the like. A silicon oxide film is adopted as the material.

Next, as shown in FIG. 15 (B), by RIE using the mask layer 322 and the sidewall film 331, the gate insulating material 303 at the bottom of the trench T _2, the second floating gate material 302B, the charge trapping material 311 Etching of the first floating gate material 302A is performed. By the etching process, the groove T _2, the gate insulating material 303, the second floating gate material 302B, the charge trapping material 311, and the side surfaces of the first floating gate material 302A is exposed (FIG. 15 (B) ).

Next, as shown in FIG. 15C, the charge trapping material 311 is etched from the side surface of the charge trapping material 311 by isotropic etching. Thereby, a part of the charge trap material 311 is removed, and a cavity C ₂ is formed on the side surface of the charge trap material 311.

Next, as shown in FIG. 16 (A), it performs a selective deposition of the fourth floating gate material 302D which is a material of the floating gate 112, the cavity C _2, embed the fourth floating gate material 302D. Thereby, the first floating gate material 302A and the second floating gate material 302B are connected by the third and fourth floating gate materials 302C and 302D. Note that the fourth floating gate material 302D may be formed by isotropic deposition instead of selective deposition.

  In this embodiment, the fourth floating gate material 302D is made of polysilicon doped with phosphorus so as to electrically connect the first floating gate material 302A and the second floating gate material 302B. It may be a semiconductor or a conductor. The fourth floating gate material 302D is, for example, polysilicon not doped with impurities, and the fourth floating gate material 302D is diffused into the fourth floating gate material 302D by diffusing impurities from the first and second floating gate materials 302A and B. The gate material 302D may be doped with impurities.

Next, as shown in FIG. 16B, the sidewall film 331 is removed. Next, as shown in FIG. 17A, the inter-gate insulating material 303 protruding into the trench T ₂ and the first, second, and fourth floating gate materials 302A, B are formed by RIE using the mask layer 322. , D are etched. Thus, the gate insulating material 303, and the first, second, fourth floating gate material 302A, B, trimmed shape and D, the groove T ₂ is processed into a shape shown in FIG. 17 (A). Next, as shown in FIG. 17B, the mask layer 322 is removed.

  In this embodiment, the sidewall insulating film of the cell transistor 201 and the diffusion layer 131 and the interlayer insulating film 132 shown in FIG. 6 are then formed. In this way, the semiconductor memory device shown in FIG. 6 is manufactured.

As described above, in the present embodiment, the first floating gate material 302A, the charge trap material 311, and the second floating gate material 302B are sequentially formed on the substrate 101, and the cavity C ₁ is formed on the side surface of the charge trap material 311. , C ₂ , and third and fourth floating gate materials 302 C, D are embedded in the cavities C ₁ , C ₂ , respectively. Thereby, a structure in which the floating gate 112 covers the entire surface of the charge trap layer 121 is realized. Therefore, according to the present embodiment, it is possible to realize a semiconductor memory device having excellent writing characteristics and data retention characteristics.

In the fifth to seventh embodiments, the cavity C ₁ corresponds to a cavity in the method for manufacturing a semiconductor memory device of the present invention, and the third floating gate material 302C is used in the method for manufacturing a semiconductor memory device of the present invention. This corresponds to the third floating gate material.

On the other hand, in the eighth embodiment, the cavities C ₁ and C ₂ correspond to the cavities in the method of manufacturing a semiconductor memory device of the present invention, and the third and fourth floating gate materials 302C and D correspond to those of the present invention. This corresponds to the third floating gate material in the method for manufacturing the semiconductor memory device.

In the eighth embodiment, the step of forming the cavity C ₁ (FIG. 8C) and the step of embedding the third floating gate material 302C in the cavity C ₁ (FIG. 9A) are omitted. It doesn't matter. Thereby, the semiconductor memory device shown in FIG. 7 can be manufactured. In this case, the cavity C ₂ corresponds to the cavity in the manufacturing method of the semiconductor memory device of the present invention, and the fourth floating gate material 302D is the third floating gate material in the manufacturing method of the semiconductor memory device of the present invention. It corresponds to.

  In the eighth embodiment, the inter-gate insulating material 303 and the control gate material 304 are dropped between the cell transistors 201 (FIG. 14A), but the inter-gate insulating material 303 and the control gate material 304 are It is not necessary to drop between the cell transistors 201.

(Ninth embodiment)
FIG. 18 is a side sectional view showing the configuration of the semiconductor memory device according to the ninth embodiment.

  FIG. 18A is a GC cross-sectional view of the I cross section shown in FIG. FIG. 18A shows the cell transistor 201 and the selection transistor 202 formed over the substrate 101.

  18B and 18C are side sectional views showing the configuration of the selection transistor 202. FIG. 18B and 18C are cross-sectional views taken along line AA in the α cross section and the β cross section shown in FIG.

  As shown in FIGS. 18A to 18C, the selection transistor 202 includes a gate insulating film 141 and a gate electrode 142 that are sequentially formed on the substrate 101. The gate insulating film 141 includes a first insulating film 151 formed on the substrate 101, and the gate electrode 142 includes a first electrode layer 152 and a second insulating film sequentially formed on the first insulating film 151. A film 153 and a second electrode layer 154 are included. In addition, the first electrode layer 152 and the second electrode layer 154 are electrically connected through an opening H provided in the second insulating film 153 (FIG. 18A).

  As shown in FIG. 18A, an opening H is provided in the second insulating film 153 of the selection transistor 202, and the second insulating film 153 is removed at the central portion (SG central portion) of the selection transistor 202. Then, the second insulating film 153 remains at the end (SG end).

  Therefore, at the SG end portion, as shown in FIG. 18B, the second electrode layer 154 is formed on the first electrode layer 152 and the element isolation insulating film 133 with the second insulating film 153 interposed therebetween. . On the other hand, in the SG central portion, as shown in FIG. 18C, the second electrode layer 154 is formed on the first electrode layer 152 and the element isolation insulating film 133 without the second insulating film 153 interposed therebetween. The first electrode layer 152 and the second electrode layer 154 are in direct contact with each other.

  Further, as shown in FIGS. 18A to 18C, the selection transistor 202 is further formed so as to be sandwiched and surrounded by the first electrode layer 152 and has a function of trapping charges. 155.

  As shown in FIGS. 18A to 18C, the charge trap layer 155 has a rod-like shape extending in the X direction, and the first electrode layer 152 surrounds the charge trap layer 155. It has a cylindrical shape extending in the X direction. 18B and 18C show the cross-sectional shapes of these rods and cylinders.

Therefore, although the first electrode layer 152 of each selection transistor 202 appears to be divided into an upper layer portion and a lower layer portion when viewed in FIG. 18A, actually, the first electrode layer 152 in FIGS. The upper layer part and the lower layer part are connected by the side wall part shown in FIG. Therefore, the first and second electrode layers 152 and 154 of each selection transistor 202 are entirely formed of a continuous member. Thereby, the potentials of the first and second electrode layers 152 and 154 of each selection transistor 202 are substantially uniform as a whole if the influence of the depletion layer and the like is ignored. In FIGS. 18B and 18C, a pair of side surfaces of the charge trap layer 155 facing each other are denoted by S ₅ and S ₆ .

In the present embodiment, as described above, the charge trap layer 155 has a rod-like shape extending in the X direction, and the first electrode layer 152 extends in the X direction so as to surround the charge trap layer 155. It has a cylindrical shape. As a result, as shown in FIGS. 18A to 18C, the first electrode layer 152 covers the upper and lower surfaces of the charge trap layer 155 and the pair of side surfaces S ₅ and S ₆ perpendicular to the Y direction. ing.

  As described above, in the present embodiment, the first electrode layer 152 of the selection transistor 202 is formed of the charge trap layer 155 in the same manner as the floating gate 112 of the cell transistor 201 sandwiches and surrounds the charge trap layer 121. Surrounds the top and bottom.

  Such a structure of the cell transistor 201 and the selection transistor 202 includes a first insulating film 151, a first electrode layer 152, a second insulating film 153, a second electrode layer 154, and a charge trapping layer 155, respectively. This is because the floating gate 112, the inter-gate insulating film 113, the control gate 114, and the charge trap layer 114 are formed from the same material layer.

  That is, the first insulating film 151 is formed by forming a common insulating material layer on the substrate 101 for forming the gate insulating film 111 and the first insulating film 151, and etching the insulating material layer by etching the gate insulating film 111 and the first insulating film 151. The first electrode layer 152, the second insulating film 153, the second electrode layer 154, and the charge trap layer 155 are formed in the same manner.

  As a result, the thicknesses of the first insulating film 151, the first electrode layer 152, the second insulating film 153, the second electrode layer 154, and the charge trap layer 155 are the gate insulating film 111, the floating gate 112, and the inter-gate insulation, respectively. The thickness is equal to that of the film 113, the control gate 114, and the charge trap layer 121. Note that the thickness of the floating gate 112 means the width from the upper surface of the gate insulating film 111 to the lower surface of the inter-gate insulating film 113, and the thickness of the first electrode layer 152 is from the upper surface of the first insulating film 151. 2 means the width to the lower surface of the insulating film 153.

  Thus, in the present embodiment, the first electrode layer 152 of the selection transistor 202 surrounds the charge trap layer 155 with the upper and lower sides sandwiched therebetween. On the other hand, in this embodiment, it may be considered that the charge trap layer 155 is not provided in the selection transistor 202. However, in this case, a removal process of the charge trap layer 155 is necessary, and the manufacturing process of the semiconductor memory device is complicated, and the film quality of the material constituting the selection transistor 202 is deteriorated due to the removal of the charge trap layer 155. It becomes a problem to do. In addition, it is conceivable that the first electrode layer 152 is formed of a material layer different from that of the floating gate insulating film 112. However, in this case as well, the manufacturing process of the semiconductor memory device is complicated.

  On the other hand, according to the present embodiment, since these problems can be avoided, it is possible to easily manufacture the select transistor 202 with good characteristics.

  In particular, in this embodiment, the first insulating film 151, the first electrode layer 152, the second insulating film 153, the second electrode layer 154, and the charge trap layer 155 are respectively formed of the gate insulating film 111, the floating gate 112, and the gate-to-gate. Since the insulating film 113, the control gate 114, and the charge trap layer 121 are formed from the same material layer, most of the manufacturing process of the cell transistor 201 and the manufacturing process of the selection transistor 202 are shared. Thereby, in this embodiment, the cell transistor 201 and the selection transistor 202 can be manufactured at a low cost with a relatively small number of manufacturing steps.

  As described above, according to the present embodiment, the floating gate 112 of the cell transistor 201 has a structure in which the charge trap layer 121 is sandwiched between and surrounded by the floating gate 112, and the selection transistor 202 has excellent characteristics and can be easily manufactured. It becomes possible to do.

  In the method of manufacturing the semiconductor memory device of the fifth embodiment (FIGS. 8 and 9), the first insulating film 151, the first electrode layer 152, the second insulating film 153, the second electrode layer 154, and the charge trap layer 155 is formed of a gate insulating material 301, a floating gate material 302 (302 </ b> A to C), an inter-gate insulating material 303, a control gate material 304, and a charge trap material 311. The same applies to the sixth to eighth embodiments. However, in the eighth embodiment, the first electrode layer 152 is formed of the first to fourth floating gate materials 302A to 302D.

  The select transistor 202 can be manufactured by a method similar to the method of manufacturing the cell transistor 201 described in the fifth to eighth embodiments. However, when the selection transistor 202 is manufactured, it is necessary to form the opening H in the inter-gate insulating material 303 between the formation process of the inter-gate insulating material 303 and the formation process of the control gate material 304. The opening H forms the lower layer of the control gate material 304 on the inter-gate insulating material 303, forms the opening H penetrating the inter-gate insulating material 303 and the lower layer, and the lower portion where the opening is formed. The upper layer of the control gate material 304 may be formed on the layer.

  As described above, in the present embodiment, the first electrode layer 152 of the selection transistor 202 is formed of the charge trap layer 155 in the same manner as the floating gate 112 of the cell transistor 201 sandwiches and surrounds the charge trap layer 121. Surrounds the top and bottom. As a result, many of the manufacturing steps of the cell transistor 201 and the selection transistor 202 can be made common. Therefore, according to the present embodiment, it is possible to improve the characteristics of the selection transistor 202 and facilitate manufacture while adopting a structure in which the floating gate 112 of the cell transistor 201 surrounds the charge trap layer 121 and surrounds the periphery. It becomes possible.

  Note that the structure in which the first electrode layer 152 of the selection transistor 202 surrounds the charge trap layer 155 with the upper and lower sides surrounding the periphery does not adopt the structure in which the floating gate 112 of the cell transistor 201 surrounds the charge trap layer 121 with the upper and lower sides surrounded. It can also be adopted.

  The first electrode layer 152 may cover the upper and lower surfaces of the charge trap layer 155 and a set of side surfaces perpendicular to the X direction, like the floating gate 112 of the fourth embodiment.

  The first electrode layer 152 may cover the upper and lower surfaces of the charge trap layer 155 and two sets of side surfaces facing each other, like the floating gate 112 of the third embodiment.

  Further, the second insulating film 153 and the second electrode layer 154 may be dropped between the select transistors 202, similarly to the inter-gate insulating film 113 and the control gate 114 of the second embodiment.

(10th Embodiment)
FIG. 19 is a side sectional view showing the configuration of the semiconductor memory device according to the tenth embodiment.

  In the ninth embodiment, as shown in FIG. 18A, the opening H is formed so as to penetrate the second insulating film 153, and the bottom thereof is formed by the upper layer portion of the first electrode layer 152.

  On the other hand, in the tenth embodiment, as shown in FIG. 19A, the opening H is formed so as to penetrate the upper layer portion of the second insulating film 153 and the first electrode layer 152, and the bottom thereof is charged. A side wall portion of the trap layer 155 and the first electrode layer 152 is formed. Accordingly, in FIG. 19B, the first electrode layer 152 surrounds and surrounds the charge trap 155, whereas in FIG. 19C, the first electrode layer 152 is the lower surface of the charge trap layer 155. And covers only the sides.

  The tenth embodiment has an advantage that the opening H can be formed using the charge trap layer 155 as an etching stopper.

  In the tenth embodiment, as in the ninth embodiment, the first electrode layer 152 of the selection transistor 202 surrounds the charge trap layer 155 with the upper and lower sides therebetween. As a result, many of the manufacturing steps of the cell transistor 201 and the selection transistor 202 can be made common. Therefore, according to the tenth embodiment, the characteristics of the selection transistor 202 are improved and the manufacturing is facilitated while adopting a structure in which the floating gate 112 of the cell transistor 201 surrounds the charge trap layer 121 and surrounds the periphery. Is possible.

  In the tenth embodiment, when the opening H is formed, the charge trap layer 155 can be used as an etching stopper.

(Eleventh embodiment)
FIG. 20 is a side sectional view showing the configuration of the semiconductor memory device according to the eleventh embodiment.

  In the eleventh embodiment, as shown in FIG. 20A, the opening H is formed so as to penetrate the second insulating film 153, the upper layer portion of the first electrode layer 152, and the charge trap layer 155, and the bottom portion thereof. Is formed in the lower layer portion of the first electrode layer 152. Therefore, in FIG. 20B, the first electrode layer 152 surrounds and surrounds the charge trap 155, whereas in FIG. 20C, the lower layer portion and the second electrode of the first electrode layer 152 are surrounded. Layer 154 is in direct contact.

  As in the tenth embodiment, the eleventh embodiment has an advantage that the opening H can be formed using the charge trap layer 155 as an etching stopper. In the eleventh embodiment, after the opening H is formed using the charge trap layer 155 as an etching stopper, the charge trap layer 155 at the bottom of the opening H is removed, and a lower layer portion of the first electrode layer 152 is formed inside the opening H. To expose.

  In the eleventh embodiment, as in the ninth and tenth embodiments, the first electrode layer 152 of the selection transistor 202 surrounds the charge trap layer 155 with the upper and lower sides therebetween. As a result, many of the manufacturing steps of the cell transistor 201 and the selection transistor 202 can be made common. Therefore, according to the eleventh embodiment, the floating gate 112 of the cell transistor 201 has a structure in which the charge trap layer 121 is sandwiched between and surrounded, and the selection transistor 202 has excellent characteristics and is easily manufactured. Is possible.

  In the eleventh embodiment, as in the tenth embodiment, the charge trap layer 155 can be used as an etching stopper when the opening H is formed.

(Twelfth embodiment)
FIG. 21 is a side sectional view showing the configuration of the semiconductor memory device according to the twelfth embodiment.

  In the twelfth embodiment, as shown in FIG. 21A, the opening H is formed so as to penetrate the upper insulating layer of the second insulating film 153 and the first electrode layer 152. In the twelfth embodiment, as shown in FIG. 21A, the charge trap layer 155 is completely removed. Therefore, in FIG. 21B, the first electrode layer 152 surrounds the upper and lower sides of the second electrode layer 155, and in FIG. 21C, the lower layer portion of the first electrode layer 152 and the second electrode layer 154 is in direct contact.

  As in the tenth and eleventh embodiments, the twelfth embodiment has an advantage that the opening H can be formed using the charge trap layer 155 as an etching stopper. In the twelfth embodiment, after the opening H is formed using the charge trap layer 155 as an etching stopper, the charge trap layer 155 is completely removed using the opening H, and the first electrode layer 152 is formed inside the opening H. Expose the lower layer of.

  In the twelfth embodiment, unlike the ninth to eleventh embodiments, the charge trap layer 155 of the selection transistor 202 is completely removed. However, in the twelfth embodiment, due to the presence of the charge trap layer 155 until the opening H is formed, the thickness of the first electrode layer 152 of the selection transistor 202 is the same as in the ninth to eleventh embodiments. Is equal to the thickness of the floating gate 112 of the cell transistor 201.

  Thus, in the twelfth embodiment, by manufacturing the selection transistor 202 using the charge trap layer 155, it is possible to share many of the manufacturing process of the cell transistor 201 and the manufacturing process of the selection transistor 202. Become. Therefore, according to the twelfth embodiment, the characteristics of the selection transistor 202 are improved and the manufacturing is facilitated while adopting a structure in which the floating gate 112 of the cell transistor 201 surrounds the charge trap layer 121 and surrounds the periphery. Is possible.

  In the twelfth embodiment, as in the tenth and eleventh embodiments, the charge trap layer 155 can be used as an etching stopper when the opening H is formed.

(13th Embodiment)
FIG. 22 is a side sectional view showing the configuration of the semiconductor memory device according to the thirteenth embodiment.

  FIG. 22A shows the structure of the cell transistor 201 and the selection transistor 202 as in FIG. FIGS. 22B and 22C show configurations of the LV (low voltage drive) transistor 203 and the HV (high voltage drive) transistor 204, which are peripheral transistors, respectively.

As shown in FIG. 22B, the LV transistor 203 includes a gate insulating film 161 and a gate electrode 162 that are sequentially formed over the substrate 101. The gate insulating film 161 of the LV transistor 203 includes a first insulating film 171 formed on the substrate 101, and the gate electrode 162 is a first electrode layer 172 formed in order on the first insulating film 171. , A second insulating film 173, and a second electrode layer 174. The first electrode layer 172 and the second electrode layer 174 are electrically connected to each other through the opening H ₁ provided in the second insulating film 173 (FIG. 22B).

  Further, as shown in FIG. 22B, the LV transistor 203 further includes a charge trap layer 175 formed so as to be surrounded by the first electrode layer 172 and surrounded by the first electrode layer 172 and having a function of trapping charges. Yes.

  As in the case of the select transistor 202, the charge trap layer 175 has a rod shape extending in a predetermined direction parallel to the surface of the substrate 101, and the first electrode layer 172 surrounds the charge trap layer 175. Thus, it has a cylindrical shape extending in the predetermined direction. As a result, the first electrode layer 172 covers the upper and lower surfaces of the charge trap layer 175 and a set of side surfaces facing each other.

Further, as shown in FIG. 22C, the HV transistor 204 includes a gate insulating film 181 and a gate electrode 182 that are sequentially formed over the substrate 101. The gate insulating film 181 of the HV transistor 204 includes a first insulating film 191 formed on the substrate 101, and the gate electrode 182 is a first electrode layer 192 formed in order on the first insulating film 191. , A second insulating film 193, and a second electrode layer 194. In addition, the first electrode layer 192 and the second electrode layer 194 are electrically connected to each other through an opening H ₂ provided in the second insulating film 193 (FIG. 22C).

  Further, as shown in FIG. 22C, the HV transistor 204 further includes a charge trap layer 195 formed so as to be surrounded by the first electrode layer 192 and surrounded by the first electrode layer 192 and having a function of trapping charges. Yes.

  As in the case of the selection transistor 202 and the LV transistor 203, the charge trap layer 195 has a rod-like shape extending in a predetermined direction parallel to the surface of the substrate 101, and the first electrode layer 192 includes the charge trap layer 195. It has the cylindrical shape extended in the said predetermined direction so that the circumference | surroundings may be surrounded. As a result, the first electrode layer 192 covers the upper and lower surfaces of the charge trap layer 195 and a set of side surfaces facing each other.

  As described above, in this embodiment, the first electrode layer 172 of the LV transistor 203 surrounds and surrounds the charge trap layer 175, and the first electrode layer 192 of the HV transistor 204 is above and below the charge trap layer 195. Surrounds the surrounding area. This is because the LV transistor 203 and the HV transistor 204 are formed of the same material layer as that of the cell transistor 201, like the selection transistor 202. Therefore, according to the present embodiment, the floating gate 112 of the cell transistor 201 has a structure in which the charge trap layer 121 is sandwiched between and surrounded, and the characteristics of the LV transistor 203 and the HV transistor 204 are improved and manufacturing is easy. It becomes possible to.

  Note that the gate insulating film 181 of the HV transistor 204 generally needs to be thicker than the gate insulating film 111 of the cell transistor 201. Therefore, in this embodiment, the gate insulating film 181 of the HV transistor 204 is separately formed from the gate insulating film 111 of the cell transistor 201, and the effective film thickness is made thicker than that of the gate insulating film 111 of the cell transistor 201 ( FIG. 22 (C)).

  The gate insulating film 181 of the HV transistor 204 can be manufactured as follows.

  First, before forming the insulating material layer for the gate insulating film 111 of the cell transistor 201, the insulating material layer for the gate insulating film 181 of the HV transistor 204 is formed. Next, the insulating material layer for the HV transistor 204 is removed from a region other than the region where the HV transistor 204 is to be formed. Next, an insulating material layer for the gate insulating film 111 of the cell transistor 201 is formed, and the insulating material layer is removed from regions other than the regions where the cell transistor 201, the selection transistor 202, the LV transistor 203, and the HV transistor 204 are to be formed. As a result, gate insulating films 111, 141, 146, and 181 of these transistors are formed, and the thickness of the gate insulating film 181 is larger than the thickness of the other gate insulating films 111, 141, and 161.

  In this embodiment, in addition to the gate insulating film 181 of the HV transistor 204, the gate insulating film 161 of the LV transistor 203 may be thicker than the gate insulating film 111 of the cell transistor 201. However, in this case, the gate insulating film 181 of the HV transistor 204 needs to be thicker than the gate insulating film 161 of the LV transistor 203.

  The layers of the LV and HV transistors 203 and 204 other than the gate insulating films 161 and 181 can be manufactured by the same method as that of the selection transistor 202. For example, in the method of manufacturing the semiconductor memory device of the fifth embodiment (FIGS. 8 and 9), the first electrode layers 172 and 192, the second insulating films 173 and 193, the second electrode layers 174 and 194, and the charge trap layer 175 and 195 are each formed of a gate insulating material 301, a floating gate material 302 (302 </ b> A to C), an inter-gate insulating material 303, a control gate material 304, and a charge trap material 311. The same applies to the sixth to eighth embodiments. However, in the eighth embodiment, the first electrode layers 172 and 192 are formed of the first to fourth floating gate materials 302A to 302D.

Further, the LV and HV transistors 203 and 204 can be manufactured by a method similar to the manufacturing method of the cell transistor 201 described in the fifth to eighth embodiments. However, when the LV and HV transistors 203 and 204 are manufactured, the openings H ₁ and H ₂ are formed in the inter-gate insulating material 303 between the forming process of the inter-gate insulating material 303 and the forming process of the control gate material 304. Need to form. The openings H ₁ and H ₂ form a lower layer of the control gate material 304 on the inter-gate insulating material 303, and form openings H ₁ and H ₂ penetrating the inter-gate insulating material 303 and the lower layer, You may form by forming the upper layer of the control gate material 304 on the said lower layer in which the opening part was formed.

  As described above, in this embodiment, the first electrode layer 172 of the LV transistor 203 surrounds and surrounds the charge trap layer 175, and the first electrode layer 192 of the HV transistor 204 is above and below the charge trap layer 195. Surrounds the surrounding area. Therefore, according to the present embodiment, the characteristics of the LV transistor 203 and the HV transistor 204 are improved and the manufacturing is facilitated while adopting a structure in which the floating gate 112 of the cell transistor 201 surrounds the charge trap layer 121. Is possible.

  The structure in which the first electrode layer 172 of the LV transistor 203 surrounds the upper and lower sides of the charge trap layer 175 and the structure of the first electrode layer 192 of the HV transistor 204 sandwiches the upper and lower sides of the charge trap layer 195 and surrounds the periphery. The present invention can also be adopted when the floating gate 112 of the cell transistor 201 does not employ a structure that surrounds the charge trap layer 121 and surrounds it.

  The first electrode layer 172 may cover the upper and lower surfaces of the charge trap layer 175 and two sets of side surfaces facing each other. Similarly, the first electrode layer 192 may cover the upper and lower surfaces of the charge trap layer 195 and two sets of side surfaces facing each other.

The shapes of the openings H ₁ and H ₂ may be the same as the shapes of the openings H in the tenth to twelfth embodiments. That is, when forming the openings H ₁ and H ₂ , the charge trap layers 175 and 195 may be used as etching stoppers. Further, the charge trap layers 175 and 195 may be partially or completely removed using the openings H ₁ and H ₂ .

  In particular, since the peripheral transistors (203, 204) generally have a longer gate length than the selection transistor 202, it may be difficult to completely remove the charge trap layers 175, 195. In that case, the charge trap layers 175 and 195 may partially remain.

  As mentioned above, although the example of the specific aspect of this invention was demonstrated by 1st-13th embodiment, this invention is not limited to these embodiment.

DESCRIPTION OF SYMBOLS 101 Substrate 111 Gate insulating film 112 Floating gate 113 Intergate insulating film 114 Control gate 121 Charge trap layer 131 Diffusion layer 132 Interlayer insulating film 133 Element isolation insulating films 141, 161, 181 Gate insulating films 142, 162, 182 Gate electrodes 151, 171, 191 First insulating film 152, 172, 192 First electrode layer 153, 173, 193 Second insulating film 154, 174, 194 Second electrode layer 155, 175, 195 Charge trap layer 201 Cell transistor 202 Select transistor 203 LV Transistor 204 HV transistor 301 Gate insulating material 302 Floating gate material 302A First floating gate material 302B Second floating gate material 303C Third floating gate material 304D Fourth floating gate material 303 Intergate insulating material 30 The control gate material 311 charge trapping material 321 mask layer 322 masking layer 331 side wall film

Claims (5)

A substrate,
A memory cell transistor formed in order on the substrate, including a gate insulating film functioning as an FN (Fowler-Nordheim) tunnel film, a floating gate, an inter-gate insulating film functioning as a charge blocking film, and a control gate With
The memory cell transistor further includes a charge trap layer formed to be sandwiched between the floating gate and having a function of trapping charges,
The semiconductor memory device, wherein the floating gate covers an upper surface and a lower surface of the charge trap layer and a set of side surfaces facing each other. Furthermore,
A bit line extending in a first direction parallel to the surface of the substrate and electrically connected to the memory cell transistor;
A word line extending in a second direction parallel to the surface of the substrate and electrically connected to the memory cell transistor;
2. The semiconductor memory device according to claim 1, wherein a pair of side surfaces facing each other covered by the floating gate of the charge trapping layer are oriented in an extending direction of the word line.   3. The semiconductor memory device according to claim 1, wherein the floating gate covers an upper surface and a lower surface of the charge trap layer and two sets of side surfaces facing each other. A substrate,
A selection or peripheral transistor including a gate insulating film sequentially formed on the substrate, and a gate electrode;
The gate insulating film includes a first insulating film formed on the substrate,
The gate electrode includes a first electrode layer, a second insulating film, and a second electrode layer sequentially formed on the first insulating film, and the first electrode layer and the second electrode layer are Electrically connected through an opening provided in the second insulating film;
The selection or peripheral transistor further includes a charge trap layer formed to be sandwiched between the first electrode layer and having a function of trapping charges,
The semiconductor memory device, wherein the first electrode layer covers an upper surface and a lower surface of the charge trap layer and a set of side surfaces facing each other. Furthermore,
A selection or peripheral transistor including a gate insulating film formed in order on the substrate and a gate electrode;
The gate insulating film includes a first insulating film formed on the substrate,
The gate electrode includes a first electrode layer, a second insulating film, and a second electrode layer sequentially formed on the first insulating film, and the first electrode layer and the second electrode layer are Electrically connected through an opening provided in the second insulating film;
4. The semiconductor memory device according to claim 1, wherein a thickness of the first electrode layer of the selection or peripheral transistor is equal to a thickness of the floating gate of the memory cell transistor. 5.

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