JP2011135317A - Integrated circuit apparatus and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit apparatus, along with an electronic device or the like, capable of improving the static electricity protection withstand voltage with maintaining the performance of an oscillation circuit. <P>SOLUTION: The integrated circuit apparatus includes a first pad P1 connected to one end of a vibrator XTAL; a second pad P2 connected to the other end of the vibrator XTAL, a buffer circuit BF for oscillation of the vibrator XTAL, a first protection resistance element R1 provided between a first connection node NC1 on the first pad P1 side and an input node NI of the buffer circuit BF, a second protection resistance element R2 provided between the second connection node NC2 on the second pad P2 side and an output node NQ of the buffer circuit BF, and a capacitor circuit CX1(CX2) connected to one of the first and second connection nodes NC1 and NC2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an integrated circuit device, an electronic device, and the like.

  Conventionally, an oscillation circuit using a vibrator such as a crystal vibrator is known. According to the oscillation circuit using such a vibrator, a highly accurate clock signal can be obtained as compared with a CR oscillation circuit using a capacitor and a resistor. As a conventional technique of such an oscillation circuit, for example, a technique disclosed in Patent Document 1 is known.

  In this prior art, the temperature is measured by a temperature sensor, and the load capacitance of the crystal oscillation circuit is changed according to the measured temperature. In this way, even when there is a temperature variation, the clock accuracy can be maintained, and highly accurate temperature compensation can be realized.

  However, in this prior art, no mention is made of countermeasures for protection against static electricity when static electricity is applied. It has been found that when a circuit element for electrostatic protection is provided, there is a problem that the performance of the oscillation circuit deteriorates due to the presence of the circuit element.

  Further, when this conventional technique is applied to, for example, a wireless communication device, the following problem occurs. In other words, not only when a high-accuracy oscillation frequency is required for wireless transmission operation and reception operation, but also when a highly accurate oscillation frequency is not necessary in the standby state of the wireless communication device, the oscillation circuit has the same load. It will oscillate with the capacity. Therefore, it has been found that there is a problem that wasteful power is consumed in the oscillation circuit during standby.

JP 2002-171132 A

  According to some aspects of the present invention, it is possible to provide an integrated circuit device, an electronic device, and the like that can improve the electrostatic protection withstand voltage while maintaining the performance of the oscillation circuit.

  One embodiment of the present invention includes a first pad connected to one end of a vibrator, a second pad connected to the other end of the vibrator, a buffer circuit for oscillation of the vibrator, the first pad A first protection resistance element provided between a first connection node on one pad side and an input node of the buffer circuit; a second connection node on the second pad side; and The present invention relates to an integrated circuit device including a second protective resistance element provided between the output node and a capacitor circuit connected to one of the first connection node or the second connection node.

  According to one embodiment of the present invention, the first protection resistance element is provided between the first connection node on the first pad side and the input node of the buffer circuit, and the second protection side is provided on the second pad side. A second protective resistance element is provided between the connection node and the output node of the buffer circuit. Accordingly, when static electricity is applied through the first and second pads, the situation in which the circuit elements of the buffer circuit are electrostatically destroyed can be suppressed using the first and second protective resistance elements. become. Further, it is possible to prevent the performance of the oscillation circuit from deteriorating due to the presence of the first and second protective resistance elements. Accordingly, the electrostatic protection breakdown voltage can be improved while maintaining the performance of the oscillation circuit.

  In one embodiment of the present invention, when the direction opposite to the first direction is the second direction, the first protective resistance element is disposed in a region on the first direction side of the buffer circuit, The second protective resistance element may be arranged in a region on the second direction side of the buffer circuit.

  In this way, the buffer circuit and the first and second protective resistance elements can be arranged in an efficient layout, and a compact layout arrangement can be realized.

  In one embodiment of the present invention, the capacitor circuit is disposed in a region on the first direction side of the first protective resistance element or a region on the second direction side of the second protective resistance element. Also good.

  In this way, the buffer circuit, the first and second protection resistance elements, and the capacitor circuit can be arranged in an efficient layout, and a compact layout arrangement can be realized.

  In one embodiment of the present invention, it includes a waveform shaping circuit that performs waveform shaping of an oscillation signal generated by the vibrator and the buffer circuit and outputs a clock signal, and the waveform shaping circuit includes the waveform circuit. It may be arranged in a region on the first direction side or a region on the second direction side of the capacitor circuit.

  In this way, the signal line from the first pad or the second pad can be connected to the waveform shaping circuit by a short path, and efficient layout wiring can be realized.

  In one embodiment of the present invention, the current control for detecting the amplitude of the oscillation signal generated by the vibrator and the buffer circuit and controlling the current flowing in the buffer circuit so that the amplitude of the oscillation signal is constant. The current control circuit may be arranged in a region on the third direction side of the buffer circuit when a circuit is included and a direction orthogonal to the first direction is a third direction.

  In this way, the current control circuit and the buffer circuit can be connected by a short path, an efficient layout arrangement can be realized, and malfunctions can be prevented.

  In one embodiment of the present invention, when a direction opposite to the third direction is a fourth direction, the first protection resistor element includes a first protection diode in a region on the fourth direction side. I / O cells may be arranged, and a second I / O cell having a protection diode may be arranged in a region on the fourth direction side of the second protection resistance element.

  In this way, the protective diode can be laid out near the first and second pads, and the electrostatic protection breakdown voltage can be improved.

  In one embodiment of the present invention, at least one of the first I / O cell and the second I / O cell may be disposed between the first pad and the second pad. .

  In this way, an efficient layout arrangement of the first and second pads and the I / O cell can be realized.

  In one embodiment of the present invention, a second capacitor circuit connected to the other of the first connection node or the second connection node may be included.

  As described above, if the capacitance circuits are provided on both the input side and the output side of the buffer circuit, a balanced oscillation operation can be realized.

  In one embodiment of the present invention, the input signal line of the buffer circuit and the output signal line of the buffer circuit may be wired so as to be non-overlapping in plan view.

  In this way, it is possible to suppress a situation where the input signal line and the output signal line cross to deteriorate the oscillation performance.

  In the aspect of the invention, the buffer circuit, the first protection resistance element, and the second protection resistance element may be arranged adjacent to each other in plan view.

  In this way, the buffer circuit and the first and second protective resistance elements can be laid out in a compact layout.

  In one embodiment of the present invention, the distance in plan view between the first pad and the second pad is LA, and the distance in plan view between the first protection resistance element and the second protection resistance element is LA. May be LA> LB, where LB is LB.

  In this way, it is possible to realize a layout arrangement in which the first and second protection resistance elements are arranged closer to the buffer circuit.

  In one aspect of the present invention, the capacitance circuit is a variable capacitance circuit in which a capacitance value is variably set. During normal operation, the capacitance value of the variable capacitance circuit is set to CN, and during standby, the variable capacitance circuit The capacitance value of the circuit is set to CS, and CN> CS may be satisfied.

  According to one aspect of the present invention, the capacitance value of the variable capacitance circuit is set to CN larger than CS during normal operation, and is set to CS smaller than CN during standby. Therefore, the oscillation frequency can be made more accurate during normal operation than during standby. On the other hand, at the time of standby, the capacitance value of the variable capacitance circuit, which is a load capacitance, decreases, so that power saving can be achieved. Accordingly, it is possible to obtain a highly accurate oscillation frequency during normal operation while suppressing wasteful power consumption during standby.

  In one embodiment of the present invention, the standby circuit includes a standby circuit that operates based on a standby clock signal from the oscillation circuit during the standby, and the standby circuit has a capacitance value of the variable capacitance circuit of CS. The operation may be performed based on the standby clock signal generated by the setting.

  In this way, even when the integrated circuit device is in a standby state, the standby circuit is operated based on the standby clock signal from the oscillation circuit, so that a necessary operation in the standby state can be executed.

  According to another aspect of the present invention, the wireless circuit includes a wireless circuit that performs wireless communication during the normal operation, and the wireless circuit generates a clock signal for normal operation generated by setting a capacitance value of the variable capacitance circuit to CN. May operate on the basis of

  In this way, wireless communication of the wireless circuit can be realized by using the highly accurate clock signal for normal operation obtained by setting the capacitance value of the variable capacitance circuit to CN.

  Another aspect of the invention relates to an electronic device including any one of the integrated circuit devices described above.

The structural example of this embodiment. The structural example of a comparative example. 3A and 3B are diagrams showing the relationship between the resistance value and the operating current. An example of the layout arrangement of an integrated circuit device. Another example of layout arrangement of an integrated circuit device. The detailed structural example of this embodiment. 2 is a configuration example of a variable capacitance circuit. Explanatory drawing of the capacitor of a MIM structure. The structural example of a waveform shaping circuit. 2 is a configuration example of a current control circuit. The signal waveform example explaining amplitude and voltage conversion. 4 is a detailed example of a layout arrangement of an integrated circuit device. Explanatory drawing of the capacitance value setting method of this embodiment. 14A and 14B are also explanatory diagrams of the capacitance value setting method of the present embodiment. 2 shows a configuration example of an integrated circuit device. FIG. 9 is an operation explanatory diagram of the integrated circuit device. 2 shows a detailed configuration example of an integrated circuit device. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration of Integrated Circuit Device and Oscillator Circuit FIG. 1 shows a configuration example of an integrated circuit device and an oscillator circuit of this embodiment. Note that the configuration of the integrated circuit device and the oscillation circuit of the present embodiment is not limited to the configuration of FIG. 1, and various modifications such as omitting some of the components or adding other components are possible. is there.

  As shown in FIG. 1, the integrated circuit device (oscillation circuit) of this embodiment includes an oscillation buffer circuit BF of a vibrator XTAL such as a crystal vibrator, first and second protective resistance elements R1 and R2, and , First and second capacitance circuits CX1, CX2 (first and second capacitors). The first and second pads P1 and P2 and the first and second I / O cells IO1 and IO2 may be included.

  The oscillation buffer circuit BF is a buffer circuit (amplifier circuit) for oscillating the vibrator XTAL, and is realized by an inverter circuit (an inverting circuit) in FIG. This buffer circuit BF is provided between one end and the other end of the vibrator XTAL. In FIG. 1, the input node of the buffer circuit BF is connected to one end of the transducer XTAL via the pad P1, and the output node of the buffer circuit BF is connected to the other end of the transducer XTAL via the pad P2.

  The buffer circuit BF may be a circuit other than the inverter circuit as long as the oscillation condition that the phase difference between the signal at one end of the vibrator XTAL and the signal at the other end is 180 degrees is satisfied. The vibrator XTAL is not limited to a crystal vibrator, and various vibrators such as a SAW (surface acoustic wave) device can be used. Further, as an external component, a feedback resistance element of the vibrator XTAL (for example, a resistance of about 1 M ohm) may be provided.

  The first protective resistance element R1 is provided between the first connection node NC1 on the first pad P1 side and the input node NI of the buffer circuit BF. The second protection resistance element R2 is provided between the second connection node NC2 on the second pad P2 side and the output node NQ of the buffer circuit BF. These protection resistance elements R1 and R2 function as an ESD protection resistance for protecting the gate and drain of the transistor of the buffer circuit BF from static electricity applied via the pads P1 and P2. The protective resistance elements R1 and R2 have a resistance value of, for example, several hundred ohms, and can be realized by, for example, a polysilicon resistance or a diffusion resistance.

  The I / O cell IO1 includes a protection diode DI1A provided between the connection node NC1 and the VSS node (first power supply node in a broad sense), a connection node NC1 and a VDD node (second power supply node in a broad sense). Including a protective diode DI1B. I / O cell IO2 includes a protection diode DI2A provided between connection node NC2 and the VSS node, and a protection diode DI2B provided between connection node NC2 and the VDD node. These protection diodes DI1A, DI1B, DI2A, and DI2B function as ESD protection elements for releasing static electricity from the pads P1 and P2 to the VDD side and the VSS side, and are realized by, for example, a semiconductor PN junction. The I / O cells IO1 and IO2 generally include a signal input / output buffer, but in FIG. 1, this input / output buffer is not used but only a protective diode is used.

  The pads P1 and P2 are external connection terminals for connecting the integrated circuit device (IC) of the present embodiment and an external device. In FIG. 1, the input side of the buffer circuit BF is connected to one end of a resonator XTAL such as a crystal resonator which is an external component (external device) via a pad P1, and the output side of the buffer circuit BF is connected to a pad P2. To the other end of the vibrator XTAL.

  The first capacitor circuit CX1 is connected to the first connection node NC1 on the input side of the buffer circuit BF. That is, the capacitor of the capacitance circuit CX1 is provided between the connection node NC1 and the VSS node (first power supply node). The second capacitor circuit CX2 is connected to the second connection node NC2 on the output side of the buffer circuit BF. That is, the capacitor of the capacitance circuit CX2 is provided between the connection node NC2 and the VSS node (first power supply node).

  The capacitance circuits CX1 and CX2 are preferably variable capacitance circuits whose capacitance values are variably set. Therefore, hereinafter, CX1 and CX2 are referred to as variable capacitance circuits.

The capacitance values of these variable capacitance circuits CX1 and CX2 can be arbitrarily changed within a given range by, for example, an external capacitance value control signal. For example, the capacitance value can be set in ²ⁿ steps by digital data with n bits by the capacitance value control signal. Alternatively, the capacitance value may be variably set by controlling a capacitive element such as a varactor with an analog control voltage.

  CX1 and CX2 may be first and second capacitors whose capacitance values are not variably set. In FIG. 1, the variable capacitance circuits CX1 and CX2 are provided in both the connection nodes NC1 and NC1, but the variable capacitance circuit may be provided in only one of the connection nodes NC1 and NC1. That is, the variable capacitance circuit (capacitance circuit in a broad sense) may be provided at a connection node on at least one side of the input side or the output side of the buffer circuit BF. For example, a variable capacitance circuit may be connected to only one of the connection nodes NC1 and NC2, and a capacitance circuit (capacitor) whose capacitance value is not set to be variable may be connected to the other node. Alternatively, a capacitor, which is an external component, may be used without providing a built-in capacitance circuit at the other node.

  According to the embodiment of FIG. 1 described above, the protective resistance element R1 is provided between the input node NI of the buffer circuit BF and the connection node NC1, and the protective resistance is provided between the output node NQ of the buffer circuit BF and the connection node NC2. Element R2 is provided. Therefore, when the static electricity is applied through the pad P1, the protective resistance element R1 can prevent the gate of the transistor of the buffer circuit BF from being electrostatically destroyed. Even when static electricity is applied through the pad P2, the protective resistance element R2 can prevent the drain of the transistor of the buffer circuit BF from being electrostatically destroyed. Therefore, the electrostatic protection breakdown voltage of the integrated circuit device can be increased, and the reliability can be improved.

  In FIG. 1, a protective resistance element is provided on the first path between one end of the transducer XTAL and the variable capacitance circuit CX1 and on the second path between the other end of the transducer XTAL and the variable capacitance circuit CX2. Not provided. Therefore, it is possible to prevent the operating current of the oscillation circuit (buffer circuit) from increasing due to the presence of the protective resistance element. In addition, oscillation frequency fluctuation when power supply voltage fluctuation occurs can be reduced.

  FIG. 2 shows a configuration of a comparative example of this embodiment. In the comparative example of FIG. 2, a protective resistance element R1 is provided between one end of the vibrator XTAL and the variable capacitance circuit CX1, and a protective resistance element R2 is provided between the other end of the vibrator XTAL and the variable capacitance circuit CX2. It has been. That is, in the comparative example of FIG. 2, the protective resistance elements R1 and R2 are arranged as close as possible to the pads P1 and P2 to which static electricity is applied, thereby improving the electrostatic protection breakdown voltage. Specifically, for example, protective resistance elements included in the I / O cells IO1 and IO2 are used as R1 and R2.

  However, in the comparative example of FIG. 2, when viewed from the vibrator XTAL, the protective resistance element R1 exists between the pad P1 and the variable capacitance circuit CX1, and the protective resistance between the pad P2 and the variable capacitance circuit CX2 exists. Element R2 will be present. In addition, most of the high frequency components of the drive signal of the buffer circuit BF escape to the capacitive circuit CX2 side, not to the transducer XTAL side. Therefore, in order to maintain oscillation at a high frequency such as 16 MHz, for example, a high drive capability of the buffer circuit BF is required, and the operating current of the oscillation circuit increases. In other words, in order to keep the amplitude of the oscillation signal above a certain level and continue without stopping the oscillation, it is necessary to increase the operating current flowing through the buffer circuit BF, which hinders the reduction in power consumption. It becomes.

  For example, FIG. 3A is a diagram showing the relationship between the resistance values of the protective resistance elements R1 and R2 and the operating current of the oscillation circuit (such as a short current flowing in the buffer circuit) in the comparative example of FIG. As shown in FIG. 3A, in the comparative example of FIG. 2, when the resistance values of the protective resistance elements R1 and R2 are increased in order to increase the electrostatic protection withstand voltage, the operating current of the oscillation circuit increases accordingly. This hinders low power consumption.

  On the other hand, FIG. 3B is a diagram showing the relationship between the resistance values of the protective resistance elements R1 and R2 and the operating current of the oscillation circuit in this embodiment of FIG. As shown in FIG. 3B, in the present embodiment of FIG. 1, even if the resistance values of the protective resistance elements R1 and R2 are increased in order to increase the electrostatic protection withstand voltage, the operating current of the oscillation circuit hardly increases. Accordingly, it is possible to achieve both improvement of the electrostatic protection withstand voltage and low power consumption. In the configuration of the present embodiment shown in FIG. 1 as well, the protective resistance element R1 is included in the first path between the pad P1 and the variable capacitance circuit CX1 and the second path between the pad P2 and the variable capacitance circuit CX2. Further, a modification in which a resistance element having a resistance value sufficiently lower than R2 is provided is also possible.

2. Layout Arrangement FIG. 4 shows a layout arrangement example of the integrated circuit device of this embodiment. In FIG. 4, the right direction toward the paper surface is the first direction D1, and the opposite direction of the first direction D1 is the second direction D2. Further, the upper direction toward the paper surface is the third direction D3, and the opposite direction of the third direction D3 is the fourth direction D4. However, the upper, lower, left, and right directions are not limited to those in FIG. 4 and may be arbitrary. For example, the first direction D1 may be the left direction, or the third direction D3 may be the lower direction.

  In FIG. 4, the protective resistance element R1 is disposed in the D1 direction area (D1 direction area) of the buffer circuit BF, and the protective resistance element R2 is disposed in the D2 direction area (D2 direction area) of the buffer circuit. Is placed. That is, the buffer circuit BF and the protective resistance elements R1 and R2 are arranged along the first direction. More specifically, the buffer circuit BF and the protective resistance elements R1 and R2 are adjacently disposed in plan view. Here, the term “adjacent arrangement” means, for example, arrangement without any other circuit block or circuit element interposed therebetween.

  According to such a layout arrangement, the buffer circuit BF and the protective resistance elements R1 and R2 can be arranged in an efficient layout, and a compact layout arrangement can be realized. Further, as shown in FIG. 1, a circuit in which a protective resistance element R1 is provided between the input node NI of the buffer circuit BF and the connection node NC1, and a protective resistance element R2 is provided between the output node NQ of the buffer circuit BF and the connection node NC2. The configuration can be realized with an efficient layout arrangement.

  In FIG. 4, the variable capacitance circuit (capacitance circuit in a broad sense) CX1 is arranged in the region on the D1 direction side of the protective resistance element R1. Specifically, the capacitive circuit CX1 and the protective resistance element R1 are adjacently disposed along the direction D1. Further, the variable capacitance circuit (capacitance circuit) CX2 is arranged in a region on the D2 direction side of the protective resistance element R2. Specifically, the capacitive circuit CX2 and the protective resistance element R2 are adjacently disposed along the direction D1.

  According to such a layout arrangement, the buffer circuit BF, the protective resistance elements R1 and R2, and the variable capacitance circuits CX1 and CX2 can be arranged in an efficient layout, and a compact layout arrangement can be realized. In addition, as shown in FIG. 1, the circuit configuration in which the pad P1 and the variable capacitance circuit CX1 are connected without the protection resistance element, and the pad P2 and the variable capacitance circuit CX2 are connected without the protection resistance element is effective. It can be realized by layout arrangement.

  In FIG. 4, an I / O cell IO1 having protective diodes DI1A and DI1B is arranged in a region on the D4 direction side of the protective resistance element R1. Further, an I / O cell IO2 having protective diodes DI2A and DI2B is arranged in a region on the D4 direction side of the protective resistance element R2.

  In this way, after the wiring from the pad P1 passes over the protection diode of the I / O cell IO1, it is connected to the protection resistance element R1 and the variable capacitance circuit CX1. Further, after the wiring from the pad P2 passes over the protective diode of the I / O cell IO2, it is connected to the protective resistance element R2 and the variable capacitance circuit CX2. Therefore, when static electricity is applied to the pads P1 and P2, the static electricity escapes to the VSS side or the VDD side via the protective diodes of the I / O cells IO1 and IO2 at an early stage. Can be improved.

  In FIG. 4, first and second I / O cells IO1 and IO2 are arranged between pads P1 and P2. In this way, an efficient layout arrangement of the pads P1 and P2 and the I / O cells IO1 and IO2 can be realized. Further, static electricity applied to the pads P1 and P2 can be discharged to the VSS side or the VDD side at an early stage via the protective diodes of the I / O cells IO1 and IO2. FIG. 4 shows a case where both of the I / O cells IO1 and IO2 are arranged between the pads P1 and P2, but only one of these I / O cells is connected to the pads P1 and P2. You may arrange | position between. That is, it is sufficient that at least one of the I / O cells IO1 and IO2 is disposed between the pads P1 and P2.

  In FIG. 4, the input side signal line of the buffer circuit BF and the output side signal line of the buffer circuit BF are wired so as to be non-overlapping in plan view. That is, these signal lines are wired so as not to cross. For example, at the time of oscillation, the signal on the input side signal line of the buffer circuit BF (the signal line extending from the pad P1 to the gate of the transistor of the buffer circuit BF) and the output side signal line of the buffer circuit BF (from the pad P2 to the buffer circuit BF) The phase difference from the signal on the signal line leading to the drain of the transistor is, for example, 180 degrees. Therefore, if these input side signal lines and output side signal lines cross, oscillation performance may be degraded.

  In this regard, in FIG. 4, since the input side signal line and the output side signal line are wired so as to be non-overlapping in a plan view, it is possible to prevent the deterioration of the oscillation performance due to crossing of the signal lines.

  In FIG. 4, when the distance between the pad P1 and the pad P2 in plan view is LA and the distance between the protective resistance element R1 and the protective resistance element R2 is LB, LA> LB is satisfied. Yes. That is, the protective resistance elements R1 and R2 are arranged at a pitch narrower than the pitch between the pads P1 and P2. In this way, the layout arrangement is such that the protective resistance elements R1 and R2 are closer to the buffer circuit BF, and a compact layout arrangement can be realized. Here, the distance LA is, for example, the distance between the center position of the pad P1 and the center position of the pad P2. The distance LB is, for example, the distance between the center position of the arrangement region of the protection resistance element R1 and the center position of the arrangement region of the protection resistance element R2.

  The layout arrangement of the integrated circuit device according to the present embodiment is not limited to the arrangement shown in FIG. 4, and various modifications can be made. For example, FIG. 5 shows another layout arrangement example.

  In FIG. 4, the buffer circuit BF and the protective resistance elements R1 and R2 are arranged along the direction D1. On the other hand, in FIG. 5, protection resistance elements R1 and R2 are arranged on the D4 direction side of the buffer circuit BF. The variable capacitance circuit CX1 is disposed in the region on the D1 direction side of the buffer circuit BF and the protection resistance element R1, and the variable capacitance circuit CX2 is disposed in the region on the D2 direction side of the buffer circuit BF and the protection resistance element R2.

  Also by the layout arrangement of FIG. 5, the buffer circuit BF, the protective resistance elements R1 and R2, and the variable capacitance circuits CX1 and CX2 can be arranged in an efficient layout, and a compact layout arrangement can be realized. Further, as shown in FIG. 1, a circuit in which a protective resistance element R1 is provided between the input node NI of the buffer circuit BF and the connection node NC1, and a protective resistance element R2 is provided between the output node NQ of the buffer circuit BF and the connection node NC2. The configuration can be realized with an efficient layout arrangement.

  In FIG. 5, as in FIG. 4, the buffer circuit BF and the protective resistance elements R1 and R2 are adjacently disposed in plan view. Also in FIG. 5, an I / O cell IO1 having a protection diode is arranged in a region on the D4 direction side of the protective resistance element R1, and an I / O cell having a protection diode in a region on the D4 direction side of the protective resistance element R2. Cell IO2 is arranged. Further, the input side signal line and the output side signal line of the buffer circuit BF are wired so as to be non-overlapping in plan view. Further, when the distance in the plan view between the pads P1 and P2 is LA and the distance in the plan view between the protective resistance elements R1 and R2 is LB, the relationship of LA> LB is established.

3. Detailed Configuration Example FIG. 6 shows a detailed configuration example of the present embodiment. The present embodiment is not limited to the configuration shown in FIG. 6, and various modifications may be made such as omitting some of the configuration requirements or adding other configuration requirements.

  In FIG. 6, in addition to the components shown in FIG. 1, the components of the control circuit 20, the selector SEL, the waveform shaping circuit 30, the frequency divider circuit 40, and the current control circuit 50 are further provided.

  The control circuit 20 is a logic circuit that performs various control processes. The control circuit 20 manages whether the current state (mode) is a normal operation state (normal operation mode) or a standby state (standby mode).

  The normal operation setting file (normal operation setting register) describes (stores) capacity value setting data used during normal operation. The standby setting file (standby setting register) describes (stores) capacity value setting data used during standby.

  During normal operation, the selector SEL selects a normal operation setting file in accordance with an instruction signal from the control circuit 20. As a result, the capacitance values of the variable capacitance circuits CX1, CX2 are set to the capacitance value CN for normal operation. On the other hand, at the time of standby, the selector SEL selects the standby setting file by an instruction signal from the control circuit 20. Thereby, the capacitance values of the variable capacitance circuits CX1, CX2 are set to the standby capacitance value CS.

  The waveform shaping circuit 30 shapes the waveform of the oscillation signal SOC. Specifically, the waveform shaping of the oscillation signal SOC generated by the vibrator XTAL and the buffer circuit BF is performed, and the clock signal CLK is output. The frequency divider circuit 40 divides the clock signal CLK. The frequency divider circuit 40 outputs clock signals CKN1 and CKN2 for normal operation and a clock signal CKS for standby.

  For example, when the oscillation frequency of the vibrator XTAL is 16 MHz and the integrated circuit device provided with the oscillation circuit is for wireless communication, the frequency divider circuit 40 uses 16 MHz for baseband processing as the clock signal CKN1 during normal operation. The clock signal is output. The 16 MHz clock signal CKN1 is used to perform baseband processing such as reception data demodulation processing and transmission data modulation processing.

  Further, the frequency dividing circuit 40 outputs, for example, a clock signal of 0.5 MHz or 1 MHz for a PLL (Phase locked Loop) circuit as the clock signal CKN2 during normal operation. For example, a 0.5 MHz clock signal is output as CKN2 at the time of reception, and a local frequency signal is generated by a PLL circuit using CKN2 as a reference clock signal. Then, for example, a down conversion process is performed on a received signal having a carrier frequency of 2.4 GHz. At the time of transmission, a 1 MHz clock signal is output as CKN2, and transmission processing is performed using CKN2.

  Further, the frequency dividing circuit 40 outputs, for example, a 32 kHz clock signal for standby as the clock signal CKS during the standby operation. The standby circuit operates using the clock signal CKS for standby at 32 KHz. In this case, the frequency of the standby clock signal CKS is as low as 32 KHz, so that power consumption can be reduced.

  As will be described in detail later with reference to FIGS. 13 to 14B, during normal operation, the variable capacitance circuits CX1 and CX2 are set to a large capacitance value CN. Therefore, for example, high accuracy such as 16 MHz ± 50 ppm. Can generate a simple oscillation signal. Therefore, proper reception processing and transmission processing can be realized using this highly accurate oscillation signal. On the other hand, during standby, the variable capacitance circuits CX1 and CX2 are set to a capacitance value CS that is smaller than CS, so that a low-accuracy oscillation signal such as 16 MHz ± 500 ppm is generated. However, the 32 kHz clock signal CKS for standby does not need to be so accurate, so no problem occurs.

  For example, as a comparative example of the present embodiment, a method of separately providing a first oscillation circuit using a 16 MHz vibrator and a second oscillation circuit using a 32 KHz vibrator can be considered. In the method of this comparative example, for example, during normal operation, only the first oscillation circuit is operated and the second oscillation circuit is deactivated. The normal operation of the integrated circuit device is realized based on the clock signal from the first oscillation circuit. On the other hand, during standby, only the second oscillation circuit is operated and the first oscillation circuit is deactivated. The standby operation of the integrated circuit device is realized based on the clock signal from the second oscillation circuit.

  However, in the method of this comparative example, two vibrators are required as external parts, resulting in an increase in cost. On the other hand, according to this embodiment, there is an advantage that both the clock signal for normal operation and the clock signal for standby can be generated using only one oscillation circuit.

  The current control circuit 50 controls a current IB (operation current, short-circuit current) flowing through the buffer circuit BF. Specifically, the current control circuit 50 detects the amplitude of the oscillation signal SOC generated by the vibrator XTAL and the buffer circuit BF. Then, the current IB flowing through the buffer circuit BF is controlled so that the amplitude of the oscillation signal SOC becomes constant. By doing so, it becomes possible to maintain a stable oscillation state while minimizing the current consumption of the oscillation circuit.

  In FIG. 6, the waveform shaping circuit 30 performs waveform shaping of the oscillation signal SOC from the node NC1 on the input side of the buffer circuit BF, but waveform shaping of the oscillation signal from the node NC2 on the output side of the buffer circuit BF. May be performed. Similarly, in FIG. 6, the current control circuit 50 detects the amplitude of the oscillation signal SOC from the input-side node NC1, but detects the amplitude of the oscillation signal from the output-side node NC2 to detect the current IB. Control may be performed.

4). Variable Capacitance Circuit FIG. 7 shows a configuration example of the variable capacitance circuits CX1 and CX2. For example, the variable capacitance circuit CX1 includes a plurality of unit capacitors C11, C12, C13, C14 and a plurality of switch elements S11, S12, S13, S14.

  The unit capacitors C11, C12, C13, and C14 are provided between the connection node NC1 and the VSS node (first power supply node). The capacitance values of C11, C12, C13, and C14 are, for example, 1: 2: 4: 8, and are weighted binary.

  The switch elements S11, S12, S13, and S14 are provided between the connection node NC1 and the VSS node (GND). These switch elements S11, S12, S13, and S14 can be realized by, for example, a transfer gate (transistor).

  Each of the switch elements S11, S12, S13, and S14 is provided in series with a corresponding unit capacitor among the plurality of unit capacitors C11, C12, C13, and C14. That is, C11 and S11, C12 and S12, C13 and S13, and C14 and S14 are connected in series.

  A plurality of switch elements S11, S12, S13, and S14 are turned on / off by a capacitance value control signal SCTL from an external control circuit or the like, so that the capacitance value of the variable capacitance circuit CX1 is variably set. For example, in FIG. 7, since the switch elements S11 and S12 are on and S13 and S14 are off, the capacitance value of the variable capacitance circuit CX1 is a parallel capacitance value of C11 and C12.

  Since the configuration of the variable capacitance circuit CX2 is the same as that of the variable capacitance circuit CX1, the description thereof is omitted. 7 shows a case where the switching elements of the variable capacitance circuits CX1 and CX2 are controlled by the same capacitance value control signal SCTL, but different capacitance value control signals may be used for CX1 and CX2.

  For example, when an integrated circuit device including an oscillation circuit is shipped (manufactured) or the like, by setting on / off of a switch element of a variable capacitance circuit, a target as shown in A1 of FIG. The capacitance value CN of the variable capacitance circuit during normal operation is set so that the frequency deviation from the frequency is near zero. Thereby, the clock frequency can be set to the target frequency (for example, 16 MHz). In this state, by setting the capacitance value CS during standby, the oscillation frequency deviates from the target frequency, but power consumption can be reduced.

  As the unit capacitors C11 to C14 and C21 to C24 in FIG. 7, capacitors having an MIM (Metal-Insulator-Metal) structure can be used. Specifically, as shown in FIG. 8, an electrode at one end of the capacitor C (C11 to C14, C21 to C24) is formed of a lower metal layer ALC of the metal layer ALD. The electrode at the other end of the capacitor C is formed of the MIM metal layer ALM formed between the metal layer ALD and the lower metal layer ALC.

  By employing such a capacitor having an MIM structure, the thickness of the insulating film (dielectric material, oxide film) can be reduced, so that a large capacitance value can be obtained with a small layout area. In addition, the MIM structure capacitor has an advantage that the voltage dependency is small. In FIG. 6 and the like, static electricity may be applied to the pads P1 and P2 of the integrated circuit device, which may cause electrostatic breakdown (ESD). If MIM structure capacitors are used as C11 to C14 and C21 to C24, the MIM structure capacitors have a high electrostatic withstand voltage, so that electrostatic breakdown can be suppressed.

  As C11 to C14 and C21 to C24, for example, a capacitor in which electrodes at both ends are formed of polysilicon, or a capacitor in which an electrode at one end is formed of polysilicon and an electrode at the other end is formed of a metal layer is used. Also good.

5. Waveform shaping circuit In this embodiment, the power consumption is reduced by reducing the amplitude of the oscillation signal as much as possible. Specifically, the current control circuit 50 controls the current so that the amplitude of the oscillation signal becomes, for example, several hundred mV (for example, 300 mV), thereby reducing the power consumption. Therefore, it is necessary to shape the waveform of such an oscillation signal having a small amplitude of several hundred mV into a clock signal CLK having a CMOS voltage level (for example, 1.8 V). For this purpose, a waveform shaping circuit 30 is provided.

  FIG. 9 shows a configuration example of the waveform shaping circuit 30. The waveform shaping circuit 30 of the present embodiment is not limited to the configuration shown in FIG. 9, and various modifications such as omitting some of the configuration requirements and adding other configuration requirements are possible.

  The waveform shaping circuit 30 includes first and second waveform coupling AC coupling capacitors CA1 and CA2, first and second self-bias voltage setting circuits BSC1 and BSC2, and a waveform shaping buffer circuit 32. .

  One end of each of the AC coupling capacitors CA1 and CA2 is connected to the waveform shaping node on the input side or output side of the oscillation buffer circuit BF. In FIG. 9, this waveform shaping node is a connection node NC1 on the input side of the oscillation buffer circuit BF. However, the waveform shaping node may be the connection node NC2 on the output side of the buffer circuit BF.

  The DC components of the oscillation signal SOC are cut by the AC coupling capacitors CA1 and CA2, and the AC component is extracted. The AC coupling capacitors CA1 and CA2 are preferably MIM structure capacitors. By doing so, it is possible to protect the internal circuit from static electricity applied via the pads P1 and P2, and to prevent electrostatic breakdown of the internal circuit.

  The self-bias voltage setting circuit BSC1 sets the first bias node NBS1 on the other end side of the AC coupling capacitor CA1 to the first bias voltage VBS1. For example, when VDD = 1.8V, the DC voltage level of the bias node NBS1 is set to, for example, about VBS1 = 0.6V to 0.8V. As a result, a signal in which the AC component of the oscillation signal SOC is superimposed with the bias voltage VBS1 as the center of amplitude is generated. The self-bias voltage setting circuit BSC1 includes a DC voltage source DC1 and a bias voltage setting resistor RB1.

  The self-bias voltage setting circuit BSC2 sets the second bias node NBS2 on the other end side of the AC coupling capacitor CA2 to the second bias voltage VBS2. For example, when VDD = 1.8V, the DC voltage level of the bias node NBS2 is set to, for example, about VBS2 = 1.0 to 1.2V. As a result, a signal in which the AC component of the oscillation signal SOC is superimposed with the bias voltage VBS2 as the center of amplitude is generated. The self-bias voltage setting circuit BSC2 includes a DC voltage source DC2 and a bias voltage setting resistor RB2.

  The buffer circuit 32 includes an N-type transistor TA1 and a P-type transistor TA2. The gate of the N-type transistor TA1 is controlled by the bias node NBS1. The gate of the P-type transistor TA2 is controlled by the bias node NBS2. These N-type transistor TA1 and P-type transistor TA2 constitute an inverter IV0. Then, the waveform-shaped and buffered signal by the inverter IV0 is further buffered by the inverters IV1, IV2, and IV3, and the rectangular clock signal CLK at the CMOS voltage level is output from the buffer circuit 32. .

  According to the waveform shaping circuit 30 having the configuration shown in FIG. 9, an oscillation signal SOC having a small amplitude is centered on a signal centered on the low potential side VBS1 and the high potential side VBS2 by the AC coupling capacitors CA1 and CA2. Separate into signals. These separated signals are applied to the gates of the transistors TA1 and TA2 of the buffer circuit 32. Thereby, even when the amplitude of the oscillation signal SOC is sufficiently small with respect to the power supply voltage VDD, the waveform shaping of the oscillation signal SOC can be performed and the clock signal CLK at the CMOS voltage level can be generated.

6). Current Control Circuit In the present embodiment, the current control circuit 50 controls the current IB flowing through the buffer circuit BF in order to reduce the power consumption of the oscillation circuit particularly during standby. For example, when the amplitude of the oscillation signal SOC decreases and oscillation is about to stop, this is detected and the current IB is increased. As a result, the amplitude increases and oscillation continues. On the other hand, when the amplitude of the oscillation signal SOC increases, the current IB is decreased. This reduces the amplitude and keeps the amplitude constant. By doing so, the amplitude of the oscillation signal SOC can be kept constant with a small amplitude, so that the power consumption can be reduced. Even when the amplitude of the oscillation signal SOC is small as described above, by using the waveform shaping circuit 30 described with reference to FIG. 9, the CMOS signal level rectangular wave clock signal CLK can be obtained from the low amplitude sine wave oscillation signal SOC. Can be generated.

  FIG. 10 shows a configuration example of the current control circuit 50. Note that the current control circuit 50 of the present embodiment is not limited to the configuration of FIG. 10, and various modifications such as omitting some of the configuration requirements or adding other configuration requirements are possible.

  This current control circuit 50 includes an AC coupling capacitor CB for amplitude detection, an amplitude / voltage conversion circuit 52, and a voltage / current conversion circuit 54.

  One end of the AC coupling capacitor CB is connected to the amplitude detection node on the input side or output side of the oscillation buffer circuit BF. In FIG. 6, this amplitude detection node is a connection node NC1 on the input side of the oscillation buffer circuit BF. However, the amplitude detection node may be the connection node NC2 on the output side of the oscillation buffer circuit BF.

  Then, the DC component of the oscillation signal SOC is cut by the AC coupling capacitor CB, and the AC component is extracted. Note that the AC coupling capacitor CB is preferably a capacitor having an MIM structure. By doing so, it is possible to protect the internal circuit from static electricity applied via the pads P1 and P2, and to prevent electrostatic breakdown of the internal circuit.

  The amplitude / voltage conversion circuit 52 is connected to the other end of the AC coupling capacitor CB, and converts the amplitude of the oscillation signal SOC into a voltage. That is, the amplitude of the AC component of the oscillation signal SOC is converted into a voltage that increases as the amplitude increases.

  FIG. 11 shows a signal waveform example of amplitude / voltage conversion by the amplitude / voltage conversion circuit 52. As shown in FIG. 11, the signal SB after the DC cut by the AC coupling capacitor CB is a signal having an amplitude of several hundred mV. The amplitude / voltage conversion circuit 52 outputs a voltage VB corresponding to the amplitude of the signal SB. For example, when the amplitude of the signal SB is small, the voltage VB1 corresponding to the amplitude is output, and when the signal SB is large, the voltage VB2 corresponding to the amplitude is output. The amplitude / voltage conversion circuit 52 can be realized by a circuit that performs a smoothing process on the signal SB.

  The voltage / current conversion circuit 54 controls the current IB flowing through the oscillation buffer circuit BF based on the voltage VB from the amplitude / voltage conversion circuit 52. For example, in FIG. 11, when the amplitude of the signal SB is small and the voltage VB = VB1 from the amplitude / voltage conversion circuit 52 is small, the current IB flowing through the buffer circuit BF is increased. On the other hand, when the amplitude of the signal SB is large and the voltage VB = VB2 from the amplitude / voltage conversion circuit 52 is large, the current IB flowing through the buffer circuit BF is reduced.

  In this way, when the amplitude of the oscillation signal SOC is small, the current IB (operating current, short-circuit current) flowing through the transistors TB1 and TB2 of the buffer circuit BF increases and the amplitude of the oscillation signal SOC increases. Become. On the other hand, when the amplitude of the oscillation signal SOC is large, the current IB flowing through the transistors TB1 and TB2 of the buffer circuit BF decreases, and the amplitude of the oscillation signal SOC decreases. Therefore, the amplitude of the oscillation signal can be kept constant with a small amplitude, and the power consumption can be reduced.

7). Detailed Layout Arrangement FIG. 12 shows a detailed layout arrangement example of the integrated circuit device of this embodiment. The layout arrangement of the present embodiment is not limited to that shown in FIG. 12, and various modifications can be made.

  FIG. 12 further shows an example layout layout of the waveform shaping circuit 30, the frequency dividing circuit 40, and the current control circuit 50 of FIG.

  As shown in FIG. 12, the waveform shaping circuit 30 is arranged in a region on the D1 direction side of the capacitive circuit CX1. Specifically, the capacitor circuit CX1 and the waveform shaping circuit 30 are adjacently disposed along the direction D1. The frequency dividing circuit 40 is disposed on the D3 direction side of the waveform shaping circuit 30. Specifically, the waveform shaping circuit 30 and the frequency dividing circuit 40 are adjacently disposed along the direction D3. When the waveform shaping node of the waveform shaping circuit 30 in FIG. 6 is the connection node NC2 on the output side of the buffer circuit BF, the waveform shaping circuit 30 may be arranged in a region on the D2 direction side of the capacitive circuit CX2. .

  If the waveform shaping circuit 30 and the frequency dividing circuit 40 are laid out as shown in FIG. 12, the signal line from the pad P1 can be connected to the waveform shaping circuit 30 through a short path. Therefore, efficient layout wiring is possible, and a situation in which excess parasitic capacitance is superimposed can be prevented. Further, it is possible to prevent a situation in which noise is superimposed on the small amplitude oscillation signal SOC input to the waveform shaping circuit 30 to cause a malfunction.

  In FIG. 12, the current control circuit 50 is arranged in a region on the D3 direction side of the buffer circuit BF. Specifically, the buffer circuit BF and the current control circuit 50 are adjacently disposed along the direction D3. The current control circuit 50 is disposed in a region between the variable capacitance circuits CX1 and CX2.

  If the current control circuit 50 is arranged as shown in FIG. 12, the current control circuit 50 and the buffer circuit BF can be connected by a short path. Therefore, when the current control circuit 50 controls the current IB flowing through the buffer circuit BF, it is possible to prevent a situation in which noise or the like is superimposed and a malfunction occurs. In addition, a layout wiring in which the input side signal line and the output side signal line of the buffer circuit BF do not cross each other can be easily realized.

  Also in FIG. 12, the relationship LA> LB is established when the distance between the pads P1 and P2 in a plan view is LA and the distance between the protective resistance elements R1 and R2 in a plan view is LB.

8). Capacitance Value Setting Method Next, a capacitance value setting method of the variable capacitance circuits CX1 and CX2 will be described. As shown in FIG. 13, in the present embodiment, during normal operation, the capacitance value of the variable capacitance circuit CX1 is set to CN, and during standby, the capacitance value of the variable capacitance circuit CX1 is set to CS, and the relationship CN> CS is satisfied. It holds. Similarly, during normal operation, the capacitance value of the variable capacitance circuit CX2 is set to CN, and during standby, the capacitance value of the variable capacitance circuit CX2 is set to CS, and the relationship CN> CS is established.

  Note that the capacitance values (CN, CS) of the variable capacitance circuits CX1 and CX2 are preferably the same capacitance values considering the balance at the time of oscillation, but may be different capacitance values. Further, the standby time is a period in which the integrated circuit device shifts to a standby mode (sleep mode, standby mode) without performing a normal operation, for example, a period during which the power consumption operation is lower than that in the normal operation. . The normal operation is a period during which normal processing / operation that the integrated circuit device originally intends, such as wireless reception operation and transmission operation, for example, in the case of a wireless integrated circuit device.

  For example, in this embodiment, it is detected in advance whether the operation mode is the normal operation mode (first mode) that requires a high-precision frequency or the standby mode (second mode) that does not require such a high-precision frequency. . In the normal operation mode, the capacitance values of the variable capacitance circuits CX1 and CX2 are set to a large capacitance value CN. By doing so, the frequency accuracy of the clock signal generated by the oscillation signal can be increased. On the other hand, in the standby mode, the capacitance values of the variable capacitance circuits CX1 and CX2 are set to a small capacitance value CS. By doing so, the operating current can be reduced as shown in FIG. 13, and the power consumption can be reduced.

  That is, during normal operation such as wireless reception and transmission, the variable capacitance circuits CX1 and CX2 are set to a large capacitance value CN. Therefore, when the load capacity of the buffer circuit BF increases, as shown in FIG. The current IDDN increases. On the other hand, since the variable capacitance circuit is set to a small capacitance value CS during standby in the low power consumption operation mode, the load current of the buffer circuit BF is reduced, so that the standby current IDDS is smaller than the normal operation current IDDN. Get smaller. Therefore, the operating current of the oscillation circuit can be reduced in the standby mode that does not require a high-accuracy frequency.

  FIG. 14A is a diagram illustrating the relationship between the capacitance value of the variable capacitance circuit and the frequency deviation. Here, the frequency deviation represents a frequency deviation from the target frequency of oscillation.

  As shown in FIG. 14A, the larger the capacitance value (internal oscillation capacitance value) of the variable capacitance circuit, the smaller the frequency deviation (frequency deviation from the target frequency), and the higher the oscillation frequency accuracy. Therefore, during normal operation, a clock signal with high frequency accuracy can be obtained by setting a large capacitance value CN as indicated by A1 in FIG. On the other hand, in the standby mode, the frequency accuracy is lowered by setting the capacitance value CS to a small value as indicated by A2, but the problem does not occur so much because it is in the standby mode.

  FIG. 14B is a diagram illustrating the relationship between the capacitance value of the variable capacitance circuit and the operating current. As shown in FIG. 14B, the operating current (current consumption) of the oscillation circuit increases as the capacitance value of the variable capacitance circuit increases. Therefore, by setting the capacitance value CS to a small value CS as shown at A4 in FIG. 14B during standby, the operating current can be reduced compared to the normal operation shown at A3, and power consumption can be reduced.

  For example, as shown by A1 in FIG. 14A, the oscillation frequency of the oscillation circuit can be set to the target frequency by setting the capacitance value to CN so that the frequency deviation with respect to the target frequency (for example, 16 MHz) is close to zero. . In this case, since the capacitance value CN for setting the target frequency varies due to external factors such as parasitic capacitance of wirings, substrates, and elements and process variations, the frequency deviation is 0 when the integrated circuit device is shipped, for example. The optimum capacitance value CN that is in the vicinity is set. Thereby, for example, it becomes possible to satisfy the standard regarding the frequency accuracy of the carrier wave frequency in communication.

  However, such high-accuracy frequency setting is necessary in normal operation, but is unnecessary in standby time when normal operation such as communication is not performed. Therefore, at the time of standby, despite a large frequency deviation, a small capacitance value CS is set as shown in A2 of FIG. This can reduce the operating current during standby as indicated by A4 in FIG. For example, the operating current, which was 7-8 μA during the normal operation of A3 in FIG. 14B, can be reduced to 3-4 μA during the standby of A4. Since the current consumption of the oscillation circuit occupies most of the current consumption during standby, the current consumption of the integrated circuit device during standby is significantly reduced by reducing the current consumption of the oscillation circuit as shown in A4. Can be reduced.

  Note that the standby capacitance value CS may be, for example, 0 pF. That is, the capacitance value of the variable capacitance circuit is set to zero. Even in this case, the parasitic capacitance of the wiring, the substrate, and the circuit element functions as an oscillation capacitor, and the oscillation during standby can be maintained.

9. Integrated Circuit Device FIG. 15 shows a circuit configuration example of an integrated circuit device. FIG. 15 is a configuration example when the integrated circuit device is a wireless communication IC. However, the present embodiment is not limited to this, and can be applied to various integrated circuit devices such as sensor ICs.

  The integrated circuit device of FIG. 15 includes an oscillation circuit 100, a wireless circuit 110, and a standby circuit 120.

  The oscillation circuit 100 generates clock signals CKN1 and CKN2 for normal operation and outputs them to the radio circuit 110. Further, the standby clock signal CKS is generated and output to the standby circuit 120.

  The wireless circuit 110 is a circuit that performs wireless communication during normal operation. The wireless circuit 110 includes, for example, a reception circuit, a transmission circuit, and a PLL circuit for wireless communication. Note that only one of the reception circuit and the transmission circuit may be provided.

  As described with reference to FIGS. 13 to 14B, the radio circuit 110 is based on the normal operation clock signals CKN1 and CKN2 generated by setting the capacitance values of the variable capacitance circuits CX1 and CX2 to CN. Works. That is, the operation is performed based on the highly accurate clock signals CKN1 and CKN2.

  In wireless communication, it is necessary to keep the fluctuation (frequency deviation) of the carrier frequency (for example, 2.4 GHz) within a predetermined fluctuation range (predetermined frequency deviation). For example, it is necessary to be within the fluctuation range (for example, 50 ppm) defined by the communication standard.

  In this regard, in the present embodiment, as described with reference to FIG. 14A and the like, the capacitance value CN of the variable capacitance circuit in the normal operation is set so that the fluctuation of the carrier frequency of the wireless communication is within a predetermined fluctuation range. . Therefore, wireless communication standards can be satisfied, and appropriate wireless communication can be realized.

  The standby circuit 120 operates based on the standby clock signal CKS from the oscillation circuit 100 when the integrated circuit device is on standby. Specifically, it operates based on the standby clock signal CKS generated by setting the capacitance values of the variable capacitance circuits CX1, CX2 to CS.

  For example, during standby, the frequency dividing circuit 40 of FIG. 6 divides the 16 MHz clock signal CLK and outputs a standby clock signal CKS of 32 KHz. The standby circuit 120 operates based on the standby clock signal CKS of 32 KHz. Therefore, the power consumption can be reduced compared to the case of operating with a 16 MHz clock signal, and the power consumption during standby can be reduced.

  More specifically, the standby circuit 120 includes a standby counter 122 that counts the standby period. The standby counter 122 performs a counting process using the standby clock signal CKS and counts the standby period. In this case, the capacitance values CS of the variable capacitance circuits CX1 and CX2 at the time of standby are set so that the fluctuation of the standby period falls within a predetermined fluctuation range (for example, 500 ppm).

  For example, FIG. 16 is an operation explanatory diagram of the integrated circuit device of the present embodiment which is a wireless communication IC. At the time of standby, for example, the wireless communication IC on the slave (client) side is in a standby mode and operates based on the standby clock signal. At this time, the wireless communication IC on the master (host) side may also operate in the standby mode.

  During normal operation, the wireless communication IC shifts from the standby mode to the normal operation mode. Then, a series of wireless communication is performed in which the master side transmits information (TX) wirelessly and the slave side receives (RX) the information, or the slave side transmits information wirelessly and the master side receives the information. Is done. When the series of wireless communication is completed, the wireless communication IC shifts from the normal operation mode to the standby mode.

  And when it transfers to standby mode in this way, it is necessary to measure the standby | waiting period which is a period until the next series of radio | wireless communication is started. The standby counter 122 in FIG. 15 performs a counting process for measuring this standby period. When it is determined that the standby period determined by the communication processing on the master side and the slave side has elapsed based on the count processing result of the standby counter 122, the wireless communication IC changes from the standby mode to the normal operation mode. Migrate to Then, a series of wireless communication is executed.

  Such a waiting period counting process does not require high-precision frequency accuracy such as a carrier frequency. For this reason, the standby counter 122 performs a count process based on the low-accuracy clock signal CKS obtained by setting the capacitance value CS. However, for example, if there is a deviation between the master side and the slave side with respect to the length of the standby period, there is a possibility that a malfunction of the operation may occur or useless power may be consumed. For this reason, the capacitance values CS of the variable capacitance circuits CX1 and CX2 at the time of standby are set so that the fluctuation of the standby period falls within a predetermined fluctuation range.

  FIG. 17 shows a detailed configuration example of an integrated circuit device for wireless communication. This integrated circuit device includes a reception circuit 230, a demodulation circuit 236, a transmission circuit 240, a modulation circuit 246, an oscillation circuit 247, a PLL circuit 248, and a control circuit 250.

  The reception circuit 230 includes a low noise amplifier LNA, a mixer 232, and a filter unit 234. The low noise amplifier LNA performs processing for amplifying an RF reception signal input from the antenna ANT with low noise. The mixer 232 performs mixing (mixing) processing of the amplified received signal and the local signal (local frequency signal) from the PLL circuit 248 to perform down conversion. The filter unit 234 performs a filtering process on the received signal after down conversion. Specifically, the filter unit 234 performs bandpass filter processing realized by a complex filter or the like, and extracts a baseband signal while performing image removal.

  The demodulation circuit 236 performs demodulation processing based on the signal from the reception circuit 230. For example, demodulation processing of a signal modulated by FSK (frequency shift keying) is performed on the transmission side, and the demodulated reception signal is output to the control circuit 250.

  The modulation circuit 246 performs modulation processing on the transmission signal from the control circuit 250. For example, the transmission signal is modulated by FSK, and the modulated transmission signal is output to the transmission circuit 240. Then, the transmission circuit 240 outputs the transmission signal amplified by the power amplifier PA to the antenna ANT.

  The PLL circuit 248 is configured by a VCO (voltage controlled oscillator) or the like, and generates a local signal or the like based on the clock signal from the oscillation circuit 247.

  The control circuit 250 performs overall control of the integrated circuit device, baseband digital processing, and the like. The control circuit 250 includes, for example, a link layer circuit 252 and a host I / F (interface) 254, and executes link layer protocol processing, interface processing with an external host, and the like.

10. Electronic Device FIG. 18 shows a configuration example of an electronic device including the integrated circuit device 310 of this embodiment. The electronic device includes an antenna ANT, an integrated circuit device 310, a host 320, a detection device 330, a sensor 340, and a power supply unit 350. Note that the electronic apparatus according to the present embodiment is not limited to the configuration shown in FIG. Various modifications such as addition of) are possible.

  The integrated circuit device 310 is a wireless circuit device realized by a circuit configuration as shown in FIGS. 15 and 17, and performs a signal reception process from the antenna ANT and a signal transmission process to the antenna ANT. The host 320 controls the entire electronic device, and controls the integrated circuit device 310 and the detection device 330. The detection device 330 performs various detection processes (physical quantity detection processes) based on sensor signals from the sensor 340 (physical quantity transducer). For example, processing for detecting a desired signal from the sensor signal is performed, and the digital data after A / D conversion is output to the host 320. The sensor 340 is, for example, a smoke sensor, an optical sensor, a human sensor, a pressure sensor, a biological sensor, a gyro sensor, or the like. The power supply unit 350 supplies power to the integrated circuit device 310, the host 320, the detection device 330, and the like. For example, the power supply unit 350 supplies power using a dry battery (such as a round battery) or a battery.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (VSS node, VDD node, etc.) described at least once together with different terms (first power supply node, second power supply node, etc.) in a broader sense or synonymous The different terms can be used anywhere in the drawing. Further, the configurations and operations of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

BF oscillation buffer circuit,
CX1, CX2 first and second variable capacitance circuits (capacitance circuits),
XTAL vibrator, P1, P2 first and second pads,
NC1, NC2 first and second connection nodes, R1, R2 first and second protective resistance elements,
DI1A, DI1B, DI2A, DI2B Protection diode,
C11-C14, C21-C24 unit capacitors,
S11 to S14, S21 to S24 switch elements,
CA1, CA2, AC coupling capacitor for waveform shaping,
CB AC coupling capacitor for amplitude detection,
BSC1, BSC2 first and second self-bias voltage setting circuits,
20 control circuit, 30 waveform shaping circuit, 32 buffer circuit, 40 frequency dividing circuit,
50 current control circuit, 52 amplitude / voltage conversion circuit, 54 voltage / current conversion circuit,
100 oscillation circuit, 110 radio circuit, 120 standby circuit,
122 counter for standby, 230 receiving circuit, 232 mixer section,
234 filter section, 236 demodulation circuit, 240 transmission circuit, 246 modulation circuit,
247 oscillator circuit, 248 PLL circuit, 250 control circuit,
252 link layer circuit, 254 host I / F, 310 integrated circuit device,
320 host, 330 detector, 340 sensor, 350 power supply

Claims (15)

A first pad connected to one end of the vibrator;
A second pad connected to the other end of the vibrator;
A buffer circuit for oscillation of the vibrator;
A first protective resistance element provided between a first connection node on the first pad side and an input node of the buffer circuit;
A second protective resistance element provided between a second connection node on the second pad side and an output node of the buffer circuit;
A capacitive circuit connected to one of the first connection node or the second connection node;
An integrated circuit device comprising: In claim 1,
When the direction opposite to the first direction is the second direction,
The first protective resistance element is disposed in a region on the first direction side of the buffer circuit,
2. The integrated circuit device according to claim 1, wherein the second protective resistance element is disposed in a region on the second direction side of the buffer circuit. In claim 2,
The capacitance circuit is
An integrated circuit device, wherein the integrated circuit device is disposed in a region on the first direction side of the first protection resistance element or a region on the second direction side of the second protection resistance element. In claim 3,
A waveform shaping circuit that performs waveform shaping of an oscillation signal generated by the vibrator and the buffer circuit and outputs a clock signal;
The waveform shaping circuit is
An integrated circuit device, wherein the integrated circuit device is arranged in a region on the first direction side of the capacitor circuit or a region on the second direction side of the capacitor circuit. In any one of Claims 1 thru | or 4,
A current control circuit that detects an amplitude of an oscillation signal generated by the vibrator and the buffer circuit and controls a current flowing through the buffer circuit so that the amplitude of the oscillation signal is constant;
When the direction orthogonal to the first direction is the third direction,
The current control circuit is
An integrated circuit device, wherein the integrated circuit device is arranged in a region on the third direction side of the buffer circuit. In claim 5,
When the direction opposite to the third direction is the fourth direction,
A first I / O cell having a protection diode is disposed in a region on the fourth direction side of the first protection resistance element;
An integrated circuit device, wherein a second I / O cell having a protection diode is disposed in a region on the fourth direction side of the second protection resistance element. In claim 6,
An integrated circuit device, wherein at least one of the first I / O cell and the second I / O cell is disposed between the first pad and the second pad. In any one of Claims 1 thru | or 7,
An integrated circuit device comprising a second capacitor circuit connected to the other of the first connection node or the second connection node. In any one of Claims 1 thru | or 8.
An integrated circuit device, wherein an input side signal line of the buffer circuit and an output side signal line of the buffer circuit are wired so as to be non-overlapping in a plan view. In any one of Claims 1 thru | or 9,
The integrated circuit device, wherein the buffer circuit, the first protection resistance element, and the second protection resistance element are adjacently disposed in a plan view. In any one of Claims 1 thru | or 10.
When the distance in plan view between the first pad and the second pad is LA, and the distance in plan view between the first protection resistance element and the second protection resistance element is LB, LA An integrated circuit device, characterized in that> LB. In any one of Claims 1 thru | or 11,
The capacitance circuit is a variable capacitance circuit in which a capacitance value is variably set.
During normal operation, the capacitance value of the variable capacitance circuit is set to CN,
During standby, the capacitance value of the variable capacitance circuit is set to CS,
An integrated circuit device, wherein CN> CS. In claim 12,
A standby circuit that operates based on a standby clock signal from the oscillation circuit during the standby;
The standby circuit is:
An integrated circuit device, which operates based on the standby clock signal generated by setting a capacitance value of the variable capacitance circuit to CS. In claim 12 or 13,
Including a wireless circuit for performing wireless communication during the normal operation,
The wireless circuit is
An integrated circuit device, which operates based on a clock signal for normal operation generated by setting a capacitance value of the variable capacitance circuit to CN.   An electronic apparatus comprising the integrated circuit device according to claim 1.

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