WO2007138690A1 - Noncontact type electronic device and semiconductor integrated circuit device mounted on same - Google Patents

Noncontact type electronic device and semiconductor integrated circuit device mounted on same Download PDF

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Publication number
WO2007138690A1
WO2007138690A1 PCT/JP2006/310855 JP2006310855W WO2007138690A1 WO 2007138690 A1 WO2007138690 A1 WO 2007138690A1 JP 2006310855 W JP2006310855 W JP 2006310855W WO 2007138690 A1 WO2007138690 A1 WO 2007138690A1
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WO
WIPO (PCT)
Prior art keywords
terminal
antenna terminal
mos transistor
antenna
capacitor
Prior art date
Application number
PCT/JP2006/310855
Other languages
French (fr)
Japanese (ja)
Inventor
Kazuki Watanabe
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2008517750A priority Critical patent/JP4759053B2/en
Priority to PCT/JP2006/310855 priority patent/WO2007138690A1/en
Publication of WO2007138690A1 publication Critical patent/WO2007138690A1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • H04B5/75

Definitions

  • the present invention relates to a technology of a non-contact type electronic device, and in particular, a technology effective when applied to a non-contact type electronic device typified by an IC card or an IC tag and a semiconductor integrated circuit device mounted thereon. It is about.
  • Non-contact type electronic devices having a semiconductor integrated circuit device having functions such as a CPU and a memory inside are becoming widespread in the fields of transportation and logistics.
  • the contactless electronic device does not have a power source such as a battery, and operates by generating power from electromagnetic waves received by an antenna.
  • the non-contact electronic device receives data transmitted by modulating electromagnetic waves from a reader / writer (interrogator), and further performs signal processing on the received data by a CPU, a memory, or the like.
  • the electromagnetic wave received by the antenna is modulated by changing the load between the antenna terminals according to the obtained data, and the data is transmitted to the reader / writer.
  • a capacitor and a variable capacitive element are connected in series between the antenna terminals, and a resonance voltage is controlled by applying a control voltage to the variable capacitive element, whereby the contactless electronic device
  • a technique for suppressing the power supplied to the battery see, for example, Patent Document 1.
  • the resonance frequency is changed by logically switching the capacitance connected between the antenna terminals, and the power supplied to the non-contact type electronic device.
  • Patent Document 2 describes that the resonance frequency is changed stepwise by switching a plurality of capacitors.
  • Patent Document 1 Japanese Patent Laid-Open No. 9-147070
  • Patent Document 2 JP 2005-204493 A Disclosure of the invention
  • a sensor circuit that detects a temperature or the like is mounted on a non-contact electronic device that operates by generating an electromagnetic force power source received by an antenna, and according to data transmitted from a reader / writer.
  • Some sensors measure the sensor circuit and can transmit the measurement data to the reader / writer by the above modulation operation.
  • a non-contact type electronic device operates by generating a power source by rectifying and smoothing an electromagnetic wave to which a reader / writer force is also supplied. Generally, since the electric power supplied to the non-contact type electronic device changes depending on the distance between the reader / writer and the non-contact type electronic device, the degree of self-heating of the non-contact type electronic device changes.
  • the present inventors have studied a technique for preventing excessive power from being supplied to the non-contact electronic device by controlling the resonance frequency according to the power received by the non-contact electronic device. It came to do.
  • the resonance frequency is usually set in a semiconductor manufacturing process used for mounting a logic circuit or the like. In some cases, a variable capacitance element that can be changed sufficiently was installed.
  • the resonance capacitance when the resonant capacitance is logically switched, it is necessary to detect the power received by the non-contact electronic device and binarize the received power level. For example, when the electric power received by the non-contact type electronic device exceeds a predetermined level, the resonance capacitance is logically switched. However, as a result of switching the resonance capacitance, the received power of the contactless electronic device is reduced to a predetermined level. If it falls below the bell, the resonance capacity is controlled to return to the original value. However, since the received power level again exceeds the predetermined level, the resonance capacity is switched. As described above, when the received power level is close to the level at which the resonance capacitor is switched, the switching operation of the resonance capacitor is repeated, and the power received by the non-contact type electronic device may not be stable.
  • an object of the present invention is to provide a circuit technique capable of stably controlling the power received by the non-contact type electronic device.
  • the non-contact electronic device according to the present invention and the semiconductor integrated circuit device mounted thereon include a resonance capacitance control circuit.
  • a first capacitor and a second capacitor are connected in series between a first antenna terminal and a second antenna terminal to which an antenna is connected, and the first capacitor and the second capacitor are connected.
  • the charge / discharge control circuit is connected to the connection point of the capacity.
  • the charge / discharge control circuit controls the charge accumulated in the first capacitor when the potential of the first antenna terminal is higher than the potential of the second antenna terminal, and controls the second antenna.
  • the resonance between the first antenna terminal and the second antenna terminal is controlled by controlling the charge accumulated in the second capacitor. Control the capacitance value.
  • FIG. 1 is a block diagram showing a basic configuration of a contactless electronic device and a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 2 is a perspective view showing configurations of a non-contact electronic device and a semiconductor integrated circuit device, a wiring board, and a reader / writer according to Embodiment 1 of the present invention.
  • FIG. 3 is a circuit diagram showing a configuration example of a resonance capacitance control circuit mounted on the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • IV is a circuit diagram showing a configuration example of a resonance capacitance control circuit mounted on the semiconductor integrated circuit device according to the second embodiment of the present invention.
  • FIG. 5 is a diagram showing an operation waveform of each terminal voltage of the resonance capacitance control circuit shown in FIG.
  • FIG. 6 is a circuit diagram showing a configuration example of a resonant capacitance control circuit mounted on a semiconductor integrated circuit device according to a third embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing a configuration example of a resonant capacitance control circuit mounted on a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
  • FIG. 8 is a block diagram showing a configuration example of a resonant capacitance control circuit and a rectifying / smoothing circuit mounted on a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
  • FIG. 1 is a block diagram showing a basic configuration of a non-contact electronic device and a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
  • the contactless electronic device according to the first embodiment is, for example, an IC force card, an IC tag, an RFID, or a mobile phone.
  • B1 is a non-contact type electronic device
  • B2 is a semiconductor integrated circuit device mounted on the non-contact type electronic device B1
  • LO is an antenna mounted on the non-contact type electronic device B1.
  • the semiconductor integrated circuit device B2 has a resonance capacitance control circuit B3, a rectifying / smoothing circuit B4, and an internal circuit B5, and has antenna terminals LA and LB for connecting the antenna LO.
  • the antenna LO is not necessarily connected because it is adjusted in consideration of the force resonance capacitance control circuit B3 in which the resonance capacitance CO is connected in parallel and the parasitic capacitance.
  • FIG. 2 shows a structural example of the non-contact type electronic device B1.
  • Figure 2 shows an example of an IC card, but this is not a limitation.
  • the non-contact type electronic device B1 is in the form of a card by a resin-molded printed circuit board B10.
  • the antenna LO that receives electromagnetic waves from the external reader / writer B13 is constituted by a spiral coil B11 formed by the wiring of the printed board B10.
  • a coil B11 serving as an antenna LO is connected to the IC chip B12.
  • the antenna LO (coil B11) receiving the electromagnetic wave from the reader / writer B13 outputs a high-frequency AC signal to the antenna terminals LA and LB. This AC signal is partially modulated by an information signal (data).
  • the present invention is typically applied to a non-contact type electronic device having no external input / output terminal on the surface of the non-contact type electronic device.
  • a non-contact type electronic device having no external input / output terminal on the surface of the non-contact type electronic device.
  • the semiconductor integrated circuit device B2 is formed on a single semiconductor substrate such as single crystal silicon or the like by a known semiconductor integrated circuit device manufacturing technique.
  • the resonance capacitance control circuit B3 is configured by the antenna LO, the resonance capacitance control circuit B3, and the resonance capacitance CO by controlling the resonance capacitance according to the power supplied between the antenna terminals.
  • the resonance frequency of the resonance circuit is changed.
  • the rectifying / smoothing circuit B4 includes a rectifying circuit and a smoothing capacitor, and may have a regulator function.
  • the regulator function controls so that the voltage generated by the rectifier circuit and the smoothing capacitor does not exceed a predetermined voltage level.
  • the output voltage of the rectifying / smoothing circuit B4 is supplied as the power supply voltage VDD of the internal circuit B5.
  • the internal circuit B5 includes a receiving circuit B6, a transmitting circuit B7, a control unit B8, and a memory B9. .
  • the reception circuit B6 demodulates the information signal superimposed on the AC signal received by the antenna LO provided in the non-contact type electronic device B1, and supplies it to the control unit B8 as a digital information signal.
  • the transmission circuit B7 receives the information signal of the digital signal output from the control unit B8, and modulates the AC signal received by the antenna LO with the information signal.
  • the reader / writer B13 (see FIG. 2) receives the information signal from the control unit B8 in response to the reflection of the electromagnetic wave from the antenna LO being changed by the modulation.
  • the memory B9 is used for recording information data and transmission data demodulated with the control unit B8.
  • FIG. 3 is a basic configuration diagram of a resonance capacitance control circuit B3 mounted on the semiconductor integrated circuit device B2 according to the present invention.
  • the resonance capacitance control circuit B3 is connected between the antenna terminal LA (first antenna terminal) and the antenna terminal LB (second antenna terminal).
  • the resonant capacity control circuit B3 has a capacity C1 (first capacity) and a capacity C2 (second capacity) between the antenna terminals LA and LB that connect the antenna mounted on the non-contact type electronic device B1. Connected in series, the connection point between capacitors C1 and C2 and charge / discharge control circuit B14 connected to antenna terminals LA and LB are connected.
  • the charge / discharge control circuit B14 includes variable resistors R1 and R2 connected in series between the antenna terminals LA and LB, and a connection point between the variable resistors R1 and R2 and a connection point between the capacitors C1 and C2 are connected. .
  • a rectifying / smoothing circuit B4 mounted on the semiconductor integrated circuit device B2 is connected to the antenna terminals LA and LB, and the power supply voltage VDD is output between the output terminal OUT and the ground terminal.
  • the charge / discharge control circuit B14 controls the resistances of the resistors R1 and R2 connected in parallel to the capacitors C1 and C2 so as to increase.
  • the current is controlled so as to hardly flow through the resistors R1 and R2.
  • the capacitors C1 and C2 are connected in series between the antenna terminals, and a capacitor having a capacitance value half that of the capacitor C1 or C2 is connected.
  • the capacitance values of the capacitors C1 and C2 are equal.
  • the charge / discharge control circuit B14 When the voltage between the antenna terminals higher than the potential of the antenna terminal LA is higher than a predetermined voltage level, the charge / discharge control circuit B14 The resistance R2 connected in parallel with the capacitor C2 is controlled to be small according to the voltage level between the terminals. In addition, when the voltage between the antenna terminals, which is higher than the potential of the antenna terminal LA, is higher than a predetermined voltage level, it is connected in parallel to the capacitor C1 according to the voltage level between the antenna terminals. The resistance R1 is controlled to be small.
  • the charge accumulated in the capacitor C 1 is controlled, and when the potential of the antenna terminal LB is higher than the potential of the antenna terminal LA, the capacitance By controlling the charge stored in C2, the resonant capacitance between antenna terminal LA and antenna terminal LB is controlled.
  • the resonance capacitance can be controlled in a range from a capacitance value half of the capacitance C1 to a capacitance value equivalent to the capacitance C1, according to the voltage level generated between the antenna terminals.
  • the resonance frequency of the resonance circuit configured by the resonance capacitance control circuit B3 can be controlled.
  • the capacitance values of the capacitors C1 and C2 are set to twice the capacitance value that resonates with the frequency of the electromagnetic wave supplied to the antenna LO, the voltage level generated between the antenna terminals becomes a predetermined voltage. If the voltage level is lower than the level, the maximum power can be received by resonating.If the voltage level generated between the antenna terminals is higher than the specified voltage level, the resonance frequency can be lowered by increasing the resonance capacity of the antenna terminal. The electric power supplied to the rectifying / smoothing circuit B4 can be reduced.
  • the charge / discharge control circuit B14 is connected to the capacitors C1 and C2 connected between the antenna terminals.
  • the resonance capacitance between the antenna terminals is controlled by controlling the resistance connected in parallel to the low-potential side capacitor, but the resistance connected in parallel to the high-potential side capacitance is controlled.
  • the same effect can be obtained.
  • FIG. 4 is a circuit configuration diagram showing another embodiment of the resonance capacitance control circuit B3 mounted in the semiconductor integrated circuit device B2 according to the present invention. This shows another circuit configuration example of the charge / discharge control circuit B14 mounted on the resonance capacitance control circuit B3 shown in FIG.
  • the resonant capacitance control circuit B3 connected between the antenna terminals LA and LB has capacitors C1 and C2 between the antenna terminals LA and LB that connect the antenna mounted on the non-contact type electronic device B1.
  • the charge / discharge control circuit B14 is connected to the connection point of the capacitors C1 and C2 and the antenna terminals LA and LB.
  • the charge / discharge control circuit B14 has a MOS transistor Ml (first MOS transistor) whose gate terminal is connected to the antenna terminal LB and a MOS transistor M2 (second MOS transistor) whose gate terminal is connected to the antenna terminal LA.
  • a variable resistor R3 variable resistor element is connected between the connection point of the capacitors C1 and C2 and the connection point of the MOS transistors Ml and M2.
  • FIG. 5 shows an example of the operation waveform of each terminal voltage in FIG. This shows the operating waveform of each terminal voltage based on the potential at the connection point of the MOS transistors Ml and M2, W0 is the voltage waveform at the connection point of the MOS transistors Ml and M2, and W1 is the antenna terminal LA.
  • Voltage waveform, W2 is the voltage waveform at the antenna terminal LB
  • W3 and W4 are the voltage waveforms at the connection point of the capacitors C1 and C2
  • W3 is the voltage waveform when the variable resistance R3 is extremely large
  • the resistance value, W4 is variable Show the voltage waveform when resistance R3 is very small and resistance! / Speak.
  • the MOS transistor M2 When the potential of the antenna terminal LA is higher than the potential of the antenna terminal LB, the MOS transistor M2 is turned on and the MOS transistor Ml is turned off. Also, when the potential of the antenna terminal LB is higher than the potential of the antenna terminal LA, the MOS transistor Ml is turned on and the MOS transistor M2 is turned off.
  • connection point of the MOS transistors Ml and M2 is controlled to be equal to the potential of the antenna terminal LA or LB on the low potential side.
  • the voltage waveform is Wl and W2. Therefore, the variable resistor R3 operates in a state where it is connected in parallel with the low-potential side capacitor C1 or C2, and when the variable resistor R3 has a very large resistance value, the variable resistor R3 can be ignored. As shown in W3, the connection point between capacitors C1 and C2 is half the voltage between antenna terminals.
  • variable resistor R3 when the variable resistor R3 has a very small resistance value, it is equivalent to a state in which both ends of the variable resistor R3 are short-circuited.As shown in W4, the connection point of the capacitors C1 and C2 is WO and It is almost equal and can be approximated to the state where the capacitor C1 or C2 is connected between the antenna terminals.
  • the resonance capacitance can be controlled in the range from half the capacitance value of the capacitance C1 to the capacitance value equivalent to the capacitance C1, and is configured by the antenna LO and the resonance capacitance control circuit B3 This shows that the resonant frequency of the resonant circuit can be controlled.
  • the circuit shown in FIG. 3 requires two variable resistors, it becomes possible to share the variable resistors and reduce variations due to the variable resistors.
  • the threshold voltages of the MOS transistors Ml and M2 can also contribute to the characteristic error.
  • the MOS transistors Ml and M2 are turned on / off, the influence on the resonant capacitance characteristics is not affected.
  • FIG. 6 is a circuit configuration diagram showing another embodiment of the resonance capacitance control circuit B3 mounted on the semiconductor integrated circuit device B2 according to the present invention.
  • This is an example in which the variable resistor R3 constituting the charge / discharge control circuit B14 mounted on the resonance capacitance control circuit B3 shown in FIG. 4 is configured by a MOS transistor.
  • the resonant capacitance control circuit B3 connected between the antenna terminals LA and LB has capacitors C1 and C2 between the antenna terminals LA and LB that connect the antenna mounted on the non-contact type electronic device B1. Are connected in series, and the connection point of the capacitors C1 and C2 and the charge / discharge control circuit B14 connected to the antenna terminals LA and LB are connected.
  • the charge / discharge control circuit B14 has a MOS transistor Ml having a gate terminal connected to the antenna terminal LB and a MOS transistor M2 having a gate terminal connected to the antenna terminal LA connected in series, and a connection point between the capacitors C1 and C2. And the connection point of MOS transistors Ml and M2, A MOS transistor M3 (variable resistance element, seventh MOS transistor) is connected, and a voltage detection circuit B15 is connected between the antenna terminals LA and LB. At this time, the connection point of MOS transistors Ml and M2 is connected to the ground terminal.
  • a MOS transistor M4 (first rectifier element) having a gate terminal and a drain terminal connected is connected between the antenna terminal LA and the output terminal OUT2, and the antenna terminal LB and the output terminal are connected.
  • a MOS transistor M5 (second rectifier) with the gate and drain terminals connected between OUT2, connect a capacitor C3 between the output terminal OUT2 and the ground terminal, and connect the output terminal OUT2 and the ground terminal.
  • Connect the connection point of resistors R4 and R5 connected in series between them to the non-inverting input terminal (+) of the operational amplifier circuit A1, and input the reference voltage VI to the inverting input terminal (one) of the operational amplifier circuit A1.
  • the output terminal N1 of the operational amplifier circuit A1 is input to the gate terminal of the MOS transistor M3.
  • the operational amplifier circuit A 1 detects the power supplied between the antenna terminals as a voltage generated at the output terminal OUT 2 and controls the current flowing through the MOS transistor M 3.
  • the voltage generated at the output terminal OUT2 is higher than a predetermined voltage level, that is, when the voltage generated at the antenna terminal is higher than the predetermined voltage level, depending on the voltage generated at the output terminal OTU2 Since the current flowing through the MOS transistor M3 is controlled, the charge stored in the capacitors C1 and C2 is controlled, and the capacitance connected between the antenna terminals changes. For example, when the current flowing through the MOS transistor M3 is controlled to an extremely large current value, either the capacitor C1 or C2 is short-circuited, so that the capacity value equivalent to the capacity C1 is between the antenna terminals. Can be approximated to a connected state.
  • the resonance capacitance can be controlled in a range from a capacitance value half of the capacitance C1 to a capacitance value equivalent to the capacitance C1, according to the voltage level generated between the antenna terminals.
  • the resonant frequency of the resonant circuit composed of the tenor LO and resonant capacity control circuit B3 can be controlled.
  • the capacitance value of the capacitor C1 is set to twice the capacitance value that resonates with the frequency of the electromagnetic wave supplied to the antenna LO, the voltage level generated between the antenna terminals will be higher than the predetermined voltage level. If it is small, the maximum power can be received by resonating with the frequency of the electromagnetic wave, and if the voltage level generated between the antenna terminals is higher than the predetermined voltage level, the resonance frequency can be increased by increasing the resonance capacity of the antenna terminal. The power supplied to the rectifying / smoothing circuit B4 can be reduced.
  • the on-resistance of the MOS transistor M3 is increased to resonate the antenna terminal.
  • the resonance frequency may be controlled to be higher by reducing the capacitance.
  • MOS transistor M2 is turned on only when the potential of antenna terminal LA is higher than the potential of antenna terminal LB, and MOS transistor Ml is turned on only when the potential of antenna terminal LB is higher than the potential of antenna terminal LA. Therefore, the MOS transistors Ml and M2 also operate as a rectifying element on the low potential side.
  • a current flows through the MOS transistor M4 only when the potential of the antenna terminal LA is higher than the potential of the output terminal OUT2, and a current flows through the MOS transistor M5 only when the potential of the antenna terminal LB is higher than the potential of the output terminal OUT2. Since it flows, the MOS transistors M4 and M5 also operate as rectifiers on the high potential side.
  • the charge / discharge control circuit B14 also functions as a rectifier circuit, and the capacitor C3 functions as a smoothing capacitor. Therefore, the voltage generated at the output terminal OUT2 is transferred to the internal circuit B5 of the semiconductor integrated circuit device B2. Can be used as a power supply voltage. As a result, it is not necessary to mount the rectifying / smoothing circuit B4 independent of the resonance capacitance control circuit B3, and the chip area can be reduced.
  • FIG. 7 is a circuit configuration diagram showing another embodiment of the resonance capacitance control circuit B3 mounted in the semiconductor integrated circuit device B2 according to the present invention. This is the resonant capacitance control circuit shown in Fig. 3. 10 shows another circuit configuration example of the charge / discharge control circuit B14 mounted on B3.
  • the resonant capacitance control circuit B3 connected between the antenna terminals LA and LB has capacitors C1 and C2 between the antenna terminals LA and LB connecting the antenna arranged in the non-contact type electronic device B1. Are connected in series, and the connection point of the capacitors C1 and C2 and the charge / discharge control circuit B14 connected to the antenna terminals LA and LB are connected.
  • the charge / discharge control circuit B14 includes a MOS transistor M6 (third MOS transistor) in which a resistor R6 (first resistor) is connected between the antenna terminal LB and the gate terminal between the antenna terminals LA and LB. ) And a MOS transistor M7 (fourth MOS transistor) with a resistor R7 (second resistor) connected between the antenna terminal LA and the gate terminal, and between the gate terminal of the MOS transistor M6 and the ground terminal.
  • the MOS transistor M8 (fifth MOS transistor) with the gate terminal connected to the antenna terminal LB and the MOS transistor M10 (variable resistance element, seventh MOS transistor) with the gate terminal connected to the output terminal N1 of the voltage detection circuit B15 ) Are connected in series, and the MOS transistor M9 (sixth MOS transistor) has a gate terminal connected to the antenna terminal LA between the gate terminal of the MOS transistor M7 and the drain terminal of the MOS transistor M10. It is connected.
  • the voltage detection circuit B15 is configured to output a voltage corresponding to the voltage generated between the antenna terminals.
  • the voltage detection circuit B15 may have the circuit configuration illustrated in FIG. However, in order to connect to the ground terminal in the chip, a rectifier on the low potential side represented by MOS transistors Ml and M2 shown in FIG. 6 is also required.
  • the voltage detection circuit B15 depending on the voltage generated between the antenna terminals,
  • the voltage generated between the antenna terminals is higher than a predetermined voltage level, the current flowing through the MOS transistor M10 is controlled according to the voltage generated at the antenna terminal. Therefore, the voltage generated in the resistor R6 or R7 is controlled to increase, and the gate voltages of the MOS transistors M6 and M7 are suppressed. As a result, since the current flowing through the MOS transistors M6 and M7 is controlled, the charge stored in the capacitors C1 and C2 is controlled, and the capacitance connected between the antenna terminals changes.
  • the current flowing through the MOS transistors M6 and M7 is controlled to a very small current value, it can be approximated to the state where the capacitors C1 and C2 are connected in series between the antenna terminals, and the capacitance having a capacitance value half that of the capacitor C1 is obtained. It will be connected.
  • the resonance capacitance can be controlled in the range from the capacitance value equivalent to the capacitance C1 to the capacitance value half of the capacitance C1, according to the voltage level generated at the antenna terminal.
  • the resonance frequency of the resonance circuit configured by the resonance capacitance control circuit B3 can be controlled.
  • FIG. 8 is a block diagram showing an embodiment of the resonant capacitance control circuit B3 and the rectifying / smoothing circuit B4 mounted on the semiconductor integrated circuit device B2 according to the present invention.
  • the regulator circuit B16 can be mounted to stabilize the power supply voltage supplied to the internal circuit B5. good. As a result, it is possible to reduce chip heat generation by suppressing excessive power supply by the resonance capacitance control circuit B3, and to stabilize power supply voltage. Can be supplied to the internal circuit B5.
  • the voltage level at which the resonant capacitance control circuit B3 starts to control the resonant capacitance is made larger than the voltage level at which the regulator circuit B16 starts to suppress the output voltage. Adjustment of circuit characteristics is facilitated, which is preferable.
  • a force P-type MOS transistor in which the resonance capacitance control circuit is configured by an N-type MOS transistor may be used.
  • the location of the capacitors C1 and C2 for controlling the resonant capacitance is not limited to the semiconductor integrated circuit device B2, but may be arranged other than the semiconductor integrated circuit device B2, and moreover, In addition to the capacitors C1 and C2, other capacitors can be connected between the antenna terminals.
  • the present invention is suitable for application to non-contact electronic devices typified by IC cards and IC tags.

Abstract

There has been problems of deterioration of performance, accuracy and the like of circuits mounted inside other than a noncontact type electronic device, due to heat generated by the noncontact type electronic device by excessive power supplied thereto. A capacitor (C1) and a capacitor (C2) are connected in series to the terminals on the both sides of an antenna (L0) mounted on the noncontact type electronic device (B1), a charge/discharge control circuit (B14) is connected to the contact point of the capacitor (C1) and the capacitor (C2), the resonance frequency is controlled by changing the charges accumulated in the capacitor (C1) and the capacitor (C2), and excessive power supply is suppressed.

Description

非接触型電子装置及びそれに搭載される半導体集積回路装置 技術分野  Non-contact electronic device and semiconductor integrated circuit device mounted thereon
[0001] 本発明は、非接触型電子装置の技術に関し、特に、 ICカードや ICタグを代表とす る非接触型電子装置とそれに搭載される半導体集積回路装置に適用して有効な技 術に関するものである。  TECHNICAL FIELD [0001] The present invention relates to a technology of a non-contact type electronic device, and in particular, a technology effective when applied to a non-contact type electronic device typified by an IC card or an IC tag and a semiconductor integrated circuit device mounted thereon. It is about.
背景技術  Background art
[0002] 本発明者が検討した技術として、例えば、 ICカード、 ICタグ、 RFID、携帯電話等の 非接触型電子装置においては、以下の技術が考えられる。  [0002] As technologies studied by the present inventors, for example, the following technologies can be considered in non-contact type electronic devices such as IC cards, IC tags, RFIDs, and mobile phones.
[0003] 内部に CPUやメモリ等の機能を有した半導体集積回路装置を備える非接触型電 子装置が、交通や物流等の分野で普及しつつある。特に限定はされないが、上記非 接触型電子装置はバッテリ等の電源を持たず、アンテナで受けた電磁波から電源を 生成して動作する。上記非接触型電子装置は、リーダ'ライタ (質問器)から電磁波を 変調して送られるデータを受信し、更に、受信したデータを CPUやメモリ等によって 信号処理を行う。その結果、得られたデータに応じて、アンテナ端子間の負荷を変動 させることによりアンテナで受信している電磁波を変調し、そのデータをリーダ 'ライタ に送信する。  [0003] Non-contact type electronic devices having a semiconductor integrated circuit device having functions such as a CPU and a memory inside are becoming widespread in the fields of transportation and logistics. Although not particularly limited, the contactless electronic device does not have a power source such as a battery, and operates by generating power from electromagnetic waves received by an antenna. The non-contact electronic device receives data transmitted by modulating electromagnetic waves from a reader / writer (interrogator), and further performs signal processing on the received data by a CPU, a memory, or the like. As a result, the electromagnetic wave received by the antenna is modulated by changing the load between the antenna terminals according to the obtained data, and the data is transmitted to the reader / writer.
[0004] このような非接触型電子装置において、アンテナ端子間に容量と可変容量素子を 直列接続し、可変容量素子に制御電圧を印加することで共振周波数を制御し、非接 触型電子装置に供給される電力を抑制する技術がある (例えば特許文献 1参照)。  In such a contactless electronic device, a capacitor and a variable capacitive element are connected in series between the antenna terminals, and a resonance voltage is controlled by applying a control voltage to the variable capacitive element, whereby the contactless electronic device There is a technique for suppressing the power supplied to the battery (see, for example, Patent Document 1).
[0005] また、非接触型電子装置に供給される電力に応じて、アンテナ端子間に接続される 容量を論理的に切替えることで共振周波数を変化させ、非接触型電子装置に供給さ れる電力を抑制する技術がある(例えば特許文献 2参照)。更に、特許文献 2には、 複数の容量を切替えることで、段階的に共振周波数を変化させることが記載されてい る。  [0005] In addition, according to the power supplied to the non-contact type electronic device, the resonance frequency is changed by logically switching the capacitance connected between the antenna terminals, and the power supplied to the non-contact type electronic device. There is a technique for suppressing the above (for example, see Patent Document 2). Furthermore, Patent Document 2 describes that the resonance frequency is changed stepwise by switching a plurality of capacitors.
特許文献 1:特開平 9— 147070号公報  Patent Document 1: Japanese Patent Laid-Open No. 9-147070
特許文献 2:特開 2005 - 204493号公報 発明の開示 Patent Document 2: JP 2005-204493 A Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] ところで、前記のような非接触型電子装置の技術にっ 、て、本発明者が検討した結 果、以下のようなことが明ら力となった。  [0006] By the way, as a result of studies made by the inventor of the non-contact electronic device as described above, the following has become apparent.
[0007] 近年では、アンテナで受けた電磁波力 電源を生成して動作する非接触型電子装 置に、温度等を検知するセンサ回路を搭載し、リーダ'ライタカゝら送信されたデータに 応じてセンサ回路を測定させ、測定データを上記変調動作によって、リーダ'ライタに 送信することができるものがある。  [0007] In recent years, a sensor circuit that detects a temperature or the like is mounted on a non-contact electronic device that operates by generating an electromagnetic force power source received by an antenna, and according to data transmitted from a reader / writer. Some sensors measure the sensor circuit and can transmit the measurement data to the reader / writer by the above modulation operation.
[0008] 非接触型電子装置は、リーダ'ライタ力も供給される電磁波を整流 ·平滑することで 電源を生成して動作する。一般的に、リーダ'ライタと非接触型電子装置の間の距離 によって、非接触型電子装置に供給される電力が変化するため、非接触型電子装置 の自己発熱の程度が変化する。  [0008] A non-contact type electronic device operates by generating a power source by rectifying and smoothing an electromagnetic wave to which a reader / writer force is also supplied. Generally, since the electric power supplied to the non-contact type electronic device changes depending on the distance between the reader / writer and the non-contact type electronic device, the degree of self-heating of the non-contact type electronic device changes.
[0009] 例えば、このような非接触型電子装置に温度センサ回路を搭載した場合、通信距 離に応じて自己発熱量が変化してしまうため、温度センサ回路が測定する温度に誤 差が生じてしま!/、、正 、測定結果が得られな 、と 、う問題があった。  [0009] For example, when a temperature sensor circuit is mounted on such a non-contact type electronic device, the amount of self-heating is changed according to the communication distance, so that an error occurs in the temperature measured by the temperature sensor circuit. There was a problem that the measurement results could not be obtained.
[0010] そこで、本発明者は、非接触型電子装置が受信する電力に応じて共振周波数を制 御することで、非接触型電子装置に過大な電力が供給されないようにする技術を検 討するに至った。  [0010] In view of this, the present inventors have studied a technique for preventing excessive power from being supplied to the non-contact electronic device by controlling the resonance frequency according to the power received by the non-contact electronic device. It came to do.
[0011] しかし、可変容量素子を用いて共振周波数を変化させる場合、何らかの手段を用 V、て、共振周波数を十分に変化させることが可能な可変容量素子を非接触型電子 装置に搭載する必要がある。非接触型電子装置に搭載される半導体集積回路装置 の中に、可変容量素子を配置することが好ましいが、通常、論理回路等を搭載する のに利用されている半導体製造プロセスでは、共振周波数を十分に変化させること ができる可変容量素子を搭載して 、な 、場合があった。  [0011] However, when changing the resonance frequency using a variable capacitance element, it is necessary to use some means V and mount the variable capacitance element that can sufficiently change the resonance frequency in the non-contact type electronic device. There is. Although it is preferable to arrange a variable capacitance element in a semiconductor integrated circuit device mounted in a non-contact type electronic device, the resonance frequency is usually set in a semiconductor manufacturing process used for mounting a logic circuit or the like. In some cases, a variable capacitance element that can be changed sufficiently was installed.
[0012] また、共振容量を論理的に切替える場合、非接触型電子装置が受信している電力 を検知し、受信電力レベルを 2値化する必要がある。例えば、非接触型電子装置が 受信している電力が所定のレベルを上回っていた場合、共振容量を論理的に切替 える。しかし、共振容量を切替えた結果、非接触型電子装置の受信電力が所定のレ ベルを下回ってしまった場合、共振容量を元に戻すように制御されるが、再び受信電 カレベルが所定のレベルを上回るため、共振容量が切替えられる。このように、受信 電力レベルが共振容量を切替えるレベル付近であるときには、共振容量の切替え動 作が繰り返され、非接触型電子装置が受信する電力が安定しないという場合があつ た。 [0012] In addition, when the resonant capacitance is logically switched, it is necessary to detect the power received by the non-contact electronic device and binarize the received power level. For example, when the electric power received by the non-contact type electronic device exceeds a predetermined level, the resonance capacitance is logically switched. However, as a result of switching the resonance capacitance, the received power of the contactless electronic device is reduced to a predetermined level. If it falls below the bell, the resonance capacity is controlled to return to the original value. However, since the received power level again exceeds the predetermined level, the resonance capacity is switched. As described above, when the received power level is close to the level at which the resonance capacitor is switched, the switching operation of the resonance capacitor is repeated, and the power received by the non-contact type electronic device may not be stable.
[0013] 以上のように、非接触型電子装置に供給される過大な電力によって非接触型電子 装置が発熱することを抑制するための共振周波数制御手段はあったが、一般的な半 導体集積回路装置に搭載する上での制限や、境界条件における安定性が劣化する という問題があった。  [0013] As described above, although there has been a resonance frequency control means for suppressing the non-contact type electronic device from generating heat due to excessive electric power supplied to the non-contact type electronic device, the general semiconductor integration There were problems such as restrictions on mounting on circuit devices and deterioration of stability in boundary conditions.
[0014] そこで、本発明の目的は、非接触型電子装置が受信する電力を安定して制御する ことが可能な回路技術を提供することにある。  Accordingly, an object of the present invention is to provide a circuit technique capable of stably controlling the power received by the non-contact type electronic device.
[0015] 本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図 面から明らかになるであろう。 [0015] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
課題を解決するための手段  Means for solving the problem
[0016] 本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 次のとおりである。 [0016] Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0017] すなわち、本発明に係る非接触型電子装置及びそれに搭載される半導体集積回 路装置は、共振容量制御回路を具備している。前記共振容量制御回路は、アンテナ が接続される第 1のアンテナ端子と第 2のアンテナ端子の間に、第 1の容量と第 2の 容量が直列接続され、前記第 1の容量と前記第 2の容量の接続点に充放電制御回 路が接続される。そして、前記充放電制御回路は、前記第 1のアンテナ端子の電位 が前記第 2のアンテナ端子の電位より高いときには、前記第 1の容量に蓄積される電 荷を制御し、前記第 2のアンテナ端子の電位が前記第 1のアンテナ端子の電位より 高いときには、前記第 2の容量に蓄積される電荷を制御することで、前記第 1のアン テナ端子と前記第 2のアンテナ端子の間の共振容量値を制御する。  That is, the non-contact electronic device according to the present invention and the semiconductor integrated circuit device mounted thereon include a resonance capacitance control circuit. In the resonant capacitance control circuit, a first capacitor and a second capacitor are connected in series between a first antenna terminal and a second antenna terminal to which an antenna is connected, and the first capacitor and the second capacitor are connected. The charge / discharge control circuit is connected to the connection point of the capacity. The charge / discharge control circuit controls the charge accumulated in the first capacitor when the potential of the first antenna terminal is higher than the potential of the second antenna terminal, and controls the second antenna. When the potential of the terminal is higher than the potential of the first antenna terminal, the resonance between the first antenna terminal and the second antenna terminal is controlled by controlling the charge accumulated in the second capacitor. Control the capacitance value.
発明の効果  The invention's effect
[0018] 本願において開示される発明のうち、代表的なものによって得られる効果を簡単に 説明すれば、以下のとおりである。 [0019] すなわち、アンテナと共振容量制御回路によって構成される共振回路の共振周波 数を制御し、整流回路への過剰な電力供給を抑制することが可能になる。 [0018] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to control the resonance frequency of the resonance circuit constituted by the antenna and the resonance capacitance control circuit, and to suppress excessive power supply to the rectifier circuit.
図面の簡単な説明  Brief Description of Drawings
[0020] [図 1]本発明の実施の形態 1に係る非接触型電子装置及び半導体集積回路装置の 基本構成を示すブロック図である。  FIG. 1 is a block diagram showing a basic configuration of a contactless electronic device and a semiconductor integrated circuit device according to a first embodiment of the present invention.
[図 2]本発明の実施の形態 1に係る非接触型電子装置及び半導体集積回路装置と、 配線基板と、リーダ.ライタの構成を示す斜視図である。  FIG. 2 is a perspective view showing configurations of a non-contact electronic device and a semiconductor integrated circuit device, a wiring board, and a reader / writer according to Embodiment 1 of the present invention.
[図 3]本発明の実施の形態 1に係る半導体集積回路装置に搭載される共振容量制御 回路の構成例を示す回路図である。  FIG. 3 is a circuit diagram showing a configuration example of a resonance capacitance control circuit mounted on the semiconductor integrated circuit device according to the first embodiment of the present invention.
圆 4]本発明の実施の形態 2に係る半導体集積回路装置に搭載される共振容量制御 回路の構成例を示す回路図である。  IV] is a circuit diagram showing a configuration example of a resonance capacitance control circuit mounted on the semiconductor integrated circuit device according to the second embodiment of the present invention.
[図 5]図 4に示した共振容量制御回路の各端子電圧の動作波形を示す図である。  FIG. 5 is a diagram showing an operation waveform of each terminal voltage of the resonance capacitance control circuit shown in FIG.
[図 6]本発明の実施の形態 3に係る半導体集積回路装置に搭載される共振容量制御 回路の構成例を示す回路図である。  FIG. 6 is a circuit diagram showing a configuration example of a resonant capacitance control circuit mounted on a semiconductor integrated circuit device according to a third embodiment of the present invention.
[図 7]本発明の実施の形態 4に係る半導体集積回路装置に搭載される共振容量制御 回路の構成例を示す回路図である。  FIG. 7 is a circuit diagram showing a configuration example of a resonant capacitance control circuit mounted on a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
[図 8]本発明の実施の形態 5に係る半導体集積回路装置に搭載される共振容量制御 回路及び整流平滑回路の構成例を示すブロック図である。  FIG. 8 is a block diagram showing a configuration example of a resonant capacitance control circuit and a rectifying / smoothing circuit mounted on a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0021] 以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態 を説明するための全図において、同一部材には原則として同一の符号を付し、その 繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[0022] (実施の形態 1) [0022] (Embodiment 1)
図 1は、本発明の実施の形態 1に係る非接触型電子装置及び半導体集積回路装 置の基本構成を示すブロック図である。  FIG. 1 is a block diagram showing a basic configuration of a non-contact electronic device and a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
[0023] まず、図 1により、本実施の形態 1による非接触型電子装置及び半導体集積回路装 置の構成の一例を説明する。本実施の形態 1の非接触型電子装置は、例えば、 IC力 ード、 ICタグ、 RFID、携帯電話などである。 [0024] 図 1において、 B1は非接触型電子装置、 B2は非接触型電子装置 B1に搭載される 半導体集積回路装置、 LOは非接触型電子装置 B1に搭載されるアンテナである。半 導体集積回路装置 B2は、共振容量制御回路 B3、整流平滑回路 B4、内部回路 B5 を有し、アンテナ LOを接続するためのアンテナ端子 LA及び LBを有している。図 1で は、アンテナ LOには共振容量 COが並列接続されている力 共振容量制御回路 B3 や寄生容量等を考慮して調整されるため、必ずしも接続されるものではない。 First, an example of the configuration of the non-contact electronic device and the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIG. The contactless electronic device according to the first embodiment is, for example, an IC force card, an IC tag, an RFID, or a mobile phone. In FIG. 1, B1 is a non-contact type electronic device, B2 is a semiconductor integrated circuit device mounted on the non-contact type electronic device B1, and LO is an antenna mounted on the non-contact type electronic device B1. The semiconductor integrated circuit device B2 has a resonance capacitance control circuit B3, a rectifying / smoothing circuit B4, and an internal circuit B5, and has antenna terminals LA and LB for connecting the antenna LO. In Fig. 1, the antenna LO is not necessarily connected because it is adjusted in consideration of the force resonance capacitance control circuit B3 in which the resonance capacitance CO is connected in parallel and the parasitic capacitance.
[0025] 図 2に、非接触型電子装置 B1の構造例を示す。図 2は、 ICカードの例を示すが、こ れに限定されるものではな 、。  FIG. 2 shows a structural example of the non-contact type electronic device B1. Figure 2 shows an example of an IC card, but this is not a limitation.
[0026] 非接触型電子装置 B1は、榭脂モールドされたプリント基板 B10によってカードの形 態を成す。外部のリーダ'ライタ B13からの電磁波を受けるアンテナ LOは、プリント基 板 B10の配線により形成される渦巻き状のコイル B11によって構成される。 1個の IC チップ B12で構成された半導体集積回路装置 B2には、 ICチップ B12にアンテナ LO となるコイル B 11が接続される。リーダ ·ライタ B13からの電磁波を受けたアンテナ LO (コイル B11)は、アンテナ端子 LA及び LBに高周波の交流信号を出力する。この交 流信号は、情報信号 (データ)によって部分的に変調されている。  [0026] The non-contact type electronic device B1 is in the form of a card by a resin-molded printed circuit board B10. The antenna LO that receives electromagnetic waves from the external reader / writer B13 is constituted by a spiral coil B11 formed by the wiring of the printed board B10. In the semiconductor integrated circuit device B2 composed of one IC chip B12, a coil B11 serving as an antenna LO is connected to the IC chip B12. The antenna LO (coil B11) receiving the electromagnetic wave from the reader / writer B13 outputs a high-frequency AC signal to the antenna terminals LA and LB. This AC signal is partially modulated by an information signal (data).
[0027] 本発明は典型的には外部と入出力のための端子を非接触型電子装置表面に持た ない非接触型電子装置に適用される。勿論、非接触インターフェースと入出力端子 の両方を持つデュアルタイプ非接触型電子装置に用いても良い。また、特に限定は されないが、半導体集積回路装置 B2は、公知の半導体集積回路装置の製造技術 によって、単結晶シリコン等のような 1個の半導体基板上に形成される。  [0027] The present invention is typically applied to a non-contact type electronic device having no external input / output terminal on the surface of the non-contact type electronic device. Of course, you may use for the dual type non-contact type electronic device which has both a non-contact interface and an input / output terminal. Although not particularly limited, the semiconductor integrated circuit device B2 is formed on a single semiconductor substrate such as single crystal silicon or the like by a known semiconductor integrated circuit device manufacturing technique.
[0028] 図 1において、共振容量制御回路 B3は、アンテナ端子間に供給される電力に応じ て共振容量を制御することで、アンテナ LO、共振容量制御回路 B3、共振容量 CO〖こ よって構成される共振回路の共振周波数を変化させる。  In FIG. 1, the resonance capacitance control circuit B3 is configured by the antenna LO, the resonance capacitance control circuit B3, and the resonance capacitance CO by controlling the resonance capacitance according to the power supplied between the antenna terminals. The resonance frequency of the resonance circuit is changed.
[0029] また、整流平滑回路 B4は、整流回路、平滑容量から構成され、レギユレータ機能を 有しても良い。レギユレータ機能は、整流回路及び平滑容量によって生成される電圧 が所定の電圧レベルを超えないように制御する。整流平滑回路 B4の出力電圧は、 内部回路 B5の電源電圧 VDDとして供給される。  [0029] The rectifying / smoothing circuit B4 includes a rectifying circuit and a smoothing capacitor, and may have a regulator function. The regulator function controls so that the voltage generated by the rectifier circuit and the smoothing capacitor does not exceed a predetermined voltage level. The output voltage of the rectifying / smoothing circuit B4 is supplied as the power supply voltage VDD of the internal circuit B5.
[0030] 内部回路 B5は、受信回路 B6、送信回路 B7、制御部 B8、メモリ B9から構成される 。受信回路 B6は、非接触型電子装置 B1に備えられるアンテナ LOによって受信され た交流信号に重畳された情報信号を復調してディジタルの情報信号として制御部 B 8に供給する。送信回路 B7は、制御部 B8から出力されるディジタル信号の情報信号 を受け、アンテナ LOが受信している交流信号を同情報信号によって変調する。リー ダ'ライタ B13 (図 2参照)は、アンテナ LOからの電磁波の反射が上記変調によって変 化することを受けて、制御部 B8からの情報信号を受信する。メモリ B9は、制御部 B8 との間で復調された情報データや送信データの記録などに利用される。 [0030] The internal circuit B5 includes a receiving circuit B6, a transmitting circuit B7, a control unit B8, and a memory B9. . The reception circuit B6 demodulates the information signal superimposed on the AC signal received by the antenna LO provided in the non-contact type electronic device B1, and supplies it to the control unit B8 as a digital information signal. The transmission circuit B7 receives the information signal of the digital signal output from the control unit B8, and modulates the AC signal received by the antenna LO with the information signal. The reader / writer B13 (see FIG. 2) receives the information signal from the control unit B8 in response to the reflection of the electromagnetic wave from the antenna LO being changed by the modulation. The memory B9 is used for recording information data and transmission data demodulated with the control unit B8.
[0031] 図 3は、本発明に係る半導体集積回路装置 B2に搭載される共振容量制御回路 B3 の基本構成図である。 FIG. 3 is a basic configuration diagram of a resonance capacitance control circuit B3 mounted on the semiconductor integrated circuit device B2 according to the present invention.
[0032] 半導体集積回路装置 B2において、アンテナ端子 LA (第 1のアンテナ端子)及びァ ンテナ端子 LB (第 2のアンテナ端子)の間に共振容量制御回路 B3が接続される。共 振容量制御回路 B3は、非接触型電子装置 B1に搭載されるアンテナを接続するアン テナ端子 LA及び LBの間に、容量 C1 (第 1の容量)及び容量 C2 (第 2の容量)を直 列接続し、容量 C1と C2の接続点とアンテナ端子 LA及び LBに接続される充放電制 御回路 B14が接続される。充放電制御回路 B14は、アンテナ端子 LA及び LBの間 に直列接続された可変抵抗 R1及び R2によって構成され、可変抵抗 R1と R2の接続 点と、容量 C1と C2の接続点とが接続される。また、半導体集積回路装置 B2に搭載 される整流平滑回路 B4がアンテナ端子 LA及び LBに接続され、出力端子 OUTとグ ランド端子の間に電源電圧 VDDが出力される。  In the semiconductor integrated circuit device B2, the resonance capacitance control circuit B3 is connected between the antenna terminal LA (first antenna terminal) and the antenna terminal LB (second antenna terminal). The resonant capacity control circuit B3 has a capacity C1 (first capacity) and a capacity C2 (second capacity) between the antenna terminals LA and LB that connect the antenna mounted on the non-contact type electronic device B1. Connected in series, the connection point between capacitors C1 and C2 and charge / discharge control circuit B14 connected to antenna terminals LA and LB are connected. The charge / discharge control circuit B14 includes variable resistors R1 and R2 connected in series between the antenna terminals LA and LB, and a connection point between the variable resistors R1 and R2 and a connection point between the capacitors C1 and C2 are connected. . A rectifying / smoothing circuit B4 mounted on the semiconductor integrated circuit device B2 is connected to the antenna terminals LA and LB, and the power supply voltage VDD is output between the output terminal OUT and the ground terminal.
[0033] 充放電制御回路 B14は、アンテナ端子 LA及び LBの電圧が所定のレベルより低い 場合には、容量 C1及び C2に並列接続される抵抗 R1及び R2の抵抗を大きくなるよう に制御することで、抵抗 R1及び R2にほとんど電流が流れないように制御される。これ により、アンテナ端子間には容量 C1及び C2が直列接続された状態に近似でき、容 量 C1または C2の半分の容量値の容量が接続されている状態になる。なお、以下に おいて、これに限定されるものではないが、容量 C1と容量 C2の容量値は等しいもの と仮定する。  [0033] When the voltage at the antenna terminals LA and LB is lower than a predetermined level, the charge / discharge control circuit B14 controls the resistances of the resistors R1 and R2 connected in parallel to the capacitors C1 and C2 so as to increase. Thus, the current is controlled so as to hardly flow through the resistors R1 and R2. As a result, it can be approximated that the capacitors C1 and C2 are connected in series between the antenna terminals, and a capacitor having a capacitance value half that of the capacitor C1 or C2 is connected. In the following, although not limited to this, it is assumed that the capacitance values of the capacitors C1 and C2 are equal.
[0034] 一方、充放電制御回路 B14は、アンテナ端子 LAの電位力 アンテナ端子 LBの電 位より高ぐアンテナ端子間の電圧が所定の電圧レベルより高い場合には、アンテナ 端子間の電圧レベルに応じて、容量 C2に並列接続された抵抗 R2を小さくするように 制御される。また、アンテナ端子 LBの電位力 アンテナ端子 LAの電位より高ぐアン テナ端子間の電圧が所定の電圧レベルより高い場合には、アンテナ端子間の電圧レ ベルに応じて、容量 C1に並列接続された抵抗 R1を小さくするように制御される。 [0034] On the other hand, when the voltage between the antenna terminals higher than the potential of the antenna terminal LA is higher than a predetermined voltage level, the charge / discharge control circuit B14 The resistance R2 connected in parallel with the capacitor C2 is controlled to be small according to the voltage level between the terminals. In addition, when the voltage between the antenna terminals, which is higher than the potential of the antenna terminal LA, is higher than a predetermined voltage level, it is connected in parallel to the capacitor C1 according to the voltage level between the antenna terminals. The resistance R1 is controlled to be small.
[0035] すなわち、アンテナ端子 LAの電位がアンテナ端子 LBの電位より高いときには、容 量 C 1に蓄積される電荷を制御し、アンテナ端子 LBの電位がアンテナ端子 LAの電 位より高いときには、容量 C2に蓄積される電荷を制御することで、アンテナ端子 LAと アンテナ端子 LBの間の共振容量値を制御する。  That is, when the potential of the antenna terminal LA is higher than the potential of the antenna terminal LB, the charge accumulated in the capacitor C 1 is controlled, and when the potential of the antenna terminal LB is higher than the potential of the antenna terminal LA, the capacitance By controlling the charge stored in C2, the resonant capacitance between antenna terminal LA and antenna terminal LB is controlled.
[0036] これにより、アンテナ端子間の電圧レベル力 所定の電圧レベルより大きい場合に は、容量 C1及び C2に蓄積される電荷が制御され、アンテナ端子間に接続される容 量が変化する。例えば、抵抗 R1または R2が極めて小さい抵抗値に制御された場合 、アンテナ端子間には容量 C2またはじ 1と同等の容量値の容量が接続された状態に 近似できること〖こなる。  [0036] Thereby, when the voltage level force between the antenna terminals is larger than the predetermined voltage level, the charges accumulated in the capacitors C1 and C2 are controlled, and the capacitance connected between the antenna terminals changes. For example, when the resistance R1 or R2 is controlled to a very small resistance value, it can be approximated to a state where a capacitance having a capacitance value equivalent to the capacitance C2 or the same capacitance 1 is connected between the antenna terminals.
[0037] 上述の動作により、アンテナ端子間に発生する電圧レベルに応じて、共振容量を 容量 C1の半分の容量値から、容量 C1と同等の容量値までの範囲で制御でき、アン テナ LOと共振容量制御回路 B3によって構成される共振回路の共振周波数が制御 できる。  [0037] According to the above-described operation, the resonance capacitance can be controlled in a range from a capacitance value half of the capacitance C1 to a capacitance value equivalent to the capacitance C1, according to the voltage level generated between the antenna terminals. The resonance frequency of the resonance circuit configured by the resonance capacitance control circuit B3 can be controlled.
[0038] 例えば、容量 C1及び C2のそれぞれの容量値を、アンテナ LOに供給される電磁波 の周波数に共振する容量値の 2倍に設定すれば、アンテナ端子間に発生する電圧 レベルが所定の電圧レベルより小さい場合は、共振することで最大電力を受信でき、 アンテナ端子間に発生する電圧レベルが所定の電圧レベルより大きい場合は、アン テナ端子の共振容量を大きくすることで、共振周波数が低くなるように制御され、整 流平滑回路 B4に供給される電力を小さくすることができる。  [0038] For example, if the capacitance values of the capacitors C1 and C2 are set to twice the capacitance value that resonates with the frequency of the electromagnetic wave supplied to the antenna LO, the voltage level generated between the antenna terminals becomes a predetermined voltage. If the voltage level is lower than the level, the maximum power can be received by resonating.If the voltage level generated between the antenna terminals is higher than the specified voltage level, the resonance frequency can be lowered by increasing the resonance capacity of the antenna terminal. The electric power supplied to the rectifying / smoothing circuit B4 can be reduced.
[0039] これにより、整流平滑回路 B4に過大な電力が供給されることがなくなり、チップの発 熱を小さくすることが可能になる。更には、アンテナ端子間に発生する電圧振幅を小 さく制御することが容易になるため、整流平滑回路 B4を構成する素子の耐圧を保護 することち容易〖こなる。  [0039] As a result, excessive power is not supplied to the rectifying / smoothing circuit B4, and the heat generation of the chip can be reduced. Furthermore, since it becomes easy to control the voltage amplitude generated between the antenna terminals to be small, it is easy to protect the withstand voltage of the elements constituting the rectifying and smoothing circuit B4.
[0040] 以上、充放電制御回路 B14は、アンテナ端子間に接続された容量 C1及び C2にお いて、低電位側の容量に並列接続された抵抗を制御することで、アンテナ端子間の 共振容量を制御する手段を例に説明したが、高電位側の容量に並列接続された抵 抗を制御しても、同様の効果を得ることができる。 [0040] As described above, the charge / discharge control circuit B14 is connected to the capacitors C1 and C2 connected between the antenna terminals. In this example, the resonance capacitance between the antenna terminals is controlled by controlling the resistance connected in parallel to the low-potential side capacitor, but the resistance connected in parallel to the high-potential side capacitance is controlled. However, the same effect can be obtained.
[0041] (実施の形態 2)  [0041] (Embodiment 2)
図 4は、本発明に係る半導体集積回路装置 B2に搭載される共振容量制御回路 B3 の他の一実施例を示す回路構成図である。これは、図 3に示した共振容量制御回路 B3に搭載される充放電制御回路 B14の他の回路構成例を示したものである。  FIG. 4 is a circuit configuration diagram showing another embodiment of the resonance capacitance control circuit B3 mounted in the semiconductor integrated circuit device B2 according to the present invention. This shows another circuit configuration example of the charge / discharge control circuit B14 mounted on the resonance capacitance control circuit B3 shown in FIG.
[0042] アンテナ端子 LA及び LBの間に接続される共振容量制御回路 B3は、非接触型電 子装置 B1に搭載されるアンテナを接続するアンテナ端子 LA及び LBの間に、容量 C 1及び C2を直列接続し、容量 C1及び C2の接続点とアンテナ端子 LA及び LBに充 放電制御回路 B14が接続される。充放電制御回路 B14は、ゲート端子をアンテナ端 子 LBに接続した MOSトランジスタ Ml (第 1の MOSトランジスタ)とゲート端子をアン テナ端子 LAに接続した MOSトランジスタ M2 (第 2の MOSトランジスタ)を直列接続 し、容量 C1及び C2の接続点と MOSトランジスタ Ml及び M2の接続点の間に、可変 抵抗 R3 (可変抵抗素子)が接続された構成である。  [0042] The resonant capacitance control circuit B3 connected between the antenna terminals LA and LB has capacitors C1 and C2 between the antenna terminals LA and LB that connect the antenna mounted on the non-contact type electronic device B1. Are connected in series, and the charge / discharge control circuit B14 is connected to the connection point of the capacitors C1 and C2 and the antenna terminals LA and LB. The charge / discharge control circuit B14 has a MOS transistor Ml (first MOS transistor) whose gate terminal is connected to the antenna terminal LB and a MOS transistor M2 (second MOS transistor) whose gate terminal is connected to the antenna terminal LA. In this configuration, a variable resistor R3 (variable resistor element) is connected between the connection point of the capacitors C1 and C2 and the connection point of the MOS transistors Ml and M2.
[0043] 図 5には、図 4における各端子電圧の動作波形の一例を示す。これは、 MOSトラン ジスタ Ml及び M2の接続点の電位を基準とした各端子電圧の動作波形を示してお り、 W0は MOSトランジスタ Ml及び M2の接続点の電圧波形、 W1はアンテナ端子 L Aの電圧波形、 W2はアンテナ端子 LBの電圧波形、 W3及び W4は容量 C1及び C2 の接続点の電圧波形を示し、 W3は可変抵抗 R3が極めて大き 、抵抗値の場合の電 圧波形、 W4は可変抵抗 R3が極めて小さ 、抵抗値の場合の電圧波形を示して!/ヽる。  FIG. 5 shows an example of the operation waveform of each terminal voltage in FIG. This shows the operating waveform of each terminal voltage based on the potential at the connection point of the MOS transistors Ml and M2, W0 is the voltage waveform at the connection point of the MOS transistors Ml and M2, and W1 is the antenna terminal LA. Voltage waveform, W2 is the voltage waveform at the antenna terminal LB, W3 and W4 are the voltage waveforms at the connection point of the capacitors C1 and C2, W3 is the voltage waveform when the variable resistance R3 is extremely large, and the resistance value, W4 is variable Show the voltage waveform when resistance R3 is very small and resistance! / Speak.
[0044] アンテナ端子 LAの電位がアンテナ端子 LBの電位より高い場合に、 MOSトランジ スタ M2がオンし、 MOSトランジスタ Mlがオフする。また、アンテナ端子 LBの電位が アンテナ端子 LAの電位より高い場合に、 MOSトランジスタ Mlがオンし、 MOSトラン ジスタ M2がオフする。  [0044] When the potential of the antenna terminal LA is higher than the potential of the antenna terminal LB, the MOS transistor M2 is turned on and the MOS transistor Ml is turned off. Also, when the potential of the antenna terminal LB is higher than the potential of the antenna terminal LA, the MOS transistor Ml is turned on and the MOS transistor M2 is turned off.
[0045] 以上の MOSトランジスタ Ml及び M2の動作により、 MOSトランジスタ Ml及び M2 の接続点は、低電位側のアンテナ端子 LAまたは LBの電位と等しくなるように制御さ れるため、図 5の W0、 Wl、 W2の電圧波形となる。 [0046] したがって、可変抵抗 R3は、低電位側の容量 C1または C2と並列接続された状態 で動作し、可変抵抗 R3が極めて大きい抵抗値である場合には、可変抵抗 R3は無視 できるため、 W3に示すように、容量 C1及び C2の接続点は、アンテナ端子間電圧の 半分の電圧になる。逆に、可変抵抗 R3が極めて小さい抵抗値である場合には、可変 抵抗 R3の両端が短絡された状態と等価になるため、 W4に示すように、容量 C1及び C2の接続点は、 WOとほぼ等しくなり、アンテナ端子間に容量 C1または C2が接続さ れた状態に近似できる。これは、可変抵抗 R3の抵抗値に応じて、共振容量を容量 C 1の半分の容量値から、容量 C1と同等の容量値までの範囲で制御でき、アンテナ LO と共振容量制御回路 B3によって構成される共振回路の共振周波数が制御できること を示している。 [0045] By the operation of the MOS transistors Ml and M2, the connection point of the MOS transistors Ml and M2 is controlled to be equal to the potential of the antenna terminal LA or LB on the low potential side. The voltage waveform is Wl and W2. Therefore, the variable resistor R3 operates in a state where it is connected in parallel with the low-potential side capacitor C1 or C2, and when the variable resistor R3 has a very large resistance value, the variable resistor R3 can be ignored. As shown in W3, the connection point between capacitors C1 and C2 is half the voltage between antenna terminals. Conversely, when the variable resistor R3 has a very small resistance value, it is equivalent to a state in which both ends of the variable resistor R3 are short-circuited.As shown in W4, the connection point of the capacitors C1 and C2 is WO and It is almost equal and can be approximated to the state where the capacitor C1 or C2 is connected between the antenna terminals. According to the resistance value of the variable resistor R3, the resonance capacitance can be controlled in the range from half the capacitance value of the capacitance C1 to the capacitance value equivalent to the capacitance C1, and is configured by the antenna LO and the resonance capacitance control circuit B3 This shows that the resonant frequency of the resonant circuit can be controlled.
[0047] また、図 3に示した回路では 2つの可変抵抗が必要であつたが、可変抵抗を共通化 することが可能になり、可変抵抗によるバラツキを低減することが可能になる。ここで、 MOSトランジスタ Ml及び M2のしきい値電圧なども特性誤差の一要因となり得るが 、 MOSトランジスタ Ml及び M2はオン ·オフ動作であるため、共振容量特性に与え る影響は  [0047] Although the circuit shown in FIG. 3 requires two variable resistors, it becomes possible to share the variable resistors and reduce variations due to the variable resistors. Here, the threshold voltages of the MOS transistors Ml and M2 can also contribute to the characteristic error. However, since the MOS transistors Ml and M2 are turned on / off, the influence on the resonant capacitance characteristics is not affected.
極めて小さい。  Very small.
[0048] (実施の形態 3)  [0048] (Embodiment 3)
図 6は、本発明に係る半導体集積回路装置 B2に搭載される共振容量制御回路 B3 の他の一実施例を示す回路構成図である。これは、図 4に示した共振容量制御回路 B3に搭載される充放電制御回路 B14を構成する可変抵抗 R3を MOSトランジスタで 構成した例である。  FIG. 6 is a circuit configuration diagram showing another embodiment of the resonance capacitance control circuit B3 mounted on the semiconductor integrated circuit device B2 according to the present invention. This is an example in which the variable resistor R3 constituting the charge / discharge control circuit B14 mounted on the resonance capacitance control circuit B3 shown in FIG. 4 is configured by a MOS transistor.
[0049] アンテナ端子 LA及び LBの間に接続される共振容量制御回路 B3は、非接触型電 子装置 B1に搭載されるアンテナを接続するアンテナ端子 LA及び LBの間に、容量 C 1及び C2を直列接続し、容量 C1及び C2の接続点とアンテナ端子 LA及び LBに接 続される充放電制御回路 B14が接続される。  [0049] The resonant capacitance control circuit B3 connected between the antenna terminals LA and LB has capacitors C1 and C2 between the antenna terminals LA and LB that connect the antenna mounted on the non-contact type electronic device B1. Are connected in series, and the connection point of the capacitors C1 and C2 and the charge / discharge control circuit B14 connected to the antenna terminals LA and LB are connected.
[0050] また、充放電制御回路 B14は、ゲート端子をアンテナ端子 LBに接続した MOSトラ ンジスタ Mlとゲート端子をアンテナ端子 LAに接続した MOSトランジスタ M2を直列 接続し、容量 C1及び C2の接続点と MOSトランジスタ Ml及び M2の接続点の間に、 MOSトランジスタ M3 (可変抵抗素子、第 7の MOSトランジスタ)を接続し、アンテナ 端子 LA及び LBの間には電圧検出回路 B15が接続される。このとき、 MOSトランジ スタ Ml及び M2の接続点をグランド端子に接続している。 [0050] Further, the charge / discharge control circuit B14 has a MOS transistor Ml having a gate terminal connected to the antenna terminal LB and a MOS transistor M2 having a gate terminal connected to the antenna terminal LA connected in series, and a connection point between the capacitors C1 and C2. And the connection point of MOS transistors Ml and M2, A MOS transistor M3 (variable resistance element, seventh MOS transistor) is connected, and a voltage detection circuit B15 is connected between the antenna terminals LA and LB. At this time, the connection point of MOS transistors Ml and M2 is connected to the ground terminal.
[0051] 電圧検出回路 B15は、アンテナ端子 LAと出力端子 OUT2の間に、ゲート端子とド レイン端子を接続した MOSトランジスタ M4 (第 1の整流素子)を接続し、アンテナ端 子 LBと出力端子 OUT2の間に、ゲート端子とドレイン端子を接続した MOSトランジ スタ M5 (第 2の整流素子)を接続し、出力端子 OUT2とグランド端子の間に容量 C3 を接続し、出力端子 OUT2とグランド端子の間に直列接続された抵抗 R4と R5の接 続点を演算増幅回路 A1の非反転入力端子(+ )に接続し、演算増幅回路 A1の反 転入力端子(一)に基準電圧 VIを入力し、演算増幅回路 A1の出力端子 N1を MOS トランジスタ M3のゲート端子に入力した構成である。  [0051] In the voltage detection circuit B15, a MOS transistor M4 (first rectifier element) having a gate terminal and a drain terminal connected is connected between the antenna terminal LA and the output terminal OUT2, and the antenna terminal LB and the output terminal are connected. Connect a MOS transistor M5 (second rectifier) with the gate and drain terminals connected between OUT2, connect a capacitor C3 between the output terminal OUT2 and the ground terminal, and connect the output terminal OUT2 and the ground terminal. Connect the connection point of resistors R4 and R5 connected in series between them to the non-inverting input terminal (+) of the operational amplifier circuit A1, and input the reference voltage VI to the inverting input terminal (one) of the operational amplifier circuit A1. In this configuration, the output terminal N1 of the operational amplifier circuit A1 is input to the gate terminal of the MOS transistor M3.
[0052] 図 6において、演算増幅回路 A1は、アンテナ端子間に供給される電力を、出力端 子 OUT2に発生する電圧として検出し、 MOSトランジスタ M3に流れる電流を制御 する。  In FIG. 6, the operational amplifier circuit A 1 detects the power supplied between the antenna terminals as a voltage generated at the output terminal OUT 2 and controls the current flowing through the MOS transistor M 3.
[0053] 出力端子 OUT2に発生する電圧が所定の電圧レベルより小さい場合、つまり、アン テナ端子に発生する電圧が所定の電圧レベルより小さ ヽ場合は、 MOSトランジスタ M3に電流は流れないため、アンテナ端子間には容量 C1及び C2が直列接続された 状態に近似でき、容量 C 1の半分の容量値の容量が接続されて!ヽる状態になる。  [0053] When the voltage generated at the output terminal OUT2 is lower than the predetermined voltage level, that is, when the voltage generated at the antenna terminal is lower than the predetermined voltage level, no current flows through the MOS transistor M3. Capacitors C1 and C2 can be approximated in series between the terminals, and a capacitor with a capacitance value half that of capacitor C1 is connected.
[0054] また、出力端子 OUT2に発生する電圧が所定の電圧レベルより大きい場合、つまり 、アンテナ端子に発生する電圧が所定の電圧レベルより大きい場合は、出力端子 O TU2に発生する電圧に応じて、 MOSトランジスタ M3に流れる電流が制御されるた め、容量 C1及び C2に蓄積される電荷が制御され、アンテナ端子間に接続される容 量が変化する。例えば、 MOSトランジスタ M3に流れる電流が極めて大きい電流値 に制御された場合、容量 C1または C2のどちらかが短絡された状態になるため、アン テナ端子間には容量 C1と同等の容量値の容量が接続された状態に近似できること になる。  [0054] Further, when the voltage generated at the output terminal OUT2 is higher than a predetermined voltage level, that is, when the voltage generated at the antenna terminal is higher than the predetermined voltage level, depending on the voltage generated at the output terminal OTU2 Since the current flowing through the MOS transistor M3 is controlled, the charge stored in the capacitors C1 and C2 is controlled, and the capacitance connected between the antenna terminals changes. For example, when the current flowing through the MOS transistor M3 is controlled to an extremely large current value, either the capacitor C1 or C2 is short-circuited, so that the capacity value equivalent to the capacity C1 is between the antenna terminals. Can be approximated to a connected state.
[0055] 上述の動作により、アンテナ端子間に発生する電圧レベルに応じて、共振容量が 容量 C1の半分の容量値から、容量 C1と同等の容量値までの範囲で制御でき、アン テナ LOと共振容量制御回路 B3によって構成される共振回路の共振周波数が制御 できる。 [0055] According to the above-described operation, the resonance capacitance can be controlled in a range from a capacitance value half of the capacitance C1 to a capacitance value equivalent to the capacitance C1, according to the voltage level generated between the antenna terminals. The resonant frequency of the resonant circuit composed of the tenor LO and resonant capacity control circuit B3 can be controlled.
[0056] 例えば、容量 C1の容量値を、アンテナ LOに供給される電磁波の周波数に共振す る容量値の 2倍に設定すれば、アンテナ端子間に発生する電圧レベルが所定の電 圧レベルより小さい場合は、電磁波の周波数に共振することで最大電力を受信でき、 アンテナ端子間に発生する電圧レベルが所定の電圧レベルより大きい場合は、アン テナ端子の共振容量を大きくすることで、共振周波数が低くなるように制御され、整 流平滑回路 B4に供給される電力を小さくすることができる。  [0056] For example, if the capacitance value of the capacitor C1 is set to twice the capacitance value that resonates with the frequency of the electromagnetic wave supplied to the antenna LO, the voltage level generated between the antenna terminals will be higher than the predetermined voltage level. If it is small, the maximum power can be received by resonating with the frequency of the electromagnetic wave, and if the voltage level generated between the antenna terminals is higher than the predetermined voltage level, the resonance frequency can be increased by increasing the resonance capacity of the antenna terminal. The power supplied to the rectifying / smoothing circuit B4 can be reduced.
[0057] また、演算増幅回路 A1の極性を逆にして、アンテナ端子間に発生する電圧レベル が所定の電圧レベルより大き ヽ場合は、 MOSトランジスタ M3のオン抵抗を大きくし て、アンテナ端子の共振容量を小さくすることで、共振周波数が高くなるように制御し てもよい。  [0057] When the polarity of the operational amplifier circuit A1 is reversed and the voltage level generated between the antenna terminals is larger than the predetermined voltage level, the on-resistance of the MOS transistor M3 is increased to resonate the antenna terminal. The resonance frequency may be controlled to be higher by reducing the capacitance.
[0058] ここで、アンテナ端子 LAの電位がアンテナ端子 LBの電位より高い場合のみ MOS トランジスタ M2がオンし、アンテナ端子 LBの電位がアンテナ端子 LAの電位より高 ヽ 場合のみ MOSトランジスタ Mlがオンすることから、 MOSトランジスタ Ml及び M2は 、低電位側の整流素子としても動作する。  Here, MOS transistor M2 is turned on only when the potential of antenna terminal LA is higher than the potential of antenna terminal LB, and MOS transistor Ml is turned on only when the potential of antenna terminal LB is higher than the potential of antenna terminal LA. Therefore, the MOS transistors Ml and M2 also operate as a rectifying element on the low potential side.
[0059] また、アンテナ端子 LAの電位が出力端子 OUT2の電位より高い場合のみ MOSト ランジスタ M4に電流が流れ、アンテナ端子 LBの電位が出力端子 OUT2の電位より 高い場合のみ MOSトランジスタ M5に電流が流れることから、 MOSトランジスタ M4 及び M5は、高電位側の整流素子としても動作する。  [0059] Further, a current flows through the MOS transistor M4 only when the potential of the antenna terminal LA is higher than the potential of the output terminal OUT2, and a current flows through the MOS transistor M5 only when the potential of the antenna terminal LB is higher than the potential of the output terminal OUT2. Since it flows, the MOS transistors M4 and M5 also operate as rectifiers on the high potential side.
[0060] 以上のことから、充放電制御回路 B14は整流回路としても機能し、容量 C3が平滑 容量として機能することから、出力端子 OUT2に発生する電圧を半導体集積回路装 置 B2の内部回路 B5の電源電圧として利用することができる。これにより、共振容量 制御回路 B3と独立した整流平滑回路 B4を搭載する必要が無くなり、チップ面積を 低減することも可能になる。  [0060] From the above, the charge / discharge control circuit B14 also functions as a rectifier circuit, and the capacitor C3 functions as a smoothing capacitor. Therefore, the voltage generated at the output terminal OUT2 is transferred to the internal circuit B5 of the semiconductor integrated circuit device B2. Can be used as a power supply voltage. As a result, it is not necessary to mount the rectifying / smoothing circuit B4 independent of the resonance capacitance control circuit B3, and the chip area can be reduced.
[0061] (実施の形態 4)  [Embodiment 4]
図 7は、本発明に係る半導体集積回路装置 B2に搭載される共振容量制御回路 B3 の他の一実施例を示す回路構成図である。これは、図 3に示した共振容量制御回路 B3に搭載される充放電制御回路 B14の他の回路構成例を示したものである。 FIG. 7 is a circuit configuration diagram showing another embodiment of the resonance capacitance control circuit B3 mounted in the semiconductor integrated circuit device B2 according to the present invention. This is the resonant capacitance control circuit shown in Fig. 3. 10 shows another circuit configuration example of the charge / discharge control circuit B14 mounted on B3.
[0062] アンテナ端子 LA及び LBの間に接続される共振容量制御回路 B3は、非接触型電 子装置 B1に配置されるアンテナを接続するアンテナ端子 LA及び LBの間に、容量 C 1及び C2を直列接続し、容量 C1及び C2の接続点とアンテナ端子 LA及び LBに接 続される充放電制御回路 B14が接続される。  [0062] The resonant capacitance control circuit B3 connected between the antenna terminals LA and LB has capacitors C1 and C2 between the antenna terminals LA and LB connecting the antenna arranged in the non-contact type electronic device B1. Are connected in series, and the connection point of the capacitors C1 and C2 and the charge / discharge control circuit B14 connected to the antenna terminals LA and LB are connected.
[0063] 充放電制御回路 B14は、アンテナ端子 LA及び LBの間に、アンテナ端子 LBとゲ ート端子の間に抵抗 R6 (第 1の抵抗)を接続した MOSトランジスタ M6 (第 3の MOS トランジスタ)と、アンテナ端子 LAとゲート端子の間に抵抗 R7 (第 2の抵抗)を接続し た MOSトランジスタ M7 (第 4の MOSトランジスタ)が接続され、 MOSトランジスタ M6 のゲート端子とグランド端子の間に、アンテナ端子 LBにゲート端子を接続した MOS トランジスタ M8 (第 5の MOSトランジスタ)と電圧検出回路 B15の出力端子 N1にゲ ート端子を接続した MOSトランジスタ M10 (可変抵抗素子、第 7の MOSトランジスタ )が直列接続され、 MOSトランジスタ M7のゲート端子と MOSトランジスタ M10のドレ イン端子の間に、アンテナ端子 LAにゲート端子を接続した MOSトランジスタ M9 (第 6の MOSトランジスタ)が接続される。  [0063] The charge / discharge control circuit B14 includes a MOS transistor M6 (third MOS transistor) in which a resistor R6 (first resistor) is connected between the antenna terminal LB and the gate terminal between the antenna terminals LA and LB. ) And a MOS transistor M7 (fourth MOS transistor) with a resistor R7 (second resistor) connected between the antenna terminal LA and the gate terminal, and between the gate terminal of the MOS transistor M6 and the ground terminal The MOS transistor M8 (fifth MOS transistor) with the gate terminal connected to the antenna terminal LB and the MOS transistor M10 (variable resistance element, seventh MOS transistor) with the gate terminal connected to the output terminal N1 of the voltage detection circuit B15 ) Are connected in series, and the MOS transistor M9 (sixth MOS transistor) has a gate terminal connected to the antenna terminal LA between the gate terminal of the MOS transistor M7 and the drain terminal of the MOS transistor M10. It is connected.
[0064] 電圧検出回路 B15は、アンテナ端子間に発生する電圧に応じた電圧を出力する構 成であり、例えば、図 6に示した回路構成でも良い。但し、チップ内のグランド端子と 接続するために、図 6に示した MOSトランジスタ Ml及び M2に代表される低電位側 の整流素子も必要である。  [0064] The voltage detection circuit B15 is configured to output a voltage corresponding to the voltage generated between the antenna terminals. For example, the voltage detection circuit B15 may have the circuit configuration illustrated in FIG. However, in order to connect to the ground terminal in the chip, a rectifier on the low potential side represented by MOS transistors Ml and M2 shown in FIG. 6 is also required.
[0065] 図 7において、電圧検出回路 B15は、アンテナ端子間に発生する電圧に応じて、 [0065] In FIG. 7, the voltage detection circuit B15, depending on the voltage generated between the antenna terminals,
MOSトランジスタ M10に流れる電流を制御する。アンテナ端子間に発生する電圧が 所定の電圧レベルより小さい場合は、出力端子 N1の電位が低くなり、 MOSトランジ スタ M10に電流は流れないため、 MOSトランジスタ M6及び M7はそれぞれのゲート 電位が高い場合にオンする。これにより、アンテナ端子間には容量 C1及び C2のどち らか一方の容量の両端電圧が短絡されるため、アンテナ端子間には容量 C1と同等 の容量値の容量が接続された状態に近似できることになる。 Controls the current flowing through MOS transistor M10. If the voltage generated between the antenna terminals is lower than the specified voltage level, the potential at the output terminal N1 will be low and no current will flow through the MOS transistor M10, so that the MOS transistors M6 and M7 have high gate potentials. Turn on. As a result, the voltage across one of the capacitors C1 and C2 is short-circuited between the antenna terminals, so that it can be approximated to a state where a capacitor having a capacitance value equivalent to that of the capacitor C1 is connected between the antenna terminals. become.
[0066] また、アンテナ端子間に発生する電圧が所定の電圧レベルより大きい場合は、アン テナ端子に発生する電圧に応じて、 MOSトランジスタ M10に流れる電流が制御され るため、抵抗 R6または R7に発生する電圧が大きくなるように制御され、 MOSトランジ スタ M6及び M7はそれぞれのゲート電圧が抑圧される。その結果、 MOSトランジス タ M6及び M7に流れる電流が制御されるため、容量 C1及び C2に蓄積される電荷が 制御され、アンテナ端子間に接続される容量が変化する。例えば、 MOSトランジスタ M6及び M7に流れる電流が極めて小さい電流値に制御された場合、アンテナ端子 間には容量 C1及び C2が直列接続された状態に近似でき、容量 C1の半分の容量値 の容量が接続されて 、る状態になる。 [0066] If the voltage generated between the antenna terminals is higher than a predetermined voltage level, the current flowing through the MOS transistor M10 is controlled according to the voltage generated at the antenna terminal. Therefore, the voltage generated in the resistor R6 or R7 is controlled to increase, and the gate voltages of the MOS transistors M6 and M7 are suppressed. As a result, since the current flowing through the MOS transistors M6 and M7 is controlled, the charge stored in the capacitors C1 and C2 is controlled, and the capacitance connected between the antenna terminals changes. For example, when the current flowing through the MOS transistors M6 and M7 is controlled to a very small current value, it can be approximated to the state where the capacitors C1 and C2 are connected in series between the antenna terminals, and the capacitance having a capacitance value half that of the capacitor C1 is obtained. It will be connected.
[0067] 以上の動作により、アンテナ端子に発生する電圧レベルに応じて、共振容量が容 量 C1と同等の容量値から、容量 C1の半分の容量値までの範囲で制御でき、アンテ ナ LOと共振容量制御回路 B3によって構成される共振回路の共振周波数が制御でき る。 [0067] By the above operation, the resonance capacitance can be controlled in the range from the capacitance value equivalent to the capacitance C1 to the capacitance value half of the capacitance C1, according to the voltage level generated at the antenna terminal. The resonance frequency of the resonance circuit configured by the resonance capacitance control circuit B3 can be controlled.
[0068] 更には、アンテナ端子間に発生する電圧レベルが所定の電圧レベルより大きくなつ た場合に、共振周波数を高くするように制御することが可能になるため、過剰な電力 が供給されることを抑制することができると共に、容量に流れる電流も小さくすることも できるため、共振容量による発熱も抑制することが可能になる。特に、容量 C1及び C 2を半導体集積回路装置 B2に搭載する場合などに有効な手段となる。  [0068] Furthermore, when the voltage level generated between the antenna terminals becomes higher than a predetermined voltage level, it is possible to control the resonance frequency to be increased, so that excessive power is supplied. Can be suppressed, and the current flowing through the capacitor can be reduced, so that heat generation by the resonant capacitor can also be suppressed. This is particularly effective when the capacitors C1 and C2 are mounted on the semiconductor integrated circuit device B2.
[0069] (実施の形態 5)  [Embodiment 5]
図 8は、本発明に係る半導体集積回路装置 B2に搭載される共振容量制御回路 B3 及び整流平滑回路 B4の一実施例を示す構成図である。  FIG. 8 is a block diagram showing an embodiment of the resonant capacitance control circuit B3 and the rectifying / smoothing circuit B4 mounted on the semiconductor integrated circuit device B2 according to the present invention.
[0070] これは、アンテナ端子 LA及び LBの間に共振容量制御回路 B3が接続され、アンテ ナ端子 LA及び LBに、整流平滑回路 B4が接続され、整流平滑回路 B4の出力端子 OUTに得られる電圧をレギユレータ回路 B16によって抑制した電圧が出力端子 OU T3から得られる構成である。共振容量制御回路 B3としては、例えば、前記実施の形 態 1〜4における図 3、図 4、図 6及び図 7の回路が用いられる。  [0070] This is obtained by connecting the resonant capacitance control circuit B3 between the antenna terminals LA and LB, connecting the rectifying and smoothing circuit B4 to the antenna terminals LA and LB, and obtaining the output terminal OUT of the rectifying and smoothing circuit B4. In this configuration, the voltage suppressed by the regulator circuit B16 is obtained from the output terminal OUT3. As the resonance capacitance control circuit B3, for example, the circuits of FIGS. 3, 4, 6, and 7 in the first to fourth embodiments are used.
[0071] 共振容量制御回路 B3によって、整流平滑回路 B4の出力電圧が十分に制御でき ない場合は、レギユレータ回路 B16を搭載することで、内部回路 B5に供給される電 源電圧を安定化すれば良い。これにより、共振容量制御回路 B3によって、過大な電 力供給を抑制することでチップ発熱の低減を可能にすると共に、安定した電源電圧 を内部回路 B5に供給することが可能になる。 [0071] If the output voltage of the rectifying / smoothing circuit B4 cannot be sufficiently controlled by the resonance capacitance control circuit B3, the regulator circuit B16 can be mounted to stabilize the power supply voltage supplied to the internal circuit B5. good. As a result, it is possible to reduce chip heat generation by suppressing excessive power supply by the resonance capacitance control circuit B3, and to stabilize power supply voltage. Can be supplied to the internal circuit B5.
[0072] このとき、特に限定はされるものではないが、共振容量制御回路 B3が共振容量を 制御し始める電圧レベルを、レギユレータ回路 B16が出力電圧を抑制し始める電圧 レベルより大きくする方が、回路特性の調整が容易になり好適である。  [0072] At this time, although not particularly limited, the voltage level at which the resonant capacitance control circuit B3 starts to control the resonant capacitance is made larger than the voltage level at which the regulator circuit B16 starts to suppress the output voltage. Adjustment of circuit characteristics is facilitated, which is preferable.
[0073] また、同様に、図 6で示した整流平滑機能を有する共振容量制御回路 B3において も、その出力端子 OUT2にレギユレータを搭載することが可能である。  Similarly, also in the resonance capacitance control circuit B3 having the rectifying and smoothing function shown in FIG. 6, it is possible to mount a regulator at the output terminal OUT2.
[0074] 以上、本発明者によってなされた発明をその実施の形態に基づき具体的に説明し たが、本発明は前記実施の形態に限定されるものではなぐその要旨を逸脱しない 範囲で種々変更可能であることは 、うまでもな!/、。  [0074] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. It's possible that it's possible!
[0075] 例えば、前記実施の形態にお!、ては、共振容量制御回路を N型 MOSトランジスタ によって構成した力 P型 MOSトランジスタを用いてもよい。また、共振容量を制御す るための容量 C1及び C2の配置場所は半導体集積回路装置 B2の中に限定されるも のではなぐ半導体集積回路装置 B2以外に配置されても良いし、更には、容量 C1 及び C2の他にアンテナ端子間に他の容量が接続されて ヽても良!ヽ。  For example, in the embodiment described above, a force P-type MOS transistor in which the resonance capacitance control circuit is configured by an N-type MOS transistor may be used. Further, the location of the capacitors C1 and C2 for controlling the resonant capacitance is not limited to the semiconductor integrated circuit device B2, but may be arranged other than the semiconductor integrated circuit device B2, and moreover, In addition to the capacitors C1 and C2, other capacitors can be connected between the antenna terminals.
産業上の利用可能性  Industrial applicability
[0076] 本発明は、 ICカードや ICタグを代表とする非接触型電子装置に適用して好適であ る。 The present invention is suitable for application to non-contact electronic devices typified by IC cards and IC tags.

Claims

請求の範囲 The scope of the claims
[1] アンテナと、  [1] with antenna,
前記アンテナに接続された共振容量制御回路とを具備し、  A resonant capacitance control circuit connected to the antenna;
前記共振容量制御回路は、  The resonant capacitance control circuit is
前記アンテナが接続される第 1のアンテナ端子と第 2のアンテナ端子の間に、第 1 の容量と第 2の容量が直列接続され、  A first capacitor and a second capacitor are connected in series between a first antenna terminal and a second antenna terminal to which the antenna is connected,
前記第 1の容量と前記第 2の容量の接続点に充放電制御回路が接続され、 前記充放電制御回路は、  A charge / discharge control circuit is connected to a connection point between the first capacitor and the second capacitor, and the charge / discharge control circuit is:
前記第 1のアンテナ端子の電位が前記第 2のアンテナ端子の電位より高いときには 前記第 1の容量に蓄積される電荷を制御し、  When the potential of the first antenna terminal is higher than the potential of the second antenna terminal, the charge accumulated in the first capacitor is controlled,
前記第 2のアンテナ端子の電位が前記第 1のアンテナ端子の電位より高いときには 前記第 2の容量に蓄積される電荷を制御することで、  When the potential of the second antenna terminal is higher than the potential of the first antenna terminal, by controlling the charge accumulated in the second capacitor,
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間の共振容量値を制御する ことを特徴とする非接触型電子装置。  A contactless electronic device, wherein a resonance capacitance value between the first antenna terminal and the second antenna terminal is controlled.
[2] 請求項 1記載の非接触型電子装置において、 [2] The contactless electronic device according to claim 1,
前記充放電制御回路は、  The charge / discharge control circuit includes:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に、  Between the first antenna terminal and the second antenna terminal,
前記第 2のアンテナ端子にゲート端子が接続された第 1の MOSトランジスタと、 前記第 1のアンテナ端子にゲート端子が接続された第 2の MOSトランジスタとが直 列接続され、  A first MOS transistor having a gate terminal connected to the second antenna terminal and a second MOS transistor having a gate terminal connected to the first antenna terminal are connected in series,
前記第 1の容量と前記第 2の容量の接続点と、  A connection point between the first capacitor and the second capacitor;
前記第 1の MOSトランジスタと前記第 2の MOSトランジスタの接続点との間に、 可変抵抗素子が接続されていることを特徴とする非接触型電子装置。  A contactless electronic device, wherein a variable resistance element is connected between a connection point of the first MOS transistor and the second MOS transistor.
[3] 請求項 1記載の非接触型電子装置において、 [3] The contactless electronic device according to claim 1,
前記充放電制御回路は、  The charge / discharge control circuit includes:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に、 前記第 2のアンテナ端子とゲート端子の間に第 1の抵抗が接続された第 3の MOSト ランジスタと、 Between the first antenna terminal and the second antenna terminal, A third MOS transistor in which a first resistor is connected between the second antenna terminal and the gate terminal;
前記第 1のアンテナ端子とゲート端子の間に第 2の抵抗が接続された第 4の MOSト ランジスタとが直列接続され、  A fourth MOS transistor having a second resistor connected between the first antenna terminal and the gate terminal is connected in series;
前記第 3の MOSトランジスタのゲート端子と前記第 4の MOSトランジスタのゲート端 子の間に、  Between the gate terminal of the third MOS transistor and the gate terminal of the fourth MOS transistor,
ゲート端子が前記第 2のアンテナ端子に接続された第 5の MOSトランジスタと、 ゲート端子が前記第 1のアンテナ端子に接続された第 6の MOSトランジスタが直列 接続され、  A fifth MOS transistor having a gate terminal connected to the second antenna terminal and a sixth MOS transistor having a gate terminal connected to the first antenna terminal are connected in series,
前記第 5の MOSトランジスタと前記第 6の MOSトランジスタの接続点とグランド端子 の間に可変抵抗素子が接続されていることを特徴とする非接触型電子装置。  A contactless electronic device, wherein a variable resistance element is connected between a connection point of the fifth MOS transistor and the sixth MOS transistor and a ground terminal.
[4] 請求項 2または 3記載の非接触型電子装置にお 、て、 [4] In the contactless electronic device according to claim 2 or 3,
前記可変抵抗素子は、  The variable resistance element is:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に発生する電圧が所定の 電圧より大きい場合に、抵抗値が小さくなるように制御されることを特徴とする非接触 型電子装置。  The contactless electronic device, wherein a resistance value is controlled to be small when a voltage generated between the first antenna terminal and the second antenna terminal is larger than a predetermined voltage.
[5] 請求項 2または 3記載の非接触型電子装置にお 、て、  [5] In the contactless electronic device according to claim 2 or 3,
前記可変抵抗素子は、  The variable resistance element is:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に発生する電圧が所定の 電圧より小さい場合に、抵抗値が大きくなるように制御されることを特徴とする非接触 型電子装置。  A contactless electronic device, wherein a resistance value is controlled to increase when a voltage generated between the first antenna terminal and the second antenna terminal is smaller than a predetermined voltage.
[6] 請求項 2または 3記載の非接触型電子装置にお 、て、  [6] In the contactless electronic device according to claim 2 or 3,
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に発生する電圧に応じた 電圧を出力する電圧検出回路を具備し、  A voltage detection circuit that outputs a voltage corresponding to a voltage generated between the first antenna terminal and the second antenna terminal;
前記可変抵抗素子は、  The variable resistance element is:
前記電圧検出回路の出力がゲート端子に接続された第 7の MOSトランジスタで構 成されて!/ゝることを特徴とする非接触型電子装置。  The output of the voltage detection circuit consists of a seventh MOS transistor connected to the gate terminal! A non-contact electronic device characterized by squeezing.
[7] 請求項 2または 3記載の非接触型電子装置にお 、て、 前記第 1のアンテナ端子と第 1の出力端子の間に第 1の整流素子が接続され、 前記第 2のアンテナ端子と前記第 1の出力端子の間に第 2の整流素子が接続され、 前記第 1の MOSトランジスタと前記第 2の MOSトランジスタの接続点が第 2の出力 端子に接続されることで前記第 1及び第 2の MOSトランジスタが整流素子として動作 し、 [7] In the contactless electronic device according to claim 2 or 3, A first rectifier element is connected between the first antenna terminal and the first output terminal; a second rectifier element is connected between the second antenna terminal and the first output terminal; The connection point between the first MOS transistor and the second MOS transistor is connected to the second output terminal, so that the first and second MOS transistors operate as rectifier elements,
前記第 1の出力端子と前記第 2の出力端子の間に発生する電圧が、電源電圧とし て内部に搭載される他の回路に供給されることを特徴とする非接触型電子装置。  A non-contact type electronic device, wherein a voltage generated between the first output terminal and the second output terminal is supplied as a power supply voltage to another circuit mounted therein.
[8] 非接触型電子装置に搭載される半導体集積回路装置であって、 [8] A semiconductor integrated circuit device mounted on a non-contact electronic device,
共振容量制御回路を具備し、  A resonant capacitance control circuit;
前記共振容量制御回路は、  The resonant capacitance control circuit is
前記非接触型電子装置に搭載されるアンテナが接続される第 1のアンテナ端子と 第 2のアンテナ端子の間に、第 1の容量と第 2の容量が直列接続され、  A first capacitor and a second capacitor are connected in series between a first antenna terminal and a second antenna terminal to which an antenna mounted on the contactless electronic device is connected,
前記第 1の容量と前記第 2の容量の接続点に充放電制御回路が接続され、 前記充放電制御回路は、  A charge / discharge control circuit is connected to a connection point between the first capacitor and the second capacitor, and the charge / discharge control circuit is:
前記第 1のアンテナ端子の電位が前記第 2のアンテナ端子の電位より高いときには 前記第 1の容量に蓄積される電荷を制御し、  When the potential of the first antenna terminal is higher than the potential of the second antenna terminal, the charge accumulated in the first capacitor is controlled,
前記第 2のアンテナ端子の電位が前記第 1のアンテナ端子の電位より高いときには 前記第 2の容量に蓄積される電荷を制御することで、  When the potential of the second antenna terminal is higher than the potential of the first antenna terminal, by controlling the charge accumulated in the second capacitor,
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間の共振容量値を制御する ことを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device characterized by controlling a resonance capacitance value between the first antenna terminal and the second antenna terminal.
[9] 請求項 8記載の半導体集積回路装置において、 [9] The semiconductor integrated circuit device according to claim 8,
前記充放電制御回路は、  The charge / discharge control circuit includes:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に、  Between the first antenna terminal and the second antenna terminal,
前記第 2のアンテナ端子にゲート端子が接続された第 1の MOSトランジスタと、 前記第 1のアンテナ端子にゲート端子が接続された第 2の MOSトランジスタとが直 列接続され、 前記第 1の容量と前記第 2の容量の接続点と、 A first MOS transistor having a gate terminal connected to the second antenna terminal and a second MOS transistor having a gate terminal connected to the first antenna terminal are connected in series, A connection point between the first capacitor and the second capacitor;
前記第 1の MOSトランジスタと前記第 2の MOSトランジスタの接続点との間に、 可変抵抗素子が接続されていることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device, wherein a variable resistance element is connected between a connection point of the first MOS transistor and the second MOS transistor.
[10] 請求項 8記載の半導体集積回路装置において、 [10] The semiconductor integrated circuit device according to claim 8,
前記充放電制御回路は、  The charge / discharge control circuit includes:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に、  Between the first antenna terminal and the second antenna terminal,
前記第 2のアンテナ端子とゲート端子の間に第 1の抵抗が接続された第 3の MOSト ランジスタと、  A third MOS transistor in which a first resistor is connected between the second antenna terminal and the gate terminal;
前記第 1のアンテナ端子とゲート端子の間に第 2の抵抗が接続された第 4の MOSト ランジスタとが直列接続され、  A fourth MOS transistor having a second resistor connected between the first antenna terminal and the gate terminal is connected in series;
前記第 3の MOSトランジスタのゲート端子と前記第 4の MOSトランジスタのゲート端 子の間に、  Between the gate terminal of the third MOS transistor and the gate terminal of the fourth MOS transistor,
ゲート端子が前記第 2のアンテナ端子に接続された第 5の MOSトランジスタと、 ゲート端子が前記第 1のアンテナ端子に接続された第 6の MOSトランジスタが直列 接続され、  A fifth MOS transistor having a gate terminal connected to the second antenna terminal and a sixth MOS transistor having a gate terminal connected to the first antenna terminal are connected in series,
前記第 5の MOSトランジスタと前記第 6の MOSトランジスタの接続点とグランド端子 の間に可変抵抗素子が接続されていることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device, wherein a variable resistance element is connected between a connection point of the fifth MOS transistor and the sixth MOS transistor and a ground terminal.
[11] 請求項 9または 10記載の半導体集積回路装置において、 [11] The semiconductor integrated circuit device according to claim 9 or 10,
前記可変抵抗素子は、  The variable resistance element is:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に発生する電圧が所定の 電圧より大きい場合に、抵抗値が小さくなるように制御されることを特徴とする半導体 集積回路装置。  A semiconductor integrated circuit device, wherein a resistance value is controlled to be small when a voltage generated between the first antenna terminal and the second antenna terminal is larger than a predetermined voltage.
[12] 請求項 9または 10記載の半導体集積回路装置において、  [12] The semiconductor integrated circuit device according to claim 9 or 10,
前記可変抵抗素子は、  The variable resistance element is:
前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に発生する電圧が所定の 電圧より小さい場合に、抵抗値が大きくなるように制御されることを特徴とする半導体 集積回路装置。  A semiconductor integrated circuit device, wherein a resistance value is controlled to increase when a voltage generated between the first antenna terminal and the second antenna terminal is smaller than a predetermined voltage.
[13] 請求項 9または 10記載の半導体集積回路装置において、 前記第 1のアンテナ端子と前記第 2のアンテナ端子の間に発生する電圧に応じた 電圧を出力する電圧検出回路を具備し、 [13] The semiconductor integrated circuit device according to claim 9 or 10, A voltage detection circuit that outputs a voltage corresponding to a voltage generated between the first antenna terminal and the second antenna terminal;
前記可変抵抗素子は、  The variable resistance element is:
前記電圧検出回路の出力がゲート端子に接続された第 7の MOSトランジスタで構 成されて!/ヽることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device comprising: a seventh MOS transistor having an output of the voltage detection circuit connected to a gate terminal.
請求項 9または 10記載の半導体集積回路装置において、  The semiconductor integrated circuit device according to claim 9 or 10,
前記第 1のアンテナ端子と第 1の出力端子の間に第 1の整流素子が接続され、 前記第 2のアンテナ端子と前記第 1の出力端子の間に第 2の整流素子が接続され、 前記第 1の MOSトランジスタと前記第 2の MOSトランジスタの接続点が第 2の出力 端子に接続されることで前記第 1及び第 2の MOSトランジスタが整流素子として動作 し、  A first rectifier element is connected between the first antenna terminal and the first output terminal; a second rectifier element is connected between the second antenna terminal and the first output terminal; The connection point between the first MOS transistor and the second MOS transistor is connected to the second output terminal, so that the first and second MOS transistors operate as rectifier elements,
前記第 1の出力端子と前記第 2の出力端子の間に発生する電圧が、電源電圧とし て内部に搭載される他の回路に供給されることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device, wherein a voltage generated between the first output terminal and the second output terminal is supplied as a power supply voltage to another circuit mounted therein.
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