JP2011134957A5 - - Google Patents

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Publication number
JP2011134957A5
JP2011134957A5 JP2009294435A JP2009294435A JP2011134957A5 JP 2011134957 A5 JP2011134957 A5 JP 2011134957A5 JP 2009294435 A JP2009294435 A JP 2009294435A JP 2009294435 A JP2009294435 A JP 2009294435A JP 2011134957 A5 JP2011134957 A5 JP 2011134957A5
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JP
Japan
Prior art keywords
land
multilayer wiring
wiring board
diameter side
wiring layer
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JP2009294435A
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Japanese (ja)
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JP2011134957A (en
JP5355380B2 (en
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Priority to JP2009294435A priority Critical patent/JP5355380B2/en
Priority claimed from JP2009294435A external-priority patent/JP5355380B2/en
Priority to US12/975,703 priority patent/US8952270B2/en
Publication of JP2011134957A publication Critical patent/JP2011134957A/en
Publication of JP2011134957A5 publication Critical patent/JP2011134957A5/ja
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Description

上記の従来技術の課題を解決するため、本発明によれば、内層の配線層に対してその両面に対向する方向からビアが形成され、前記配線層においてそれぞれ当該ビアと接続される箇所に画定されるランドが、その側面がテーパ状となるように形成された構造を有する多層配線基板であって、前記ランドは、小径側の面にビアが接続される第１のランドと、大径側の面にのみビアが接続される第２のランドからなり、前記第１のランドと前記第２のランドとは同層に形成されており、前記第２のランドの大径側の面の面積が、前記第１のランドの小径側の面の面積と同じになることを特徴とする多層配線基板が提供される。   In order to solve the above-described problems of the prior art, according to the present invention, vias are formed from a direction facing both surfaces of an inner wiring layer, and are defined at locations connected to the vias in the wiring layer, respectively. The land to be formed is a multilayer wiring board having a structure formed such that a side surface thereof is tapered, and the land includes a first land having a via connected to a surface on a small diameter side, and a large diameter side The first land and the second land are formed in the same layer, and the area of the surface on the large-diameter side of the second land. However, there is provided a multilayer wiring board having the same area as the surface of the first land on the small diameter side.

Claims (5)

内層の配線層に対してその両面に対向する方向からビアが形成され、前記配線層においてそれぞれ当該ビアと接続される箇所に画定されるランドが、その側面がテーパ状となるように形成された構造を有する多層配線基板であって、
前記ランドは、小径側の面にビアが接続される第１のランドと、大径側の面にのみビアが接続される第２のランドからなり、前記第１のランドと前記第２のランドとは同層に形成されており、前記第２のランドの大径側の面の面積が、前記第１のランドの小径側の面の面積と同じになることを特徴とする多層配線基板。 Vias are formed from the direction facing both surfaces of the inner wiring layer, and lands defined at locations connected to the vias in the wiring layer are formed so that the side surfaces thereof are tapered. A multilayer wiring board having a structure,
The land includes a first land whose via is connected to the surface on the small diameter side and a second land whose via is connected only to the surface on the large diameter side. The first land and the second land The multilayer wiring board is characterized in that the area of the large-diameter side surface of the second land is the same as the area of the small-diameter surface of the first land. 内層の配線層に対してその両面に対向する方向からビアが形成され、前記配線層においてそれぞれ当該ビアと接続される箇所に画定されるランドが、その側面がテーパ状となるように形成された構造を有する多層配線基板であって、
前記ランドは、小径側の面にビアが接続される第１のランドと、大径側の面にのみビアが接続される第２のランドからなり、前記第１のランドと前記第２のランドとは同層に形成されており、前記第１のランドの大径側の面の面積の方が、前記第２のランドの大径側の面の面積よりも広いことを特徴とする多層配線基板。 Vias are formed from the direction facing both surfaces of the inner wiring layer, and lands defined at locations connected to the vias in the wiring layer are formed so that the side surfaces thereof are tapered. A multilayer wiring board having a structure,
The land includes a first land whose via is connected to the surface on the small diameter side and a second land whose via is connected only to the surface on the large diameter side. The first land and the second land The multilayer wiring is characterized in that the area of the large-diameter surface of the first land is larger than the area of the large-diameter surface of the second land. substrate. 前記内層の配線層を挟んで上下に設けられる各絶縁層は、その材料としてプリプレグが使用されていることを特徴とする請求項１又は２に記載の多層配線基板。   3. The multilayer wiring board according to claim 1, wherein a prepreg is used as a material of each of the insulating layers provided above and below the inner wiring layer. 前記内層の配線層は、前記各絶縁層に設けられる配線に比べて厚く形成されていることを特徴とする請求項３に記載の多層配線基板。   4. The multilayer wiring board according to claim 3, wherein the inner wiring layer is formed thicker than the wiring provided in each of the insulating layers. 前記多層配線基板は、前記ランドの小径側に形成された一面側と、前記ランドの大径側に形成された他面側を有しており、半導体素子搭載面が前記他面側に設けられていることを特徴とする請求項１乃至４のいずれか一項に記載の多層配線基板。   The multilayer wiring board has one surface formed on the small diameter side of the land and the other surface formed on the large diameter side of the land, and a semiconductor element mounting surface is provided on the other surface side. The multilayer wiring board according to any one of claims 1 to 4, wherein the multilayer wiring board is provided.
JP2009294435A 2009-12-25 2009-12-25 Multilayer wiring board Active JP5355380B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009294435A JP5355380B2 (en) 2009-12-25 2009-12-25 Multilayer wiring board
US12/975,703 US8952270B2 (en) 2009-12-25 2010-12-22 Multilayer wiring board having lands with tapered side surfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009294435A JP5355380B2 (en) 2009-12-25 2009-12-25 Multilayer wiring board

Publications (3)

Publication Number Publication Date
JP2011134957A JP2011134957A (en) 2011-07-07
JP2011134957A5 true JP2011134957A5 (en) 2012-12-13
JP5355380B2 JP5355380B2 (en) 2013-11-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009294435A Active JP5355380B2 (en) 2009-12-25 2009-12-25 Multilayer wiring board

Country Status (2)

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US (1) US8952270B2 (en)
JP (1) JP5355380B2 (en)

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JP2014075515A (en) * 2012-10-05 2014-04-24 Shinko Electric Ind Co Ltd Wiring board and wiring board manufacturing method
JP2014120651A (en) * 2012-12-18 2014-06-30 Toppan Printing Co Ltd Laminated wiring board, and method for manufacturing the same
JP2014127623A (en) 2012-12-27 2014-07-07 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
JP2015082524A (en) * 2013-10-21 2015-04-27 ソニー株式会社 Wiring board and semiconductor device
KR102472945B1 (en) * 2015-04-23 2022-12-01 삼성전기주식회사 Printed circuit board, semiconductor package and method of manufacturing the same
US9659853B2 (en) * 2015-04-24 2017-05-23 Advanced Semiconductor Engineering, Inc. Double side via last method for double embedded patterned substrate
JP6816964B2 (en) 2016-03-10 2021-01-20 新光電気工業株式会社 Manufacturing method of wiring board, semiconductor device and wiring board
JP6615701B2 (en) 2016-06-24 2019-12-04 新光電気工業株式会社 WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
KR102530322B1 (en) 2018-12-18 2023-05-10 삼성전자주식회사 Semiconductor package
CN114080088B (en) * 2020-08-10 2024-05-31 鹏鼎控股(深圳)股份有限公司 Circuit board and preparation method thereof

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US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
JPH08116174A (en) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd Circuit formation board and manufacture thereof
JP3112059B2 (en) * 1995-07-05 2000-11-27 株式会社日立製作所 Thin film multilayer wiring board and method of manufacturing the same
US6240636B1 (en) * 1998-04-01 2001-06-05 Mitsui Mining & Smelting Co., Ltd. Method for producing vias in the manufacture of printed circuit boards
US6810583B2 (en) * 2001-08-07 2004-11-02 International Business Machines Corporation Coupling of conductive vias to complex power-signal substructures
JP2003158379A (en) 2001-11-19 2003-05-30 Kyocera Corp Multi-layer wiring board
JP2003298240A (en) * 2002-04-05 2003-10-17 Sohwa Corporation Multilayer circuit board
JP2005072328A (en) 2003-08-26 2005-03-17 Kyocera Corp Multilayer wiring board
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JP5407667B2 (en) * 2008-11-05 2014-02-05 株式会社村田製作所 Semiconductor device

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