JP2011129963A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit for achieving control of an I/O circuit stably operating without using power-on procedures only with a digital circuit restraining an increase in a circuit size, without requiring any tuning. <P>SOLUTION: A signal generated by a signal generator 113 is converted to signal amplitude of a supply voltage Vcc2 by a level shift circuit 111. Then, the signal converted to the signal amplitude of Vcc2 is converted to signal amplitude of an internal supply voltage Vcc1 by a level shift circuit 112 again to generate a feedback signal. A comparator 114 logically compares the original signal generated by the signal generator 113 with the feedback signal generated through the two level shifts. When the original signal does not coincide with the feedback signal, it is regarded that a power supply of Vcc2 has been interrupted, and control is performed to prevent unstable propagation in the I/O circuit 115. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device having an input / output circuit for passing a signal to a peripheral device operating at a power supply voltage different from an internal voltage, a level shift circuit, and a set device incorporating the semiconductor integrated circuit device. is there.

  In recent years, in a semiconductor integrated circuit device, it is necessary to exchange signals with semiconductor integrated circuit devices constituting a plurality of peripheral devices. The plurality of semiconductor integrated circuit devices may operate with individual power supply voltages, and the input / output circuit of the semiconductor integrated circuit device needs to operate with the power supply voltage of the connected device.

  On the other hand, since the internal circuit operates at a low power supply voltage for high integration and low power consumption, a level shift circuit that mutually converts signal amplitude is provided between the input and output circuits. ing. However, due to differences in the power-on sequence and rise time of the internal circuit and the input / output circuit, the input / output signal becomes an indefinite level, and a large through current flows in the input / output circuit that receives it or a voltage collision occurs. There is a problem of causing element destruction.

  Even when the power supply of the input / output circuit is cut off while the internal circuit is operating, the undefined input from the input / output circuit propagates to the internal circuit, and the same problem occurs.

  Conventionally, as a solution to this problem, the power supply detection circuit is used to measure the power supply level applied to the input / output circuit, and the input / output circuit is controlled to prevent indefinite propagation from the input / output circuit. (For example, refer to Patent Document 1).

When the power supply voltage of the input / output circuit reaches a specified level, the control signal from the power supply detection circuit enables the indeterminate propagation prevention part of the level shifter circuit provided in the input / output circuit, and indefinite propagation to the internal circuit Is preventing.
JP 2005-286675 A

  However, in the conventional configuration, the power supply detection circuit is used to monitor the power supply status from the input / output circuit, and the input / output circuit is controlled so as to prevent indefinite propagation, so the normal power supply detection circuit uses an analog circuit. And has a problem that the circuit scale becomes large and hinders downsizing of the apparatus.

  In addition, due to the characteristics of the analog circuit, tuning of the detection voltage is necessary to obtain the expected detection signal, and the characteristics change depending on various factors of the operating environment such as voltage and temperature. It had the subject that it was unsuitable for control of.

  The present invention solves the above-described conventional problems, and realizes the control of the input / output circuit with only the digital circuit, suppresses the increase in circuit scale, and eliminates the need for tuning, and is stable regardless of the power-on procedure. An object of the present invention is to provide a semiconductor integrated circuit device that performs the above operation.

  In order to solve the above-described conventional problems, a semiconductor integrated circuit device of the present invention includes a signal generator that generates a signal to be supplied to a first level shift circuit, and a signal output from the signal generator as a first power supply voltage. The corresponding signal amplitude is input to a first level shift circuit that converts the signal amplitude into a signal amplitude corresponding to the second power supply voltage, and the signal amplitude corresponding to the second power supply voltage is converted from the signal output from the first level shift circuit to the first power supply. A comparator for comparing an output signal from the second level shift circuit generated by inputting to the second level shift circuit that converts the signal amplitude to a voltage corresponding to the voltage and a signal output from the signal generator; When the two input signal levels do not match, the comparator outputs a control signal to prevent indefinite propagation.

  Here, the signal generator may be any circuit as long as it generates an arbitrary waveform in which regular or irregular H intervals and L intervals appear. Specifically, for example, a timer is used. A circuit, a counter circuit, an oscillation circuit, or the like can be used. The level shift circuit may be any circuit as long as it can transfer signal levels and logic between different power supplies, and specifically, a transformer, a relay circuit, or the like can be used.

  According to the semiconductor integrated circuit device of the present invention configured as described above, only the digital circuit, such as the level shift circuit, the signal generator, and the comparator, which is hardly affected by the conditions such as the operating voltage and the operating temperature is used. The control signal for preventing indefinite propagation of signals can be generated, so that the circuit scale can be minimized and the semiconductor integrated circuit device can operate stably regardless of the power-on sequence of the internal power supply and peripheral circuits. Can be made possible. Even when only the operating power supply voltage of the peripheral circuit is cut off while the internal circuit and the peripheral circuit are operating, the semiconductor integrated circuit device can operate stably. In this case, the power consumption of the entire set is reduced. It is possible to contribute.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a schematic block diagram of a semiconductor integrated circuit device according to the first embodiment of the present invention.
In the figure, signals are exchanged with a semiconductor integrated circuit device of a peripheral circuit device operating at an operating power supply voltage Vcc2 different from the operating power supply voltage Vcc1 of the internal circuit via an input / output circuit formed in the I / O region. I do.

  Reference numeral 111 denotes a first level shift circuit for converting the signal 101 having the signal amplitude of the power supply voltage Vcc1 generated by the internal circuit into a signal having the signal amplitude of the power supply voltage Vcc2. Reference numeral 112 denotes a second level shift circuit that converts a signal having the signal amplitude of the power supply voltage Vcc2 into a signal having the signal amplitude of the power supply voltage Vcc1. The first level shift circuit 111 and the second level shift circuit 112 operate with two power supply voltages Vcc1 and Vcc2 in order to perform the level conversion operation as described above. The first level shift circuit 111 and the second level shift circuit 112 are connected by a signal line 102. In addition, the first level shift circuit 111 is supplied with a reset signal RST having a signal amplitude of the power supply voltage Vcc2. In the present embodiment, Vcc1 and Vcc2 may be different voltages or the same voltage.

  A signal generator 113 provided in the internal circuit outputs a predetermined signal and supplies a signal to the first level shifter 111 and the comparator 114 via the signal line 101. In the present embodiment, the predetermined signal is a signal in which both the H section and the L section appear regularly or irregularly. The signal generator 113 may be an oscillation circuit or a counter circuit.

  Reference numeral 114 denotes a comparator that compares the signal 103 output from the second level shift circuit 112 with the signal 101 output from the signal generator 113. The comparator 114 compares each signal to confirm that a predetermined condition is satisfied. The control signal 104 for controlling the input / output circuit 115 is generated. The second level shift circuit 112 and the comparator 114 are connected by a signal line 103, and the signal line 103 is connected to Vcc1 through a pull-up resistor 116. The pull-up resistor 116 can be a pull-down resistor. Note that the predetermined condition may be a case where the exclusive OR of the signal 103 and the signal 101 does not match, or a condition generated by a combination of AND, OR, and NOT logic.

  An input / output circuit 115 transmits a signal generated in the internal circuit to the semiconductor integrated circuit device of the peripheral circuit device, and conversely transmits a signal received from the semiconductor integrated circuit device of the peripheral circuit device to the internal circuit. In addition, the input / output circuit 115 performs the level conversion operation in the same manner as the IO buffer for storing the signal transferred to and from the semiconductor integrated circuit device of the peripheral circuit device, and the first level shift circuit 111 and the second level shift circuit 112. A first IO level shift circuit and a second IO level shift circuit are provided. That is, the first IO level shift circuit is a level shift circuit that converts a signal having the signal amplitude of the power supply voltage Vcc1 generated in the internal circuit into a signal having the signal amplitude of the power supply voltage Vcc2, and the second IO level. The shift circuit is a level shift circuit that converts a signal having the signal amplitude of the power supply voltage Vcc2 into a signal having the signal amplitude of the power supply voltage Vcc1. A reset signal RST having a signal amplitude of the power supply voltage Vcc2 is input to the first IO level shift circuit and the second IO level shift circuit. Note that in this embodiment, the number of the input / output circuits 115 may be one, or two or more. Vcc1 and Vcc2 may be different from each other or the same voltage. Further, the reset signal RST may be a signal generated in the I / O region or a signal input from the outside.

  FIG. 2 is a waveform diagram for explaining an example of the operation of the semiconductor integrated circuit device of FIG. In the figure, the internal power supply voltage Vcc1 rises and the power supply voltage Vcc2 rises with a delay. The reset signal RST is released after the internal circuit is stabilized, and is released immediately after the internal power supply voltage Vcc1 rises. When the power supply voltage is supplied in this order, the first level shift circuit 111 and the second level shift circuit 112 are not operating because the power supply voltage Vcc2 is not supplied in the period T1, and the signal line 103 is not operated. Is fixed to the same potential as internal power supply voltage Vcc1 through pull-up resistor 116. Therefore, the signal 101 output from the signal generator 113 and the signal 103 are not equal, and the control signal 104 for preventing indefinite propagation in the input / output circuit 115 is set, and indefinite propagation can be prevented. In the period T2, the supply of the power supply voltage Vcc starts, and the first level shift circuit 111 and the second level shift circuit 112 operate. Therefore, the signal 101 and the signal 103 output from the signal generator 113 become equal, and the control signal 104 that prevents indefinite propagation in the input / output circuit 115 is canceled.

  FIG. 3 shows a state in which the power supply voltage Vcc2 rises and the internal power supply voltage Vcc1 rises with a delay. The reset signal RST is released after the internal circuit is stabilized, and is released immediately after the internal power supply voltage Vcc1 rises. When the power supply voltage is supplied in this order, the internal power supply Vcc1 is not supplied in the interval T1, and the comparator 113 that generates the control signal 104 that prevents indefinite propagation in the input / output circuit 115 is operating. However, since the reset signal RST is in the reset state until Vcc1 rises, indefinite propagation from the input / output circuit is prevented. In the period T2, the internal power supply voltage Vcc1 rises, the reset signal RST is released, and the signal generator 113 and the comparator 114 are operated. Therefore, the signal 101 output from the signal generator 113 and the first level shift It is determined that the signal 103 via the circuit 111 and the second level shift circuit 112 are equal, and the control signal 104 for preventing indefinite propagation in the input / output circuit 115 is canceled.

  FIG. 4 is a waveform diagram for explaining an example of the operation of the semiconductor integrated circuit device of FIG. The power supply voltage Vcc2 is lowered during the operation, and the internal power supply voltage Vcc1 is delayed and the power supply is shut off. When the power supply is shut off in this order, the power supply voltage Vcc2 is not supplied during the period T1, so the operations of the first level shift circuit 111 and the second level shift circuit 112 are stopped, and the signal line 103 is pulled up. It is fixed at the same potential as internal power supply voltage Vcc1 through resistor 116. For this reason, the signal 101 output from the signal generator 113 and the signal 103 are not equal, and the control signal 104 for preventing indefinite propagation in the input / output circuit 115 is set to prevent indefinite propagation and perform stable operation. be able to.

  When the power supply voltage Vcc2 is supplied again during the period T1, the internal power supply voltage Vcc1 rises and the power supply voltage Vcc2 rises with a delay as shown in the example of the operation in FIG. Operation can be performed.

(Embodiment 2)
FIG. 5 is a schematic block diagram of the semiconductor integrated circuit device according to the second embodiment of the present invention. Since the input / output circuit and the like are the same as those in the first embodiment, they are omitted.

  Reference numeral 517 denotes a control circuit that switches ON / OFF of the pull-up resistor 516. The control signal 505 is generated in response to the signal 504 that is the comparison result of the comparator 514. During the period in which the comparator 514 determines that the signal 503 and the signal 501 are not equal, the pull-up control circuit 517 turns on the pull-up resistor 516 in the same manner as in the first embodiment, and the second level shift circuit 512 When indefinite is output, indefinite propagation to the comparator 514 can be prevented. On the contrary, during the period when the signal 503 and the signal 501 are determined to be equal, the pull-up control circuit 517 turns off the pull-up resistor 516, and the output of the second level shift circuit 512 passes through the pull-up resistor 516 to It is possible to prevent a short circuit with the power supply voltage Vcc1. In this embodiment, the ON / OFF switching control is used as the control of the pull-up resistor 516. However, the flowing current can be suppressed by the control of changing the resistance value. In this embodiment, the output signal 504 of the comparator 514 is used for pull-up control. However, the output signal 501 of the signal generator 513 may be used, or the output signal 503 of the second level shift circuit 512 is used. Alternatively, it may be a signal generated by an internal circuit. In addition, the same effect can be obtained by using a pull-down resistor as the pull-up resistor.

(Embodiment 3)
FIG. 6 is a schematic block diagram showing an example of a digital video camera incorporating the semiconductor integrated circuit device according to the first embodiment of the present invention.

  Reference numeral 618 denotes a CCD image sensor, which is a device having a function of digitizing optical information of the outside world that has passed through the lens 619 and taking it into a digital video camera. Although a CCD image sensor is used in the present embodiment, a CMOS image sensor may be used.

  A hard disk device 620 records data digitized by the CCD image sensor 618 and results processed by an internal circuit. In this embodiment, a hard disk is used as a recording medium. However, not only a hard disk but also a non-volatile memory such as an SD card or a compact flash may be used, or recording may be performed on an optical disk medium such as a CD / DVD. It may be the structure which records, and the structure which records on magnetic tape media, such as a DV tape, may be sufficient.

  Reference numeral 621 denotes a liquid crystal display capable of reproducing data recorded on the hard disk device 620. In this embodiment, a liquid crystal display is used, but an organic EL display or a plasma display may be used.

  Reference numeral 625 denotes a microcomputer including the configuration of the first embodiment of the present invention.

  Reference numeral 610 denotes a communication path extending in the set. The signal line 607 is connected to the CCD image sensor 618, the signal line 608 is connected to the hard disk device 620, the signal line 609 is connected to the liquid crystal display 621, and the microcomputer 625 is connected. Each signal line 606 is connected to the communication path 610. Note that in this embodiment, the communication path 610 is configured to share the communication path 610 in the signal transfer between the CCD image sensor 618, the hard disk device 620, the liquid crystal display 621, and the microcomputer 625, but each device is individually connected. The communication path may be configured, the communication path capable of communicating in only one direction may be configured, or the communication path capable of bidirectional communication may be configured.

  Reference numeral 622 denotes a first power supply device that supplies a power supply voltage Vcc1 to the internal circuit and I / O area of the microcomputer 625. Reference numeral 624 denotes a second power supply device that supplies the power supply voltage Vcc2 to the CCD image pickup device 618, the hard disk device 620, and the liquid crystal display 621. It is a power supply device.

  Reference numeral 623 denotes a power supply control device capable of individually controlling ON / OFF of the first power supply device 622 and the second power supply device 624. Control by the power supply control device 623 such as turning on only the first power supply device 622 or turning off only the second power supply device 624 when both the first power supply device 622 and the second power supply device 624 are turned on. It can be performed.

  In particular, when both the first power supply device 622 and the second power supply device 624 are turned on by the power supply control device 623, only the second power supply device 624 is turned off. Since the microcomputer 625 as a constituent element can prevent indefinite propagation inside, the power source of the CCD image sensor 618, the hard disk device 620, and the liquid crystal display 621 can be shut off while maintaining a stable operation. As a whole digital video camera, power consumption can be suppressed.

  The present invention relates to a semiconductor integrated circuit device having an input / output circuit for passing a signal to a peripheral device operating at a power supply voltage different from the internal voltage and a level shift circuit, and turning on / off the internal voltage and the power supply voltage of the peripheral device. This is useful in realizing a semiconductor integrated circuit device that performs stable operation without limiting the order. Also, by mounting and using the semiconductor integrated circuit device in the set device, it is possible to contribute to the reduction in power consumption of the entire set device.

1 is a schematic block diagram showing a first embodiment of a semiconductor integrated circuit device according to the present invention. 1 is a waveform diagram showing an example of a state in which the internal power supply voltage Vcc1 rises and the power supply voltage Vcc2 rises with a delay in the operation of the semiconductor integrated circuit device of FIG. 1 is a waveform diagram showing an example of a state in which the power supply voltage Vcc2 rises and the internal power supply voltage Vcc1 rises with a delay in the operation of the semiconductor integrated circuit device of FIG. In the operation of the semiconductor integrated circuit device of FIG. 1, a waveform diagram showing an example when the power supply voltage Vcc2 falls during operation and the internal power supply voltage Vcc1 falls after a delay. Schematic block diagram showing a second embodiment of a semiconductor integrated circuit device according to the present invention. 1 is a schematic block diagram showing an embodiment of a set circuit incorporating a semiconductor integrated circuit device according to the present invention.

Explanation of symbols

111,511 First level shift circuit 112,512 Second level shift circuit 113,513 Signal generator 114,514 Comparator 115,515 Input / output circuit 517 Pull-up control circuit 610 Communication path 618 CCD image sensor 619 Lens 620 Hard disk device 621 Liquid crystal display 622 1st power supply device 623 Power supply control device 624 2nd power supply device

Claims (5)

An internal circuit using the first power supply voltage as an operating voltage;
The second power supply voltage that is higher than the first power supply voltage is used as the operating voltage,
A first IO level shift circuit that converts a signal amplitude corresponding to the first power supply voltage into a signal amplitude corresponding to the second power supply voltage, and converts a signal amplitude corresponding to the second power supply voltage into a signal amplitude corresponding to the first power supply voltage. An input / output circuit including a second IO level shift circuit that
A first level shift circuit that converts a signal amplitude corresponding to the first power supply voltage into a signal amplitude corresponding to the second power supply voltage;
A second level shift circuit that converts a signal amplitude corresponding to the second power supply voltage into a signal amplitude corresponding to the first power supply voltage;
A signal generator for generating a signal to be supplied to the first level shift circuit;
In order to generate a control signal for controlling the input / output circuit, a signal output from the signal generator is input to the first level shift circuit, and a signal output from the first level shift circuit is input to the second level shift circuit. A comparator that compares the output signal from the second level shift circuit generated by inputting to the level shift circuit with the signal output from the signal generator;
When the signal output from the second level shift circuit becomes an indeterminate signal, a pull-up resistor, the first IO level shift circuit, the second IO level shift circuit, and the first to prevent indefinite input to the comparator The one-level shift circuit includes a level conversion unit that performs signal amplitude conversion, and an indefinite propagation prevention unit that includes a gate circuit that receives the output signal of the level conversion unit, the control signal, and the reset signal. A semiconductor integrated circuit device. In claim 1,
A semiconductor integrated circuit device comprising a circuit in which the pull-up resistor can be switched ON or OFF according to the output of the comparator. In claim 1,
A semiconductor integrated circuit device comprising a pull-down resistor instead of a pull-up resistor. In claim 3,
A semiconductor integrated circuit device comprising a circuit in which the pull-down resistor can be switched ON or OFF according to the output of the comparator. A digital video camera using the semiconductor integrated circuit device according to claim 1, 2, 3, or 4 as a part of a system.