JP2011119472A - Semiconductor manufacturing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus that suppresses the quantity of warpage in a substrate by forming a film having an internal stress only on the rear surface of the substrate without damaging the front surface thereof and consistently applies film formation to the rear surface and pattern formation to the front surface. <P>SOLUTION: The semiconductor manufacturing apparatus includes a chemical application section 102 for applying chemical to a substrate, a heating treatment section 104 for heating the substrate, a resist coating section 107 for coating a resist on the front surface of the substrate, an exposure section 105 for exposing a specified pattern in the resist, and a developing section 108 for developing the resist to form the specified pattern. The chemical application section 102 is provided with a chemical application means that applies chemical only to the rear surface of the substrate while the substrate is floated and rotated, and the heating treatment section 104 is provided with a heat treatment means that heat treats the substrate to form a stress application film having the internal stress, thus performing consistently the formation of both the stress application film on the rear surface and the specified pattern on the front surface. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing apparatus, and more particularly to a semiconductor manufacturing apparatus including means for forming a film on the back surface of a semiconductor substrate.

  Conventionally, speeding up of semiconductor devices has been advanced by miniaturization of transistor shapes. However, in recent years, advances in lithography technology have stopped, and there is a technique for increasing the mobility of carriers in the inversion layer serving as the channel or the relative dielectric constant of the gate insulating film, rather than improving the on-current of the transistor by miniaturization. Attention has been paid.

  A gate insulating film used for a CMOS (complementary metal oxide semiconductor) device is generally a silicon oxide film and has a dielectric constant of about 3.9. However, when the gate insulating film is made thinner with the miniaturization of the transistor, the leakage current increases, and the device has high power consumption and standby power. Therefore, a gate insulating film having a dielectric constant of 4.0 or more is used, and an equivalent oxide thickness (EOT) which is an effective film thickness is obtained even if the actual film thickness is thicker than the silicon oxide film. Development of a high-k gate insulating film that can be thinned is in progress.

  However, if a conventional polysilicon gate electrode and a high-k gate insulating film are combined, a depletion layer is formed between the high-k gate insulating film and the polysilicon gate electrode due to a phenomenon called depletion of the gate electrode. Since the capacitance is formed, the advantage of the high-k gate insulating film with a thin EOT is lost. Therefore, in order to prevent depletion of the gate electrode, a combination of the high-k gate insulating film and the metal gate electrode is essential, and proper threshold voltage control by the high-k gate insulating film and the metal gate electrode is required for the CMOS. This is an important issue in building devices.

  In the study of the work function in the combination of the high-k gate insulating film and the metal gate electrode, titanium, tungsten, tantalum and molybdenum, and nitrides and carbides thereof are used. However, since both have large internal stresses in units of gigapascal (GPa), the warpage of the semiconductor substrate when performing gate lithography cannot be ignored.

  Lithography technology for reducing the length of gates and the like has a shallower depth of focus as the resolution is improved, and it is necessary to introduce a new technology for steps due to elements formed on the semiconductor substrate and warping of the semiconductor substrate. It has become.

  The immersion exposure technology, which is the current mainstream microlithography technology, uses ultrapure water (n = 1.3), which has a higher refractive index than air (n = 1.0), between the semiconductor substrate and the lens. By satisfying this, the depth of focus is increased (see, for example, Patent Document 1).

  Further, the focus monitoring system is used to adjust the focus for each chip, thereby canceling the influence of the warp of the semiconductor substrate (see, for example, Patent Document 2).

  In recent years, a technique for increasing the speed of a transistor by increasing the mobility of carriers by applying strain to a channel region has been reported.

  There is an example in which a silicon nitride film having a film stress is formed as a contact liner film in order to introduce strain into the channel region (see, for example, Patent Document 3). That is, when a contact hole is formed in the interlayer insulating film by etching, stress is applied to the channel region by the liner film formed as an etch stop film. More specifically, when a silicon nitride film having a film stress is used as a liner film, a silicon nitride film having a tensile stress is formed for nMOS, and a silicon nitride film having a compressive stress is formed for pMOS. To do.

  In order to further improve the carrier mobility using this method, the strain applied to the channel region may be increased by increasing the thickness of the liner film. In many cases, a silicon nitride film used for nMOS is a method in which tensile stress is generated by causing film shrinkage by a post-deposition process.

  It is also known that when the thickness of the liner film is increased, the liner film has a multilayer structure. In this case, film shrinkage may be performed for each layer. A multilayered structure of the liner film is presented in, for example, Patent Document 4 and the like.

  Further, in order to effectively give strain to the channel region, a larger strain can be applied as a film having a large stress approaches the channel region. A method of forming a liner film having stress after removing the sidewall by the disposable sidewall technique is proposed in Patent Document 5 and the like.

JP 2004-289126 A JP 2006-195353 A JP 2003-060076 A Japanese Patent No. 3050193 JP 2008-091536 A

  When adopting a structure of a metal gate electrode having a large internal stress and a high-k insulating film, a fine line-shaped gate lithography having a width of 32 nm or less is formed after a transistor is formed, a strain applying film is formed, It must be done with the semiconductor substrate warped. Further, it is required to form hole-shaped contact lithography on a wafer surface having a diameter of 300 mm without deviation from the base active region and the gate region.

  In order to eliminate the warpage of the semiconductor substrate, a method of forming a film having an internal stress on the semiconductor substrate can be considered. However, when a conventional chemical vapor deposition (CVD) method and a wet etching method are used, In addition, the surface on which the transistor or the like is formed may be damaged.

  In addition, when a strain is applied to the channel region of the transistor, since a film having stress is formed on the surface of the semiconductor substrate on which the transistor is formed, a thick film cannot be formed depending on the distance between the transistors. Stress cannot be applied to the channel region. Furthermore, when the stress film is selectively formed in the nMOS and the pMOS, a process for forming a film and a process for not forming a film are required, and the mask cost and the number of processes are enormous. Cost-effectiveness against

  In view of the above-described conventional problems, the object of the present invention is to form a film having internal stress only on the back surface of the semiconductor substrate, thereby suppressing the amount of warping of the semiconductor substrate, and in doing so damages the surface of the semiconductor substrate. Therefore, a semiconductor manufacturing apparatus that consistently performs film formation on the back surface of the semiconductor substrate and pattern formation on the front surface of the semiconductor substrate can be obtained.

  Furthermore, in the process of applying strain to the channel region, when the density of the transistors is improved and a thick stress applying film cannot be formed on the surface of the semiconductor substrate, a thick stress applying film is formed on the back surface where the transistor is not formed. An object is to improve the driving capability of the transistor.

  In order to achieve the above object, the present invention has a configuration in which a semiconductor manufacturing apparatus has means for applying a chemical only to the back surface of a semiconductor substrate.

  Specifically, a semiconductor manufacturing apparatus according to the present invention includes a chemical solution application unit that applies a chemical solution to a semiconductor substrate, a heat treatment unit that heats the semiconductor substrate, a resist application unit that applies a resist to the surface of the semiconductor substrate, and an application An exposure unit that exposes a predetermined pattern on the resist and a development unit that obtains the predetermined pattern by developing the exposed resist, and the chemical solution application unit floats the semiconductor substrate in a state where the semiconductor substrate is suspended. It has a chemical solution application means for applying a chemical solution only to the back surface of the semiconductor substrate while rotating, and the heat treatment unit has a heat treatment means for forming a stress application film having internal stress by performing a heat treatment on the semiconductor substrate. The present invention is characterized in that the stress applying film is formed on the back surface of the semiconductor substrate and the process of forming a predetermined pattern on the surface of the semiconductor substrate is performed consistently.

  According to the semiconductor manufacturing apparatus according to the present invention, since the film having the internal stress is formed on the entire back surface of the semiconductor substrate without contaminating the surface of the semiconductor substrate, warping of the semiconductor substrate can be suppressed. It is possible to improve overlay in the lithography process and reduce pattern formation defects.

  The semiconductor manufacturing apparatus according to the present invention sequentially calculates a coating thickness of a chemical solution that is optimal for correcting the warpage amount based on a measurement means that measures the warpage amount of the semiconductor substrate and the warpage amount measured by the measurement means. It is preferable to further include an arithmetic means for performing the above.

  In this way, since the film thickness of the film formed on the semiconductor substrate can be determined in accordance with the warpage amount of the semiconductor substrate, the warpage amount can be controlled to be constant.

  In the semiconductor manufacturing apparatus according to the present invention, the chemical solution preferably contains polysilazane and has a viscosity coefficient of 0.5 Pa · s or more and 1.5 Pa · s or less.

  In this case, the stress application film is preferably a silicon nitride film.

  Furthermore, in this case, the heat treatment means is preferably means for performing heat treatment on the semiconductor substrate at 450 ° C. or more and 550 ° C. or less in a nitrogen gas atmosphere or under reduced pressure.

  In this case, the internal stress of the stress application film is preferably −100 MPa or less.

In this case, the film density of the stress application film is preferably 2.0 g / cm ³ or more.

  According to the semiconductor manufacturing apparatus according to the present invention, the pattern formation on the surface of the semiconductor substrate and the film formation having the internal stress on the back surface of the semiconductor substrate can be performed consistently without contaminating the surface of the semiconductor substrate. Since warpage of the semiconductor substrate can be suppressed, it is possible to improve overlay accuracy and reduce pattern formation defects in the lithography process. In addition, since stress can be applied to the channel region of the transistor, the performance of the transistor can be improved.

It is a mimetic diagram showing the composition of the semiconductor manufacturing device concerning a 1st embodiment of the present invention. It is a graph which shows the relationship between the coating film thickness of a polysilazane solution, and the rotational speed of the semiconductor substrate at the time of application | coating. It is a figure showing a process of a method of manufacturing a semiconductor device using a semiconductor manufacturing device concerning a 1st embodiment of the present invention. It is a figure which shows the reaction formula in which silicon nitride is formed from polysilazane. It is a graph which shows the relationship between the curvature amount of a semiconductor substrate, and the overlay accuracy of a gate and an active region. (A) And (b) is sectional drawing which shows the method of manufacturing a semiconductor device using the semiconductor manufacturing apparatus concerning the 2nd Embodiment of this invention in order of a process. It is a graph which shows the relationship between annealing atmosphere and annealing temperature in the internal stress of polysilazane. It is a graph which shows the magnitude | size of the drive current of an n-type transistor at the time of forming a silicon nitride film in the back surface of a semiconductor substrate using the semiconductor manufacturing apparatus concerning the 2nd Embodiment of this invention.

(First embodiment)
A semiconductor manufacturing apparatus according to a first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor manufacturing apparatus according to the first embodiment of the present invention includes a warpage measuring device 101, a polysilazane coating chamber 102, a hot plate 103, an annealing chamber 104, an exposure unit 105, a chill plate 106, a resist. A coating module 107 and a developer 108 are provided.

  In the warpage amount measuring device 101, for example, the amount of warpage of the semiconductor substrate is measured using the reflection of the laser and the focus position of the lens. Based on the measured amount of warpage, the optimum polysilazane coating thickness is sequentially calculated to correct the measured amount of warpage to a predetermined amount based on the previously evaluated polysilazane coating thickness and warpage correction. .

  In the polysilazane coating chamber 102, polysilazane is coated on the back surface of the semiconductor substrate while rotating the semiconductor substrate. Here, it is preferable to use perhydropolysilazane as the polysilazane. When this is used, a silicon nitride film can be formed at a temperature of about 400 ° C. to 800 ° C. However, other silazane polymers may be used. In order to apply polysilazane to the back surface of the semiconductor substrate, it is necessary to invert the semiconductor substrate and hold the surface thereof. For example, a Bernoulli chuck is used to float and hold the surface of the semiconductor substrate. Further, when polysilazane is applied, the coating thickness of the polysilazane can be controlled by controlling the rotation speed of the semiconductor substrate. Details of this will be described later.

  In the hot plate 103, a semiconductor substrate coated with polysilazane having a predetermined film thickness is baked at a high temperature. Thereby, the solvent contained in the coating solution is volatilized. The baking temperature is desirably between 150 ° C and 250 ° C.

In the annealing chamber 104, an annealing process under reduced pressure is performed on the semiconductor substrate subjected to the above process. The annealing chamber 104 is a single wafer type or a batch type, and it is preferable to perform an annealing process in a nitrogen gas atmosphere or under a reduced pressure without flowing a gas at 400 ° C. to 800 ° C. Since this annealing treatment forms a silicon nitride film only on the back surface of the semiconductor substrate, warping of the semiconductor substrate is eliminated or suppressed. In addition, the formed silicon nitride film can prevent metal contamination from the back surface of the semiconductor substrate in a wiring process performed later. In this case, the film density of the formed silicon nitride film is preferably 2.0 g / cm ³ or more.

  The exposure unit 105 performs an exposure process on the semiconductor substrate on which the resist is applied by the resist application module 107. Since the warpage of the semiconductor substrate is eliminated or suppressed by the silicon nitride film formed on the back surface of the semiconductor substrate, occurrence of pattern formation defects and misalignment is further suppressed. Before applying the resist, hexamethyldisilazane (HMDS) may be applied in order to improve the wettability between the surface of the semiconductor substrate and the resist.

  In the chill plate 106, the semiconductor substrate is cooled after exposure by the exposure unit 105. In the chill plate 106, the semiconductor may be cooled between the resist application and the exposure.

  Development is performed in the developer 108.

  By performing a series of measurements from the warpage measuring instrument 101 to the developer 108, forming a silicon nitride film on the back surface of the semiconductor substrate, and performing an exposure process, it is possible to form a pattern with high accuracy and a process with high processing capability. Become.

  Here, control of the polysilazane coating thickness will be described. Due to the rotation of the semiconductor substrate during the application of polysilazane, the polysilazane solution receives centrifugal force and scatters from the outer periphery of the semiconductor substrate. However, a slight amount of polysilazane solution remains between the polysilazane solution and the surface of the semiconductor substrate due to the action of viscosity and surface tension. When the application and rotation are stopped, the remaining polysilazane solution is re-formed almost uniformly on the surface of the semiconductor substrate by surface tension. As a result, a thin film of polysilazane solution is formed on the surface of the semiconductor substrate.

  As shown in FIG. 2, the centrifugal force is increased by increasing the rotation speed of the semiconductor substrate, and the amount of the polysilazane solution remaining without scattering from the outer periphery of the semiconductor substrate is reduced. As a result, it is formed from the polysilazane solution. The film thickness is reduced. That is, the film thickness of polysilazane can be controlled by controlling the rotation speed.

  Next, a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 3, first, the warpage amount of the semiconductor substrate is measured by the warpage amount measuring device 101. The optimum polysilazane film thickness for correcting the warpage amount to a predetermined amount is calculated from the measurement result of the warpage amount and the previously evaluated polysilazane coating film thickness and warpage amount correction data.

  Next, polysilazane is applied to the back surface of the semiconductor substrate by the polysilazane coating chamber 102. Here, in the film formation, the calculated coating thickness of the optimum polysilazane is formed by controlling the rotation speed of the semiconductor substrate after coating.

  The polysilazane to be applied is contained in a solvent so that it can be applied in a liquid state on the back surface of the semiconductor substrate. The solvent is mainly composed of an organic component, and acts as an impurity when polysilazane is converted into a silicon nitride film. For this reason, after uniformly applying polysilazane by coating, it is necessary to volatilize the solvent by baking.

  As the solvent, it is desirable to use an organic solvent having a low boiling point and DBE (registered trademark) developed by Du Pont. In order to apply polysilazane having a uniform film thickness to the back surface of the semiconductor substrate, the viscosity coefficient of the chemical solution in which polysilazane is dissolved is preferably 0.5 Pa · s or more and 1.5 Pa · s or less. In addition, the boiling point of the solvent is desirably 300 ° C. or lower so that the solvent can be removed by subsequent baking.

  The polysilazane is applied using a single wafer type spin coater. Conventionally, a batch type or single wafer type chemical vapor deposition (CVD) apparatus is used for forming a silicon nitride film on the back surface of a semiconductor substrate. However, in a batch type CVD apparatus, there are variations in temperature and gas density depending on the position in the batch furnace, resulting in variations in the thickness of the silicon nitride film, which makes it difficult to control the thickness sufficiently. Further, the throughput is insufficient in a single wafer type CVD apparatus.

  Next, the applied polysilazane solvent is removed by baking the semiconductor substrate, for example, at 150 to 200 ° C. using the hot plate 103. The film thickness of the polysilazane becomes thinner by removing the solvent and further increasing the density by heat compared to before this treatment. The most important factor for correcting the warpage amount of the semiconductor substrate is the product of the stress and the film thickness, and the film thickness is an important parameter. For this reason, it is necessary to optimize the film thickness by applying and baking polysilazane.

Next, the annealing process is performed on the semiconductor substrate by the annealing chamber 104. FIG. 4 is a reaction formula showing polysilazane on the left side and silicon nitride on the right side. As shown in FIG. 4, polysilazane is a polymer having (—SiH ₂ NH—) as a basic skeleton. When polysilazane is annealed at a high temperature of 400 ° C. to 800 ° C. in a nitrogen atmosphere or under reduced pressure, hydrogen is released and a silicon nitride film is obtained.

  Next, exposure for pattern formation is performed on the surface of the semiconductor substrate. First, HMDS is applied to improve the wettability between the surface of the semiconductor substrate and the resist. Next, a resist is applied to the surface of the semiconductor substrate by the resist application module 107. Here, the resist may be a single layer or a multilayer. After applying the resist, exposure is performed by the exposure unit 105, but heating by the hot plate 103 and cooling by the chill plate 106 may be performed before the exposure. After the exposure, development is performed by the developer 108 to form a pattern forming mask.

  FIG. 5 shows the relationship between the amount of warpage of the semiconductor substrate and the overlay accuracy between the gate and the active region. In the amount of warpage of the semiconductor substrate, 0 or more indicates warpage that has a convex shape upward, and 0 or less indicates upward. The warpage which becomes a concave shape is shown. As shown in FIG. 5, when the warp of the semiconductor substrate is convex, the overlay accuracy is poor, and when the warp amount of the semiconductor substrate is 0, the overlay accuracy is the best. Further, it is expected that the overlay accuracy deteriorates as the warp of the semiconductor substrate becomes concave, but in FIG. 5, only the warp amount up to 30 μm can be obtained in the concave shape, and the deterioration of the overlay accuracy is observed. Was not.

  According to the semiconductor manufacturing apparatus according to the first embodiment of the present invention, from the measurement of the amount of warpage of the semiconductor substrate to the formation of a film having a film thickness based on the measurement result on the back surface of the semiconductor substrate, the pattern formation on the surface of the semiconductor substrate is consistent. By controlling the amount of warpage of the semiconductor substrate without contaminating the surface, the lithography overlay accuracy can be improved. Further, by forming a silicon nitride film on the back surface of the semiconductor substrate, metal contamination from the back surface of the semiconductor substrate in the wiring process can be prevented.

  Although the present result shows the result of the overlay accuracy of the transistor gate and the active region that require the highest accuracy, the same result can be obtained by lithography in the contact hole forming process and the wiring process.

(Second Embodiment)
In a transistor having a MIS (Metal Insulator Semiconductor) structure and a MIPS (Metal Inserted Polysilicon Stack) structure, a strain applying technique is used to improve transistor performance. This is a technique for improving carrier mobility by applying stress strain to a semiconductor substrate. For example, electron mobility is improved by applying strain due to tensile stress in the gate length direction for an n-type transistor formed on a semiconductor substrate made of silicon whose principal plane is the (100) plane. As a result, the driving power of the transistor increases. At this time, strain due to tensile stress is also applied to the p-type transistor side, but if a semiconductor substrate with a plane orientation of (100) is used, the strain is canceled to the orientation of the silicon lattice, so the mobility of holes is reduced. It is possible to maintain without deteriorating. In addition, as a method for imparting strain due to tensile stress and compressive stress to a transistor, a so-called stress memorization technique (SMT) method in which stress strain is stored in a channel region in an active region forming the transistor, There is a method called.

  In this method, a silicon nitride film or a silicon oxide film is formed on the gate and source / drain regions, and after activation annealing of the source / drain regions, the film is removed. When the heat treatment is performed in a state where the silicon lattice of the semiconductor substrate is distorted by the stress of the silicon nitride film or the like, the lattice is stabilized in the distorted state. Even if the silicon nitride film or silicon oxide film formed on the transistor is removed, the strain state of the silicon lattice is preserved. Since the electron mobility is determined by the interatomic distance of the lattice, the effect of the film stress remains until the subsequent process, and the stress is stored. The present embodiment is a method of manufacturing a semiconductor device in which a silicon nitride film is not formed on the surface of a semiconductor substrate, but is formed on the back side, and strain is applied to or stored in a transistor as in the SMT method. is there.

  Hereinafter, a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus according to the second embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 6A, an element isolation region 202 is formed in a semiconductor substrate 201 whose principal surface has a (100) plane orientation by using a shallow trench isolation (STI) method. . Thereby, the n-type transistor region A and the p-type transistor region B are partitioned, and an n-type transistor and a p-type transistor are formed by a known technique. That is, in the n-type transistor region A, the first active region 203a and the p-type well 204a are formed in the semiconductor substrate 201, and the first gate insulating film 205a and the n-type gate electrode are formed on the first active region 203a. 206a are sequentially formed. At the same time, in the p-type transistor region B, the second active region 203b and the n-type well 204b are formed in the semiconductor substrate 201, and the second gate insulating film 205b and the p-type gate electrode are formed on the second active region 203b. 206b are sequentially formed. Next, the first sidewall film 207a is formed on the side surface of the n-type gate electrode 206a, and the second sidewall film 207b is formed on the side surface of the p-type gate electrode 206b. For example, the first gate insulating film 205a and the second gate insulating film 205b are silicon oxide films or silicon oxynitride films, the n-type gate electrode 206a and the p-type gate electrode 206b are polysilicon films, The first sidewall film 207a and the second sidewall film 207b are silicon oxide films. Thereafter, an n-type extension region 208a is formed in the first active region 203a by implanting an n-type impurity using the n-type gate electrode 206a and the first sidewall film 207a as a mask. In the second active region 203b, a p-type extension region 208b is formed by implanting p-type impurities using the p-type gate electrode 206b and the second sidewall film 207b as a mask.

  Next, the first sidewall 211a is formed on the side surface of the first sidewall film 207a, and the second sidewall 211b is formed on the side surface of the second sidewall film 207b. Here, the first side wall 211a and the second side wall 211b are silicon oxide films, and the first inner side wall 209a and the second inner side wall 209b having an L-shaped cross section are formed on the first side wall 211a and the second inner side wall 209b. The first outer side wall 210a and the second outer side wall 210b are respectively formed of silicon nitride films formed.

  Next, arsenic (As), which is an n-type impurity, is selectively implanted into the first active region 203a, whereby an n-type source / drain region is formed outside the first sidewall 211a in the first active region 203a. 212a is formed. Further, boron (B) is selectively implanted into the second active region 203b, thereby forming the p-type source / drain region 212b outside the second sidewall 211b in the second active region 203b.

  Next, as shown in FIG. 6B, the semiconductor substrate 201 is heat-treated at about 1050 ° C. for 1 ms to 10 s to activate the source / drain implantation region and the gate polysilicon implantation region. To do. Thereafter, a metal silicide layer 214 is formed on each of the n-type source / drain region 212a, the n-type gate electrode 206a, the p-type source / drain region 212b, and the p-type gate electrode 206b.

  Thereafter, a silicon nitride film having tensile stress is formed on the surface of the transistor, and strain is applied to the channel region under the gate insulating film of the transistor. A silicon epitaxial film having a carbon ratio of 1% to 3% may be formed on the n-type source / drain region 212a of the n-type transistor. At this time, if the thickness of the silicon nitride film on the surface of the transistor is increased, the amount of strain that can be applied to the channel region increases. However, if the distance between the transistors is reduced due to miniaturization and higher integration, the thickness is increased. However, the thickness of the silicon nitride film is set depending on the distance between the transistors.

  Therefore, the tensile stress on the surface side can be improved by forming an insulating film having a compressive stress in the direction opposite to that of the silicon nitride film on the front surface of the semiconductor substrate 201 on which the transistor is not formed. That is, a silicon nitride film 213 made of polysilazane as a raw material is formed on the back surface of the semiconductor substrate 201 using the semiconductor manufacturing apparatus according to the present invention. In the present embodiment, in order to realize an effect equivalent to the formation of a film having a tensile stress on the surface of the semiconductor substrate 201 using the compressive stress from the back surface of the semiconductor substrate 201, the first It is desirable to form a silicon nitride film thicker than the thickness of the silicon nitride film that eliminates the warp of the semiconductor substrate 201 in this embodiment.

  FIG. 7 shows the magnitude of the film stress of the silicon nitride film formed at each temperature when polysilazane is applied to the surface of the semiconductor substrate 201 and then heat-treated in nitrogen or water vapor. Here, in general (scientifically), the stress is 0 or more indicates a tensile stress, and 0 or less indicates a compressive stress.

  As shown in FIG. 7, when the polysilazane film is heat-treated in water vapor, when the temperature of the heat treatment is increased, the stress value is reversed from tensile stress to compressive stress at about 850 ° C.

  Since the metal silicide layer 214 has poor heat resistance, it is difficult to perform heat treatment at 500 ° C. or higher for nickel silicide and 800 ° C. or higher for cobalt silicide. Therefore, heat treatment is performed in water vapor to form a compressive stress film. Is difficult.

  When heat treatment is performed in nitrogen, compressive stress is obtained at about 500 ° C., and tensile stress is exhibited at 600 ° C. or higher. Therefore, after applying polysilazane to the back surface of the semiconductor substrate 201, a silicon nitride film 213 having compressive stress is formed on the back surface of the semiconductor substrate 201 by applying a heat treatment at 450 ° C. or more and 550 ° C. or less in a nitrogen atmosphere. be able to. Here, in order to realize an effect equivalent to forming a film having tensile stress on the surface of the semiconductor substrate 201, the internal stress of the silicon nitride film 213 formed on the back surface of the semiconductor substrate 201 is −100 MPa or less. Preferably there is. Since no transistor is formed on the back surface of the semiconductor substrate 201, there is no limitation on the film thickness as in the surface of the semiconductor substrate 201 on which the transistor is formed. The amount of distortion increases.

  After that, although not shown, an interlayer insulating film is formed on the semiconductor substrate 201, planarized, and then contact plugs and wirings are formed to complete the semiconductor device.

  As described above, by using the n-type MIS transistor capable of improving the tensile stress in the gate length direction in the channel region in the first active region 203a and the (100) silicon substrate for the semiconductor substrate 201, the second active region 203b. Thus, a semiconductor device including a p-type MIS transistor in which no stress is generated in the channel region can be obtained.

  FIG. 8 shows the relationship between the on-state current and the off-state current of the n-type transistor when a silicon nitride film having a thickness of 150 nm is formed on the back surface of the semiconductor substrate 201 by the above method and when the silicon nitride film is not formed. Is shown. As shown in FIG. 8, for example, when compared with an off current of 1000 pA / μm, the driving ability is improved by 9.7% from 820 μA / μm to 900 μA / μm.

  As described above, according to the semiconductor manufacturing apparatus according to the second embodiment of the present invention, it is possible to apply a large strain to the channel region without damaging the surface of the semiconductor substrate. Can be improved.

  The semiconductor manufacturing apparatus according to the present invention can improve overlay and reduce pattern formation defects in a lithography process, and is particularly useful for a semiconductor manufacturing apparatus provided with means for forming a film on the back surface of a semiconductor substrate.

101 Warpage measuring device 102 Polysilazane coating chamber (chemical solution coating unit)
103 Hot plate 104 Annealing chamber (heat treatment part)
105 Exposure unit 106 Chill plate 107 Resist application module (resist application unit)
108 Developer (Developer)
201 Semiconductor substrate 202 Element isolation region 203a First active region 203b Second active region 204a p-type well 204b n-type well 205a first gate insulating film 205b second gate insulating film 206a n-type gate electrode 206b p-type gate Electrode 207a First sidewall film 207b Second sidewall film 208a n-type extension region 208b p-type extension region 209a first inner sidewall 209b second inner sidewall 210a first outer sidewall 210b second outer side Wall 211a First sidewall 211b Second sidewall 212a n-type source / drain region 212b p-type source / drain region 213 Silicon nitride film 214 Metal silicide layer

Claims (7)

A chemical application part for applying a chemical to a semiconductor substrate;
A heat treatment unit for heating the semiconductor substrate;
A resist coating section for coating a resist on the surface of the semiconductor substrate;
An exposure unit that exposes a predetermined pattern to the applied resist;
A developing unit that obtains the predetermined pattern by developing the exposed resist;
The chemical solution application unit has chemical solution application means for applying a chemical solution only to the back surface of the semiconductor substrate while rotating the semiconductor substrate in a state where the semiconductor substrate is floated,
The heat treatment unit has a heat treatment means for forming a stress application film having an internal stress by performing a heat treatment on the semiconductor substrate,
A semiconductor manufacturing apparatus characterized by consistently performing the formation of the stress applying film on the back surface of the semiconductor substrate and the process of forming the predetermined pattern on the surface of the semiconductor substrate. Measuring means for measuring the amount of warpage of the semiconductor substrate;
2. The apparatus according to claim 1, further comprising a calculation unit that sequentially calculates an optimum coating thickness of the chemical solution for correcting the warp amount based on the warp amount measured by the measuring unit. The semiconductor manufacturing apparatus as described.   The semiconductor manufacturing apparatus according to claim 1, wherein the chemical solution includes polysilazane and has a viscosity coefficient of 0.5 Pa · s to 1.5 Pa · s.   The semiconductor manufacturing apparatus according to claim 3, wherein the stress applying film is a silicon nitride film.   The semiconductor manufacturing apparatus according to claim 4, wherein the heat treatment means is a means for performing heat treatment on the semiconductor substrate at 450 ° C. or more and 550 ° C. or less in a nitrogen gas atmosphere or under reduced pressure.   The semiconductor manufacturing apparatus according to claim 4, wherein an internal stress of the stress application film is −100 MPa or less. The semiconductor manufacturing apparatus according to claim 4, wherein a film density of the stress application film is 2.0 g / cm ³ or more.

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