JP2011119305A - Element mounting substrate, semiconductor module, semiconductor device, method for manufacturing the semiconductor device, and portable device - Google Patents

Element mounting substrate, semiconductor module, semiconductor device, method for manufacturing the semiconductor device, and portable device Download PDF

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JP2011119305A
JP2011119305A JP2009272854A JP2009272854A JP2011119305A JP 2011119305 A JP2011119305 A JP 2011119305A JP 2009272854 A JP2009272854 A JP 2009272854A JP 2009272854 A JP2009272854 A JP 2009272854A JP 2011119305 A JP2011119305 A JP 2011119305A
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insulating layer
opening
layer
semiconductor device
solder
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Seiji Shibata
清司 柴田
Mayumi Nakazato
真弓 中里
Masayuki Nagamatsu
正幸 長松
Ryosuke Usui
良輔 臼井
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide an element mounting substrate which is improved in connection reliability with a connecting member such as solder. <P>SOLUTION: The semiconductor module 10 has a PoP structure in which an electrode area 148 of a first wiring layer 140 provided on a first element mounting substrate 110 constituting a first semiconductor module 100 and a fourth wiring layer 242 provided on a second semiconductor module 200 are joined together by a solder ball 270. A first insulating layer 150 having an opening for exposing a drawing area of the first wiring layer 140 is provided on one main surface of an insulating resin layer 130, and a second insulating layer 152 is provided on the first insulating layer 150 so as to expose the opening of the first insulating layer. The opening diameter of the opening at a lower surface portion of the second insulating layer 152 is larger than the opening diameter of the opening at an upper surface portion of the first insulating layer 150. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体素子を搭載するための素子搭載用基板、当該素子搭載用基板を有する半導体モジュール、半導体装置および携帯機器に関する。   The present invention relates to an element mounting board for mounting a semiconductor element, a semiconductor module having the element mounting board, a semiconductor device, and a portable device.

近年、電子機器の小型化、高機能化に伴い、電子機器に使用される半導体装置のさらなる小型化、高密度化が求められている。このような要求に応えるべく、パッケージの上にパッケージを搭載したパッケージオンパッケージ（ＰｏＰ）と呼ばれる三次元パッケージング技術などの半導体モジュール積層技術が広く知られている。   In recent years, along with the downsizing and high functionality of electronic devices, there has been a demand for further downsizing and higher density of semiconductor devices used in electronic devices. In order to meet such requirements, semiconductor module stacking technology such as three-dimensional packaging technology called package-on-package (PoP) in which a package is mounted on a package is widely known.

半導体モジュールを積層する場合には、下側の半導体モジュールの基板上に設けられた電極パッドと上側の半導体モジュールの裏面に設けられた電極パッドとをはんだボールなどの接合部材を用いて接続する方法が採られる。はんだボールによる接続構造は、たとえば、特許文献１に示されている。   When stacking semiconductor modules, a method of connecting electrode pads provided on the substrate of the lower semiconductor module and electrode pads provided on the back surface of the upper semiconductor module by using a joining member such as a solder ball Is taken. A connection structure using solder balls is disclosed in Patent Document 1, for example.

無電解Ｎｉめっきで被覆された電極パッドにはんだボールを接合する場合、無電解Ｎｉめっき膜内にはＰが数％混入しているため、はんだ接合時にＰを含む金属間化合物が形成される。Ｐを含む金属間化合物は強度が低いため、はんだ接合強度の低下を招く。このの対策として、特許文献１では、無電解Ｎｉめっき膜中にＰを含有しない純Ｎｉめっき層を電極上などに形成している。   When solder balls are joined to electrode pads covered with electroless Ni plating, P is mixed in the electroless Ni plating film, so that an intermetallic compound containing P is formed during solder joining. Since the intermetallic compound containing P has low strength, the solder joint strength is reduced. As a countermeasure against this, in Patent Document 1, a pure Ni plating layer not containing P is formed on an electrode or the like in an electroless Ni plating film.

特開２００８−０４２０７１号公報JP 2008-042071 A

特許文献１に記載されたように、電極パッドに純Ｎｉめっき層を形成する場合には、特殊なめっき液が必要となり、コスト増を招くという問題がある。また、電極パッドの上にはんだボールを単に接合した構造では、接合強度が十分とはいえず、改良の余地が残されている。   As described in Patent Document 1, when a pure Ni plating layer is formed on an electrode pad, there is a problem that a special plating solution is required and the cost is increased. Further, in the structure in which the solder ball is simply bonded on the electrode pad, the bonding strength is not sufficient, and there is still room for improvement.

本発明はこうした課題に鑑みてなされたものであり、その目的は、素子搭載用基板においてはんだなどの接続部材との接続信頼性を向上させることのできる技術の提供にある。   This invention is made | formed in view of such a subject, The objective is to provide the technique which can improve the connection reliability with connection members, such as solder, in an element mounting board | substrate.

本発明のある態様は、素子搭載用基板である。当該素子搭載用基板は、基材と、基材の一方の主表面に設けられている配線層と、配線層を被覆するように設けられ、配線層の電極領域が露出する第１の開口部を有する第１の絶縁層と、第１の絶縁層の上に設けられ、第１の開口部が露出するような第２の開口部を有する第２の絶縁層と、を備え、第２の絶縁層の下面部分における第２の開口部の開口径が、第１の絶縁層の上面部分における第１の開口部の開口径より大きいことを特徴とする。   One embodiment of the present invention is an element mounting substrate. The element mounting substrate includes a base material, a wiring layer provided on one main surface of the base material, and a first opening that is provided so as to cover the wiring layer and exposes an electrode region of the wiring layer. And a second insulating layer provided on the first insulating layer and having a second opening that exposes the first opening. The opening diameter of the second opening in the lower surface portion of the insulating layer is larger than the opening diameter of the first opening in the upper surface portion of the first insulating layer.

この態様によれば、はんだなどの電気接続部材を電極領域に接続した場合に、電気接続部材と電極領域との接合部分が第１の絶縁層の開口部内にあるため、この部分に応力が加わった場合に、第１の絶縁層および第２の絶縁層が緩衝部材として機能することにより応力が緩和される。これにより、電気接続部材と電極領域との接続信頼性を向上させることができる。   According to this aspect, when an electrical connection member such as solder is connected to the electrode region, since the joint portion between the electrical connection member and the electrode region is in the opening of the first insulating layer, stress is applied to this portion. In this case, the stress is relieved by the first insulating layer and the second insulating layer functioning as a buffer member. Thereby, the connection reliability of an electrical connection member and an electrode area | region can be improved.

この態様の素子搭載用基板において、第２の絶縁層は、第２の開口部内の側面のうち少なくとも第２の絶縁層の上面近傍の側面が、第２の絶縁層の上面に近くなるほど第２の開口部の内側にせり出すように構成されていてもよい。第１の絶縁層の上面部分における第１の開口部の開口径が第１の絶縁層の下面部分における第１の開口部の開口径より小さくてもよい。また、第２の絶縁層の厚さが第１の絶縁層の厚さより厚くてもよい。この態様の素子搭載用基板は、パッケージオンパッケージ構造を有する半導体装置に用いられてもよい。   In the element mounting substrate according to this aspect, the second insulating layer includes a second insulating layer such that at least a side surface in the vicinity of the upper surface of the second insulating layer among the side surfaces in the second opening is closer to the upper surface of the second insulating layer. You may be comprised so that it may protrude inside the opening part. The opening diameter of the first opening in the upper surface portion of the first insulating layer may be smaller than the opening diameter of the first opening in the lower surface portion of the first insulating layer. Further, the thickness of the second insulating layer may be larger than the thickness of the first insulating layer. The element mounting substrate of this aspect may be used for a semiconductor device having a package-on-package structure.

本発明の他の態様は半導体モジュールである。当該半導体モジュールは、上述した態様の素子搭載用基板と、基材の一方の主表面側に搭載された半導体素子と、を備えることを特徴とする。   Another embodiment of the present invention is a semiconductor module. The semiconductor module includes the element mounting substrate according to the aspect described above and a semiconductor element mounted on one main surface side of the base material.

本発明のさらに他の態様は半導体装置である。当該半導体装置は、上述した態様の半導体モジュールと、その半導体モジュールに積層される積層体と、有する半導体装置であって、電極領域と積層体の電極領域とを電気的に接続する電気接続部材を備え、電気接続部材が第１の開口部および第２の開口部に充填され、第２の絶縁層の上面近傍の縁部が電気接続部材の内部に食い込んでいることを特徴とする。   Still another embodiment of the present invention is a semiconductor device. The semiconductor device is a semiconductor device having the semiconductor module of the above-described aspect, a stacked body stacked on the semiconductor module, and an electrical connection member that electrically connects the electrode region and the electrode region of the stacked body. The electrical connection member is filled in the first opening and the second opening, and an edge portion near the upper surface of the second insulating layer bites into the electrical connection member.

この態様の半導体装置において、第１の絶縁層の上面近傍の縁部が電気接続部材の内部に食い込んでいてもよい。   In the semiconductor device of this aspect, the edge portion near the upper surface of the first insulating layer may bite into the electrical connection member.

本発明のさらに他の態様は携帯機器である。当該携帯機器は、上述した態様の半導体装置が実装されたことを特徴とする。   Yet another embodiment of the present invention is a portable device. The portable device is characterized in that the above-described semiconductor device is mounted.

本発明のさらに他の態様は、半導体装置の製造方法である。当該半導体装置の製造方法は、上述した態様の素子搭載用基板を用意する工程と、第１の絶縁層に設けられた第１の開口部に第１のはんだ部材の少なくとも一部を載置し、第１のはんだ部材と配線層の電極領域とを接触させる工程と、第１のはんだ部材より径が大きい第２のはんだ部材を第１のはんだ部材の上方に載置し、第１のはんだ部材と第２のはんだ部材とを接触させる工程と、第１のはんだ部材および第２のはんだ部材を溶融させて、電極領域とよび前記第２のはんだ部材を溶融させて、前記電極領域と他の基板に設けられた電極領域とを電気的に接続する電気接続部材を形成する工程と、を備えることを特徴とする。   Yet another embodiment of the present invention is a method for manufacturing a semiconductor device. In the method of manufacturing the semiconductor device, the element mounting substrate having the above-described aspect is prepared, and at least a part of the first solder member is placed in the first opening provided in the first insulating layer. A step of bringing the first solder member into contact with the electrode region of the wiring layer, and placing a second solder member having a diameter larger than that of the first solder member above the first solder member, A step of bringing the member into contact with the second solder member, melting the first solder member and the second solder member, melting the electrode region and the second solder member, and the electrode region and the like Forming an electrical connection member that electrically connects the electrode region provided on the substrate.

なお、上述した各要素を適宜組み合わせたものも、本件特許出願によって特許による保護を求める発明の範囲に含まれうる。   A combination of the above-described elements as appropriate can also be included in the scope of the invention for which protection by patent is sought by this patent application.

本発明によれば、素子搭載用基板において、はんだなどの接続部材との接続信頼性を向上させることができる。   ADVANTAGE OF THE INVENTION According to this invention, connection reliability with connection members, such as solder, can be improved in the element mounting substrate.

実施の形態１に係る半導体装置の構成を示す概略断面図である。1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. 図２（Ａ）〜（Ｃ）は、実施の形態１に係る半導体装置の製造方法を示す工程断面図である。2A to 2C are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図３（Ａ）〜（Ｂ）は、実施の形態１に係る半導体装置の製造方法を示す工程断面図である。3A to 3B are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図４（Ａ）〜（Ｂ）は、実施の形態１に係る半導体装置の製造方法を示す工程断面図である。4A to 4B are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 第１の素子搭載用基板上にはんだボールを設置する方法を示す図である。It is a figure which shows the method of installing a solder ball on the board | substrate for 1st element mounting. 実施の形態２に係る携帯電話の構成を示す図である。6 is a diagram showing a configuration of a mobile phone according to Embodiment 2. FIG. 携帯電話の部分断面図である。It is a fragmentary sectional view of a mobile phone.

以下、本発明の実施の形態を図面を参照して説明する。なお、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

（実施の形態１）
図１は、実施の形態１に係る半導体装置１０の構成を示す概略断面図である。半導体装置１０は、第１の半導体モジュール１００の上に第２の半導体モジュール２００が積層されたＰｏＰ（Ｐａｃｋａｇｅ Ｏｎ Ｐａｃｋａｇｅ）構造を有する。 (Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device 10 according to the first embodiment. The semiconductor device 10 has a PoP (Package On Package) structure in which a second semiconductor module 200 is stacked on a first semiconductor module 100.

第１の半導体モジュール１００は、第１の素子搭載用基板１１０に第１の半導体素子１２０が実装された構成を有する。   The first semiconductor module 100 has a configuration in which a first semiconductor element 120 is mounted on a first element mounting substrate 110.

第１の素子搭載用基板１１０は、基材となる絶縁樹脂層１３０と、絶縁樹脂層１３０の一方の主表面に形成された第１の配線層１４０、第１の絶縁層１５０、第２の絶縁層１５２と、絶縁樹脂層１３０の他方の主表面に形成された第２の配線層１４２、第３の絶縁層１５４とを含む。   The first element mounting substrate 110 includes an insulating resin layer 130 serving as a base material, a first wiring layer 140 formed on one main surface of the insulating resin layer 130, a first insulating layer 150, a second Insulating layer 152, second wiring layer 142 formed on the other main surface of insulating resin layer 130, and third insulating layer 154 are included.

絶縁樹脂層１３０としては、たとえば、ＢＴレジン等のメラミン誘導体、液晶ポリマー、エポキシ樹脂、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の熱硬化性樹脂で形成することができる。   The insulating resin layer 130 can be formed of a thermosetting resin such as a melamine derivative such as BT resin, a liquid crystal polymer, an epoxy resin, a PPE resin, a polyimide resin, a fluororesin, a phenol resin, or a polyamide bismaleimide.

絶縁樹脂層１３０の一方の主表面（本実施の形態では、半導体素子搭載面）に所定パターンの第１の配線層１４０が設けられている。第１の配線層１４０は、銅などの導体で形成され、外部接続端子用の電極領域１４８および第１の素子搭載用基板１１０に搭載される電子部品の接続端子用の電極領域１４９を有する。電極領域１４８は、主に、第１の配線層１４０の引き回し先の端部に設けられる。第１の配線層１４０の電極領域１４８の表面には、後述するように金めっき層１６６が形成されている。なお、金めっき層１６６は、「電極領域」あるいは「電極パッド」の一部を構成する。   A first wiring layer 140 having a predetermined pattern is provided on one main surface of the insulating resin layer 130 (in this embodiment, a semiconductor element mounting surface). The first wiring layer 140 is formed of a conductor such as copper and has an electrode region 148 for external connection terminals and an electrode region 149 for connection terminals of electronic components mounted on the first element mounting substrate 110. The electrode region 148 is mainly provided at an end portion of the first wiring layer 140 that is routed. A gold plating layer 166 is formed on the surface of the electrode region 148 of the first wiring layer 140 as described later. The gold plating layer 166 constitutes a part of the “electrode region” or “electrode pad”.

絶縁樹脂層１３０の所定位置において絶縁樹脂層１３０を貫通するビア導体（図示せず）が設けられている。ビア導体は、たとえば、銅めっきにより形成される。ビア導体により、第１の配線層１４０の所定領域と第２の配線層１４２とが電気的に接続されている。   A via conductor (not shown) penetrating the insulating resin layer 130 is provided at a predetermined position of the insulating resin layer 130. The via conductor is formed by, for example, copper plating. A predetermined region of the first wiring layer 140 and the second wiring layer 142 are electrically connected by the via conductor.

絶縁樹脂層１３０の一方の主表面に第１の絶縁層１５０が設けられている。第１の絶縁層１５０は、第１の配線層１４０を被覆するように設けられており、第１の配線層１４０の電極領域１４８が露出する開口部１５１を有する。また、第１の絶縁層１５０は、第１の配線層１４０の電極領域１４９が露出する開口部１５３を有する。この開口部１５３において、第１の配線層１４０の電極領域１４９の表面にＮｉ／Ａｕ層などの金めっき層１４１が形成されている。第１の配線層１４０の電極領域１４９は金めっき層１４１で被覆されることにより酸化が抑制される。金めっき層１４１としてＮｉ／Ａｕ層を形成する場合には、Ｎｉ層の厚さは、たとえば約１μｍ〜約１５μｍであり、Ａｕ層の厚さは、たとえば約０．０３〜約１μｍである。   A first insulating layer 150 is provided on one main surface of the insulating resin layer 130. The first insulating layer 150 is provided so as to cover the first wiring layer 140 and has an opening 151 through which the electrode region 148 of the first wiring layer 140 is exposed. Further, the first insulating layer 150 has an opening 153 through which the electrode region 149 of the first wiring layer 140 is exposed. In the opening 153, a gold plating layer 141 such as a Ni / Au layer is formed on the surface of the electrode region 149 of the first wiring layer 140. The electrode region 149 of the first wiring layer 140 is covered with the gold plating layer 141, whereby oxidation is suppressed. When a Ni / Au layer is formed as the gold plating layer 141, the thickness of the Ni layer is, for example, about 1 μm to about 15 μm, and the thickness of the Au layer is, for example, about 0.03 to about 1 μm.

第２の絶縁層１５２は、開口部１５１周縁の第１の絶縁層１５０の上面が露出するように、第１の絶縁層１５０の上に積層されている。言い換えると、開口部１５１の上方において、第２の絶縁層１５２の下面部分における開口部１５５の開口径が、第１の絶縁層１５０の上面部分における開口部１５１の開口径より大きい。また、第２の絶縁層１５２は、開口部１５５内の側面のうち少なくとも第２の絶縁層１５２の上面近傍の側面が、第２の絶縁層１５２の上面に近くなるほど開口部１５５の内側にせり出すような逆テーパ状に構成されている。   The second insulating layer 152 is laminated on the first insulating layer 150 so that the upper surface of the first insulating layer 150 at the periphery of the opening 151 is exposed. In other words, above the opening 151, the opening diameter of the opening 155 in the lower surface portion of the second insulating layer 152 is larger than the opening diameter of the opening 151 in the upper surface portion of the first insulating layer 150. The second insulating layer 152 protrudes to the inside of the opening 155 so that at least a side surface in the vicinity of the upper surface of the second insulating layer 152 is closer to the upper surface of the second insulating layer 152 among the side surfaces in the opening 155. It is configured in such a reverse taper shape.

なお、本実施の形態では、第２の絶縁層１５２は、電極領域１４８の周囲のみならず、絶縁樹脂層１３０の周縁に沿って堤防状に設けられている。すなわち、第２の絶縁層１５２で囲まれた領域が凹部（キャビティ）となっており、このキャビティに後述する第１の半導体素子１２０が搭載されている。   In the present embodiment, the second insulating layer 152 is provided in a bank shape along the periphery of the insulating resin layer 130 as well as around the electrode region 148. That is, a region surrounded by the second insulating layer 152 is a recess (cavity), and the first semiconductor element 120 described later is mounted in this cavity.

第１の絶縁層１５０および第２の絶縁層１５２は、たとえば、フォトソルダーレジストにより形成される。第２の絶縁層１５２の厚さは、第１の絶縁層１５０の厚さより厚いことが好ましい。第１の絶縁層１５０の厚さは、たとえば約４０μｍである。また、第２の絶縁層１５２の厚さは、たとえば約１００μｍである。   The first insulating layer 150 and the second insulating layer 152 are formed by, for example, a photo solder resist. The thickness of the second insulating layer 152 is preferably larger than the thickness of the first insulating layer 150. The thickness of the first insulating layer 150 is about 40 μm, for example. The thickness of the second insulating layer 152 is, for example, about 100 μm.

開口部１５１内において、電極領域１４８の表面にＮｉ／Ａｕ層などの金めっき層１６６が形成されている。金めっき層１６６により電極領域１４８の酸化が抑制される。金めっき層１６６としてＮｉ／Ａｕ層を形成する場合には、Ｎｉ層の厚さは、たとえば約１μｍ〜約１５μｍであり、Ａｕ層の厚さは、たとえば約０．０３〜約１μｍである。なお、金めっき層１６６にはんだボール２７０が接合された状態では、金めっき層１６６からＡｕが拡散し、金めっき層１６６中でＡｕが確認できない場合がある。   A gold plating layer 166 such as a Ni / Au layer is formed on the surface of the electrode region 148 in the opening 151. The gold plating layer 166 suppresses oxidation of the electrode region 148. When a Ni / Au layer is formed as the gold plating layer 166, the thickness of the Ni layer is, for example, about 1 μm to about 15 μm, and the thickness of the Au layer is, for example, about 0.03 to about 1 μm. Note that in a state where the solder balls 270 are joined to the gold plating layer 166, Au may diffuse from the gold plating layer 166, and Au may not be confirmed in the gold plating layer 166.

絶縁樹脂層１３０の他方の主表面に所定パターンの第２の配線層１４２が設けられている。第２の配線層１４２の表面には、金めっき層１４４が設けられている。第１の配線層１４０および第２の配線層１４２を構成する材料としては銅が挙げられる。第１の配線層１４０および第２の配線層１４２の厚さは、たとえば２０μｍである。   A second wiring layer 142 having a predetermined pattern is provided on the other main surface of the insulating resin layer 130. A gold plating layer 144 is provided on the surface of the second wiring layer 142. An example of a material constituting the first wiring layer 140 and the second wiring layer 142 is copper. The thickness of the first wiring layer 140 and the second wiring layer 142 is, for example, 20 μm.

また、絶縁樹脂層１３０の他方の主表面に第３の絶縁層１５４が設けられている。第３の絶縁層１５４には、第２の配線層１４２にはんだボール８０を搭載するための開口部が設けられている。はんだボール８０は、第３の絶縁層１５４に設けられた開口内において第２の配線層１４２の電極領域と接続されている。   A third insulating layer 154 is provided on the other main surface of the insulating resin layer 130. The third insulating layer 154 is provided with an opening for mounting the solder ball 80 on the second wiring layer 142. The solder ball 80 is connected to the electrode region of the second wiring layer 142 in the opening provided in the third insulating layer 154.

以上説明した第１の素子搭載用基板１１０に形成された第１の絶縁層１５０の半導体素子搭載領域の上に第１の半導体素子１２０が搭載されている。第１の半導体素子１２０に設けられた素子電極（図示せず）と第１の配線層１４０の電極領域上の金めっき層１４１とが金線１２１によりワイヤボンディング接続されている。なお、第１の半導体素子１２０の具体例としては、集積回路（ＩＣ）、大規模集積回路（ＬＳＩ）などの半導体チップが挙げられる。   The first semiconductor element 120 is mounted on the semiconductor element mounting region of the first insulating layer 150 formed on the first element mounting substrate 110 described above. An element electrode (not shown) provided on the first semiconductor element 120 and a gold plating layer 141 on the electrode region of the first wiring layer 140 are wire-bonded by a gold wire 121. Note that specific examples of the first semiconductor element 120 include a semiconductor chip such as an integrated circuit (IC) or a large-scale integrated circuit (LSI).

封止樹脂層１８０は、第１の半導体素子１２０およびこれに接続された金めっき層１４１を封止している。封止樹脂層１８０は、たとえばエポキシ樹脂を用いて、トランスファーモールド法により形成される。   The sealing resin layer 180 seals the first semiconductor element 120 and the gold plating layer 141 connected thereto. The sealing resin layer 180 is formed by transfer molding using, for example, an epoxy resin.

第２の半導体モジュール２００は、第２の素子搭載用基板２１０に第２の半導体素子２２０が搭載された構成を有する。   The second semiconductor module 200 has a configuration in which the second semiconductor element 220 is mounted on the second element mounting substrate 210.

第２の素子搭載用基板２１０は、基材となる絶縁樹脂層２３０と、絶縁樹脂層２３０の一方の主表面に形成された第３の配線層２４０と、絶縁樹脂層２３０の他方の主表面に形成された第４の配線層２４２と、絶縁樹脂層２３０の一方の主表面に形成された第４の絶縁層２５０と、絶縁樹脂層２３０の他方の主表面に形成された第５の絶縁層２５２とを含む。   The second element mounting substrate 210 includes an insulating resin layer 230 serving as a base material, a third wiring layer 240 formed on one main surface of the insulating resin layer 230, and the other main surface of the insulating resin layer 230. The fourth wiring layer 242 formed on the first insulating layer, the fourth insulating layer 250 formed on one main surface of the insulating resin layer 230, and the fifth insulating layer formed on the other main surface of the insulating resin layer 230. Layer 252.

絶縁樹脂層２３０としては、たとえば、ＢＴレジン等のメラミン誘導体、液晶ポリマー、エポキシ樹脂、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の熱硬化性樹脂で形成することができる。   The insulating resin layer 230 can be formed of a thermosetting resin such as a melamine derivative such as BT resin, a liquid crystal polymer, an epoxy resin, a PPE resin, a polyimide resin, a fluororesin, a phenol resin, or a polyamide bismaleimide.

絶縁樹脂層２３０の一方の主表面（半導体素子搭載面）に所定パターンの第３の配線層２４０が設けられている。第３の配線層２４０の電極領域上に金めっき層２４６が形成されている。また、絶縁樹脂層２３０の他方の主表面に第４の配線層２４２が設けられている。第３の配線層２４０および第４の配線層２４２を構成する材料としては銅が挙げられる。第３の配線層２４０および第４の配線層２４２とは、絶縁樹脂層２３０の所定位置において絶縁樹脂層２３０を貫通するビア導体（図示せず）により電気的に接続されている。   A third wiring layer 240 having a predetermined pattern is provided on one main surface (semiconductor element mounting surface) of the insulating resin layer 230. A gold plating layer 246 is formed on the electrode region of the third wiring layer 240. A fourth wiring layer 242 is provided on the other main surface of the insulating resin layer 230. An example of a material constituting the third wiring layer 240 and the fourth wiring layer 242 is copper. The third wiring layer 240 and the fourth wiring layer 242 are electrically connected by a via conductor (not shown) penetrating the insulating resin layer 230 at a predetermined position of the insulating resin layer 230.

絶縁樹脂層２３０の一方の主表面にフォトソルダーレジストなどからなる第４の絶縁層２５０が設けられている。また、絶縁樹脂層２３０の他方の主表面にフォトソルダーレジストなどからなる第５の絶縁層２５２が設けられている。第５の絶縁層２５２には、第４の配線層２４２にはんだボール２７０を搭載するための開口が設けられている。はんだボール２７０は、第５の絶縁層２５２に設けられた開口内において第４の配線層２４２に接続されている。   A fourth insulating layer 250 made of a photo solder resist or the like is provided on one main surface of the insulating resin layer 230. In addition, a fifth insulating layer 252 made of a photo solder resist or the like is provided on the other main surface of the insulating resin layer 230. The fifth insulating layer 252 is provided with an opening for mounting the solder ball 270 on the fourth wiring layer 242. The solder ball 270 is connected to the fourth wiring layer 242 in the opening provided in the fifth insulating layer 252.

以上説明した第２の素子搭載用基板２１０に第２の半導体素子２２０が搭載されている。具体的には、第４の絶縁層２５０の半導体素子搭載領域の上に、第２の半導体素子２２０が搭載されている。第２の半導体素子２２０に設けられた素子電極（図示せず）と所定領域の第３の配線層２４０の電極領域上の金めっき層２４６とが金線２２１によりワイヤボンディング接続されている。なお、第２の半導体素子２２０の具体例としては、集積回路（ＩＣ）、大規模集積回路（ＬＳＩ）などの半導体チップが挙げられる。   The second semiconductor element 220 is mounted on the second element mounting substrate 210 described above. Specifically, the second semiconductor element 220 is mounted on the semiconductor element mounting region of the fourth insulating layer 250. An element electrode (not shown) provided in the second semiconductor element 220 and a gold plating layer 246 on the electrode region of the third wiring layer 240 in a predetermined region are connected by wire bonding with a gold wire 221. Specific examples of the second semiconductor element 220 include semiconductor chips such as an integrated circuit (IC) and a large scale integrated circuit (LSI).

封止樹脂２８０は、第２の半導体素子２２０およびこれに接続された第３の配線層２４０を封止している。封止樹脂２８０は、たとえばエポキシ樹脂を用いて、トランスファーモールド法により形成される。   The sealing resin 280 seals the second semiconductor element 220 and the third wiring layer 240 connected thereto. The sealing resin 280 is formed by a transfer molding method using, for example, an epoxy resin.

第１の半導体モジュール１００の電極領域１４８上の金めっき層１６６と、第２の半導体モジュール２００の第４の配線層２４２の電極領域とが、はんだボール２７０に接合されることにより、第２の半導体モジュール２００が第１の半導体モジュール１００の上方（封止樹脂層１８０の上方）に搭載されたＰｏＰ構造が実現されている。なお、はんだボール２７０は、第１の絶縁層１５０に設けられた開口部１５１および第２の絶縁層１５２に設けられた開口部１５５に充填されている。   The gold plating layer 166 on the electrode region 148 of the first semiconductor module 100 and the electrode region of the fourth wiring layer 242 of the second semiconductor module 200 are joined to the solder ball 270, whereby the second A PoP structure in which the semiconductor module 200 is mounted above the first semiconductor module 100 (above the sealing resin layer 180) is realized. Note that the solder balls 270 are filled in the opening 151 provided in the first insulating layer 150 and the opening 155 provided in the second insulating layer 152.

なお、本実施の形態では、第２の絶縁層１５２の上面近傍の縁部（逆テーパ状のせり出し部分）がはんだボール２７０の内部に食い込んでいる。   In this embodiment mode, an edge portion (an inverted taper protruding portion) near the upper surface of the second insulating layer 152 bites into the solder ball 270.

実施の形態に係る半導体装置１０によれば少なくとも以下に挙げる効果が得られる。   According to the semiconductor device 10 according to the embodiment, at least the following effects can be obtained.

（１）はんだボール２７０と金めっき層１６６との接合部分が第１の絶縁層１５０の開口部１５１内にあるため、この部分に応力が加わった場合に、第１の絶縁層１５０および第２の絶縁層１５２が緩衝部材として機能することにより応力が緩和される。これにより、はんだボール２７０と金めっき層１６６ひいては電極領域１４８との接続信頼性を向上させることができる。   (1) Since the joint portion between the solder ball 270 and the gold plating layer 166 is in the opening 151 of the first insulating layer 150, when stress is applied to this portion, the first insulating layer 150 and the second The insulating layer 152 functions as a buffer member to relieve stress. Thereby, the connection reliability between the solder ball 270 and the gold plating layer 166 and thus the electrode region 148 can be improved.

（２）第２の絶縁層１５２の下面部分における開口部１５５の開口径が、第１の絶縁層１５０の上面部分における開口部１５１の開口径より大きいため、開口部１５１の上方で開口部１５５がステップ状に広がっている。これにより、はんだボール２７０と第１の絶縁層１５０との接触面積が増大するため、はんだボール２７０と第１の絶縁層１５０との密着強度を高めることができる。   (2) Since the opening diameter of the opening 155 in the lower surface portion of the second insulating layer 152 is larger than the opening diameter of the opening 151 in the upper surface portion of the first insulating layer 150, the opening 155 is located above the opening 151. Is spreading in steps. Thereby, the contact area between the solder ball 270 and the first insulating layer 150 is increased, so that the adhesion strength between the solder ball 270 and the first insulating layer 150 can be increased.

（３）第２の絶縁層１５２の上面近傍の縁部がはんだボール２７０の内部に食い込んでいる構造により、はんだボール２７０と第２の絶縁層１５２との接触面積が増大するとともに、アンカー効果が得られるため、はんだボール２７０と第２の絶縁層１５２との密着強度を高めることができる。この効果は、開口部１５５内の側面のうち少なくとも第２の絶縁層１５２の上面近傍の側面が、第２の絶縁層１５２の上面に近くなるほど開口部１５５の内側にせり出す逆テーパ構造を取ることによりさらに顕著となる。また、この効果は、第１の絶縁層１５０の上面近傍の縁部がはんだボール２７０の内部に食い込む構造によっても得られる。なお、図示しないが、第１の絶縁層１５０の上面部分における開口部１５１の開口径が第１の絶縁層１５０の下面部分における開口部１５１の開口径より小さくすることにより、第１の絶縁層１５０の上面近傍の縁部をはんだボール２７０の内部に食い込みやすくすることができる。   (3) The structure in which the edge near the upper surface of the second insulating layer 152 bites into the interior of the solder ball 270 increases the contact area between the solder ball 270 and the second insulating layer 152 and increases the anchor effect. Thus, the adhesion strength between the solder ball 270 and the second insulating layer 152 can be increased. This effect is that an inverted taper structure is adopted in which at least the side surface in the vicinity of the upper surface of the second insulating layer 152 of the side surface in the opening 155 protrudes to the inside of the opening 155 as the surface approaches the upper surface of the second insulating layer 152. Becomes even more prominent. This effect can also be obtained by a structure in which the edge near the upper surface of the first insulating layer 150 bites into the solder ball 270. Although not shown, the opening diameter of the opening 151 in the upper surface portion of the first insulating layer 150 is made smaller than the opening diameter of the opening 151 in the lower surface portion of the first insulating layer 150, whereby the first insulating layer The edge near the upper surface of 150 can be easily bited into the solder ball 270.

（４）第２の絶縁層１５２の厚さを第１の絶縁層１５０の厚さより厚くすることにより、第２の絶縁層１５２によりはんだボール２７０をかさ上げしつつ、第１の素子搭載用基板１１０の低背化を図ることができる。   (4) By making the thickness of the second insulating layer 152 larger than the thickness of the first insulating layer 150, the solder ball 270 is raised by the second insulating layer 152, and the first element mounting substrate 110 can be reduced in height.

（半導体装置の製造方法）
実施の形態１に係る第１の素子搭載用基板１１０および第１の半導体モジュール１００を含む半導体装置１０の製造方法について、図２乃至図４を参照して説明する。図２（Ａ）〜図２（Ｃ）、図３（Ａ）〜図３（Ｂ）、図４（Ａ）〜図４（Ｂ）は、実施の形態１に係る半導体装置１０の製造方法を示す工程断面図である。 (Method for manufacturing semiconductor device)
A method for manufacturing the semiconductor device 10 including the first element mounting substrate 110 and the first semiconductor module 100 according to the first embodiment will be described with reference to FIGS. 2A to FIG. 2C, FIG. 3A to FIG. 3B, and FIG. 4A to FIG. 4B show a method for manufacturing the semiconductor device 10 according to the first embodiment. It is process sectional drawing shown.

まず、図２（Ａ）に示すように、一方の主表面に第１の配線層１４０と第１の絶縁層１５０とが設けられ、他方の主表面に下面側配線層（図示せず）と第２の配線層１４２と第３の絶縁層１５４とが形成された絶縁樹脂層１３０を用意する。第１の絶縁層１５０には、第１の配線層１４０の電極領域１４８、電極領域１４９に対応して、それぞれ開口部１５１および開口部１５３が設けられ、第３の絶縁層１５４には、所定領域に開口部が設けられている。各配線層は、周知のフォトリソグラフィ法およびエッチング法などを用いて形成することができる。また、第１の絶縁層１５０の開口部１５１、開口部１５３および第３の絶縁層１５４の開口部も、周知のフォトリソグラフィ法およびエッチング法などを用いて形成することができる。   First, as shown in FIG. 2A, a first wiring layer 140 and a first insulating layer 150 are provided on one main surface, and a lower surface side wiring layer (not shown) is provided on the other main surface. An insulating resin layer 130 in which the second wiring layer 142 and the third insulating layer 154 are formed is prepared. The first insulating layer 150 is provided with an opening 151 and an opening 153 corresponding to the electrode region 148 and the electrode region 149 of the first wiring layer 140, respectively. An opening is provided in the region. Each wiring layer can be formed using a known photolithography method, etching method, or the like. In addition, the opening 151, the opening 153, and the third insulating layer 154 in the first insulating layer 150 can also be formed by a known photolithography method, an etching method, or the like.

次に、図２（Ｂ）に示すように、第１の絶縁層１５０の上に、第１の配線層１４０を被覆するようにして第２の絶縁層１５２ａ、第２の絶縁層１５２ｂを順に積層する。   Next, as illustrated in FIG. 2B, the second insulating layer 152 a and the second insulating layer 152 b are sequentially formed on the first insulating layer 150 so as to cover the first wiring layer 140. Laminate.

次に、図２（Ｃ）に示すように、フォトリソグラフィ法により、第２の絶縁層１５２ｂの主表面に、第１の絶縁層１５０の開口部１５１および図１に示した第１の半導体素子１２０の搭載予定領域に対応したパターンのマスク３００を選択的に形成する。そして、マスク３００をマスクとして第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂを露光する（図２（Ｃ）における矢印は露光光を示している）。第２の絶縁層１５２ｂの主表面に照射された露光光は、第２の絶縁層１５２ｂ内を進行して第２の絶縁層１５２ａに到達する。これにより第２の絶縁層１５２ａも露光される。第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂは、ネガ型のフォトソルダーレジストからなる。そのため、当該露光によって感光した部分が溶媒に対して不溶性となる。したがって、第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂを露光した後、現像することにより、図３（Ａ）に示すように、露光された部分の第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂが溶け残る。その結果、第１の絶縁層１５０の開口部１５１に埋め込まれた第２の絶縁層１５２ａが除去され、第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂに開口部１５５が形成される。これにより、開口部１５１および開口部１５５を通して第１の配線層１４０の電極領域１４８が露出する。また、第１の半導体素子１２０の搭載予定領域にある第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂが除去されて、第１の配線層１４０の電極領域１４９と、第１の半導体素子１２０が搭載される部分の第１の絶縁層１５０が露出する。   Next, as shown in FIG. 2C, the opening 151 of the first insulating layer 150 and the first semiconductor element shown in FIG. 1 are formed on the main surface of the second insulating layer 152b by photolithography. A mask 300 having a pattern corresponding to the 120 planned mounting areas is selectively formed. Then, the second insulating layer 152a and the second insulating layer 152b are exposed using the mask 300 as a mask (the arrow in FIG. 2C indicates exposure light). The exposure light applied to the main surface of the second insulating layer 152b travels through the second insulating layer 152b and reaches the second insulating layer 152a. As a result, the second insulating layer 152a is also exposed. The second insulating layer 152a and the second insulating layer 152b are made of a negative type photo solder resist. Therefore, the part exposed by the exposure becomes insoluble in the solvent. Therefore, by exposing and developing the second insulating layer 152a and the second insulating layer 152b, the exposed portions of the second insulating layer 152a and the second insulating layer 152a are exposed as shown in FIG. The insulating layer 152b remains undissolved. As a result, the second insulating layer 152a embedded in the opening 151 of the first insulating layer 150 is removed, and an opening 155 is formed in the second insulating layer 152a and the second insulating layer 152b. As a result, the electrode region 148 of the first wiring layer 140 is exposed through the opening 151 and the opening 155. Further, the second insulating layer 152a and the second insulating layer 152b in the region where the first semiconductor element 120 is to be mounted are removed, and the electrode region 149 of the first wiring layer 140 and the first semiconductor element 120 are removed. The portion of the first insulating layer 150 where the is mounted is exposed.

露光光は、第２の絶縁層１５２ｂ、第２の絶縁層１５２ａを進行するにつれて、絶縁体に吸収されて、または絶縁体によって散乱されて減衰する。そのため、第２の絶縁層１５２ｂ、第２の絶縁層１５２ａは、露光表面から遠い部分（深い部分）ほど硬化しにくくなる。この現象は、マスク開口の周辺部分で顕著になる。図２（Ｃ）に示すように、マスク３００を積層して第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂを露光した場合は、マスク３００の開口部内で、開口部側面に近いほど露光光が減衰しやすい。その結果、図３（Ａ）に示すように、第２の絶縁層１５２ａおよび第２の絶縁層１５２ｂの開口部１５５内の側面は、それぞれの上側主表面に近くなるほど開口部１５５内にせり出した形状となる。   The exposure light is absorbed by the insulator or scattered by the insulator and attenuates as it travels through the second insulating layer 152b and the second insulating layer 152a. For this reason, the second insulating layer 152b and the second insulating layer 152a are harder to be hardened as a portion (deep portion) farther from the exposure surface. This phenomenon becomes remarkable in the peripheral portion of the mask opening. As shown in FIG. 2C, when the mask 300 is stacked and the second insulating layer 152a and the second insulating layer 152b are exposed, the exposure light is closer to the side of the opening in the opening of the mask 300. Is prone to decay. As a result, as shown in FIG. 3A, the side surfaces in the opening 155 of the second insulating layer 152a and the second insulating layer 152b protrude into the opening 155 as they become closer to the respective upper main surfaces. It becomes a shape.

なお、第１の絶縁層１５０の開口部１５１の上方に設けられるマスクの径を調節することにより、開口部１５１の上方において、第２の絶縁層１５２ｂの下面部分における開口部１５５の開口径を、第１の絶縁層１５０の上面部分における開口部１５１の開口径より大きくすることができる。   Note that by adjusting the diameter of the mask provided above the opening 151 of the first insulating layer 150, the opening diameter of the opening 155 in the lower surface portion of the second insulating layer 152 b is adjusted above the opening 151. The opening diameter of the opening 151 in the upper surface portion of the first insulating layer 150 can be made larger.

次に、図３（Ｂ）に示すように、たとえば電解めっき法により、第１の配線層１４０の電極領域１４８の表面に金めっき層１６６を形成し、第１の配線層１４０の電極領域１４９の表面に金めっき層１４１を形成する。また、第２の配線層１４２の表面に金めっき層１４４を形成する。以上の工程により、本実施の形態に係る第１の素子搭載用基板１１０が形成される。なお、第２の絶縁層１５２ａと第２の絶縁層１５２ｂを合わせた絶縁体層が図１に示す第２の絶縁層１５２に相当する。   Next, as shown in FIG. 3B, a gold plating layer 166 is formed on the surface of the electrode region 148 of the first wiring layer 140 by, for example, electrolytic plating, and the electrode region 149 of the first wiring layer 140 is formed. A gold plating layer 141 is formed on the surface. In addition, a gold plating layer 144 is formed on the surface of the second wiring layer 142. Through the above steps, the first element mounting substrate 110 according to the present embodiment is formed. Note that an insulator layer including the second insulating layer 152a and the second insulating layer 152b corresponds to the second insulating layer 152 illustrated in FIG.

次に、図４（Ａ）に示すように、絶縁樹脂層１３０の中央領域において第１の絶縁層１５０上に第１の半導体素子１２０を搭載する。そして、ワイヤボンディング法を用いて、第１の半導体素子１２０の上面周縁に設けられた素子電極（図示せず）と第１の配線層１４０の電極領域１４９の表面とを金線１２１により接続する。続いて、トランスファーモールド法を用いて、第１の半導体素子１２０を封止樹脂層１８０により封止する。また、はんだボール２７０を設ける位置に開口部が形成されたマスクを、開口部１５１が形成された第１の絶縁層１５０、第２の絶縁層１５２上に設け、マスクの開口部に球状のはんだボールを配置して（載せて）、第１の配線層１４０の電極領域１４８上にはんだボール２７０を搭載する。その後、マスクを除去する。また、同様にして、第３の絶縁層１５４の開口部において第２の配線層１４２の電極領域上の金めっき層１４４にはんだボール８０を搭載する。また、例えばスクリーン印刷法により、第１の絶縁層１５０の開口部１５１にはんだボール２７０を搭載してもよい。具体的には、樹脂とはんだ材をペースト状にしたはんだペーストをスクリーンマスクにより所望の箇所に印刷してはんだボール２７０を形成する。また、同様にしてはんだボール８０を搭載してもよい。以上の工程により、本実施の形態１に係る第１の半導体モジュール１００が形成される。   Next, as shown in FIG. 4A, the first semiconductor element 120 is mounted on the first insulating layer 150 in the central region of the insulating resin layer 130. Then, a wire bonding method is used to connect a device electrode (not shown) provided on the periphery of the upper surface of the first semiconductor device 120 and the surface of the electrode region 149 of the first wiring layer 140 with a gold wire 121. . Subsequently, the first semiconductor element 120 is sealed with the sealing resin layer 180 using a transfer molding method. In addition, a mask in which an opening is formed at a position where the solder ball 270 is provided is provided over the first insulating layer 150 and the second insulating layer 152 in which the opening 151 is formed, and a spherical solder is formed in the opening of the mask. A ball is placed (mounted), and a solder ball 270 is mounted on the electrode region 148 of the first wiring layer 140. Thereafter, the mask is removed. Similarly, the solder ball 80 is mounted on the gold plating layer 144 on the electrode region of the second wiring layer 142 in the opening of the third insulating layer 154. Further, the solder balls 270 may be mounted in the openings 151 of the first insulating layer 150 by, for example, screen printing. Specifically, a solder ball 270 is formed by printing a solder paste made of a resin and a solder material in a paste form at a desired location using a screen mask. Similarly, the solder ball 80 may be mounted. Through the above steps, the first semiconductor module 100 according to the first embodiment is formed.

また、はんだボール２７０の設置方法としては、以下の手法が好適である。図５は、第１の素子搭載用基板上にはんだボールを設置する方法を示す図である。同図に示すように、はんだボール２７０を構成するはんだ部材として、第１のはんだ部材２７０ａと第２のはんだ部材２７０ｂを用意する。第１のはんだ部材２７０ａの径は、第２のはんだ部材２７０ｂの径より小さい。たとえば、第１のはんだ部材２７０ａの径、第２のはんだ部材２７０ｂの径は、それぞれ、１５０μｍφ、４００μｍφである。   Further, as a method for installing the solder ball 270, the following method is suitable. FIG. 5 is a diagram showing a method of installing solder balls on the first element mounting board. As shown in the figure, a first solder member 270a and a second solder member 270b are prepared as solder members constituting the solder ball 270. The diameter of the first solder member 270a is smaller than the diameter of the second solder member 270b. For example, the diameter of the first solder member 270a and the diameter of the second solder member 270b are 150 μmφ and 400 μmφ, respectively.

第１のはんだ部材２７０ａの少なくとも一部が第１の絶縁層１５０の開口部１５１に入り込むようにし、第１の絶縁層１５０の開口部１５１において、第１のはんだ部材２７０ａと第１の配線層１４０上の金めっき層１６６とを接触させる。また、第１のはんだ部材２７０ａの上方に第２のはんだ部材２７０ｂを設置し、第１のはんだ部材２７０ａと第２のはんだ部材２７０ｂとを接触させる。このように、相対的に径が小さい第１のはんだ部材２７０ａを開口が比較的小さい第１の絶縁層１５０の開口部１５１に予め設置しておくことにより、リフロー工程によりはんだを溶融させたときに、ボイドの発生を抑制しつつ、第１の絶縁層１５０の開口部１５１をはんだ部材で充填することができる。また、第１のはんだ部材２７０ａおよび第２のはんだ部材２７０ｂを溶融させたときに、第１の配線層１４０上の金めっき層１６６と第１のはんだ部材２７０ａ、および第１のはんだ部材２７０ａと第２のはんだ部材２７０ｂとがなじみやすいため、充填性の向上を図ることができ、ひいては接続信頼性を高めることができる。   At least a part of the first solder member 270a enters the opening 151 of the first insulating layer 150, and the first solder member 270a and the first wiring layer are formed in the opening 151 of the first insulating layer 150. The gold plating layer 166 on 140 is brought into contact. In addition, the second solder member 270b is installed above the first solder member 270a, and the first solder member 270a and the second solder member 270b are brought into contact with each other. As described above, when the first solder member 270a having a relatively small diameter is previously installed in the opening 151 of the first insulating layer 150 having a relatively small opening, the solder is melted by the reflow process. In addition, the opening 151 of the first insulating layer 150 can be filled with the solder member while suppressing the generation of voids. Further, when the first solder member 270a and the second solder member 270b are melted, the gold plating layer 166, the first solder member 270a, and the first solder member 270a on the first wiring layer 140 Since the second solder member 270b is easily compatible with the second solder member 270b, it is possible to improve the filling property and thus to improve the connection reliability.

次に、図４（Ｂ）に示すように、上述した第２の半導体モジュール２００を準備する。そして、第１の半導体モジュール１００の上に第２の半導体モジュール２００を搭載した状態で、リフロー工程によりはんだボール２７０を溶融して、電極領域１４８と第４の配線層２４２とを接合する。これにより、はんだボール２７０を介して第１の半導体モジュール１００と第２の半導体モジュール２００とが電気的に接続される。以上の工程により、半導体装置１０が形成される。   Next, as shown in FIG. 4B, the above-described second semiconductor module 200 is prepared. Then, in a state where the second semiconductor module 200 is mounted on the first semiconductor module 100, the solder ball 270 is melted by a reflow process to join the electrode region 148 and the fourth wiring layer 242. Thereby, the first semiconductor module 100 and the second semiconductor module 200 are electrically connected via the solder balls 270. Through the above steps, the semiconductor device 10 is formed.

（実施の形態２）
次に、上述の実施の形態に係る半導体装置１０を備えた携帯機器について説明する。なお、携帯機器として携帯電話に搭載する例を示すが、たとえば、個人用携帯情報端末（ＰＤＡ）、デジタルビデオカメラ（ＤＶＣ）、及びデジタルスチルカメラ（ＤＳＣ）といった電子機器であってもよい。 (Embodiment 2)
Next, a portable device including the semiconductor device 10 according to the above-described embodiment will be described. In addition, although the example mounted in a mobile telephone is shown as a portable apparatus, electronic devices, such as a personal digital assistant (PDA), a digital video camera (DVC), and a digital still camera (DSC), may be sufficient, for example.

図６は実施の形態２に係る携帯電話の構成を示す図である。携帯電話１１１１は、第１の筐体１１１２と第２の筐体１１１４が可動部１１２０によって連結される構造になっている。第１の筐体１１１２と第２の筐体１１１４は可動部１１２０を軸として回動可能である。第１の筐体１１１２には文字や画像等の情報を表示する表示部１１１８やスピーカ部１１２４が設けられている。第２の筐体１１１４には操作用ボタンなどの操作部１１２２やマイク部１１２６が設けられている。実施の形態１に係る半導体装置１０はこうした携帯電話１１１１の内部に搭載されている。   FIG. 6 is a diagram showing the configuration of the mobile phone according to the second embodiment. A cellular phone 1111 has a structure in which a first housing 1112 and a second housing 1114 are connected by a movable portion 1120. The first housing 1112 and the second housing 1114 can be rotated around the movable portion 1120. The first housing 1112 is provided with a display portion 1118 and a speaker portion 1124 for displaying information such as characters and images. The second housing 1114 is provided with an operation portion 1122 such as operation buttons and a microphone portion 1126. The semiconductor device 10 according to the first embodiment is mounted inside such a mobile phone 1111.

図７は図６に示した携帯電話の部分断面図（第１の筐体１１１２の断面図）である。上述の実施形態１乃至３に係る半導体装置１０は、はんだボール８０を介してプリント基板１１２８に搭載され、こうしたプリント基板１１２８を介して表示部１１１８などと電気的に接続されている。また、半導体装置１０の裏面側（はんだボール８０とは反対側の面）には金属基板などの放熱基板１１１６が設けられ、たとえば、半導体装置１０から発生する熱を第１の筐体１１１２内部に篭もらせることなく、効率的に第１の筐体１１１２の外部に放熱することができるようになっている。   7 is a partial cross-sectional view (cross-sectional view of the first housing 1112) of the mobile phone shown in FIG. The semiconductor device 10 according to the first to third embodiments described above is mounted on the printed board 1128 via the solder balls 80 and is electrically connected to the display unit 1118 and the like via the printed board 1128. Further, a heat radiating substrate 1116 such as a metal substrate is provided on the back surface side (surface opposite to the solder ball 80) of the semiconductor device 10. For example, heat generated from the semiconductor device 10 is transferred into the first housing 1112. The heat can be efficiently radiated to the outside of the first housing 1112 without stagnation.

実施の形態１に係る半導体装置１０によれば、第１の素子搭載用基板１１０の接続信頼性を高めることができ、したがって半導体装置１０の実装信頼性を高めることができる。そのため、こうした半導体装置１０を搭載した本実施の形態に係る携帯機器について、動作信頼性の向上を図ることができる。   According to the semiconductor device 10 according to the first embodiment, the connection reliability of the first element mounting substrate 110 can be increased, and therefore the mounting reliability of the semiconductor device 10 can be increased. Therefore, it is possible to improve the operation reliability of the portable device according to the present embodiment on which such a semiconductor device 10 is mounted.

本発明は、上述の各実施の形態に限定されるものではなく、当業者の知識に基づいて各種の設計変更等の変形を加えることも可能であり、そのような変形が加えられた実施の形態も本発明の範囲に含まれうるものである。   The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention.

１０ 半導体装置、８０ はんだボール、１００ 第１の半導体モジュール、１１０ 第１の素子搭載用基板、１２０ 第１の半導体素子、１３０ 絶縁樹脂層、１４０ 第１の配線層、１４２ 第２の配線層、１５０ 第１の絶縁層、１５２ 第２の絶縁層、１６６ 金めっき層、２００ 第２の半導体モジュール、２１０ 第２の素子搭載用基板、２２０ 第２の半導体素子、２３０ 絶縁樹脂層、２４０ 第３の配線層、２４２ 第４の配線層、２５０ 第４の絶縁層、２５２ 第５の絶縁層、２７０ はんだボール DESCRIPTION OF SYMBOLS 10 Semiconductor device, 80 Solder ball, 100 1st semiconductor module, 110 1st element mounting board | substrate, 120 1st semiconductor element, 130 Insulating resin layer, 140 1st wiring layer, 142 2nd wiring layer, 150 first insulating layer, 152 second insulating layer, 166 gold plating layer, 200 second semiconductor module, 210 second element mounting substrate, 220 second semiconductor element, 230 insulating resin layer, 240 third Wiring layer, 242 4th wiring layer, 250 4th insulating layer, 252 5th insulating layer, 270 solder ball

Claims (10)

基材と、
前記基材の一方の主表面に設けられている配線層と、
前記配線層を被覆するように設けられ、前記配線層の電極領域が露出する第１の開口部を有する第１の絶縁層と、
前記第１の絶縁層の上に設けられ、前記第１の開口部が露出するような第２の開口部を有する第２の絶縁層と、
を備え、
前記第２の絶縁層の下面部分における前記第２の開口部の開口径が、前記第１の絶縁層の上面部分における前記第１の開口部の開口径より大きいことを特徴とする素子搭載用基板。 A substrate;
A wiring layer provided on one main surface of the substrate;
A first insulating layer provided to cover the wiring layer and having a first opening from which an electrode region of the wiring layer is exposed;
A second insulating layer provided on the first insulating layer and having a second opening such that the first opening is exposed;
With
For mounting an element, the opening diameter of the second opening in the lower surface portion of the second insulating layer is larger than the opening diameter of the first opening in the upper surface portion of the first insulating layer substrate. 前記第２の絶縁層は、前記第２の開口部内の側面のうち少なくとも前記第２の絶縁層の上面近傍の側面が、前記第２の絶縁層の上面に近くなるほど前記第２の開口部の内側にせり出すように構成されている請求項１に記載の素子搭載用基板。   In the second insulating layer, at least a side surface in the vicinity of the upper surface of the second insulating layer among the side surfaces in the second opening is closer to the upper surface of the second insulating layer. The element mounting substrate according to claim 1, wherein the element mounting substrate is configured to protrude inside. 前記第１の絶縁層の上面部分における前記第１の開口部の開口径が前記第１の絶縁層の下面部分における前記第１の開口部の開口径より小さい請求項１または２に記載の素子搭載用基板。   The element according to claim 1, wherein an opening diameter of the first opening in the upper surface portion of the first insulating layer is smaller than an opening diameter of the first opening in the lower surface portion of the first insulating layer. Mounting board. 前記第２の絶縁層の厚さが前記第１の絶縁層の厚さより厚い請求項１乃至３のいずれか１項に記載の素子搭載用基板。   The element mounting substrate according to claim 1, wherein a thickness of the second insulating layer is larger than a thickness of the first insulating layer. パッケージオンパッケージ構造を有する半導体装置に用いられる請求項１乃至４のいずれか１項に記載の素子搭載用基板。   The element mounting substrate according to claim 1, which is used for a semiconductor device having a package-on-package structure. 請求項１乃至５のいずれか１項に記載の素子搭載用基板と、
前記基材の一方の主表面側に搭載された半導体素子と、
を備えることを特徴とする半導体モジュール。 The element mounting substrate according to any one of claims 1 to 5,
A semiconductor element mounted on one main surface side of the substrate;
A semiconductor module comprising: 請求項６に記載の半導体モジュールと、その半導体モジュールに積層される積層体と、を有する半導体装置であって、
前記電極領域と積層体の電極領域とを電気的に接続する電気接続部材を備え、
前記電気接続部材が前記第１の開口部および前記第２の開口部に充填され、
前記第２の絶縁層の上面近傍の縁部が前記電気接続部材の内部に食い込んでいることを特徴とする半導体装置。 A semiconductor device comprising: the semiconductor module according to claim 6; and a stacked body stacked on the semiconductor module,
An electrical connection member for electrically connecting the electrode region and the electrode region of the laminate;
The electrical connection member fills the first opening and the second opening;
A semiconductor device, wherein an edge near the upper surface of the second insulating layer bites into the electrical connection member. 前記第１の絶縁層の上面近傍の縁部が前記電気接続部材の内部に食い込んでいる請求項７に記載の半導体装置。   The semiconductor device according to claim 7, wherein an edge portion in the vicinity of the upper surface of the first insulating layer bites into the electric connection member. 請求項７または８に記載の半導体装置が実装されたことを特徴とする携帯機器。   A portable device comprising the semiconductor device according to claim 7 or 8 mounted thereon. 請求項１乃至５のいずれか１項に記載の素子搭載用基板を用意する工程と、
前記第１の絶縁層に設けられた第１の開口部に第１のはんだ部材の少なくとも一部を載置し、前記第１のはんだ部材と前記配線層の電極領域とを接触させる工程と、
前記第１のはんだ部材より径が大きい第２のはんだ部材を前記第１のはんだ部材の上方に載置し、前記第１のはんだ部材と前記第２のはんだ部材とを接触させる工程と、
前記第１のはんだ部材および前記第２のはんだ部材を溶融させて、前記電極領域と他の基板に設けられた電極領域とを電気的に接続する電気接続部材を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。 Preparing a device mounting substrate according to any one of claims 1 to 5,
Placing at least a portion of the first solder member in a first opening provided in the first insulating layer, and contacting the first solder member with an electrode region of the wiring layer;
Placing a second solder member having a diameter larger than that of the first solder member above the first solder member, and bringing the first solder member and the second solder member into contact with each other;
Melting the first solder member and the second solder member to form an electrical connection member that electrically connects the electrode region and an electrode region provided on another substrate;
A method for manufacturing a semiconductor device, comprising:
JP2009272854A 2009-11-30 2009-11-30 Element mounting substrate, semiconductor module, semiconductor device, method for manufacturing the semiconductor device, and portable device Pending JP2011119305A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113113374A (en) * 2021-04-08 2021-07-13 重庆群崴电子材料有限公司 Ball for encapsulation and encapsulation structure thereof

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