JP2011114462A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shift circuit capable of suppressing deterioration in characteristics even when driven at the maximum value within the rated range of a power supply voltage. <P>SOLUTION: The level shift circuit 2A includes a first input terminal 11, second input terminal 12, third input terminal 13, first output terminal 21, second output terminal 22, first PMOS transistor 31, second PMOS transistor 32, first NMOS transistor 41, second NMOS transistor 42, first buffer circuit 51A, second buffer circuit 52A, and first inverter circuit 60. The first buffer circuit 51A is configured such that an inverter circuit at a previous stage constituted of a PMOS transistor QP<SB>11</SB>and an NMOS transistor QN<SB>11</SB>, and an inverter circuit at a post stage constituted of a PMOS transistor QP<SB>12</SB>and an NMOS transistor QN<SB>12</SB>are subjected to cascade connection, and further includes a PMOS transistor QP<SB>13</SB>. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a level shift circuit.

  The level shift circuit inputs a first input signal and a second input signal which are complementary to each other, and is complementary to each other having a high level voltage value larger than the high level voltage value of the first input signal and the second input signal. The first output signal and the second output signal are output. Here, when one of the first input signal and the second input signal is at a high level, the other is at a low level. Similarly, when one of the first output signal and the second output signal is at a high level, the other is at a low level. The change of the high level / low level of the first output signal and the second output signal is the same as the change of the high level / low level of the first input signal and the second input signal.

  For example, when the CPU core is driven with a power supply voltage Vddl of 1.8 V and the peripheral circuit for the CPU is driven with a power supply voltage Vddh of 3.3 V, the level shift circuit outputs the signal output from the CPU core. The high level voltage value is converted from 1.8 V to 3.3 V, and the signal after the level conversion is output to the peripheral circuit.

  A circuit disclosed in Patent Document 1 is known as such a level shift circuit. The level shift circuit disclosed in this document includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor as a basic configuration. In the level shift circuit disclosed in this document, the drain terminal of the first PMOS transistor and the drain terminal of the first NMOS transistor are connected to each other, and the connection point becomes the first output terminal. 1 output signal is output, the drain terminal of the second PMOS transistor and the drain terminal of the second NMOS transistor are connected to each other, and the connection point becomes the second output terminal, and the second output signal is output from the second output terminal. Output.

  In addition, at the input stage of the level shift circuit, a first buffer circuit for inputting a signal having the same level as that of the first input signal to the source terminal of the first NMOS transistor, and a signal having the same level as that of the second input signal are provided. In some cases, a second buffer circuit is provided for input to the source terminal of the 2NMOS transistor. Each of the first buffer circuit and the second buffer circuit is configured by cascading two stages of inverter circuits.

JP-A-6-177744

  The inventor has found that a level shift circuit including the first buffer circuit and the second buffer circuit in the input stage as described above has the following problems. That is, even if it operates without any problem when it is driven with a typical value (eg, Vddl = 1.0V, Vddh = 3.3V) in the rated range of the power supply voltage, the maximum value (eg, In the case of driving with Vddl = 1.1V, Vddh = 3.6V), an overvoltage may be applied to the transistors included in each of the first buffer circuit and the second buffer circuit. Then, application of an overvoltage to the transistor may deteriorate the characteristics of the transistor, which in turn may deteriorate the characteristics of the level shift circuit.

  The present invention has been made to solve the above problems, and provides a level shift circuit capable of suppressing deterioration of characteristics even when driven at the maximum value in the rated range of the power supply voltage. With the goal.

The level shift circuit according to the present invention inputs a first input signal and a second input signal that are complementary to each other, and has a high level voltage value that is larger than the high level voltage value of the first input signal and the second input signal. A level shift circuit for outputting a first output signal and a second output signal complementary to each other, comprising: (1) a first input terminal for inputting a first input signal; and (2) an input of a second input signal. And (3) a first output terminal for outputting a first output signal, (4) a second output terminal for outputting a second output signal, and (5) input to the first input terminal. a first buffer circuit for outputting a first input signal and the level signal to the node N _11, (6) the outputs of the second input signal and the level of the signal inputted to the second input terminal to the node N ₂₁ Two buffer circuits, (7) a source terminal to which the first reference potential Vddh is input, A drain terminal connected to the first output terminal, a first 1PMOS transistor having a gate terminal connected to the node N _21, the source terminal is input (8) the first reference potential Vddh, connected to the second output terminal a drain terminal, a second 2PMOS transistor having a gate terminal connected to node N _11, and a source terminal connected to (9) node N _11, and a drain terminal connected to the first output terminal, first a first 1NMOS transistor having a gate terminal to which first reference potential Vddh is input, (10) and a source terminal connected to the node N _21, and a drain terminal connected to the second output terminal, the first reference potential Vddh And a second NMOS transistor having an input gate terminal.

In the level shift circuit according to the present invention, the first buffer circuit includes PMOS transistors QP ₁₁ , QP ₁₂ , QP ₁₃ and NMOS transistors QN ₁₁ , QN ₁₂ , and the source terminals of the PMOS transistors QP ₁₁ , QP ₁₂ are Connected to the second reference potential Vddl, the source terminals of the NMOS transistors QN ₁₁ and QN ₁₂ are connected to the third reference potential Vss, and the gate terminals of the PMOS transistor QP ₁₁ and the NMOS transistor QN ₁₁ are connected to the first input terminal. is, PMOS source terminal of the transistor _{QP 12} and an NMOS transistor _{QN 12} respective drain terminals and PMOS transistor _{QP 13} is connected to the node _{N 11,} PMOS transistors _QP 11, _{QP 13} and NMOS Transistors _{QN 11} respective drain terminals and PMOS transistors _QP 12, _{QP 13} and NMOS transistors _{QN 12} each gate terminal, characterized in that it is connected to the node _{N 12.}

Furthermore, in the level shift circuit according to the present invention, the second buffer circuit includes PMOS transistors QP ₂₁ , QP ₂₂ , QP ₂₃ and NMOS transistors QN ₂₁ , QN ₂₂ , and the source terminals of the PMOS transistors QP ₂₁ , QP ₂₂ are Connected to the second reference potential Vddl, the source terminals of the NMOS transistors QN ₂₁ and QN ₂₂ are connected to the third reference potential Vss, and the gate terminals of the PMOS transistor QP ₂₁ and the NMOS transistor QN ₂₁ are connected to the second input terminal. is, the source terminal of the PMOS transistor _{QP 22} and an NMOS transistor _{QN 22} respective drain terminals and PMOS transistor _{QP 23} is connected to the node _{N 21,} PMOS transistors _QP 21, _{QP 23} and NMO Wherein the transistor _{QN 21} respective drain terminals and PMOS transistor _QP 22, _{QP 23} and NMOS transistors _{QN 22} respective gate terminal connected to node _{N 22.}

  However, there is a relationship Vddh> Vdd> Vss among the first reference potential Vddh, the second reference potential Vddl, and the third reference potential Vss.

In the level shift circuit according to the present invention, the first buffer circuit includes a pre-stage of the inverter circuit consisting of PMOS transistors _{QP 11} and an NMOS transistor _{QN 11,} and the subsequent stage of the inverter circuit consisting of PMOS transistors _{QP 12} and an NMOS transistor _{QN 12,} It has been constructed by cascade, the first input signal and the level of the signal input to the first input terminal 11 can output to the node N _11. The first buffer circuit further comprises a PMOS transistor _{QP 13.} The source terminal of the PMOS transistor QP ₁₃ is connected to the node N ₁₁ , and the drain terminal and the gate terminal of the PMOS transistor QP ₁₃ are each connected to the node N ₁₂ .

The second buffer circuit includes a pre-stage of the inverter circuit consisting of PMOS transistors _{QP 21} and an NMOS transistor _{QN 21,} and the rear stage of the inverter circuit consisting of PMOS transistors _{QP 22} and NMOS transistor _{QN 22} is being constructed by cascade Te, a second input signal and the level of the signal inputted to the second input terminal 12 can be outputted to the node N _21. The second buffer circuit further comprises a PMOS transistor _{QP 23.} The source terminal of the PMOS transistor QP ₂₃ is connected to the node N ₂₁ , and the drain terminal and the gate terminal of the PMOS transistor QP ₂₃ are each connected to the node N ₂₂ .

In the level shift circuit according to the present invention, the first buffer circuit further includes the PMOS transistor QP ₁₃ , and the second buffer circuit further includes the PMOS transistor QP _23. Even when driven at the maximum value within the rated voltage range, the deterioration of characteristics can be suppressed.

Level shift circuit according to the present invention, (1) the first buffer circuit further comprises a switch SW ₁ for turning on / off the connection between the source terminal and the node N ₁₁ of the PMOS transistor QP _13, (2) a second buffer circuit, selects a connection between the source terminal and the node _{N 21} of the PMOS transistor _{QP 23} on / off further includes a switch SW ₂ that, in any one of (3) turns on the switch SW ₁ and the switch SW ₂ at the same time and at the same time off It is preferable to further include switch setting means for setting automatically.

  In addition, the level shift circuit according to the present invention has a gate potential that selectively sets the potential input to the gate terminals of the first NMOS transistor and the second NMOS transistor to either the first reference potential Vddh or the third reference potential Vss. It is preferable to further include setting means.

  The level shift circuit according to the present invention can suppress the deterioration of characteristics even when driven at the maximum value in the rated range of the power supply voltage.

It is a figure which shows the structure of the level shift circuit 1 of a comparative example. It is a diagram illustrating a simulation result on the level nodes N _11, N ₁₂ each potential shift circuit 1 of the comparative example. It is a figure which shows the structure of the level shift circuit 2A which concerns on 1st Embodiment. It is a diagram illustrating a simulation result on the node N _11, N ₁₂ each potential of the level shift circuit 2A according to the first embodiment. It is a figure which shows the structure of the level shift circuit 2B which concerns on 2nd Embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Also, after first describing the level shift circuit of the comparative example, the level shift circuit of the embodiment will be described.

  FIG. 1 is a diagram illustrating a configuration of a level shift circuit 1 of a comparative example. The level shift circuit 1 shown in this figure includes a first input terminal 11, a second input terminal 12, a third input terminal 13, a first output terminal 21, a second output terminal 22, a first PMOS transistor 31, and a second PMOS transistor 32. , A first NMOS transistor 41, a second NMOS transistor 42, a first buffer circuit 51, a second buffer circuit 52, and a first inverter circuit 60.

  The level shift circuit 1 receives a first input signal LSip and a second input signal LSin complementary to each other, and outputs a first output signal LSop and a second output signal LSo complementary to each other.

High-level voltage value of the first output signal LSop is determined by the low-level voltage value of the node N ₂₁ by the voltage value and the second input signal LSin the high level of the node N ₁₁ by the first input signal LSIP. When the node N ₂₁ has a low level voltage value, the node N ₂₁ becomes approximately Vss. Therefore, the voltage between the gate terminal and the source terminal of the first PMOS transistor 31 becomes approximately Vddh, and the node N ₁₁ becomes high. In the case of the level voltage value, the voltage between the gate terminal and the source terminal of the first NMOS transistor 41 is approximately Vddh-Vddl. The high level voltage value of the first output signal LSop is determined by the ratio of the on-resistance of the first PMOS transistor 31 and the first NMOS transistor 41 at that time.

Further, the voltage value of the high level of the second output signal LSon is determined by the low-level voltage value of the node N ₁₁ by the voltage value and the first input signal LSip the high level of the node N ₂₁ by the second input signal LSin. When the node N ₁₁ has a low level voltage value, the node N ₁₁ becomes approximately Vss. Therefore, the voltage between the gate terminal and the source terminal of the second PMOS transistor 32 becomes approximately Vddh, and the node N ₂₁ becomes high. In the case of the level voltage value, the voltage between the gate terminal and the source terminal of the second NMOS transistor 42 is approximately Vddh-Vddl. The high-level voltage value of the second output signal Lson is determined by the ratio of the on-resistance of the second PMOS transistor 32 and the second NMOS transistor 42 at that time.

The voltage value of the low level of the first output signal LSop is determined by the high-level voltage value of the node N ₂₁ by the voltage value and the second input signal LSin the low level of the node N ₁₁ by the first input signal LSIP. When the node N ₂₁ has a high level voltage value, the node N ₂₁ becomes approximately Vddl. Therefore, the voltage between the gate terminal and the source terminal of the first PMOS transistor 31 becomes approximately Vddh-Vddl, and the node N ₁₁ Is a low level voltage value, the voltage between the gate terminal and the source terminal of the first NMOS transistor 41 is approximately Vddh. The low level voltage value of the first output signal LSop is determined by the ratio of the on-resistance of the first PMOS transistor 31 and the first NMOS transistor 41 at that time.

Further, the voltage value of the low level of the second output signal LSon is determined by the high-level voltage value of the node N ₁₁ by the voltage value and the first input signal LSin the low level of the node N ₂₁ by the second input signal LSin. When the node N ₁₁ has a high level voltage value, the node N ₁₁ becomes approximately Vddl. Therefore, the voltage between the gate terminal and the source terminal of the second PMOS transistor 32 becomes approximately Vddh-Vddl, and the node N ₂₁ Is a low level voltage value, the voltage between the gate terminal and the source terminal of the second NMOS transistor 42 is approximately Vddh. The low-level voltage value of the second output signal Lson is determined by the ratio of the on-resistance of the second PMOS transistor 32 and the second NMOS transistor 42 at that time.

  The high level voltage value and the low level voltage value of the first output signal LSop and the second output signal LSo only need to be able to output an inverted voltage at which the inverter circuit connected to the next stage can operate.

  The first input terminal 11 receives the first input signal LSip. The second input terminal 12 receives the second input signal LSin. The first input signal LSip and the second input signal LSin are complementary to each other, and when one is at a high level, the other is at a low level. The third input terminal 13 receives an enable signal Enable1.

  The first output terminal 21 outputs the first output signal LSop. The second output terminal 22 receives the second output signal Lson. The first output signal LSop and the second output signal Lson are complementary to each other, and when one is at a high level, the other is at a low level.

  Note that there is a relationship Vddh> Vdd> Vss among the first reference potential Vddh, the second reference potential Vddl, and the third reference potential Vss shown in the drawing.

The 1PMOS transistor 31 has a source terminal first reference potential Vddh is input, a drain terminal connected to the first output terminal 21, and a gate terminal connected to node N _21. The 2PMOS transistor 32 has a source terminal first reference potential Vddh is input, a drain terminal connected to the second output terminal 22, and a gate terminal connected to node N _11.

The 1NMOS transistor 41 has a source terminal connected to the node N _11, and a drain terminal connected to the first output terminal 21, and a gate terminal to which an output signal of the inverter circuit 60 is input. The second NMOS transistor 42 has a source terminal connected to the node N ₂₁ , a drain terminal connected to the second output terminal 22, and a gate terminal to which the output signal of the inverter circuit 60 is input.

The first buffer circuit 51 outputs the first input signal LSip the same level of signal inputted to the first input terminal 11 to the node N _11. The first buffer circuit includes PMOS transistors QP ₁₁ and QP ₁₂ and NMOS transistors QN ₁₁ and QN ₁₂ . The source terminals of the PMOS transistors QP ₁₁ and QP ₁₂ are connected to the second reference potential Vddl. The source terminals of the NMOS transistors QN ₁₁ and QN ₁₂ are connected to the third reference potential Vss.

The gate terminals of the PMOS transistor QP ₁₁ and the NMOS transistor QN ₁₁ are connected to the first input terminal 11. The drain terminals of the PMOS transistor QP ₁₂ and the NMOS transistor QN ₁₂ are connected to the node N ₁₁ . The drain terminals of the PMOS transistor QP ₁₁ and the NMOS transistor QN ₁₁ and the gate terminals of the PMOS transistor QP ₁₂ and the NMOS transistor QN ₁₂ are connected to the node N ₁₂ .

That is, the first buffer circuit 51 has a configuration in which a front inverter circuit composed of a PMOS transistor QP ₁₁ and an NMOS transistor QN ₁₁ and a rear inverter circuit composed of a PMOS transistor QP ₁₂ and an NMOS transistor QN ₁₂ are connected in series. and have been, it is possible to output a first input signal LSip the same level of signal inputted to the first input terminal 11 to the node N _11.

The second buffer circuit 52 outputs the second input signal LSin the same level of signal inputted to the second input terminal 12 to the node N _21. The second buffer circuit includes PMOS transistors QP ₂₁ and QP ₂₂ and NMOS transistors QN ₂₁ and QN ₂₂ . The source terminals of the PMOS transistors QP ₂₁ and QP ₂₂ are connected to the second reference potential Vddl. The source terminals of the NMOS transistors QN ₂₁ and QN ₂₂ are connected to the third reference potential Vss.

The gate terminals of the PMOS transistor QP ₂₁ and the NMOS transistor QN ₂₁ are connected to the second input terminal 12. The drain terminals of the PMOS transistor QP ₂₂ and the NMOS transistor QN ₂₂ are connected to the node N ₂₁ . The drain terminals of the PMOS transistor QP ₂₁ and the NMOS transistor QN ₂₁ and the gate terminals of the PMOS transistor QP ₂₂ and the NMOS transistor QN ₂₂ are connected to the node N ₂₂ .

That is, the second buffer circuit 52 includes a pre-stage of the inverter circuit consisting of PMOS transistors _{QP 21} and an NMOS transistor _{QN 21,} and the subsequent stage of the inverter circuit consisting of PMOS transistors _{QP 22} and NMOS transistors _{QN 22,} are connected in cascade configuration and have been, it is possible to output the second input signal LSin the same level of signal inputted to the second input terminal 12 to the node N _21.

  The first inverter circuit 60 includes a PMOS transistor 61 and an NMOS transistor 62. The first reference potential Vddh is input to the source terminal of the PMOS transistor 61. The third reference potential Vss is input to the source terminal of the NMOS transistor 62. The gate terminals of the PMOS transistor 61 and the NMOS transistor 62 are connected to the third input terminal 13. The drain terminals of the PMOS transistor 61 and the NMOS transistor 62 are connected to the gate terminals of the NMOS transistors 41 and 42, respectively.

  That is, the first inverter circuit 60 gives the logically inverted version of the enable signal Enable1 input to the third input terminal 13 to the gate terminals of the NMOS transistors 41 and 42, respectively. The first inverter circuit 60 selectively sets the potential input to the gate terminals of the NMOS transistors 41 and 42 to either the first reference potential Vddh or the third reference potential Vss, and sets the operation state and the operation stop state. Acts as a means.

  The level shift circuit 1 operates as follows. When the enable signal Enable1 input to the third input terminal 13 is at the first reference potential Vddh level, the potential applied from the first inverter circuit 60 to the gate terminals of the NMOS transistors 41 and 42 becomes the third reference potential Vss level. The NMOS transistors 41 and 42 are turned off, and the level shift circuit 1 does not operate. At this time, the current flow of the first PMOS transistor 31 and the first NMOS transistor 41 is cut off, and the current flow of the second PMOS transistor 32 and the second NMOS transistor 42 is cut off. Can be suppressed.

  On the other hand, when the enable signal Enable1 input to the third input terminal 13 is at the third reference potential Vss level, the potential applied from the first inverter circuit 60 to the gate terminals of the NMOS transistors 41 and 42 is the first reference potential Vddh. The NMOS transistors 41 and 42 are turned on, and the level shift circuit 1 is operable.

The first input signal LSip input to the first input terminal is input to the node N ₁₁ through the first buffer circuit 51. The second input signal LSin inputted to the second input terminal is inputted to the node N ₂₁ via the second buffer circuit 52.

The first input signal LSIP (level of the node N ₁₁₎ is a high level, when the second input signal LSin (level of the node N ₂₁₎ is at the low level, the node N ₁₁ is approximately the second reference voltage Vddl level from becoming, the voltage between the gate terminal and the source terminal of the first 2NMOS transistor 41 will become approximately the first reference voltage Vddh level voltage obtained by subtracting the second reference voltage Vddl level, the node N ₂₁ is approximately the Since the third reference potential Vss level is reached, the voltage between the gate terminal and the source terminal of the first PMOS transistor 31 is approximately the first reference voltage Vddh level. The high level voltage value of the first output signal LSop is output as the high level voltage value of the first output signal LSop according to the ratio of the on-resistance of the first PMOS transistor 31 and the first NMOS transistor 41 at that time. Further, since the node N ₂₁ is approximately at the third reference voltage Vss level, the voltage between the gate terminal and the source terminal of the second NMOS transistor 42 is approximately at the first reference voltage Vddh level, and the node N 21 ₁₁ is approximately at the second reference potential Vddl level, the voltage between the gate terminal and the source terminal of the second PMOS transistor 32 is approximately the voltage obtained by subtracting the second reference voltage Vddl level from the first reference voltage Vddh. Become. The value of the low level voltage of the second output signal L Son is the low level voltage value of the second output signal L Son according to the ratio of the ON resistance of the second PMOS transistor 32 and the second NMOS transistor 42 at that time.

The first input signal LSIP (level of the node N ₁₁₎ is at low level, when the second input signal LSin (level of the node N ₂₁₎ is at a high level, the node N ₁₁ is roughly a third reference voltage Vss level Therefore, the voltage between the gate terminal and the source terminal of the first NMOS transistor 41 is approximately the first reference voltage Vddh level, and the node N ₂₁ is approximately the second reference potential Vddl level. The voltage between the gate terminal and the source terminal of the first PMOS transistor 31 is approximately a voltage obtained by subtracting the second reference voltage Vddl level from the first reference voltage Vddh level. The low level voltage value of the first output signal LSop is output as the low level voltage value of the first output signal LSop according to the ratio of the on-resistance of the first PMOS transistor 31 and the first NMOS transistor 41 at that time. The node N _21, since it roughly becomes the second reference voltage Vddl level, the voltage between the gate terminal and the source terminal of the second 2NMOS transistor 42 is approximately from the first reference voltage Vddh level second reference voltage Vss level becomes a voltage obtained by subtracting the node N _11, since it becomes approximately a third reference potential Vss level, the voltage between the gate terminal and the source terminal of the 2PMOS transistor 32 is approximately the first reference voltage Vddh level of voltage become. The high-level voltage value of the second output signal LSo is the high-level voltage value of the second output signal LSo according to the ratio of the on-resistance of the second PMOS transistor 32 and the second NMOS transistor 42 at that time.

  As described above, the level shift circuit 1 of the comparative example inputs the complementary input signals LSip and LSin to the input terminals 11 and 12, and the high level voltage values of the first output signal LSop and the second output signal LSon. The low level voltage value only needs to output an inverted voltage at which the inverter circuit connected to the next stage can operate.

  By the way, the level shift circuit 1 of such a comparative example operates without any problem when driven at a typical value (for example, Vddl = 1.0V, Vddh = 3.3V) in the rated range of the power supply voltage. When driven at the maximum value (eg, Vddl = 1.1V, Vddh = 3.6V) in the rated range of the power supply voltage, an overvoltage is applied to the transistors included in the first buffer circuit 51 and the second buffer circuit 52, respectively. Is done. Then, application of overvoltage to the transistor may deteriorate the characteristics of the transistor, and consequently the characteristics of the level shift circuit 1 may deteriorate. This will be further described below.

When the enable signal Enable1 input to the third input terminal 13 is at the third reference potential Vss level, the NMOS transistors 41 and 42 are turned on, and the level shift circuit 1 is operable. At this time, the first input signal LSIP (level of the node _{N 11)} is a high level, when the second input signal LSin (level of the node _{N 21)} is at the low level, the 1PMOS transistor 31 is turned on, Moreover, PMOS transistors _{QP 12} is also turned on in the first buffer circuit 51.

Thus, although the both-on state of the 1PMOS transistor 31, NMOS transistor 41 and PMOS transistor _{QP 12} which are serially connected between the first reference potential Vddh and the second reference potential Vddl, the first reference potential Vddh is for higher potential than the second reference potential Vddl, PMOS transistor QP ₁₂ becomes a reverse bias state, so that the potential of the node N _11, determined by the ratio of the on-resistance of the three transistors, the second reference potential Higher than Vddl. When the level shift circuit 1 at the maximum value of the rated range of the power supply voltage as driving, the overvoltage is applied between the PMOS transistors QP ₁₂ and NMOS transistors QN ₁₂ of the respective gate and drain terminals, the overvoltage Long-term operation in the state causes deterioration of transistor characteristics such as a decrease in current driving force and a delay in gate delay time.

FIG. 2 is a diagram illustrating a simulation result of the potentials of the nodes N ₁₁ and N ₁₂ of the level shift circuit 1 of the comparative example. As shown in this figure, the potential of the node N ₁₁ when the first input signal LSip is at a high level, which is higher than the maximum rated value (= 1.1V) of the second reference potential Vddl 1.15V . Therefore, PMOS overvoltage between the gate and drain terminals between the gate terminal and the drain terminal of the transistor QP ₁₂ and an NMOS transistor QN ₁₂ is applied, by prolonged operation under the over-voltage applied state, the current driving force As a result, the transistor characteristics deteriorate, such as a decrease in gate delay time and delay.

  The level shift circuits 2A and 2B according to the present embodiment described below can solve the problems of the level shift circuit 1 of the comparative example.

  FIG. 3 is a diagram showing a configuration of the level shift circuit 2A according to the first embodiment. The level shift circuit 2A shown in this figure includes a first input terminal 11, a second input terminal 12, a third input terminal 13, a first output terminal 21, a second output terminal 22, a first PMOS transistor 31, and a second PMOS transistor 32. , A first NMOS transistor 41, a second NMOS transistor 42, a first buffer circuit 51A, a second buffer circuit 52A, and a first inverter circuit 60.

  Compared with the configuration of the level shift circuit 1 of the comparative example shown in FIG. 1, the level shift circuit 2A according to the first embodiment shown in FIG. 3 is replaced with the first buffer circuit 51A. And the second buffer circuit 52 </ b> A is provided instead of the second buffer circuit 52.

Configuration and Comparing the first buffer circuit 51 in FIG. 1, the first buffer circuit 51A in FIG. 3, differs in that it further includes a PMOS transistor _{QP 13.} The source terminal of the PMOS transistor QP ₁₃ is connected to the node N ₁₁ , and the drain terminal and the gate terminal of the PMOS transistor QP ₁₃ are each connected to the node N ₁₂ . Compared to the configuration of the second buffer circuit 52 in FIG. 1, the second buffer circuit 52A in FIG. 3, it differs in that it further includes a PMOS transistor _{QP 23.} The source terminal of the PMOS transistor QP ₂₃ is connected to the node N ₂₁ , and the drain terminal and the gate terminal of the PMOS transistor QP ₂₃ are each connected to the node N ₂₂ .

  The operation of the level shift circuit 2A according to the first embodiment is substantially the same as the operation of the level shift circuit 1 of the comparative example. However, the level shift circuit 2A according to the first embodiment can solve the problems of the level shift circuit 1 of the comparative example described above. This will be further described below.

In the level shift circuit 2A according to the first embodiment, when the enable signal Enable1 input to the third input terminal 13 is at the third reference potential Vss level, the NMOS transistors 41 and 42 are turned on, and the level shift circuit 2A becomes operable. At this time, the first input signal LSIP (level of the node _{N 11)} is a high level, when the second input signal LSin (level of the node _{N 21)} is at the low level, the 1PMOS transistor 31 is turned on, In the first buffer circuit 51A, the PMOS transistors QP ₁₂ and QP ₁₃ and the NMOS transistor QN ₁₁ are also turned on.

Therefore, in the level shift circuit 2A according to the first embodiment, the first PMOS transistor 31, the NMOS transistor 41, and the PMOS transistor QP ₁₂ connected in series between the first reference potential Vddh and the second reference potential Vddl. Both are turned on. At the same time, both of turning on the first reference potential Vddh and the 1PMOS transistor 31 are serially connected between the second reference potential Vddl, NMOS transistor 41, PMOS transistor _{QP 13} and an NMOS transistor _{QN 11.}

Therefore, current flowing from the first reference potential Vddh to the node _{N 11} is, PMOS transistor to the one directed to the second reference potential Vddl through _{QP 12,} PMOS transistors _{QP 13} and through the NMOS transistor _{QN 11} third reference potential Vss It is divided into those that go to. As a result, in contrast to Comparative Example, with increasing the potential of the node potential _{N 11} is suppressed, since the potential of the node potential _{N 12} rises slightly, PMOS transistors _{QP 12} and NMOS transistors _{QN 12} respective gate terminals The overvoltage is suppressed from being applied between the drain terminal and the drain terminal, and the deterioration of characteristics can be suppressed even when driven at the maximum value in the rated range of the power supply voltage.

The first input signal LSIP (level of the node _{N 11)} is at low level, when the second input signal LSin (level of the node _{N 21)} is at a high level, the first 1PMOS transistor 32 is turned on, also In the second buffer circuit 52A, the PMOS transistors QP ₂₂ and QP ₂₃ and the NMOS transistor QN ₂₁ are also turned on.

Therefore, in the level shift circuit 2A according to the first embodiment, the first PMOS transistor 32, the NMOS transistor 42, and the PMOS transistor QP ₂₂ connected in series between the first reference potential Vddh and the second reference potential Vddl. Both are turned on. At the same time, all of the first PMOS transistor 32, the NMOS transistor 42, the PMOS transistor QP _23, and the NMOS transistor QN ₂₁ connected in series between the first reference potential Vddh and the second reference potential Vddl are turned on.

Therefore, current flowing from the first reference potential Vddh to the node _{N 21} is, PMOS transistor to the one directed to the second reference potential Vddl through _{QP 22,} PMOS transistors _{QP 23} and through the NMOS transistor _{QN 21} third reference potential Vss It is divided into those that go to. As a result, in contrast to the comparative example, the potential of the node potential N ₂₁ is suppressed from rising and the potential of the node potential N ₂₂ slightly increases. Therefore, the gate terminals of the PMOS transistor QP ₂₂ and the NMOS transistor QN ₂₂ The overvoltage is suppressed from being applied between the drain terminal and the drain terminal, and the deterioration of characteristics can be suppressed even when driven at the maximum value in the rated range of the power supply voltage.

FIG. 4 is a diagram illustrating a simulation result of the potentials of the nodes N ₁₁ and N _{12 of the} level shift circuit 2A according to the first embodiment. As shown in this figure, the potential of the node N ₁₁ when the first input signal LSip is at a high level, the second reference potential Vddl (= 1.1V) is from is slightly a higher 1.107V, node voltage difference between _{N 11} and the node _{N 12} is 1.08V, and the lower than the maximum rated value (= 1.1V). Therefore, PMOS transistors _{QP 12} and is prevented from overvoltage is applied between the gate terminal and the drain terminal of the NMOS transistor _{QN 12,} deterioration of the transistor characteristics can be suppressed.

In addition, in the level shift circuit 2A according to the first embodiment, the addition of the PMOS transistors QP ₁₃ and QP ₂₃ increases the parasitic capacitance connected to the nodes N ₁₁ and N ₂₁ . However, by making the transistor size of the PMOS transistors QP ₁₃ and QP ₂₃ sufficiently small compared to the PMOS transistors QP ₁₂ and QP ₂₂ , the rate of increase in the capacitance value is small, so that the operating speed of the level shift circuit 2 A is increased. The effect of is slight.

In the level shift circuit 2A according to the first embodiment, when the enable signal Enable1 input to the third input terminal 13 is at the first reference potential Vddh level, the NMOS transistors 41 and 42 are in the off state, and the level Shift circuit 2A does not operate. However, this time, if you enter the first input signal and a second input signal complementary to each other, the level of the first input signal LSIP (level of the node N ₁₁₎ is the node N ₁₂ at the high level is a low level , the level of the second input signal LSin (node _N level of ₂₁₎ the node _{N 22} is at the low level when a Haiberu, or the first input signal LSIP (level of the node _{N 11)} of the node _{N 12} in the low level level is a high level, when the level of the second input signal LSin (node-level N ₂₁₎ is the node N ₂₂ at the high level is at the low level, between the first reference potential Vddh and third reference potential Vss All of PMOS transistors QP ₁₂ and QP ₁₃ and NMOS transistor QN ₁₁ connected in series are turned on. Alternatively, all of the PMOS transistors QP ₂₂ and QP ₂₃ and the NMOS transistor QN ₂₁ are turned on. As a result, although the level shift circuit 2A does not operate, a current flows between the second reference potential Vddl and the third reference potential Vss, and the static power increases.

Furthermore, if you enter the first input signal and second input signal is not complementary, the first input signal LSip and second input signal LSin goes high both the level of the node N ₁₂ becomes low level, the node level N ₁₁ becomes high level, similarly, the level of the node N ₂₂ becomes a low level, the level of the node N ₂₁ becomes a high level. In such a state, the PMOS transistors QP ₁₂ and QP ₁₃ and the NMOS transistor QN ₁₁ connected in series between the first reference potential Vddh and the third reference potential Vss are turned on, and the PMOS transistor All of QP ₂₂ and QP ₂₃ and the NMOS transistor QN ₂₁ are turned on. As a result, although the level shift circuit 2A does not operate, a current flows between the second reference potential Vddl and the third reference potential Vss, and the static power further increases.

However, when the first input signal LSip and second input signal LSin goes low both the level of the node N ₁₂ becomes high level, the level of the node N ₁₁ becomes low level. Similarly, the level of the node N ₂₂ becomes high level, the level of the node N ₂₁ becomes low level. At this time, if the enable signal Enable1 input to the third input terminal 13 of the level shift circuit 2A is at the first reference potential Vddh level and the level shift circuit 2A does not operate, the first reference potential Vddh and the third reference potential Vss. PMOS transistors QP ₁₂ and QP ₁₃ and NMOS transistor QN ₁₁ connected in series to each other are turned off, and PMOS transistors QP ₂₂ and QP ₂₃ and NMOS transistor QN ₂₁ are both turned off. As a result, when the level shift circuit 2A does not operate, no current flows between the second reference potential Vddl and the third reference potential Vss, and static power is suppressed.

  When the first input signal LSip and the second input signal LSip complementary to each other are input as described above, and the non-complementary input signals, that is, the first input signal LSip and the second input signal LSin are at the high level. In order to avoid the problem that the static power in this case becomes large, it is preferable to adopt a configuration as shown in FIG.

  FIG. 5 is a diagram showing a configuration of the level shift circuit 2B according to the second embodiment. The level shift circuit 2B shown in this figure includes a first input terminal 11, a second input terminal 12, a third input terminal 13, a fourth input terminal 14, a first output terminal 21, a second output terminal 22, and a first PMOS transistor. 31, a second PMOS transistor 32, a first NMOS transistor 41, a second NMOS transistor 42, a first buffer circuit 51B, a second buffer circuit 52B, a first inverter circuit 60, and a second inverter circuit 70.

  Compared with the configuration of the level shift circuit 2A according to the first embodiment shown in FIG. 3, the level shift circuit 2B according to the second embodiment shown in FIG. 5 has a first buffer circuit 51A instead of the first buffer circuit 51A. It differs in that it includes a buffer circuit 51B, differs in that it includes a second buffer circuit 52B instead of the second buffer circuit 52A, and differs in that it further includes a fourth input terminal 14 and a second inverter circuit 70. .

Compared to the configuration of the first buffer circuit 51A in FIG. 3, the first buffer circuit 51B in FIG. 5, it differs in that it further includes a switch SW _1. Switch SW ₁ is turned on / off the connection between the source terminal and the node _{N 11} of the PMOS transistor _{QP 13.} Compared to the configuration of the second buffer circuit 52A in FIG. 3, the second buffer circuit 52B in FIG. 5, it differs in that it further includes a switch SW _2. Switch SW ₂ is turned on / off the connection between the source terminal and the node _{N 21} of the PMOS transistor _{QP 23.} Each of the switches SW ₁ and SW ₂ may be configured by a PMOS transistor as illustrated.

The fourth input terminal 14 inputs an enable signal Enable2. The second inverter circuit 70 includes a PMOS transistor 71 and an NMOS transistor 72. The second reference potential Vddl is input to the source terminal of the PMOS transistor 71. The third reference potential Vss is input to the source terminal of the NMOS transistor 72. The gate terminals of the PMOS transistor 71 and the NMOS transistor 72 are connected to the fourth input terminal 14. The drain terminals of the PMOS transistor 71 and the NMOS transistor 72 are connected to the gate terminals of the PMOS transistors as the switches SW ₁ and SW ₂ .

That is, the second inverter circuit 70 gives the logically inverted version of the enable signal Enable2 input to the fourth input terminal 14 to the gate terminals of the PMOS transistors as the switches SW ₁ and SW ₂ . The second inverter circuit 70 functions as a switch setting means for selectively setting the switch SW ₁ and the switch SW ₂ to either on and simultaneously off.

The level shift circuit 2B operates as follows. When the enable signal Enable1 input to the third input terminal 13 is at the first reference potential Vddh level, the potential applied from the first inverter circuit 60 to the gate terminals of the NMOS transistors 41 and 42 becomes the third reference potential Vss level. The NMOS transistors 41 and 42 are turned off, and the level shift circuit 2B does not operate. At this time, the enable signal Enable2 input to the fourth input terminal 14 is set to the third reference potential Vss level, and the potential applied from the second inverter circuit 70 to the switches SW ₁ and SW ₂ is the second reference potential Vddl level. Thus, the PMOS transistors as the switches SW ₁ and SW ₂ are turned off. Therefore, when the level shift circuit 2B is not operating, the first input signal and the second input signal are either complementary or non-complementary to each other of the PMOS transistors QP ₁₂ and QP ₁₃ and the NMOS transistor QN ₁₁ . Are also turned off, and the PMOS transistors QP ₂₂ and QP ₂₃ and the NMOS transistor QN ₂₁ are both turned off. As a result, the current is suppressed from flowing between the second reference potential Vddl and the third reference potential Vss, and an increase in the quiescent current is suppressed.

On the other hand, when the enable signal Enable1 input to the third input terminal 13 is at the third reference potential Vss level, the potential applied from the first inverter circuit 60 to the gate terminals of the NMOS transistors 41 and 42 is the first reference potential Vddh. Become a level. At this time, the enable signal Enable2 input to the fourth input terminal 14 is set to the second reference potential Vddl level, and the potential supplied from the second inverter circuit 70 to the switches SW ₁ and SW ₂ is the third reference potential Vss level. Thus, the PMOS transistors as the switches SW ₁ and SW ₂ are turned on. Therefore, the level shift circuit 2A according to the second embodiment can perform the same operation as the level shift circuit 2A according to the first embodiment and can achieve the same effect. Further, by making the transistor size of the PMOS transistors SW ₁ and SW ₂ sufficiently small with respect to the PMOS transistors QP ₁₂ and QP ₂₂ , the rate of increase in the capacitance value is small, so that the operation speed of the level shift circuit 2 B is increased. The effect of is slight.

  1, 2A, 2B ... level shift circuit, 11 ... first input terminal, 12 ... second input terminal, 13 ... third input terminal, 14 ... fourth input terminal, 21 ... first output terminal, 22 ... second output Terminals 31 ... first PMOS transistor 32 ... second PMOS transistor 41 ... first NMOS transistor 42 ... second NMOS transistor 51, 51A, 51B ... first buffer circuit 52,52A, 52B ... second buffer circuit 60 ... 1st inverter circuit, 70 ... 2nd inverter circuit.

Claims (3)

A first input signal and a second input signal complementary to each other are input, and a first output complementary to each other having a high level voltage value larger than a high level voltage value of the first input signal and the second input signal. A level shift circuit for outputting a signal and a second output signal,
A first input terminal for inputting the first input signal;
A second input terminal for inputting the second input signal;
A first output terminal for outputting the first output signal;
A second output terminal for outputting the second output signal;
A first buffer circuit for outputting the first input to the input terminal the signal of the first input signal of the same level to the node N _11,
A second buffer circuit for outputting the second input to the input terminal the signal of the second input signal of the same level to the node N _21,
A source terminal first reference potential Vddh is input, a drain terminal connected to said first output terminal, a first 1PMOS transistor having a gate terminal connected to the node N _21,
A source terminal first reference potential Vddh is input, a drain terminal connected to said second output terminal, a first 2PMOS transistor having a gate terminal connected to the node N _11,
A source terminal connected to the node N _11, and a drain terminal connected to said first output terminal, a first 1NMOS transistor having a gate terminal to which a first reference potential Vddh is inputted,
A source terminal connected to the node N _21, and the second output a drain terminal connected to terminal, and a second 2NMOS transistor having a gate terminal to which a first reference potential Vddh is inputted,
With
The first buffer circuit includes PMOS transistors QP ₁₁ , QP ₁₂ , QP ₁₃ and NMOS transistors QN ₁₁ , QN _12. The source terminals of the PMOS transistors QP ₁₁ , QP ₁₂ are connected to the second reference potential Vddl, and the NMOS The source terminals of the transistors QN ₁₁ and QN ₁₂ are connected to the third reference potential Vss, the gate terminals of the PMOS transistor QP ₁₁ and NMOS transistor QN ₁₁ are connected to the first input terminal, and the PMOS transistor QP ₁₂ and NMOS transistor The drain terminal of each QN ₁₂ and the source terminal of the PMOS transistor QP ₁₃ are connected to the node N ₁₁ , and the PMOS transistors QP ₁₁ and QP ₁₃ and the NMOS transistor QN ₁₁ respectively. And the gate terminals of the PMOS transistors QP ₁₂ and QP ₁₃ and the NMOS transistor QN ₁₂ are connected to the node N ₁₂ ,
The second buffer circuit includes PMOS transistors QP ₂₁ , QP ₂₂ , QP ₂₃ and NMOS transistors QN ₂₁ , QN ₂₂ , the source terminals of the PMOS transistors QP ₂₁ , QP ₂₂ are connected to the second reference potential Vddl, and the NMOS The source terminals of the transistors QN ₂₁ and QN ₂₂ are connected to the third reference potential Vss, the gate terminals of the PMOS transistor QP ₂₁ and the NMOS transistor QN ₂₁ are connected to the second input terminal, and the PMOS transistor QP ₂₂ and the NMOS transistor The drain terminal of each QN ₂₂ and the source terminal of the PMOS transistor QP ₂₃ are connected to the node N ₂₁ , and the PMOS transistors QP ₂₁ and QP ₂₃ and the NMOS transistor QN ₂₁ respectively. And the drain terminals of the PMOS transistors QP ₂₂ and QP ₂₃ and the NMOS transistors QN ₂₂ are connected to the node N ₂₂ , respectively.
A level shift circuit (where Vddh>Vddl> Vss). The first buffer circuit further comprises a switch SW ₁ for turning on / off the connection between the source terminal of the PMOS transistor _{QP 13} and the node _{N 11,}
The second buffer circuit further comprises a switch SW ₂ for turning on / off the connection between the source terminal of the PMOS transistor _{QP 23} and the node _{N 21,}
Switch setting means for selectively setting the switch SW ₁ and the switch SW ₂ to either ON and OFF simultaneously;
The level shift circuit according to claim 1.   It further comprises gate potential setting means for selectively setting the potential input to the respective gate terminals of the first NMOS transistor and the second NMOS transistor to either the first reference potential Vddh or the third reference potential Vss. The level shift circuit according to claim 1.

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