JP2011114066A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011114066A
JP2011114066A JP2009267499A JP2009267499A JP2011114066A JP 2011114066 A JP2011114066 A JP 2011114066A JP 2009267499 A JP2009267499 A JP 2009267499A JP 2009267499 A JP2009267499 A JP 2009267499A JP 2011114066 A JP2011114066 A JP 2011114066A
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wiring board
printed wiring
solder resist
semiconductor chip
conductor
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Tetsuya Tokunaga
哲也 徳永
Masatoshi Yago
政敏 家合
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To prevent non-bonding of a bonding wire due to contamination of a connecting electrode on a printed wiring board caused by outflow of an adhesive for mounting a semiconductor chip on the printed wiring board of a semiconductor device. <P>SOLUTION: The semiconductor device includes: a printed wiring board 1 where a conductor is formed in a part of one surface of a flat base material 8, and solder resist 6 is arranged on a part of the conductor and a part of the one surface of the base material; a semiconductor chip 9 mounted on a principal surface of the printed wiring board through an adhesive 11; and a bonding wire 12 for connecting a chip electrode 10 formed on the semiconductor chip to a connecting electrode 7 formed on the principal surface of the printed wiring board. Here, between the connecting electrode and the semiconductor chip, a first base material exposing part 8a, a damming part composed of the conductor and the solder resist, and a solder resist recessed part 6c composed by directly forming the solder resist on the base material are arranged in the order of proximity from the connecting electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置に関し、特にプリント配線基板の主面に半導体チップを搭載し、プリント配線基板の接続用電極と半導体チップのチップ電極とをボンディングワイヤで接続した半導体装置に関するものである。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip is mounted on a main surface of a printed wiring board, and a connection electrode of the printed wiring board and a chip electrode of the semiconductor chip are connected by a bonding wire.

各種電子機器に採用されているＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）形半導体装置は、プリント配線基板上に搭載された半導体チップの電極パッドと、前記プリント配線基板上のボンディング電極とを導電性ワイヤを介してワイヤボンド接続することにより電気的に接続した上で、前記プリント配線基板の前記半導体チップ搭載面を樹脂封止することにより製造される。   A BGA (Ball Grid Array) type semiconductor device employed in various electronic devices uses a conductive wire to connect an electrode pad of a semiconductor chip mounted on a printed wiring board and a bonding electrode on the printed wiring board. It is manufactured by resin-sealing the semiconductor chip mounting surface of the printed wiring board after being electrically connected by wire bond connection.

近年の電子機器の高機能化に伴い、ＢＧＡ形半導体装置の高機能化が進み、前記ＢＧＡ形半導体装置に搭載される半導体チップの大面積化が年々進んでいる。そのため、前記ＢＧＡ形半導体装置において、前記半導体チップと前記プリント配線基板上の前記ボンディング電極との間の距離が縮小する傾向にある。これにより、前記半導体チップを前記プリント配線基板上に接着するためのダイボンドペーストが前記ボンディング電極へ向かって流出することで前記ボンディング電極の表面が汚染され、ワイヤボンド不着を起こす危険性が高まっている。   With the recent increase in functionality of electronic devices, the performance of BGA type semiconductor devices has increased, and the area of semiconductor chips mounted on the BGA type semiconductor devices has increased year by year. Therefore, in the BGA type semiconductor device, the distance between the semiconductor chip and the bonding electrode on the printed wiring board tends to be reduced. As a result, the surface of the bonding electrode is contaminated due to the die bond paste for bonding the semiconductor chip on the printed wiring board flowing out toward the bonding electrode, and there is an increased risk of non-bonding of the wire bond. .

この対策として、図３に示すような半導体装置が知られている（特許文献１）。半導体装置１０１は、プリント配線基板１０２の半導体チップ搭載面に半導体チップ１０３が接着剤１０５を介して搭載されている。プリント配線基板１０２は、基板コア１０２ａの両面にソルダーレジスト１０２ｃが塗布されて形成されている。半導体チップ１０３のパッド電極１０３ａとプリント配線基板１０２上に形成されたボンディング電極１０２ｂとが、ボンディングワイヤ１０４を介して電気的に接続されており、ボンディング電極１０２ｂはプリント配線基板１０２に形成された配線を介して、プリント配線基板１０２裏面の電極に電気的に接続されている。半導体チップ１０３とボンディング電極１０２ｂとの間には、接着剤１０５の流出を防止する額縁状の溝１０２ｄがソルダーレジスト１０２ｃに設けられている。この溝１０２ｄによって、ダイボンド時に接着剤１０５が接続用電極１０２ｂまで流出し前記ボンディング電極１０２ｂ表面を汚染することを防止する。   As a countermeasure, a semiconductor device as shown in FIG. 3 is known (Patent Document 1). In the semiconductor device 101, a semiconductor chip 103 is mounted on a semiconductor chip mounting surface of a printed wiring board 102 via an adhesive 105. The printed wiring board 102 is formed by applying a solder resist 102c on both sides of a board core 102a. A pad electrode 103 a of the semiconductor chip 103 and a bonding electrode 102 b formed on the printed wiring board 102 are electrically connected via a bonding wire 104, and the bonding electrode 102 b is a wiring formed on the printed wiring board 102. And is electrically connected to the electrode on the back surface of the printed wiring board 102. Between the semiconductor chip 103 and the bonding electrode 102b, a frame-shaped groove 102d that prevents the adhesive 105 from flowing out is provided in the solder resist 102c. The groove 102d prevents the adhesive 105 from flowing out to the connection electrode 102b during the die bonding and contaminating the surface of the bonding electrode 102b.

特開２００１−２６７４５２号公報Japanese Patent Laid-Open No. 2001-267552

ところが、プリント配線基板１０２の半導体チップ搭載面における、半導体チップ１０３とボンディング電極１０２ｂの間のスペースには、ビアが多数設けられていることが多い。基板製造ルール上、ビアランドは必ずソルダーレジスト１０２ｃにより完全に被覆されなければならないため、半導体チップ１０３周縁部とボンディング電極１０２ｂの間の距離、ビアの配置によっては、ソルダーレジスト１０２ｃ上の溝１０２ｄの深さＤ１の最大値が制限されたり、あるいは、深さＤ１の加工公差によっては溝１０２ｄを設けることができない箇所が発生したりすることが起こり得る。   However, many vias are often provided in the space between the semiconductor chip 103 and the bonding electrode 102 b on the semiconductor chip mounting surface of the printed wiring board 102. The via land must be completely covered with the solder resist 102c in accordance with the substrate manufacturing rule. Therefore, depending on the distance between the peripheral edge of the semiconductor chip 103 and the bonding electrode 102b and the arrangement of the via, The maximum value of the depth D1 may be limited, or a portion where the groove 102d cannot be provided may occur depending on the processing tolerance of the depth D1.

また、特許文献１に開示された技術では、溝１０２ｄの深さＤ１は最大でもソルダーレジスト１０２ｃの厚み分となるため、ソルダーレジストの膜厚の面内バラツキや深さＤ１の加工公差、あるいは接着剤１０５の流出量、粘度によっては、上記溝１０２ｄが接着剤１０５を完全にせき止められないことが起こり得る。   In the technique disclosed in Patent Document 1, since the depth D1 of the groove 102d is at most the thickness of the solder resist 102c, the in-plane variation of the solder resist film thickness, the processing tolerance of the depth D1, or adhesion Depending on the outflow amount and viscosity of the agent 105, the groove 102d may not completely block the adhesive 105.

上記の課題を解決するために、本発明に係る半導体装置は、平板状の基材の一面の一部に導体が形成され、該導体の一部及び該基材の一面の一部上にソルダーレジストが設けられたプリント配線基板と、前記プリント配線基板の主面に接着剤を介して搭載された半導体チップと、前記半導体チップに形成されたチップ電極と前記プリント配線基板の主面に形成された接続用電極とを接続するボンディングワイヤとを備え、前記接続用電極と前記半導体チップとの間には、該接続用電極から近い順に、前記基材が露出した第１の基材露出部と、前記導体及び前記ソルダーレジストからなる堰き止め部と、前記基材上に直接前記ソルダーレジストが形成されているソルダーレジスト凹部とが設けられている構成とした。   In order to solve the above problems, a semiconductor device according to the present invention includes a conductor formed on a part of one surface of a flat substrate, and a solder on a part of the conductor and a part of one surface of the substrate. A printed wiring board provided with a resist, a semiconductor chip mounted on the main surface of the printed wiring board via an adhesive, a chip electrode formed on the semiconductor chip, and a main surface of the printed wiring board A bonding wire that connects the connecting electrode, and a first base material exposed portion where the base material is exposed between the connecting electrode and the semiconductor chip in order from the connecting electrode; A damming portion made of the conductor and the solder resist, and a solder resist concave portion in which the solder resist is directly formed on the base material are provided.

ソルダーレジスト凹部に取り囲まれている、基材が露出した第２の基材露出部がさらに設けられている構成とすることもできる。   It can also be set as the structure further provided with the 2nd base material exposed part which the base material exposed surrounded by the soldering resist recessed part.

上記の構成とすることにより、半導体チップ下面から接着剤がはみ出しても、接続用電極に達することを確実に防ぐことができ、ボンディングワイヤが接続用電極に付着しないことを防止することができる。   With the above configuration, even when the adhesive protrudes from the lower surface of the semiconductor chip, it can be reliably prevented from reaching the connection electrode, and the bonding wire can be prevented from adhering to the connection electrode.

（ａ）は第１の実施形態の半導体装置を示す平面図、（ｂ）はＡ−Ａ断面図、（ｃ）はプリント配線基板上の導体の詳細図である。(A) is a top view which shows the semiconductor device of 1st Embodiment, (b) is AA sectional drawing, (c) is detail drawing of the conductor on a printed wiring board. （ａ）は第２の実施形態の半導体装置を示す平面図、（ｂ）はＢ−Ｂ断面図、（ｃ）はプリント配線基板上の導体の詳細図である。(A) is a top view which shows the semiconductor device of 2nd Embodiment, (b) is BB sectional drawing, (c) is detail drawing of the conductor on a printed wiring board. （ａ）は従来の半導体装置を示す平面図、（ｂ）はＣ−Ｃ断面図である。(A) is a top view which shows the conventional semiconductor device, (b) is CC sectional drawing.

以下、本発明の実施形態を図面に基づいて詳細に説明する。以下の図面においては、説明の簡潔化のため、実質的に同一の機能を有する構成要素を同一の参照符号で示す。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity.

（第１の実施形態）
第１の実施形態においては、プリント配線基板の半導体チップ搭載面上に、銅等の導電体を薄く形成することにより設けられた導体の平面（導体プレーン）が存在するが、前記導体プレーンをエッチングにより部分的に除去することで、導体のない領域（導体プレーン開口）を形成することができる。また、ボンディングワイヤを介して半導体チップとプリント配線基板との電気的接続を行うためにプリント配線基板上に設けられた接続用電極を囲んでソルダーレジスト開口が設けられている。以下、具体的に説明をする。 (First embodiment)
In the first embodiment, there is a conductor plane (conductor plane) provided by thinly forming a conductor such as copper on the semiconductor chip mounting surface of the printed wiring board. The conductor plane is etched. By removing partly, a region without a conductor (conductor plane opening) can be formed. In addition, a solder resist opening is provided so as to surround a connection electrode provided on the printed wiring board for electrical connection between the semiconductor chip and the printed wiring board via a bonding wire. Hereinafter, a specific description will be given.

図１は、第１の実施形態の半導体装置の一部を示す平面図ならびに断面図である。プリント配線基板１は、基材８の一面に導体のパターン（導体プレーン２，２ａ，２ｂ，２ｃ）が形成され、その上にソルダーレジスト６が形成されている。導体のパターンは基材８の一面の一部に設けられ、ソルダーレジスト６も導体上の一部と基材８上の一部に設けられているだけであるので、上から見ると、導体の一部及び基材８の一部がソルダーレジスト６に覆われずに露出している。プリント配線基板１の主面上には、半導体チップ９が接着剤１１によって搭載されて固定されている。   FIG. 1 is a plan view and a cross-sectional view showing a part of the semiconductor device of the first embodiment. In the printed wiring board 1, a conductor pattern (conductor planes 2, 2a, 2b, 2c) is formed on one surface of a base material 8, and a solder resist 6 is formed thereon. Since the pattern of the conductor is provided on a part of one surface of the substrate 8 and the solder resist 6 is also provided only on a part on the conductor and a part on the substrate 8, when viewed from above, Part and part of the substrate 8 are exposed without being covered with the solder resist 6. On the main surface of the printed wiring board 1, a semiconductor chip 9 is mounted and fixed by an adhesive 11.

半導体チップ９上には電極パッド（チップ電極）１０が設けられていて、プリント配線基板１の半導体チップ９搭載面（主面）上に接続用電極７が設けられている。そして電極パッド１０と接続用電極７にボンディングされたボンディングワイヤ１２を介して、半導体チップ９とプリント配線基板１とが電気的に接続されている。さらに、プリント配線基板１の半導体チップ９搭載面上には導体プレーン２，２ａ（帯状）、２ｂ、２ｃならびにソルダーレジスト６が形成されており、ソルダーレジスト６の一部が除去されるような構造で、接続用電極７を囲んでソルダーレジスト開口６ａが設けられている。   Electrode pads (chip electrodes) 10 are provided on the semiconductor chip 9, and connection electrodes 7 are provided on the semiconductor chip 9 mounting surface (main surface) of the printed wiring board 1. The semiconductor chip 9 and the printed wiring board 1 are electrically connected via the bonding wire 12 bonded to the electrode pad 10 and the connection electrode 7. Furthermore, conductor planes 2, 2a (band-like), 2b, 2c and solder resist 6 are formed on the surface of the printed wiring board 1 where the semiconductor chip 9 is mounted, and a part of the solder resist 6 is removed. Thus, a solder resist opening 6 a is provided so as to surround the connection electrode 7.

接続用電極７は導体プレーン２の一部であり、接続用電極７上には金メッキ７ａが形成されている。導体プレーン２には、プリント配線基板１の下面に形成されているボールランドとの電気的接続を確保するためにビアランド４が形成され、かつ、ビア５が接続されている。   The connection electrode 7 is a part of the conductor plane 2, and a gold plating 7 a is formed on the connection electrode 7. In the conductor plane 2, via lands 4 are formed in order to ensure electrical connection with ball lands formed on the lower surface of the printed wiring board 1, and vias 5 are connected.

接続用電極７の半導体チップ９側に隣接して第一の導体プレーン開口（基材８上から導体が除去された部分）３ａならびに基材８が半導体チップ９搭載面上に露出しこの第一の導体プレーン開口３内に存する第１の基材露出部８ａが設けられている。第一の導体プレーン開口３ａの半導体チップ９側に隣接して導体プレーン２ａとその導体プレーン２ａの上面に設けられたソルダーレジスト６ｂとからなる堰き止め部が設けられ、さらにこの堰き止め部の半導体チップ９側に隣接して第二の導体プレーン開口３ｂが設けられ、第二の導体プレーン開口３ｂ部分にソルダーレジスト凹部６ｃが設けられている。ソルダーレジスト凹部６ｃは基材８上に直接ソルダーレジスト６を載せているところであるため、堰き止め部のような導体２ａ上にソルダーレジスト６ｂを載せた部分よりも基材８上の厚みが小さく、周囲に比べて窪んだ部分となっている。   A first conductor plane opening (a portion from which the conductor is removed from the base material 8) 3a and the base material 8 are exposed on the semiconductor chip 9 mounting surface adjacent to the semiconductor chip 9 side of the connection electrode 7. The first base material exposed portion 8a existing in the conductor plane opening 3 is provided. A damming portion comprising a conductor plane 2a and a solder resist 6b provided on the upper surface of the conductor plane 2a is provided adjacent to the semiconductor chip 9 side of the first conductor plane opening 3a. Further, a semiconductor of this damming portion is provided. A second conductor plane opening 3b is provided adjacent to the chip 9 side, and a solder resist recess 6c is provided in the second conductor plane opening 3b. Since the solder resist recess 6c is where the solder resist 6 is directly placed on the base 8, the thickness on the base 8 is smaller than the part where the solder resist 6b is placed on the conductor 2a such as a damming portion. It is a recessed part compared to the surroundings.

上記のような構成とすることにより、ダイボンド時に半導体チップ９下面から流出した接着剤１１をせき止めるためのダム（ソルダーレジスト凹部６ｃ）の深さを十分確保することができ、もし半導体チップ９をプリント配線基板１へ接着する際に接着剤１１が接続用電極７へ向かって流出した場合であっても、接着剤１１は、導体プレーン２ｂならびにソルダーレジスト６ｂからなる堰き止め部によってせき止められることによりソルダーレジスト凹部６ｃへ流入・滞留する。   With the above-described configuration, it is possible to secure a sufficient depth of the dam (solder resist concave portion 6c) for blocking the adhesive 11 flowing out from the lower surface of the semiconductor chip 9 during die bonding. Even when the adhesive 11 flows out toward the connection electrode 7 when adhering to the wiring board 1, the adhesive 11 is blocked by the damming portion including the conductor plane 2b and the solder resist 6b. It flows and stays in the resist recess 6c.

さらに、もし接着剤１１の流出量が多大のため、接着剤１１が堰き止め部を越えて接続用電極７へ向かって流れた場合でも、第１の基板露出部８ａに接着剤１１が滞留することで、接着剤１１による接続用電極７の上面部分の汚染を防止することができる。   Further, since the amount of the adhesive 11 flowing out is great, even if the adhesive 11 flows toward the connection electrode 7 beyond the damming portion, the adhesive 11 stays in the first substrate exposed portion 8a. Thus, contamination of the upper surface portion of the connection electrode 7 by the adhesive 11 can be prevented.

これにより、接着剤１１が接続用電極７上面に形成された金メッキ７ａ上に流入することで発生する汚染によって生ずるワイヤボンド不着を防止することができる。   Thereby, it is possible to prevent non-bonding of wire bonds caused by contamination that occurs when the adhesive 11 flows onto the gold plating 7 a formed on the upper surface of the connection electrode 7.

（第２の実施形態）
図２は、第２の実施形態の半導体装置を示す平面図ならびに断面図である。第２の実施形態は第２の基材露出部８ｂが存している点が第１の実施形態と異なっており、それ以外は同じであるので、第１の実施形態と異なっている点を以下に説明する。 (Second Embodiment)
FIG. 2 is a plan view and a cross-sectional view showing the semiconductor device of the second embodiment. The second embodiment is different from the first embodiment in that the second substrate exposed portion 8b exists, and the other points are the same. Therefore, the second embodiment is different from the first embodiment. This will be described below.

第２の実施形態の半導体装置では、第１の実施形態における構成に加えて、ソルダーレジスト凹部６ｃの領域内に基材８が露出した第２の基材露出部８ｂが設けられている。即ち、ソルダーレジスト凹部６ｃに第２の基材露出部８ｂが取り囲まれた構成となっている。   In the semiconductor device of the second embodiment, in addition to the configuration in the first embodiment, a second base material exposed portion 8b in which the base material 8 is exposed is provided in the region of the solder resist recess 6c. That is, the second substrate exposed portion 8b is surrounded by the solder resist recess 6c.

上記のような構成とすることにより、もし半導体チップ９をプリント配線基板１へ接着する際に接着剤１１が接続用電極７へ向かって流出した場合であっても、接着剤１１は、導体プレーン２ａならびにソルダーレジスト６ｂからなる堰き止め部によってせき止められることによりソルダーレジスト凹部６ｃもしくは第２の基材露出部８ｂへ流入・滞留する。本実施形態では、前記ソルダーレジスト凹部６ｃの領域内に第２の基材露出部８ｂが設けられていることにより、堰き止め部によってせき止められた接着剤１１を第１の実施形態よりも大量に、前記ソルダーレジスト凹部６ｃ内に滞留させることができる。   With the above-described configuration, even when the adhesive 11 flows out toward the connection electrode 7 when the semiconductor chip 9 is bonded to the printed wiring board 1, the adhesive 11 is used as the conductor plane. By being dammed by the damming portion made of 2a and the solder resist 6b, it flows into and stays in the solder resist concave portion 6c or the second base material exposed portion 8b. In the present embodiment, since the second base material exposed portion 8b is provided in the area of the solder resist recess 6c, a larger amount of the adhesive 11 blocked by the damming portion than in the first embodiment. The solder resist recess 6c can be retained.

さらに、もし接着剤１１の流出量が多大のため、接着剤１１が堰き止め部を越えて接続用電極７へ向かって流れた場合でも、第１の基板露出部８ａに接着剤１１が滞留することで、接着剤１１による接続用電極７の上面部分の汚染を防止することができる。   Further, since the amount of the adhesive 11 flowing out is great, even if the adhesive 11 flows toward the connection electrode 7 beyond the damming portion, the adhesive 11 stays in the first substrate exposed portion 8a. Thus, contamination of the upper surface portion of the connection electrode 7 by the adhesive 11 can be prevented.

これにより、接着剤１１が接続用電極７上面に形成された金メッキ７ａ上に流入することで発生する汚染によって生ずるワイヤボンド不着を防止することができる。   Thereby, it is possible to prevent non-bonding of wire bonds caused by contamination that occurs when the adhesive 11 flows onto the gold plating 7 a formed on the upper surface of the connection electrode 7.

以上説明したように、本発明に係る半導体装置は、各種電子機器に搭載されている半導体装置、特にＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）形半導体装置に適用可能である。   As described above, the semiconductor device according to the present invention can be applied to a semiconductor device mounted on various electronic devices, particularly a BGA (Ball Grid Array) type semiconductor device.

１ プリント配線基板
２、２ａ、２ｂ、２ｃ 導体プレーン
３ａ，３ｂ 導体プレーン開口
４ ビアランド
５ ビアホール
６、６ｂ ソルダーレジスト
６ａ ソルダーレジスト開口
６ｃ ソルダーレジスト凹部
７ 接続用電極
７ａ 金メッキ
８ 基材
８ａ 第１の基材露出部
８ｂ 第２の基材露出部
９ 半導体チップ
１０ チップ電極
１１ 接着剤
１２ ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 Printed wiring board 2, 2a, 2b, 2c Conductor plane 3a, 3b Conductor plane opening 4 Via land 5 Via hole 6, 6b Solder resist 6a Solder resist opening 6c Solder resist recessed part 7 Connection electrode 7a Gold plating 8 Base material 8a 1st group Material exposed portion 8b Second substrate exposed portion 9 Semiconductor chip 10 Chip electrode 11 Adhesive 12 Bonding wire

Claims (2)

平板状の基材の一面の一部に導体が形成され、該導体の一部及び該基材の一面の一部上にソルダーレジストが設けられたプリント配線基板と、
前記プリント配線基板の主面に接着剤を介して搭載された半導体チップと、
前記半導体チップに形成されたチップ電極と前記プリント配線基板の主面に形成された接続用電極とを接続するボンディングワイヤと
を備えた半導体装置であって、
前記接続用電極と前記半導体チップとの間には、該接続用電極から近い順に、前記基材が露出した第１の基材露出部と、前記導体及び前記ソルダーレジストからなる堰き止め部と、前記基材上に直接前記ソルダーレジストが形成されているソルダーレジスト凹部とが設けられている、半導体装置。 A printed wiring board in which a conductor is formed on a part of one surface of a flat substrate, and a solder resist is provided on a part of the conductor and a part of one surface of the substrate;
A semiconductor chip mounted on the main surface of the printed wiring board via an adhesive;
A semiconductor device comprising: a chip electrode formed on the semiconductor chip; and a bonding wire that connects a connection electrode formed on a main surface of the printed wiring board,
Between the connection electrode and the semiconductor chip, in the order closer to the connection electrode, a first substrate exposed portion where the substrate is exposed, a damming portion made of the conductor and the solder resist, The semiconductor device provided with the soldering resist recessed part in which the said soldering resist is directly formed on the said base material. 前記ソルダーレジスト凹部に取り囲まれている、前記基材が露出した第２の基材露出部がさらに設けられていることを特徴とする、請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, further comprising a second base material exposed portion that is surrounded by the solder resist recess and exposes the base material.
JP2009267499A 2009-11-25 2009-11-25 Semiconductor device Pending JP2011114066A (en)

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