JP2011109694A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a high aperture ratio without increasing the number of masks and the number of steps by providing pixels having a new configuration. <P>SOLUTION: The semiconductor device eliminates the need of power supply lines. The higher aperture ratio compared with those of previous semiconductor devices can be achieved without increasing the number of masks and the number of steps required in manufacturing a panel. Furthermore, a high aperture ratio in each pixel improves utilization efficiency of light , and a power-saving and compact semiconductor device can be achieved. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device. More specifically, the present invention relates to an active matrix semiconductor device having a transistor manufactured over a semiconductor substrate or an insulating surface.

  A semiconductor device having an image sensor function is provided with a photoelectric conversion element and one or a plurality of transistors for controlling the photoelectric conversion element. As the photoelectric conversion element, a PN type photodiode is often used. In addition, there are a PIN type photodiode, an avalanche type diode, an npn buried type diode, a Schottky type diode, a phototransistor, and the like. In addition, there are an X-ray photoconductor and an infrared sensor, but any known element can be used for the semiconductor device of the present invention.

  Semiconductor devices having an image sensor function are roughly classified into a CCD type and a CMOS type. CMOS type semiconductor devices are classified as passive types without an amplification circuit and active types with an amplification circuit. The amplification circuit has a function of amplifying the image signal of the subject read by the photoelectric conversion element. As a result, active CMOS semiconductor devices that are not easily affected by noise or the like and on which an amplification circuit is mounted are widely used.

    Here, a semiconductor device in which a photoelectric conversion element and a plurality of transistors are provided in one pixel will be described with reference to FIGS.

    FIG. 5 shows an example of a schematic diagram of a semiconductor device of the present invention. The semiconductor device in FIG. 5 includes a pixel portion 103, a source signal line driver circuit 101 and a gate signal line driver circuit 102 which are arranged around the pixel portion 103. Note that the semiconductor device described in this embodiment includes one source signal line driver circuit 101 and one gate signal line driver circuit 102; however, the present invention is not limited to this. The number of source signal line driver circuits 101 and gate signal line driver circuits 102 can be arbitrarily determined.

    The pixel portion 103 includes a plurality of pixels 100 formed in a matrix on a semiconductor substrate or an insulating surface, a signal line connected to the source signal line driver circuit 101, and a signal connected to the gate signal line driver circuit 102. Has a line. Note that the number of signal lines connected to the source signal line driver circuit 101 and the gate signal line driver circuit 102 differs depending on the configuration of the pixel 100 described later. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output line drive circuit 101c, a final output amplification circuit 101d, and the like. These circuits are described in detail in the embodiment. explain.

    6 and 7 are circuit diagrams of the pixel 100 provided in the i-th row and the j-th column in the pixel portion 103 shown in FIG.

A pixel 100 illustrated in FIG. 6A includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and gate signal lines (G1 to Gy).
And any one of the reset signal lines (R1 to Ry). In addition, the pixel 100 includes a switching transistor 512, an amplification transistor 513, a reset transistor 514, and a photoelectric conversion element 511.

    The photoelectric conversion element 511 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 521, and the other is connected to the gate electrode of the amplifying transistor 513.

    The gate electrode of the switching transistor 512 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 512 is connected to the source region of the amplifying transistor 513, and the other is connected to the signal output line (Si). The switching transistor 512 is a transistor that functions as a switching element when a signal from the photoelectric conversion element 511 is output.

    The drain region of the amplifying transistor 513 is connected to the power supply line (VBi). The source region of the amplifying transistor 513 is connected to the source region or the drain region of the switching transistor 512. The amplifying transistor 513 forms a source follower circuit with a biasing transistor (not shown) provided below the pixel portion 103. For this reason, the polarity of the amplifying transistor 513 and the biasing transistor is preferably the same.

  The gate electrode of the reset transistor 514 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 514 is connected to the power supply line (VBi), and the other is connected to the photoelectric conversion element 511 and the gate electrode of the amplification transistor 513. The resetting transistor 514 is a transistor that functions as an element (switching element) for initializing (resetting) the photoelectric conversion element 511.

  A pixel 100 illustrated in FIG. 6B includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and one of gate signal lines (G1 to Gy). And any one of the reset signal lines (R1 to Ry). In addition, the pixel 100 includes a switching capacitor 712, an amplification transistor 713, a reset transistor 714, and a photoelectric conversion element 711.

The photoelectric conversion element 711 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal.
One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 721, and the other is connected to one terminal of the switching capacitor 712.

The other terminal of the switching capacitor 712 is a gate signal line (Gj)
It is connected to the. The switching capacitor 712 is a capacitor that functions as a switching element when the signal of the photoelectric conversion element 711 is output.

  The drain region of the amplifying transistor 713 is connected to the power supply line (VBi). The source region of the amplifying transistor 713 is connected to the signal output line (Si). The amplifying transistor 713 forms a source follower circuit with a biasing transistor (not shown) provided below the pixel portion 103. For this reason, the polarity of the amplifying transistor 713 and the biasing transistor is preferably the same.

  The gate electrode of the reset transistor 714 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 714 is connected to the power supply line (VBi), and the other is connected to the photoelectric conversion element 711 and the gate electrode of the amplification transistor 713. The resetting transistor 714 is a transistor that functions as an element (switching element) for initializing (resetting) the photoelectric conversion element 711.

    A pixel 100 illustrated in FIG. 6C illustrates an example in which the connection structure of the switching transistor and the amplifying transistor in the pixel 100 illustrated in FIG. 6A is different. The pixel 100 includes one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), one of gate signal lines (G1 to Gy), and a reset signal line (R1). To Ry). In addition, the pixel 100 includes a switching transistor 5120, an amplification transistor 5130, a reset transistor 5140, and a photoelectric conversion element 5110.

    The photoelectric conversion element 5110 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 5210, and the other is connected to the gate electrode of the amplifying transistor 5130.

The gate electrode of the switching transistor 5120 is a gate signal line (Gj)
It is connected to the. One of the source region and the drain region of the switching transistor 5120 is connected to the source region of the amplifying transistor 5130, and the other is connected to the power supply line (VBi). The switching transistor 5120 is a transistor that functions as a switching element when a signal from the photoelectric conversion element 5110 is output.

    The drain region of the amplifying transistor 5130 is connected to the signal output line (Si). The source region of the amplifying transistor 5130 is connected to one of the source region and the drain region of the switching transistor 512. The amplifying transistor 5130 forms a source follower circuit with a biasing transistor (not shown) provided below the pixel portion 103. Therefore, the polarity of the amplifying transistor 5130 and the biasing transistor is preferably the same.

  The gate electrode of the reset transistor 5140 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 5140 is connected to the power supply line (VBi), and the other is connected to the gate electrodes of the photoelectric conversion element 5110 and the amplification transistor 5130. The reset transistor 5140 is a transistor that functions as an element (switching element) for initializing (resetting) the photoelectric conversion element 511.

  Note that in the pixel 100 illustrated in FIG. 6C, one of a source region and a drain region of the switching transistor 5120 is connected to the power supply line (VBi). Although not shown, such a configuration is also applied to the pixel 100 shown in FIGS.

  A pixel 100 illustrated in FIG. 7A includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and one of gate signal lines (G1 to Gy). One of the reset signal lines (R1 to Ry), one of the transfer signal lines (T1 to Ty), and one of the photogate signal lines (F1 to Fy). In addition, the pixel 100 includes a switching transistor 612, an amplification transistor 613, a reset transistor 614, a transfer transistor 615, and a photogate 611.

  One terminal of the photogate 611 is connected to the photogate signal line (Fj), and the other terminal is connected to the transfer transistor 615.

  The gate electrode of the switching transistor 612 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 612 is connected to the signal output line (Si), and the other is connected to the source region of the amplifying transistor 613. The switching transistor 612 is a transistor that functions as a switching element when a signal is output to the photogate 611.

  The drain region of the amplifying transistor 613 is connected to the power supply line (VBi). The source region of the amplifying transistor 613 is connected to the terminal of the switching transistor 612. The amplifying transistor 613 forms a source follower circuit with a biasing transistor (not shown) provided below the pixel portion 103. Therefore, it is preferable that the polarity of the amplifying transistor 613 and the biasing transistor be the same.

    The gate electrode of the reset transistor 614 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 614 is connected to the power supply line (VBi), and the other is connected to the gate electrode of the amplification transistor 613. The reset transistor 614 is a transistor that functions as an element (switching element) for initializing (resetting) the photogate 611.

    The gate electrode of the transfer transistor 615 is connected to the transfer signal line (Tj). One of the source region and the drain region of the transfer transistor 615 is connected to the gate electrode of the amplification transistor 613 and the source region of the reset transistor 614, and the other is connected to the photogate 611.

A pixel 100 illustrated in FIG. 7B includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and gate signal lines (G1 to Gy).
, Any one of reset signal lines (R1 to Ry), and transfer signal lines (T1 to Tx). In addition, the pixel 100 includes a switching transistor 812, an amplification transistor 813, a reset transistor 814, a transfer transistor 815, and a photoelectric conversion element 811.

    The photoelectric conversion element 811 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 821, and the other is connected to the source region or the drain region of the transfer transistor 815.

    The gate electrode of the switching transistor 812 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 812 is connected to the source region of the amplifying transistor 813, and the other is connected to the signal output line (Si). The switching transistor 812 is a transistor that functions as a switching element when a signal from the photoelectric conversion element 811 is output.

    The drain region of the amplifying transistor 813 is connected to the power supply line (VBi). The source region of the amplifying transistor 813 is connected to the source region or the drain region of the switching transistor 812. The amplifying transistor 813 forms a source follower circuit with a biasing transistor (not shown) provided below the pixel portion 103. Therefore, the polarity of the amplifying transistor 813 and the biasing transistor should be the same.

  The gate electrode of the reset transistor 814 is connected to the reset signal line (Rj). One of a source region and a drain region of the reset transistor 814 is connected to a power supply line (VBi), and the other is connected to a gate electrode of the amplification transistor 813. The reset transistor 814 is a transistor that functions as an element (switching element) for initializing (resetting) the gate electrodes of the photoelectric conversion element 811 and the amplification transistor 813.

  The gate electrode of the transfer transistor 815 is connected to the transfer signal line (Tj). One of a source region and a drain region of the transfer transistor 815 is connected to the gate electrode of the amplification transistor 813, and the other is connected to the photoelectric conversion element 811.

    Regarding the above contents, JIEC seminar material: Japan Industrial Technology Center (February 20, 1998): CMOS sensor development prospects, ISSCC'99 An Integrated 800 * 600 CMOS Imaging System, ISSCC'97 A 1/4 Inch 330k Square Pixel Progressive Scan CMOS Active Pixel Image Sensor, ISSCC'95 A 256 * 256 CMOS Active Pixel Image Sensor with Motion Detection, IEDM'98 A snap-shot CMOS Active Pixel Imager for Low-Noise, High-Speed Imaging, IEDM ' 97 Reported in CMOS Image Sensor-Recent Advances and Device Scaling Considerations.

  A semiconductor device having an image sensor function is required to have a high aperture ratio in order to increase the photosensitivity in terms of performance. Since each pixel has a high aperture ratio, light use efficiency is improved, and power saving and miniaturization of the semiconductor device can be achieved.

  However, in recent years, the resolution has been increased and the pixel size has been reduced. When the pixel size is reduced, the formation area of transistors and wirings occupying one pixel relatively increases, and the aperture ratio of the pixel decreases.

  Therefore, in order to obtain a high aperture ratio of each pixel within a specified pixel size, it is indispensable to efficiently lay out circuit elements necessary for the circuit configuration of the pixel.

  The present invention meets such a demand, and it is an object of the present invention to provide a semiconductor device that realizes a high aperture ratio without increasing the number of masks and the number of steps by providing a pixel having a new structure. To do.

  In order to solve the above-described problems of the prior art, the following measures are taken in the present invention.

  The semiconductor device of the present invention focuses on the point that a certain gate signal line has a constant potential in a period other than the selection period in the structure of the pixel portion. The semiconductor device of the present invention is characterized in that when an i-th gate signal line is selected, a current supply line for supplying a current to a pixel in the i-th row is a gate signal line including the i-th gate signal line. By substituting any one of these, a current supply line occupying a certain proportion in the pixel portion can be omitted.

  The semiconductor device according to the present invention is characterized in that when an i-th reset signal line is selected, a current supply line for supplying a current to a pixel in the i-th row is used as a reset signal including the i-th reset signal line. By substituting any one of the lines, the current supply line occupying a certain proportion in the pixel portion can be omitted.

  By the above method, a high aperture ratio can be realized in the pixel portion without increasing the number of masks and the number of manufacturing steps. Further, if the aperture ratio is made equal to the conventional aperture ratio, the width of the signal line can be increased, which can contribute to the improvement of image quality such as resistance reduction and noise reduction.

  In addition to the gate signal line and the reset signal line, other signal lines such as a transfer signal line and a photogate signal line can be used as a substitute for the power supply line.

  By using the semiconductor device of the present invention, a power line is not necessary, so that a higher aperture ratio can be realized without increasing the number of masks and the number of steps in the panel manufacturing process compared to conventional semiconductor devices. I can do it. Alternatively, if the aperture ratio is the same as the conventional one, the signal line can be made thicker accordingly, so that the resistivity can be reduced, crosstalk and the like can be reduced, and an improvement in image quality can be realized.

FIG. 10 is a diagram illustrating a circuit diagram of a pixel of a semiconductor device of the invention. FIG. 10 is a diagram illustrating a circuit diagram of a pixel of a semiconductor device of the invention. FIG. 10 is a diagram illustrating a circuit diagram of a pixel of a semiconductor device of the invention. FIG. 10 is a diagram illustrating a circuit diagram of a pixel of a semiconductor device of the invention. 1 is a diagram showing a schematic view of a semiconductor device of the present invention. FIG. 9 is a diagram illustrating a circuit diagram of a pixel of a conventional semiconductor device. FIG. 9 is a diagram illustrating a circuit diagram of a pixel of a conventional semiconductor device. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device. FIG. 5 is a diagram illustrating a timing chart of signals output to pixels. FIG. 9 is a diagram showing a cross-sectional structure of a semiconductor device of the invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device of the present invention. FIG. 11 illustrates an example of an electronic device to which the semiconductor device of the invention can be applied.

(Embodiment 1)
FIG. 5 shows an example of a schematic diagram of a semiconductor device of the present invention. The semiconductor device in FIG. 5 includes a pixel portion 103, a source signal line driver circuit 101 and a gate signal line driver circuit 102 which are arranged around the pixel portion 103. Note that the semiconductor device described in this embodiment includes one source signal line driver circuit 101 and one gate signal line driver circuit 102; however, the present invention is not limited to this. The number of source signal line driver circuits 101 and gate signal line driver circuits 102 can be arbitrarily determined.

    The pixel portion 103 includes a plurality of pixels 100 formed in a matrix on a semiconductor substrate or an insulating surface, a signal line connected to the source signal line driver circuit 101, and a signal connected to the gate signal line driver circuit 102. Has a line. Note that the number of signal lines connected to the source signal line driver circuit 101 and the gate signal line driver circuit 102 differs depending on the configuration of the pixel 100 described later. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output line drive circuit 101c, a final output amplification circuit 101d, and the like. These circuits are described in detail in the embodiment. explain.

    1 to 4 are circuit diagrams of the pixel 100 provided in the i-th row and the j-th column in the pixel portion shown in FIG.

    A pixel 100 shown in FIGS. 1A and 1B includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and gate signal lines (G1 to Gy). And any one of the reset signal lines (R1 to Ry). In addition, the pixel 100 includes a switching transistor 112, an amplification transistor 113, a reset transistor 114, and a photoelectric conversion element 111.

    The photoelectric conversion element 111 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 121, and the other is connected to the gate electrode of the amplifying transistor 113.

    The gate electrode of the switching transistor 112 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 112 is connected to the source region of the amplifying transistor 113, and the other is connected to the signal output line (Si). The switching transistor 112 is a transistor that functions as a switching element when a signal from the photoelectric conversion element 111 is output.

    The drain region of the amplifying transistor 113 of the pixel 100 shown in FIG. 1A is connected to the reset signal line (Rj-1) of the pixel (i, j-1) located above the pixel (i, j). , Scanning is performed before the pixel (i, j).

  The gate electrode of the reset transistor 114 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 514 is connected to the reset signal line (Rj-1), and the other is connected to the gate electrodes of the photoelectric conversion element 111 and the amplification transistor 113.

    On the other hand, the drain region of the amplifying transistor 113 of the pixel 100 shown in FIG. 1B is connected to the gate signal line (Gj + 1) of the pixel (i, j + 1) located below the pixel (i, j). Connected and scanned after pixel (i, j).

  The gate electrode of the reset transistor 114 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 114 is connected to the gate signal line (Gj + 1), and the other is connected to the gate electrodes of the photoelectric conversion element 111 and the amplification transistor 113.

    In addition, the drain region of the amplifying transistor 113 of the pixel 100 illustrated in FIG. 1C is connected to the reset signal line (Rj-1) of the pixel (i, j-1) located above the pixel (i, j). Connected and scanned after pixel (i, j).

  The gate electrode of the reset transistor 114 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 114 is connected to the gate signal line (Gj + 1) of the pixel (i, j + 1) located below the pixel (i, j), and the pixel (i, Scanned after j). The other of the source region and the drain region of the reset transistor 114 is connected to the gate electrodes of the photoelectric conversion element 111 and the amplification transistor 113.

  Next, a structure of the pixel 100 provided with a capacitor serving as a switching element will be described with reference to FIG.

  A pixel 100 shown in FIGS. 2A and 2B includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and gate signal lines (G1 to Gy). And any one of the reset signal lines (R1 to Ry). The pixel 100 includes a switching capacitor 312, an amplifying transistor 313, a resetting transistor 314, and a photoelectric conversion element 311.

The photoelectric conversion element 311 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal.
One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 321, and the other is connected to one terminal of the switching capacitor 312.

The other terminal of the switching capacitor 312 is a gate signal line (Gj).
It is connected to the. The switching capacitor 312 is a capacitor that functions as a switching element when the signal of the photoelectric conversion element 311 is output.

    The drain region of the amplifying transistor 313 of the pixel 100 shown in FIG. 2A is connected to the reset signal line (Rj-1) of the pixel (i, j-1) located above the pixel (i, j). , Scanning is performed before the pixel (i, j).

  The gate electrode of the reset transistor 314 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 514 is connected to the reset signal line (Rj-1), and the other is connected to the gate electrodes of the photoelectric conversion element 111 and the amplification transistor 113.

    On the other hand, the drain region of the amplifying transistor 313 of the pixel 100 illustrated in FIG. 2B is connected to the gate signal line (Gj + 1) of the pixel (i, j + 1) located below the pixel (i, j). Connected and scanned after pixel (i, j).

  The gate electrode of the reset transistor 314 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 314 is connected to the gate signal line (Gj + 1), and the other is connected to the gate electrodes of the photoelectric conversion element 111 and the amplification transistor 313.

  The point of the present invention is that when a signal is output from the currently selected row or when the photoelectric conversion element is reset, another row has already returned to the non-selected state. The potential is kept constant (non-selected state) until it is selected again. Therefore, the reset signal line (Rj-1) before one row and the gate signal line (Gj + 1) after one row are treated as constant potential lines, that is, current supply lines. That is, either the reset signal line or the gate signal line and the current supply line are shared. As a result, the number of wirings can be reduced and the aperture ratio can be improved.

  In the present embodiment, an example is shown in which the reset signal line (Rj-1) in the previous row and the gate signal line (Gj + 1) in the next row are used in place of the power supply line. It is not limited to. It is possible to substitute a reset signal line and a gate signal line before how many rows, or substitute a reset signal line and a gate signal line after how many rows. Alternatively, a reset signal line and a gate signal line included in the own pixel can be used instead. That is, it is only necessary to be connected to any one of the reset signal line and the gate signal line included in the pixel portion.

  In this embodiment mode, one of the source region and the drain region of the amplification transistor and one of the source region and the drain region of the reset transistor are connected to the same wiring. However, the present invention is not limited to this. For example, the terminal of the amplifying transistor is connected to the reset signal line (Rj) of its own pixel (i, j), and the terminal of the resetting transistor is connected to the gate signal line (Gj) of its own pixel (i, j). May be. With such a configuration, the power supply line can be substituted by using the reset signal line (Rj) and the gate signal line (Gj).

  Further, when applying the present invention, depending on the wiring used as a substitute for the power supply line, the polarity of each of the switching transistor 112, the amplifying transistor 113, and the resetting transistor 114 shown in FIG. 1, and the amplification shown in FIG. It is necessary to pay attention to the polarities of the transistors 313 and 314 for resetting.

  Here, FIG. 1A will be described as an example. In the pixel 100 illustrated in FIG. 1A, the reset signal line (Rj-1) is used as a power supply line. The reset signal line (Rj-1) in the previous row needs to be at a constant potential for most of the period, and the potential of the reset signal line (Rj-1) at that time has in the pixel when not deleted. Must be the same potential as the power line. Therefore, it is necessary to pay attention to the polarity of the reset transistor 114 connected to the reset signal line (Rj-1).

  If the reset signal line (Rj-1) is at a high potential in most periods, the reset transistor 114 connected to the reset signal line (Rj-1) needs to be a p-channel transistor. . This is because if an n-channel transistor is used as the reset transistor 114, the transistor is almost in a conductive state. Since the drain region of the amplifying transistor 113 is connected to the reset signal line (Rj-1), it is necessary to use an n-channel transistor. In this case, if the amplifying transistor 113 and the biasing transistor (not shown) form a source follower circuit, the biasing transistor must also be an n-channel transistor. However, if the source follower circuit is not formed, it is not necessary to use an n-channel transistor as the biasing transistor.

  In the case where the reset signal line (Rj-1) is at a low potential in almost all periods, the reset transistor 114 connected to the reset signal line (Rj-1) needs to be an n-channel transistor. . That is, it is necessary to pay attention to the potentials of the reset signal line and the gate signal line used as a substitute for the power supply line, and to use transistors with appropriate polarities.

  Furthermore, when a diode is used as the photoelectric conversion element (the photoelectric conversion element 111 shown in FIG. 1 and the photoelectric conversion element 311 shown in FIG. 2), it is necessary to pay attention to its direction.

  Here, FIG. 1A will be described as an example. When the photoelectric conversion element 111 is reset, it needs to be in a reverse bias state. Therefore, when the direction of the photoelectric conversion element 111 is reversed, it is necessary to exchange the potential of the reset signal line (Rj-1) used as the power supply line and the power supply reference line 121. When the potential is actually changed, it is necessary to pay attention to the polarity of the reset transistor 114 connected to the reset signal line (Rj-1). That is, when the reset signal line (Rj-1) is at a high potential in most periods, a p-channel transistor needs to be used as the reset transistor 114, and when it is at a low potential in most periods. The reset transistor 114 needs to be an n-channel transistor. In this case, when the reset signal lines (R1 to Ry) are used as substitutes for the power supply lines, the polarity of the switching transistor 112 is not particularly limited.

  Further, as shown in FIG. 1B, when the gate signal lines (G1 to Gy) are used as substitutes for the power supply lines, it is necessary to pay attention to the polarities of the amplifying transistor 113 and the resetting transistor 114. is there. That is, when the present invention is applied, the potential of the reset signal line and the gate signal line used as a substitute for the power supply line, and the potential of the power supply reference line (the power supply reference line 121 shown in FIG. 1 and the power supply reference line 321 shown in FIG. 2). Therefore, it is necessary to use a transistor having an appropriate polarity.

(Embodiment 2)
In this embodiment mode, a case where a transfer signal line and a photogate line are used instead of the power supply line, unlike in Embodiment Mode 1, will be described.

A pixel 100 shown in FIGS. 3A and 3B includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and gate signal lines (G1 to Gy). , Any one of the reset signal lines (R1 to Ry), any one of the transfer signal lines (T1 to Ty), and the photogate signal lines (F1 to Fy)
One of these. The pixel 100 also includes a switching transistor 212, an amplification transistor 213, a reset transistor 214, a transfer transistor 215, and a photogate 211.

  The terminal of the photogate 211 is connected to the photogate signal line (Fj), and the other terminal is connected to either the source region or the drain region of the transfer transistor 215.

  The gate electrode of the switching transistor 212 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 212 is connected to the signal output line (Si), and the other is connected to either the source region or the drain region of the amplifying transistor 213.

    The gate electrode of the transfer transistor 215 is connected to the transfer signal line (Tj). One of the source region and the drain region of the transfer transistor 215 is connected to the gate electrode of the amplification transistor 213 and the source region of the reset transistor 214, and the other is connected to the photogate 211.

  Then, either the source region or the drain region of the amplifying transistor 213 of the pixel 100 shown in FIG. 3A is a transfer signal of the pixel (i, j−1) located above the pixel (i, j). It is connected to the line (Tj-1) and scanned before the pixel (i, j).

  The gate electrode of the reset transistor 214 is connected to the reset signal line (Rj). One of the source region and the drain region of the resetting transistor 214 is connected to the transfer signal line (Tj-1), and the other is connected to the gate electrode of the amplifying transistor 213.

  In addition, either the source region or the drain region of the amplifying transistor 213 of the pixel 100 illustrated in FIG. 3B is a photogate of the pixel (i, j−1) located above the pixel (i, j). It is connected to the signal line (Tj-1) and scanned before the pixel (i, j).

  The gate electrode of the reset transistor 214 is connected to the photogate signal line (Tj-1). One of the source region and the drain region of the resetting transistor 214 is connected to the transfer signal line (Tj-1), and the other is connected to the gate electrode of the amplifying transistor 213.

  Note that in this embodiment mode, an example in which the transfer signal line (Tj-1) in the previous row and the photogate signal line (Tj-1) in the previous row are used instead of the power supply lines has been described. Is not limited to this. It is possible to substitute the transfer signal line before and how many photogate signal lines before, and substitute the transfer signal line after and how many photogate signal lines after. Further, a transfer signal line (Ti) and a photogate signal line (Fi) included in the own pixel can be used instead. That is, it is only necessary to be connected to any one of the transfer signal lines (T1 to Ty) and the photogate signal lines (F1 to Fy) included in the pixel portion.

  In this embodiment mode, one of the source region and the drain region of the amplifying transistor 213 and one of the source region and the drain region of the reset transistor 214 are connected to the same wiring; however, the present invention is not limited to this. For example, the terminal 213 of the amplifying transistor is connected to the transfer signal line (Tj) of its own pixel (i, j), and the terminal of the resetting transistor 214 is connected to the photogate signal line (Fj of its own pixel (i, j). ) May be connected. With such a configuration, a power supply line can be substituted by using a transfer signal line and a photogate signal line.

  Further, when applying the present invention, attention should be paid to the polarities of the switching transistor 212, the amplifying transistor 213, the resetting transistor 214, and the transfer transistor 215 shown in FIG. 3 depending on the wiring used as a substitute for the power supply line. There is a need.

  Here, FIG. 3A will be described as an example. In the pixel 100 illustrated in FIG. 3A, the transfer signal line (Tj-1) is used as a power supply line. The transfer signal line (Tj-1) in the previous row needs to be at a constant potential for most of the period, and the potential of the transfer signal line (Tj-1) at that time has in the pixel when not deleted. It is necessary to have the same potential as the power supply line. Therefore, it is necessary to pay attention to the polarity of the transfer transistor 215 connected to the transfer signal line (Tj-1).

  If the transfer signal line (Tj-1) is at a high potential for most of the period, it is necessary to use a p-channel transistor as the transfer transistor 215 connected to the transfer signal line (Tj-1). . This is because if an n-channel transistor is used as the transfer transistor 215, the transistor becomes almost conductive.

  In the case where the transfer signal line (Tj-1) is at a low potential in most periods, the transfer transistor 215 connected to the transfer signal line (Tj-1) needs to be an n-channel transistor. . That is, it is necessary to use a transistor having an appropriate polarity while paying attention to the potentials of the transfer signal line and the photogate signal line used as a substitute for the power supply line.

  Note that although an example using transfer signal lines and photogate signal lines is described in this embodiment mode, the present invention is not limited thereto, and other wirings such as a gate signal line and a reset signal line may be used. .

(Embodiment 3)
In this embodiment, a semiconductor device having a structure in which a transfer signal line and a gate signal line are used instead of a power supply line will be described as an example different from Embodiments 1 and 2.

    A pixel 100 shown in FIGS. 4A and 4B includes any one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), and gate signal lines (G1 to Gy). , Any one of reset signal lines (R1 to Ry), and transfer signal lines (T1 to Ty). In addition, the pixel 100 includes a switching transistor 412, an amplification transistor 413, a reset transistor 414, a transfer transistor 415, and a photoelectric conversion element 411.

    The photoelectric conversion element 411 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 421, and the other is connected to the source region or the drain region of the transfer transistor 415.

    The gate electrode of the switching transistor 412 is connected to the gate signal line (Gj). One of the source region and the drain region of the switching transistor 412 is connected to the source region of the amplifying transistor 413, and the other is connected to the signal output line (Si).

The drain region of the amplifying transistor 413 of the pixel 100 shown in FIG. 4A is the transfer signal line (Tj-1) of the pixel (i, j-1) located above the pixel (i, j).
And is scanned before the pixel (i, j).

  The gate electrode of the reset transistor 414 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 414 is connected to the transfer signal line (Tj-1), and the other is connected to the photoelectric conversion element 411 and the gate electrode of the amplification transistor 113.

    On the other hand, the drain region of the amplifying transistor 413 of the pixel 100 illustrated in FIG. 1B is connected to the gate signal line (Gj + 1) of the pixel (i, j + 1) located below the pixel (i, j). Connected and scanned after pixel (i, j).

  The gate electrode of the reset transistor 414 is connected to the reset signal line (Rj). One of the source region and the drain region of the reset transistor 414 is connected to the gate signal line (Gj + 1), and the other is connected to the gate electrodes of the photoelectric conversion element 411 and the amplification transistor 413.

  The gate electrode of the transfer transistor 415 is connected to the transfer signal line (Tj). One of the source region and the drain region of the transfer transistor 415 is connected to the gate electrode of the amplification transistor 413, and the other is connected to the photoelectric conversion element 411.

  In the present embodiment, an example in which the transfer signal line (Tj-1) in the previous row and the gate signal line (Gj + 1) in the next row are used in place of the power supply line is shown. It is not limited to this. The transfer signal line and the gate signal line before and how many rows can be substituted, and the transfer signal line and the gate signal line after how many rows can be substituted. Further, a transfer signal line and a gate signal line included in the own pixel can be used instead. That is, it is only necessary to be connected to one of the transfer signal line and the gate signal line included in the pixel portion.

  Further, although an example using the transfer signal line and the gate signal line has been described in this embodiment mode, the present invention is not limited thereto, and a reset signal line may be used.

  In this embodiment mode, one of the source region and the drain region of the amplification transistor 413 and one of the source region and the drain region of the reset transistor 414 are connected to the same wiring; however, the present invention is not limited to this. For example, the terminal of the amplifying transistor 413 is connected to the transfer signal line (Tj) of its own pixel (i, j), and the terminal of the resetting transistor 414 is connected to the gate signal line (Gj) of its own pixel (i, j). You may connect to. With such a configuration, the power supply line can be substituted by using the transfer signal line (Tj) and the gate signal line (Gj).

  Furthermore, when applying the present invention, depending on the wiring used as a substitute for the power supply line, attention should be paid to the polarities of the switching transistor 412, the amplifying transistor 413, the resetting transistor 414, and the transferring transistor 415 shown in FIG. There is a need to.

  Here, FIG. 4A will be described as an example. In the pixel 100 illustrated in FIG. 4A, the transfer signal line (Tj-1) is used as a power supply line. The transfer signal line (Tj-1) in the previous row needs to be at a constant potential for most of the period, and the potential of the transfer signal line (Tj-1) at that time has in the pixel when not deleted. Must be the same potential as the power line. Therefore, it is necessary to pay attention to the polarity of the transfer transistor 415 connected to the transfer signal line (Tj-1).

  If the transfer signal line (Tj-1) is at a high potential in most periods, the transfer transistor 415 connected to the transfer signal line (Tj-1) needs to use a p-channel transistor. . This is because if an n-channel transistor is used as the transfer transistor 415, the transistor becomes almost conductive. In the case where the transfer signal line (Tj-1) is at a low potential in most periods, the transfer transistor 415 connected to the transfer signal line (Tj-1) needs to be an n-channel transistor. . That is, it is necessary to use a transistor having an appropriate polarity while paying attention to the potentials of the transfer signal line, the gate signal line, and the reset signal line used as a substitute for the power supply line. Note that if the amplifying transistor 113 and the biasing transistor (not shown) form a source follower circuit, the amplifying transistor 113 and the biasing transistor must be transistors having the same polarity. However, this does not apply as long as the source follower circuit is not formed.

  Furthermore, it is necessary to pay attention to the direction of the photoelectric conversion element when a diode is used as the photoelectric conversion element (photoelectric conversion element 411 shown in FIG. 4).

  Here, FIG. 4A will be described as an example. When the photoelectric conversion element 111 is reset, it needs to be in a reverse bias state. Therefore, when the direction of the photoelectric conversion element 411 of the photoelectric conversion element 411 is reversed, the potential of the transfer signal line (Tj-1) used as the power supply line and the power supply reference line 421 need to be switched. When the potential is actually changed, it is necessary to pay attention to the polarity of the transfer transistor 415 connected to the transfer signal line (Tj-1). That is, when the transfer signal line (Tj-1) is at a high potential in most periods, a p-channel transistor needs to be used as the transfer transistor 415. When the transfer signal line (Tj-1) is at a low potential in most periods. The transfer transistor 415 needs to be an n-channel transistor. Note that the polarity of the switching transistor 412 is not particularly limited when the transfer signal lines (T1 to Ty) are used instead of the power supply lines as in this case.

That is, when the present invention is applied, transfer signal lines (T1 to Ty), gate signal lines (G1 to Gy), and reset signal lines (R1 to Ry) used as substitutes for power supply lines.
Therefore, it is necessary to use a transistor having an appropriate polarity while paying attention to the potential of the power supply reference line and the potential of the power supply reference line (power supply reference line 421 shown in FIG. 4).

  FIG. 5 shows an example of a schematic diagram of the semiconductor device of the present invention. In this embodiment, the source signal line driver circuit 101 shown in FIG. 5 will be described in detail. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output drive circuit 101c, and a final output amplification circuit 101d.

  Note that the present invention is not limited to this, and the source signal line driver circuit 101 may be provided with an analog / digital signal conversion circuit, a noise reduction circuit, a signal processing circuit, or the like.

  The bias circuit 101a is paired with the amplifying transistor of each pixel to form a source follower circuit. The sample hold circuit 101b has a circuit for temporarily storing a signal, performing analog-digital conversion, and reducing noise. In addition, the signal output drive circuit 101c includes a circuit that outputs a signal for sequentially outputting the temporarily stored signals. The final output amplification circuit 101d has a circuit that amplifies the signal output by the sample hold circuit 101b and the signal output drive circuit 101c. The final output amplifying circuit 101d may not be provided when it is not necessary to amplify the signal.

  Next, FIG. 8 shows a circuit diagram of the i-th row peripheral portion 101e of the bias circuit 101a, the sample hold circuit 101b, and the signal output line driving circuit 101c. In this embodiment, all transistors are n-channel transistors.

The bias circuit 101a includes a bias transistor 5510a. The bias transistor 5510a has the same polarity as the amplification transistor of each pixel, and forms a source follower circuit. A gate electrode of the bias transistor 5510 a is connected to the bias signal line 511. One of the source region and the drain region of the bias transistor 5510a is a signal output line (Si).
The other is connected to the power supply reference line 5510b. Note that although the case where an n-channel transistor is used as the biasing transistor 5510a is described in this embodiment, the present invention is not limited to this. For example, a p-channel transistor can be used as the biasing transistor 5510a. In that case, the biasing transistor 5510a is connected to the power supply line instead of the power supply reference line.

  A gate electrode of the transfer transistor 5512 is connected to the transfer signal line 5513. One of a source region and a drain region of the transfer transistor 5512 is connected to a signal output line (Si), and the other is connected to a capacitor 5514b. The transfer transistor 5512 has a function of transferring the potential of the signal output line (Si) to the capacitor 5514b. Note that in this embodiment, the case where an n-channel transistor is used as the transfer transistor 512 is described, but the present invention is not limited to this. For example, a p-channel transistor and an n-channel transistor may be connected in parallel, and these transistors may be used as transfer transistors.

  The capacitor 5514b is connected to the transfer transistor 5512 and the power supply reference line 5514c. The capacitor 5514b temporarily accumulates the signal output from the signal output line (Si).

  The gate electrode of the discharge transistor 5514a is connected to the pre-discharge signal line 5515. One of the source region and the drain region of the discharging transistor 5514a is connected to the capacitor 5514b, and the other is connected to the power supply reference line 5514c. The discharging transistor 5514a has a function of discharging the electric charge of the capacitor 514b before inputting the potential of the signal output line (Si) to the capacitor 5514b.

  A final selection transistor 5516 is connected between the capacitor 5514 b and the final output line 5518. One of the source region and the drain region of the final selection transistor 5516 is connected to the capacitor 514 b and the other is connected to the final output line 518. The gate electrode of the final selection transistor 5516 is connected to the i-th row final selection line 519.

  The final selection lines are provided in a matrix in the pixel portion, and are scanned in order from the first column to the yth column. If the i-th row final selection line 5519 is selected and the final selection transistor 5516 is turned on as shown in FIG. 8, the potential of the capacitor 5514b and the potential of the i-th row final selection line 5519 become equal. Then, the signal accumulated in capacitor 5514b can be output to final output line 5518.

  Note that charges may be accumulated in the final output line 5518 before a signal is output to the final output line 5518. Then, the potential when a signal is output to the final output line 5518 is affected by the charge. Therefore, before outputting a signal to the final output line 5518, it is necessary to initialize the potential of the final output line 5518 to a certain potential value.

  In FIG. 8, a final reset transistor 5517a is provided between the final output line 5518 and the power supply reference line 5517b. The gate electrode of the final reset transistor 5517a is connected to the i-th final reset line 5520. One of the source region and the drain region of the final reset transistor 5517a is connected to the final output line 5518, and the other is connected to the power supply reference line 5517b.

  Then, before selecting the i-th row final selection line 5519, the i-th row final reset line 5520 is selected, and the potential of the final output line 5518 is initialized to the potential of the power supply reference line 5517b. Thereafter, the i-th row final selection line 5519 is selected, and the signal accumulated in the capacitor 5514b is output to the final output line 5518.

  Note that the signal output to the final output line 5518 may be extracted to the outside as it is. However, if the output signal is weak, it is preferable to amplify it before taking it out. As a circuit for amplifying a signal, a circuit of a final output amplification circuit 101d is shown in FIGS. In this embodiment, a source follower circuit is shown as the simplest signal amplifier circuit, but the present invention is not limited to this. For example, a known amplifier circuit such as an operational amplifier may be used.

  FIG. 9A illustrates a final amplifier circuit 101d having an n-channel source follower circuit. A signal is input to the final output amplification circuit 101d through a final output line 5518. The final output line 5518 is provided in a matrix in the pixel portion, and signals are sequentially output from the first column to the y-th column.

  The signal output from the final output line 5518 is amplified by the final output amplification circuit 101d and output to the outside. The final output line 5518 is connected to the gate electrode of the amplifying transistor 5521. The drain region of the amplifying transistor 5521 is connected to the power supply line 520, and the source region is an output terminal.

  On the other hand, the gate electrode of the bias transistor 5522 is connected to the final output amplification bias signal line 5523. One of a source region and a drain region of the bias transistor 5522 is connected to the power supply reference line 524, and the other is connected to a source region of the amplification transistor 5521.

  Next, FIG. 9B illustrates a final amplifier circuit 101d having a p-channel source follower circuit. The final output line 5518 is connected to the gate electrode of the amplifying transistor 5521. The drain region of the amplifying transistor 5521 is connected to the power supply reference line 5520, and the source region serves as an output terminal.

  On the other hand, the gate electrode of the bias transistor 5522 is connected to the final output amplification bias signal line 5523. One of a source region and a drain region of the bias transistor 5522 is connected to the power supply line 520, and the other is connected to a source region of the amplification transistor 521. Note that the potential of the final output amplification bias signal line 5523 shown in FIG. 9B having a p-channel source follower circuit is the final output amplification shown in FIG. 9A having an n-channel source follower circuit. This is different from the potential of the bias signal line 523 for use.

  Next, FIG. 10 shows a timing chart of the j-th column peripheral circuit shown in FIG. In this embodiment, as an example, a timing chart when the i-th gate signal line (Gi) is selected is shown.

  First, the i-th gate signal line (Gi) is selected, and then the pre-discharge signal line 5515 is selected. Then, the discharge transistor 5514a is turned on. When the transfer signal line 5513 is selected, the signal of each pixel is output to the capacitor 5514b in each column.

  Then, the signals accumulated in the capacitors 5514b in each column are sequentially output to the final output line 5518. Next, the final reset line in the first row is selected, the final reset transistor 5517a is turned on, and the final output line 5518 is initialized to the potential of the power supply reference line 5517b. Thereafter, the final selection line in the first column is selected, the final selection transistor 5516 is turned on, and the signal of the capacitor 5514 b in the first column is output to the final output line 5518.

  Next, the final reset line in the second column is selected, the final reset transistor 5517a is turned on, and the final output line 5518 is initialized to the potential of the power supply reference line 5517b. Thereafter, the final selection line in the second column is selected, the final selection transistor 5516 is turned on, and the signal of the capacitor 5514b in the second column is output to the final output line 5518. In this way, the same operation is repeated.

  Next, the case of the i-th row will be described. First, the i-th row final reset line 5520 is selected, the final reset transistor 5157a is turned on, and the final output line 5518 is initialized to the potential of the power supply reference line 5517b. Thereafter, the i-th row final selection line 5519 is selected, the final selection transistor 5516 is turned on, and the signal of the i-th row capacitor 5514b is output to the final output line 5518.

  Next, the final reset line 5520 in the (i + 1) th column is selected, the final reset transistor 5517a is turned on, and the final output line 5518 is initialized to the potential of the power supply reference line 5517b. After that, the (i + 1) th column final selection line 5519 is selected, the final selection transistor 5516 is turned on, and the signal of the capacitor 5514b in the (i + 1) th column is output to the final output line 5518.

  In this way, the same operation is repeated, and the signals of all the columns are output to the final output line 5518. Then, the signal output to the final output line 5518 is amplified by the final output amplification circuit 101d and output to the outside. Note that the potential of the bias signal line 5511 is kept constant during a period in which a signal is output to the final output line 5518.

  In this embodiment, the case where a PN photodiode is used has been described, but the present invention is not limited to this. As the photoelectric conversion element, a PIN diode, an avalanche diode, an NPN buried diode, a Schottky diode, an X-ray photoconductor, an infrared sensor, or the like may be used. Moreover, after converting X-rays into light by a fluorescent material or a scintillator, the light may be read.

  As described above, the photoelectric conversion element is often connected to the input terminal of the source follower circuit. However, the present invention is not limited to this, and a switch may be sandwiched between them as in a photogate type, or a signal after processing to have a logarithmic value of light intensity as in a logarithmic conversion type is input to an input terminal. You may enter.

  In addition, this embodiment can be freely combined with Embodiment Modes 1 to 3.

  In this embodiment, timing of signals output to transistors provided in the pixel 100 will be described with reference to FIG. Note that in this embodiment, the timing of a signal output to a transistor provided in the pixel 100 of the semiconductor device illustrated in FIG. 1A is described as an example.

  First, the reset signal lines (R1 to Ry) are controlled, and the reset transistor 114 is turned on.

  Next, the potential of the n-channel terminal of the photoelectric conversion element 111 is charged to the power supply potential Vdd. In the semiconductor device of the present invention, since the reset signal lines (R1 to Ry) substitute for the power supply lines, the reset signal lines (R1 to Ry) must be set to the same potential as the power supply potential Vdd. . That is, the pixel 100 is reset. Then, the reset signal lines (R1 to Ry) are controlled, and the reset transistor 114 is turned off.

  Thereafter, when the photoelectric conversion element 111 is irradiated with light, a charge corresponding to the light intensity is generated in the photoelectric conversion element 111. Then, the charge charged by the reset is gradually discharged, and the potential of the n-channel terminal of the photoelectric conversion element 111 becomes low.

  As shown in FIG. 11, when the photoelectric conversion element 111 is irradiated with bright light, the amount of discharge is large, so that the potential of the n-channel terminal of the photoelectric conversion element 111 is low. When the photoelectric conversion element 111 is irradiated with dark light, the amount of discharge is small, and the potential of the n-channel terminal of the photoelectric conversion element 111 is not much lower than that when the photoelectric conversion element 111 is irradiated with bright light. .

  At a certain point in time, the switching transistor 112 is turned on, and the potential of the n-channel terminal of the photoelectric conversion element 111 is read as a signal. This signal is proportional to the intensity of light applied to the photoelectric conversion element 111. Then, the reset transistor 114 is turned on again to reset the photoelectric conversion element 111, and the above-described operation is repeated.

  However, when very bright light is irradiated, since the amount of electric charge discharged from the photoelectric conversion element 111 is very large, the potential of the n-channel terminal of the photoelectric conversion element 111 is extremely lowered. However, the potential of the n-channel terminal of the photoelectric conversion element 111 does not become lower than the potential of the p-channel terminal of the photoelectric conversion element 111, that is, the power supply reference line 121.

  In addition, when very bright light is irradiated, the potential of the n-channel terminal of the photoelectric conversion element 111 is lowered. However, when the potential is lowered to the potential of the power supply reference line 121, the potential does not change. Such a situation is called saturation. When saturated, the potential of the n-channel terminal of the photoelectric conversion element 111 does not change, so that a signal corresponding to the correct light intensity cannot be output. Therefore, in order to operate normally, it is necessary to operate the photoelectric conversion element 111 so as not to be saturated.

  A period from when the pixel 100 is reset to when a signal is output is referred to as an accumulation time. The accumulation time is a time during which light is irradiated to the light receiving portion of the photoelectric conversion element and signals are accumulated, and is also referred to as an exposure time. In the accumulation time, the photoelectric conversion element 111 accumulates charges generated by the light irradiated on the photoelectric conversion element 111.

  Therefore, if the accumulation time is different, even if the light intensity is the same, the total amount of charge generated by the light is different, and the signal value is also different. For example, when intense light is irradiated to the photoelectric conversion element 111, it is saturated in a short accumulation time. Further, even when weak light is irradiated onto the photoelectric conversion element 111, when the accumulation time is long, it eventually reaches a saturated state. That is, the signal is determined by the product of the intensity of light applied to the photoelectric conversion element 111 and the accumulation time.

  In addition, this embodiment can be freely combined with Embodiment Modes 1 to 3 and Embodiment 1.

  In this embodiment, a cross-sectional structure of a semiconductor device in which the photoelectric conversion element and the plurality of transistors described in FIG. 1 are provided in one pixel will be described with reference to FIGS.

  In FIG. 12, 6000 is a substrate having an insulating surface, and 6001 is a base film. On the base film 6001, a photoelectric conversion element 111, an amplification transistor 113, a switching transistor 112, and a reset transistor 114 are formed. In addition, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined is illustrated as a driver circuit. Each transistor may have any known structure.

  A structure of each transistor formed over the substrate 6000 having an insulating surface is described. In the amplifying transistor 113, reference numeral 6023 denotes a gate electrode, 6008 denotes a gate insulating film, 6037 denotes a source region and a drain region made of a p-type impurity region, 6042 denotes a source wiring, and 6043 denotes a drain wiring.

  In the switching transistor 112, reference numeral 6024 denotes a gate electrode, 6008 denotes a gate insulating film, 6038 denotes a source region and a drain region made of a p-type impurity region, 6044 denotes a source wiring, and 6045 denotes a drain wiring.

  In the reset transistor 114, reference numeral 6025 denotes a gate electrode, 6008 denotes a gate insulating film, 6019 denotes a source region and a drain region made of n-type impurity regions, 6030 denotes an LDD region (lightly doped drain region), 6046 denotes a source wiring, and 6047 denotes This is a drain wiring.

  In the photoelectric conversion element 111, 6036 is a p-type semiconductor layer made of a p-type impurity region, 6020b is an n-type semiconductor layer made of an n-type impurity region, and 6054 is a photoelectric conversion layer (i layer) made of an amorphous semiconductor film. It is.

  In the n-channel transistor in the driver circuit portion, 6026 is a gate electrode, 6008 is a gate insulating film, 6021 is a source region and a drain region made of an n-type impurity region, 6031 is an LDD region (lightly doped drain region), and 6050 is a source. A wiring 6051 is a drain wiring.

  In the p-channel transistor of the driver circuit portion, reference numeral 6027 denotes a gate electrode, 6008 denotes a gate insulating film, 6039 denotes a source region and a drain region made of a p-type impurity region, 6052 denotes a drain wiring, and 6053 denotes a source wiring.

  A first interlayer insulating film 6041 and a second interlayer insulating film 6059 are provided so as to cover the amplifying transistor 113, the switching transistor 112, the resetting transistor 114, the n-channel transistor, and the p-channel transistor.

  This embodiment can be freely combined with Embodiment Modes 1 to 3 and Embodiments 1 and 2.

  In Embodiment 3, the cross-sectional structure of the semiconductor device has been described. In this embodiment, a state in which the FPC is attached after sealing the semiconductor device will be described.

  FIG. 13A is a top view of a semiconductor device using the present invention, and FIG. 13B is a cross-sectional view taken along the line XX ′ of FIG. 13A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source signal line driver circuit, and 4004 denotes a gate signal line driver circuit. Each driver circuit reaches an FPC 4008 through wirings 4005, 4006, and 4007. Connected to an external device.

  At this time, a cover member 4009, a sealing member 4010, and a sealing member (also referred to as a housing member) 4011 (illustrated in FIG. 13B) are provided so as to surround at least the pixel portion, preferably the driver circuit and the pixel portion.

  FIG. 13B shows a cross-sectional structure of the semiconductor device of this embodiment. A driver circuit portion (here, a CMOS in which an n-channel TFT and a p-channel TFT are combined) is formed over a substrate 4001 and a base film 4012. 4013 and a pixel portion 4014 (however, only a photoelectric conversion element and a switching transistor are illustrated for the sake of simplicity) are formed.

  When the driver circuit portion 4013 and the pixel portion 4014 are completed using a known manufacturing method, a first interlayer insulating film (planarization film) 4015 made of a resin material is formed.

  Next, a second interlayer insulating film 4017 made of a resin material is formed, and a passivation film 4022, a filler 4023, and a cover material 4009 are formed so as to cover the second interlayer insulating film 4017.

Further, a sealing material 4011 is provided inside the cover material 4009 and the substrate 4001, and a sealing material (second sealing material) 4010 is formed outside the sealing material 4011.

At this time, the filler 4023 also functions as an adhesive for bonding the cover material 4009. As filler 4023, PVC (polyvinyl chloride)
Epoxy resin, silicon resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4023 because a moisture absorption effect can be maintained.

  Further, a spacer may be contained in the filler 4023. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic. In the case where a spacer is provided, the passivation film 4022 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.

  As the cover member 4009, a glass plate, an aluminum plate, a stainless steel plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 4023, it is preferable to use a sheet having a structure in which an aluminum foil of several tens [μm] is sandwiched between PVF films or Mylar films.

  The wiring 4007 is connected to a transistor included in the driver circuit 4013 and is electrically connected to the FPC 4008 through a gap between the sealing material 4011 and the sealing material 4010 and the substrate 4001. Note that although the wiring 4007 is described here, the other wirings 4005 and 4006 are also electrically connected to the FPC 4008 under the sealing material 4011 and the sealing material 4010 in the same manner.

In this embodiment, the cover material 4009 is bonded after the filler 4023 is provided, and the sealing material 4011 is attached so as to cover the side surface (exposed surface) of the filler 4023. However, the cover material 4009 and the sealing material 4011 are attached. After the attachment, the filler 4023 may be provided. In this case, a filler inlet that leads to a gap formed by the substrate 4001, the cover member 4009, and the sealing member 4011 is provided. Then, the void is evacuated (10 ^-2 Torr or less), the inlet is immersed in a water tank containing the filler, and the pressure outside the void is made higher than the pressure inside the void, Fill in the void.

  This embodiment can be freely combined with Embodiment Modes 1 to 3 and Embodiments 1 to 3.

  An example of an electronic device using the semiconductor device of the present invention will be described with reference to FIG.

  FIG. 14A illustrates a hand scanner using a line sensor. An optical system 1002 such as a rod lens array is provided on a CCD type (CMOS type) image sensor 1001. The optical system 1002 is used so that an image on the subject 1004 is displayed on the image sensor 1001. A light source 1003 such as an LED or a fluorescent lamp is provided at a position where light can be emitted to the subject 1004. A glass 1005 is provided below the subject 1004.

  Light emitted from the light source 1003 enters the subject 1004 through the glass 1005. Light reflected by the subject 1004 enters the optical system 1002 through the glass 1005. The light that has entered the optical system 1002 enters the image sensor 1001, where it is photoelectrically converted. The semiconductor device of the present invention can be used for the image sensor 1001.

  In FIG. 14B, reference numeral 1801 denotes a substrate, 1802 denotes a pixel portion, 1803 denotes a touch panel, and 1804 denotes a touch pen. The touch panel 1803 has a light-transmitting property, can transmit light emitted from the pixel portion 1802 and light incident on the pixel portion 1802, and can read an image on a subject through the touch panel 1803. Even when an image is displayed on the pixel portion 1802, the image on the pixel portion 1802 can be viewed through the touch panel 1803.

  When the touch pen 1804 touches the touch panel 1803, information on a position where the touch pen 1804 and the touch panel 1803 are in contact with each other can be taken into the semiconductor device as an electric signal. In the touch panel 1803 and the touch pen 1804 used in this embodiment, information on the position of the portion where the touch pen 1803 is translucent and the touch pen 1804 and the touch panel 1803 are in contact is taken into the semiconductor device as an electrical signal. Any known one can be used. Note that the semiconductor device of the present invention can be used for the pixel portion 1802.

  FIG. 14C is a portable hand scanner different from that in FIG. 14B, and includes a main body 1901, a pixel portion 1902, an upper cover 1903, an external connection port 1904, and an operation switch 1905. FIG. 14D is a view in which the upper cover 1903 of the same portable hand scanner as FIG. 14C is closed.

  An image signal read by the pixel portion 1902 can be sent from an external connection port 1904 to an electronic device connected to the outside of the portable hand scanner, and the image can be corrected, combined, edited, and the like on a personal computer. Note that the semiconductor device of the present invention can be used for the pixel portion 1802.

  Further, examples of the electronic device using the semiconductor device of the present invention include a video camera, a digital still camera, a notebook personal computer, a portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like).

  FIG. 14E shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The semiconductor device of the present invention can be used for the display portion 2602.

  FIG. 14F illustrates a mobile computer (information portable terminal), which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. It can be used for the semiconductor device 2302 of the present invention.

  FIG. 14G illustrates a cellular phone (portable terminal) which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. . The semiconductor device of the present invention can be used for the display portion 2703.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

Claims (5)

A first pixel; a second pixel disposed adjacent to the first pixel; and a third pixel disposed adjacent to the first pixel;
Each of the first pixel, the second pixel, and the third pixel includes a photoelectric conversion element, a first transistor, a second transistor, and a third transistor,
In the first pixel,
A gate of the first transistor is electrically connected to a first wiring;
One of a source and a drain of the first transistor is electrically connected to a second wiring;
A gate of the second transistor is electrically connected to the other of the source and the drain of the first transistor;
One of a source and a drain of the second transistor is electrically connected to a third wiring;
A gate of the third transistor is electrically connected to a fourth wiring;
One of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor;
The other of the source and the drain of the third transistor is electrically connected to the photoelectric conversion element,
The second wiring is electrically connected to the second pixel;
The semiconductor device is characterized in that the third wiring is electrically connected to the third pixel. In claim 1,
The second wiring has a function of transmitting a signal to the gate of the second transistor,
The third wiring has a function of supplying a current to the second transistor;
The semiconductor device, wherein the signal is a digital pulse signal. In claim 11 or claim 2,
A sample hold circuit, and a signal output circuit,
The sample and hold circuit has a function capable of holding a first signal output from the second transistor,
The semiconductor device having a function in which the signal output circuit can output a second signal for outputting the first signal from the sample hold circuit. In any one of Claims 1 thru | or 3,
A semiconductor device, wherein a lens array is provided, and light enters through the lens array.   An electronic apparatus comprising the semiconductor device according to claim 1, an antenna, and an audio input unit.

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