JP5288645B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a method for driving a semiconductor device. More specifically, the present invention relates to a method for driving an active matrix semiconductor device having a transistor manufactured over a semiconductor substrate or an insulating surface.

  A semiconductor device having an image sensor function is provided with a photoelectric conversion element and one or a plurality of transistors for controlling the photoelectric conversion element. As the photoelectric conversion element, a PN type photodiode is often used. In addition, there are a PIN photodiode, an avalanche diode, an npn buried diode, a Schottky diode, a phototransistor, an X-ray photoconductor, an infrared sensor, and the like.

  Semiconductor devices having an image sensor function are roughly classified into a CCD type and a CMOS type. CMOS type semiconductor devices are classified as passive types without an amplification circuit and active types with an amplification circuit. Since the amplification circuit has a function of amplifying the image signal of the subject read by the photoelectric conversion element, the amplification circuit is hardly affected by noise and the like, and is an active CMOS semiconductor device equipped with the amplification circuit Is widely adopted.

  In an active CMOS semiconductor device, an input terminal of an amplification circuit having a high input impedance is connected to an output terminal of a photoelectric conversion element. Therefore, the subject information can be read any number of times without deteriorating the region from which the subject information is read. This is generally called nondestructive reading.

A method for expanding the dynamic range (light / dark ratio) by outputting signals having different accumulation times using nondestructive readout has been studied. As an example, as reported in “O. Yadid-Pecht et. Al., Proc. SPIE, vol. 2654, pp82-92, 1996”, source signal line drive circuits are arranged above and below the pixel portion. Research has been conducted on a method for arranging signals one by one and outputting signals having different accumulation times. As another example, as reported in “ISSCC99: p308: A 640x512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC”, the accumulation time is T, 2T, 4T,. A method of reading with a power of 2 such as (2 ^K ) × T (where T represents a frame period) has been studied.

  Note that in this specification, the accumulation time refers to a period from when a photoelectric conversion element provided in a pixel is initialized to when a signal is output from the pixel. This is also the time for irradiating light to the light receiving portion of the photoelectric conversion element and accumulating signals, and also means the time called exposure time.

  FIG. 3 shows an example of a schematic diagram of a semiconductor device provided with a photoelectric conversion element. The semiconductor device in FIG. 3 includes a pixel portion 104, a source signal line driver circuit 101, a gate signal line driver circuit 102, and a reset signal line driver circuit 103 arranged around the pixel portion 104. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output line drive circuit 101c, and a final output amplification circuit 101d.

The pixel portion 104 has a plurality of pixels 100 arranged in a matrix.
Note that in this specification, the pixel portion 104 is provided with x columns (vertical) × y rows (horizontal) pixels 100 in a matrix.

  FIG. 4 shows a circuit diagram of the pixel 100 provided in the i-th row and j-th column. The pixel 100 includes one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), one of gate signal lines (G1 to Gy), and a reset signal line (R1). To Ry). In addition, the pixel 100 includes a switching transistor 112, an amplification transistor 113, a reset transistor 114, and a photoelectric conversion element 111.

    The photoelectric conversion element 111 provided in each pixel 100 of the semiconductor device illustrated in FIGS. 3 and 4 changes its potential when irradiated with light reflected from a subject.

    In this state, when the gate signal line (Gi) is selected, the switching transistor 112 connected to the gate signal line (Gi) is turned on, and a signal corresponding to the potential of the photoelectric conversion element 111 is switched. The signal is output to the signal output line (Sj) through the transistor 112. Then, the signal output to the signal output line (Sj) is sent to the source signal line driver circuit 101.

Here, a method for driving the semiconductor device having the above-described structure is described with reference to FIGS. In FIG. 15, the horizontal axis indicates the passage of time. In this specification, a period from when a reset signal is applied to the reset signal line R (any one of R1 to Ry) until the reset signal is applied again is defined as one frame period (F).
And In this specification, a period during which a signal is applied to the reset signal line R and a signal is applied to the reset signal line R in the next row is defined as a horizontal scanning period (P).

  First, the reset signal line (R1) is selected by a reset signal input from the reset signal line driving circuit 103 to the reset signal line (R1) in the first row. In this specification, the selection of the reset signal line means that all the reset transistors 114 connected to the reset signal line are turned on. That is, here, the reset transistors 114 of all the pixels (pixels in the first row) connected to the reset signal line (R1) are turned on. Then, the photoelectric conversion elements 111 in the first row are initialized.

  At the same time as the selection of the reset signal line (R1) is completed, the reset signal line (R2) of the next row is selected. Then, the reset transistors 114 of all the pixels connected to the reset signal line (R2) are turned on, and the photoelectric conversion elements 111 included in the pixels in the second row are initialized.

  In this way, all the reset signal lines (R1 to Ry) are sequentially selected. Then, the photoelectric conversion element 111 included in the pixel 100 connected to the selected reset signal line R is initialized.

Next, signals applied to the gate signal lines (G1 to Gy) will be described. When six horizontal scanning periods (6 × P) have elapsed since the reset signal was input to the reset signal line (R1) in the first row, the gate signal line driving circuit 102 inputs the gate signal line (G1). The gate signal line (G1) is selected by the gate signal.
Then, the switching transistor 112 connected to the gate signal line (G1) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the first row. In this case, the accumulation time (L) of the signal output from the pixel 100 is six horizontal scanning periods (6 × P).

  Next, the gate signal line (G2) in the second row is selected by the gate signal input from the gate signal line driver circuit 102 to the gate signal line (G2) in the second row. Then, the switching transistor 112 connected to the gate signal line (G2) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the second row. In this case, the accumulation time (L) of the signal output from the pixel 100 is six horizontal scanning periods (6 × P).

In this way, all the gate signal lines (G1 to Gy) are sequentially selected.
Then, the signals of the pixels 100 connected to the selected gate signal lines (G1 to Gy) are output to the signal output lines (S1 to Sx). As can be seen from FIG. 15, when this driving method is used, the accumulation time (L) of the signal of the pixel 100 output from the pixel 100 is obtained.
Are all the same and have six horizontal scanning periods (6 × P).

  Next, referring to FIG. 16, the timing of the gate signal output to the gate signal lines (G1 to Gy), the timing of the reset signal output to the reset signal lines (R1 to Ry), and the i-th and j-th columns A relationship with the potential of the photoelectric conversion element 111 provided in the pixel 100 will be described.

  First, the reset signal line (Ri) is selected by a reset signal input from the reset signal line driving circuit 103 to the reset signal line (Ri). Then, the reset transistors 114 of all the pixels 100 (i-th row pixels 100) connected to the reset signal line (Ri) are turned on. Then, the photoelectric conversion element 111 included in the pixel 100 in the i-th row is initialized.

  If the photoelectric conversion element 111 is irradiated with light after the photoelectric conversion element 111 is initialized, a charge corresponding to the light intensity is generated in the photoelectric conversion element 111. Then, the charge charged in the photoelectric conversion element 111 by the reset operation is gradually discharged, and the potential of the n-channel terminal of the photoelectric conversion element 111 becomes low.

  As shown in FIG. 16, when the photoelectric conversion element 111 is irradiated with bright light, the amount of discharge is large, and thus the potential of the n-channel terminal of the photoelectric conversion element 111 is low. On the other hand, when the photoelectric conversion element 111 is irradiated with dark light, the amount of discharge is small, and the potential of the n-channel terminal of the photoelectric conversion element 111 is much less than that when bright light is irradiated. It is not low.

Then, when six horizontal scanning periods (6 × P) have elapsed since the reset signal was input to the reset signal line (Ri), the gate signal line driving circuit 102 supplies the jth gate signal line (Gi). Depending on the input gate signal, the gate signal line (Gi)
Is selected. Then, the switching transistor 112 connected to the gate signal line (Gi) is turned on, and the potential of the n-channel terminal of the photoelectric conversion element 111 is read as a signal. This signal is proportional to the intensity of light applied to the photoelectric conversion element 111.

  Note that when very bright light is irradiated, the potential of the n-channel terminal of the photoelectric conversion element 111 decreases, but when the potential decreases to the potential of the power supply reference line 121, the potential does not change. Such a situation is called saturation.

Further, the photoelectric conversion element 111 accumulates charges generated by the irradiated light during the accumulation time. Therefore, if the accumulation times are different, the signal value is different because the total amount of charges generated by the light is different even if the light has the same light intensity.
For example, when intense light is irradiated to the photoelectric conversion element 111, it is saturated in a short accumulation time. Further, even when weak light is irradiated onto the photoelectric conversion element 111, when the accumulation time is long, it eventually reaches a saturated state. That is, the signal is determined by the product of the intensity of light applied to the photoelectric conversion element 111 and the accumulation time.

  In FIG. 16, when the gate signal is input, the potential of the photoelectric conversion element 111 irradiated with dark light is slightly lower than that when the reset signal is input, but it still reaches the saturation state. Absent.

  On the other hand, the photoelectric conversion element 111 irradiated with bright light is already saturated. In this case, the signal output from the pixel 100 cannot be read accurately. Therefore, it is preferable that the accumulation time when reading the signal of the pixel 100 including the photoelectric conversion element 111 irradiated with bright light is slightly shorter.

  When the driving method described above is used, the accumulation time (L) of the signal output from the pixel 100 is all six horizontal scanning periods (6 × P). In other words, the signal output from the pixel 100 is , All could only be output with the same accumulation time.

  For this reason, when the intensity of light applied to the pixel 100 is high, the potential of the photoelectric conversion element 111 may be saturated, and information on the subject cannot be read accurately. In addition, when the light intensity applied to the pixel 100 is low, the change in the potential of the photoelectric conversion element 111 is very weak, so there is not much difference in the signal output from the pixel 100, and the subject information can be read accurately. I couldn't.

  Further, when the method reported in “O. Yadid-Pecht et. Al., Proc. SPIE, vol. 2654, pp82-92, 1996” is used, the accumulation time of the signal output from the pixel is 2 There were only types. In addition, since the drive circuits are arranged one above the other of the pixel portion, there is a disadvantage that the drive circuit portion becomes large.

In addition, when using the method reported in “ISSCC99: p308: A 640x512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC”, the accumulation time of the signal output from the pixel is T, 2T, 4T, ..., (2 ^K ) × T. As a result, there is a drawback that the reading time becomes very long as k increases. For example, in the case of k = 3 (when the dynamic range is increased by 8 times), the read time is 8 times longer than the normal read time.

In order to solve the above-described problems of the prior art, the following measures are taken in the present invention. The driving method of the present invention will be described with reference to FIG.

  In FIG. 17, the horizontal axis indicates the passage of time. FIG. 17 also shows a timing chart of signals applied to the gate signal lines Ga and G (a + 1) by the conventional driving method, the gate signal lines (Ga to G (a + 1)) and the gate signal line by the driving method of the present application. 6 shows a timing chart of signals applied to (Gb to G (b + 2)) and gate signal lines (Gc to G (c + 2)). Note that a, b, and c are all natural numbers.

  As shown in FIG. 17, in the conventional driving method, any one of the gate signal lines (G1 to Gy) is selected in the horizontal scanning period (P). That is, in one frame period, vertical scanning is performed y times (the same number as the number of gate signal lines (G1 to Gy)).

  On the other hand, in the driving method of the present invention, any three of the gate signal lines (G1 to Gy) are selected in the horizontal scanning period (P), and (3 × y) vertical scanning is performed in one frame period. If three gate signal lines (G1 to Gy) are simultaneously selected in one horizontal scanning period (P), the signals are output from three of the pixels connected to the same signal output line (S1 to Sx). Since the signals are output to the same signal output lines (S1 to Sx), the signals are mixed. Therefore, in the present invention, the horizontal scanning period (P) is divided into three. These are defined as a first sub-horizontal scanning period, a second sub-horizontal scanning period, and a third sub-horizontal scanning period. In each sub horizontal scanning period, one of the gate signal lines (G1 to Gy) is selected. Then, a maximum of three gate signal lines (G1 to Gy) can be selected in one horizontal scanning period (P) without mixing the signal output lines (S1 to Sx) with the signals output from the pixels. .

  Although an example in which the horizontal scanning period (P) is divided into three is shown here, the present invention is not limited to this, and the horizontal scanning period (P) can be divided into an arbitrary number of designers.

  In the first sub-horizontal scanning period, a signal applied from the gate signal line driving circuit to the gate signal line G (any one of G1 to Gy) is set as the first sub-gate signal, and the second sub-horizontal scanning period. The signal applied to the gate signal line G from the gate signal line driving circuit is defined as a second sub-gate signal. In the third sub horizontal scanning period, a signal applied to the gate signal line G from the gate signal line driving circuit is set as a third sub gate signal.

  As shown in FIG. 19, in a certain horizontal scanning period (P), the gate signal line (Ga) in the a-th row is selected in the first sub-horizontal scanning period, and the b-th row in the second sub-horizontal scanning period. Gate signal line (Gb) is selected, and the gate signal line (Gc) in the c-th row is selected in the third sub-horizontal scanning period.

  In the next horizontal scanning period (P), the gate signal line (Ga) in the (a + 1) th row is selected in the first sub-horizontal scanning period, and the (b + 1) th row in the second sub-horizontal scanning period. Gate signal line (Gb) is selected, and the gate signal line (Gc) in the (c + 1) th row is selected in the third sub-horizontal scanning period.

  In this way, all the gate signal lines (G1 to Gy) are sequentially selected in each of the first sub-horizontal scanning period, the second sub-horizontal scanning period, and the third sub-horizontal scanning period. In other words, the first sub-gate signal, the second sub-gate signal, and the third sub-gate signal are sequentially applied to all the gate signal lines (G1 to Gy). In the present invention, the timing at which the first sub-gate signal, the second sub-gate signal, and the third sub-gate signal are applied to the gate signal lines (G1 to Gy) is changed. As a result, a plurality of signals are output from the pixel having the photoelectric conversion element, and the accumulation times of the plurality of signals are different from each other.

  That is, in the present invention, by dividing the horizontal scanning period (P) into n (n is a natural number), (n × y) horizontal scannings can be performed within one frame period, so that the reading time is reduced. It can be prevented from becoming long. Further, n signals can be output from each pixel, and the accumulation times of a plurality of signals are different from each other. Therefore, it is possible to select a signal suitable for the light intensity irradiated to the pixel 100.

  In the driving method of the present invention, by dividing the horizontal scanning period (P), it is possible to output a plurality of signals from the same pixel within one frame period, thereby preventing an increase in reading time. And the dynamic range can be further expanded. Since the horizontal scanning period (P) can be divided into an arbitrary number, it is easy to output signals with different accumulation times.

8A and 8B illustrate a method for driving a semiconductor device of the present invention. 10A and 10B illustrate a relationship between a potential of a photoelectric conversion element and time. 1 is a schematic diagram of a semiconductor device of the present invention. FIG. 10 is a diagram illustrating a circuit diagram of a pixel of a semiconductor device of the invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. 6A and 6B illustrate a source signal line driver circuit of a semiconductor device of the present invention. FIG. 9 is a diagram showing a cross-sectional structure of a semiconductor device of the invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device of the present invention. FIG. 14 illustrates an example of an electronic device to which the semiconductor device of the invention can be applied. 10A and 10B illustrate a conventional method for driving a semiconductor device. 10A and 10B illustrate a relationship between a potential of a photoelectric conversion element and time. 8A and 8B illustrate a method for driving a semiconductor device of the present invention.

(Embodiment 1)
The driving method of the present invention is applied to any semiconductor device having a photoelectric conversion element. 3 and 4 show an example of a semiconductor device to which the present invention is applied.

  The semiconductor device in FIG. 3 includes a pixel portion 104, a source signal line driver circuit 101, a gate signal line driver circuit 102, and a reset signal line driver circuit 103 arranged around the pixel portion 104. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output line drive circuit 101c, and a final output amplification circuit 101d.

  FIG. 3 shows an example in which the source signal line driver circuit 101 is provided with a bias circuit 101a, a sample hold circuit 101b, a signal output line driver circuit 101c, and a final output amplifier circuit 101d. Is not limited to this. The source signal line driver circuit 101 will be described in detail in the embodiments.

The pixel portion 104 has a plurality of pixels 100 arranged in a matrix.
Note that in this specification, the pixel portion 104 is provided with x columns (vertical) × y rows (horizontal) pixels 100 in a matrix.

  FIG. 4 shows a circuit diagram of the pixel 100 provided in the i-th row and j-th column. The pixel 100 includes one of signal output lines (S1 to Sx), one of power supply lines (VB1 to VBx), one of gate signal lines (G1 to Gy), and a reset signal line (R1). To Ry). In addition, the pixel 100 includes a switching transistor 112, an amplification transistor 113, a reset transistor 114, and a photoelectric conversion element 111.

    The photoelectric conversion element 111 includes an n-channel terminal, a p-channel terminal, and a photoelectric conversion layer provided between the n-channel terminal and the p-channel terminal. One of the p-channel terminal and the n-channel terminal is connected to the power supply reference line 121, and the other is connected to the gate electrode of the amplifying transistor 113.

    The gate electrode of the switching transistor 112 is connected to the gate signal line (Gi). One of the source region and the drain region of the switching transistor 112 is connected to the source region of the amplifying transistor 113, and the other is connected to the signal output line (Sj). The switching transistor 112 is a transistor that functions as a switching element when a signal from the photoelectric conversion element 111 is output.

    The drain region of the amplifying transistor 113 is connected to the power supply line (VBj). The source region of the amplifying transistor 113 is connected to the source region or the drain region of the switching transistor 112. The amplifying transistor 113 forms a source follower circuit with a biasing transistor (not shown) provided below the pixel portion 104. Therefore, it is better that the polarity of the amplifying transistor 113 and the biasing transistor are the same.

  The gate electrode of the reset transistor 114 is connected to the reset signal line (Ri). One of the source region and the drain region of the reset transistor 114 is connected to the power supply line (VBj), and the other is connected to the gate electrodes of the photoelectric conversion element 111 and the amplification transistor 113. The reset transistor 114 is a transistor that functions as an element (switching element) for initializing (resetting) the photoelectric conversion element 111.

  Note that the configuration of the pixel 100 illustrated in FIG. 4 is merely an example, and the present invention is not limited to this. For example, one transistor (transfer transistor) may be added to the pixel 100 shown in FIG. 4, and the present invention can be applied to a semiconductor device having such a structure. As the photoelectric conversion element 111, a photodiode, a photogate, or the like may be used. That is, the pixel 100 may have any configuration, and the number of transistors and capacitors included in the pixel 100 and the connection configuration thereof are not particularly limited. Further, the number of driver circuits such as the gate signal line driver circuit 102 and the reset signal line driver circuit 103 may be changed depending on the structure of the pixel 100, and the number of driver circuits provided in the semiconductor device is not particularly limited.

  Next, a driving method of the present invention applied to the semiconductor device having the above-described structure will be described with reference to FIGS.

  In FIG. 1, the horizontal axis shows the passage of time, and also shows a timing chart of signals applied to the reset signal lines (R1 to Ry) and the gate signal lines (G1 to Gy). In this embodiment, y is 14, but the present invention is not limited to this. The number of reset signal lines (R1 to Ry) and gate signal lines (G1 to Gy) (value of y) is determined by the designer. Can be arbitrarily determined.

  In this specification, a period from when the reset signal is applied to the reset signal line R (any one of R1 to Ry) until the reset signal is applied again is defined as one frame period (F). . In this specification, a period during which a signal is applied to the reset signal line R and a signal is applied to the reset signal line R in the next column is defined as a horizontal scanning period (P). A period obtained by dividing the horizontal scanning period (P) into three is defined as a first sub horizontal scanning period, a second sub horizontal scanning period, and a third sub horizontal scanning period, respectively.

  In the first sub-horizontal scanning period, a signal applied from the gate signal line driving circuit 102 to the gate signal line G (any one of G1 to Gy) is set as the first sub-gate signal, and the second sub-horizontal scanning is performed. In the period, a signal applied to the gate signal line G from the gate signal line driving circuit 102 is a second sub-gate signal. In the third sub-horizontal scanning period, a signal applied from the gate signal line driving circuit 102 to the gate signal line G is set as a third sub-gate signal.

  First, the reset signal line (R1) is selected by a reset signal input from the reset signal line driving circuit 103 to the reset signal line (R1) in the first row. Then, the reset transistors 114 of all the pixels (first row pixels) connected to the reset signal line (R1) are turned on, and the photoelectric conversion elements 111 included in the first row pixels 100 are initialized. Is done.

  At the same time as the selection of the reset signal line (R1) is completed, the reset signal line (R2) in the second row is selected. Then, the reset transistors 114 of all the pixels 100 connected to the reset signal line (R2) are turned on, and the photoelectric conversion elements 111 included in the pixels 100 in the second row are initialized.

  In this way, all the reset signal lines (R1 to Ry) are sequentially selected. Then, the photoelectric conversion element 111 included in the pixel 100 connected to the selected reset signal line R is initialized.

  Next, a timing chart of signals applied to the gate signal lines (G1 to Gy) will be described.

  When three horizontal scanning periods (3 × P) have elapsed since the reset signal was input to the first row reset signal line (R1), the gate signal line (G1) ) To select the gate signal line (G1). Then, the switching transistor 112 connected to the gate signal line (G1) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the first row. In this case, the accumulation time (L) of the signal output by the pixel 100 is three horizontal scanning periods (3 × P).

Next, the gate signal line (G12) in the 12th row from the gate signal line driving circuit 102
The gate signal line (G12) is selected by the second sub-gate signal input to. Then, the switching transistor 112 connected to the gate signal line (G12) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the twelfth row.

  Further, the gate signal line (Gb) is selected by the third sub-gate signal input from the gate signal line driving circuit 102 to the gate signal line (Gb) (not shown) in the b-th row (b is a natural number). Then, the switching transistor 112 connected to the gate signal line (Gb) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the b-th row.

In this way, the first sub-gate signal is output to the first row gate signal line (G1) in the first sub-horizontal scanning period, and the second sub-gate signal is output to the twelfth row gate signal line (G12). The third sub-gate signal is output in the horizontal scanning period, and the third sub-gate signal is output to the b-th gate signal line (Gb) in the third sub-horizontal scanning period.
A period including the first sub-horizontal scanning period, the second sub-horizontal scanning period, and the third sub-horizontal scanning period is one horizontal scanning period (P).

  Next, after four horizontal scanning periods (4 × P) have passed since the reset signal was input to the reset signal line (R1), the gate signal line driving circuit 102 supplies the gate signal line (G2) in the second row. The gate signal line (G2) is selected by the input first sub-gate signal. Then, the switching transistor 112 connected to the gate signal line (G2) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the second row. In this case, the accumulation time (L) of the signal output by the pixels 100 in the second row is three horizontal scanning periods (3 × P).

Next, the gate signal line (G13) in the 13th row from the gate signal line driving circuit 102
The gate signal line (G13) is selected by the second sub-gate signal input to. Then, the switching transistor 112 connected to the gate signal line (G13) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the 13th row.

  Further, the gate signal line (G7) is selected by the third sub-gate signal input from the gate signal line driver circuit 102 to the gate signal line (G7) in the seventh row. Then, the switching transistor 112 connected to the gate signal line (G7) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the seventh row.

  In this way, the first sub-gate signal is output to the second row gate signal line (G2) in the first sub-horizontal scanning period, and the second sub-gate signal is output to the thirteenth row gate signal line (G13). The third sub-gate signal is output in the horizontal scanning period, and is output to the gate signal line (G7) in the seventh row in the third sub-horizontal scanning period.

Then, after six horizontal scanning periods (6 × P) have passed since the reset signal was input to the reset signal line (R1), the first signal input from the gate signal line driving circuit 102 to the gate signal line (G1). 2 Sub-gate signal, gate signal line (G1)
Is selected. Then, the switching transistor 112 connected to the gate signal line (G1) is turned on, and signals output from the pixels 100 in the first row are output to the signal output lines (S1 to Sx). In this case, the accumulation time (L) of the signal output from the pixel 100 is six horizontal scanning periods (6 × P).

  Next, the gate signal line (G9) is selected by the third sub-gate signal input from the gate signal line driver circuit 102 to the gate signal line (G9) in the ninth row. Then, the switching transistor 112 connected to the gate signal line (G9) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the ninth row.

  Then, after twelve horizontal scanning periods (12 × P) have elapsed since the reset signal was input to the reset signal line (R1), the first signal input from the gate signal line driving circuit 102 to the gate signal line (G1). The gate signal line (G1) is selected by the three sub-gate signals. Then, the switching transistor 112 connected to the gate signal line (G1) is turned on, and a signal is output to the signal output lines (S1 to Sx) by the pixels 100 in the first row. In this case, the accumulation time (L) of the signal output from the pixel 100 is 12 horizontal scanning periods (12 × P).

  Thus, the first sub-gate signal is input to any one of the gate signal lines (G1 to Gy) in the first sub-horizontal scanning period, and the gate signal lines (G1 to Gy) in the second sub-horizontal scanning period. ), The second sub-gate signal is input, and the third sub-gate signal is input to any one of the gate signal lines (G1 to Gy) in the third sub-horizontal scanning period. . At this time, in a certain horizontal scanning period, the gate signal lines (G1 to Gy) to which the first subgate signal is input, the gate signal lines (G1 to Gy) to which the second subgate signal is input, and the third subgate signal are input. Different gate signal lines (G1 to Gy) are used.

In turn, all the gate signal lines (G1 to Gy) are selected in the first sub-horizontal scanning period, the second sub-horizontal scanning period, and the third sub-horizontal scanning period, respectively.
As a result, the first sub-gate signal, the second sub-gate signal, and the third sub-gate signal are input to all the gate signal lines (G1 to Gy), respectively.

  When one frame period (F) elapses, the reset signal line (R1) is selected by the reset signal input from the reset signal line driver circuit 103 to the reset signal line (R1) again. Then, the above-described operation as shown in FIG. 1 is repeated.

  Note that a period from when the reset signal is input to the reset signal lines (R1 to Ry) to when the first sub-gate signal is input to the gate signal lines (G1 to Gy) (3 × P in this embodiment), The period until the second sub-gate signal is input (6 × P in this embodiment) is different from the period until the third sub-gate signal is input (12 × P in this embodiment). As a result, three signals can be output by the pixel 100, and the accumulation times of the three signals are different.

  The first sub-gate signal is output only from the gate signal line driving circuit 102 during the first sub-horizontal scanning period, the second sub-gate signal is output only during the second sub-horizontal scanning period, and the third sub-gate signal is output. Is output only during the third sub-horizontal scanning period. Therefore, for example, the accumulation time (L) of the signal output by the pixel 100 after six horizontal scanning periods (6 × P) have elapsed since the reset signal was input to the reset signal line (R1) can be accurately calculated. Is a period obtained by adding six horizontal scanning periods (6 × P) and one sub horizontal scanning period. However, since the sub-horizontal scanning period is sufficiently shorter than the accumulation time (L), the accumulation time (L) in the above case is regarded as six horizontal scanning periods (6 × P) in this specification. I will decide.

  In the embodiment, the horizontal scanning period (P) is equally divided into three, but the present invention is not limited to this. The horizontal scanning period (P) can be divided into an arbitrary number by the designer.

  In this embodiment, the signal is output so that the accumulation time (L) is a power of 2 of 3 × P, 6 × P, and 12 × P. However, the present invention is not limited to this. For example, a signal may be output so that the accumulation time (L) is doubled, or a signal may be output so as to be ten times.

(Embodiment 2)
Next, referring to FIG. 2, the timing at which the first sub-gate signal, the second sub-gate signal, and the third sub-gate signal are output to the gate signal lines (G1 to Gy) and the reset signal are output to the reset signal lines (R1 to Ry). The relationship between the timing to be applied and the potential of the photoelectric conversion element 111 will be described. In this embodiment, as an example, the pixel 100 provided in the i-th row and the j-th column will be described.

First, the reset signal line (Ri) of the i-th row from the reset signal line driving circuit 103
The reset signal line (Ri) is selected by the reset signal input to. Then, the reset transistors 114 of all the pixels (i-th row pixels) connected to the reset signal line (Ri) are turned on. Then, the photoelectric conversion element 111 included in the pixel in the i-th row is initialized.

  Then, when three horizontal scanning periods (3 × P) have elapsed since the reset signal was input to the reset signal line (Ri), the gate signal line driving circuit 102 supplies the gate signal line (Gi) in the i-th row. The gate signal line (Gi) is selected by the input first sub-gate signal. Then, the switching transistor 112 connected to the gate signal line (Gi) is turned on, and the potential of the n-channel terminal of the photoelectric conversion element 111 is read as a signal. This signal is proportional to the intensity of light applied to the photoelectric conversion element 111.

  Next, after six horizontal scanning periods (6 × P) have elapsed since the reset signal was input to the reset signal line (Ri), the gate signal line driving circuit 102 supplies the gate signal line (Gi) in the i-th row. The gate signal line (Gi) is selected by the input second subgate signal. Then, the switching transistor 112 connected to the gate signal line (Gi) is turned on, and the potential of the n-channel terminal of the photoelectric conversion element 111 is read as a signal.

  Next, after twelve horizontal scanning periods (12 × P) have elapsed since the reset signal was input to the reset signal line (Ri), the gate signal line driving circuit 102 supplies the gate signal line (Gi) in the i-th row. The gate signal line (Gi) is selected by the input third sub-gate signal. Then, the switching transistor 112 connected to the gate signal line (Gi) is turned on, and the potential of the n-channel terminal of the photoelectric conversion element 111 is read as a signal.

  When one frame period (F) elapses, the reset signal line (R (i + 1)) is reset by a reset signal input from the reset signal line driver circuit 103 to the reset signal line (R (i + 1)) in the (i + 1) th row. Is selected. Then, the reset transistor 114 is turned on again to reset the photoelectric conversion element 111, and the above-described operation is repeated.

  According to the present invention, a plurality of signals are output from the pixel 100 in one frame period, and the accumulation times of the plurality of signals are different from each other. In FIG. 2, the potential of the photoelectric conversion element 111 indicated by a solid line is a case where dark light is irradiated, and the potential of the photoelectric conversion element 111 indicated by a dotted line indicates a case where bright light is irradiated.

  In FIG. 2, when the first sub-gate signal is input, there is no significant difference between the potential of the photoelectric conversion element 111 irradiated with bright light and the potential of the photoelectric conversion element 111 irradiated with dark light.

  However, when the second sub-gate signal is input, the photoelectric conversion element 111 irradiated with bright light is already close to saturation. On the other hand, the potential of the photoelectric conversion element 111 irradiated with dark light is slightly lower than that at the time when the first sub-gate signal is input, but has not yet reached the saturation state.

  When the third sub-gate signal is input, the photoelectric conversion element 111 that has already been irradiated with bright light is already in a saturated state. On the other hand, the potential of the photoelectric conversion element 111 irradiated with dark light is close to a saturated state.

  As described above, the signal output from the pixel 100 is determined by the product of the intensity of light applied to the photoelectric conversion element 111 included in the pixel 100 (the potential of the photoelectric conversion element 111) and the accumulation time. That is, the signal of the pixel 100 having the photoelectric conversion element 111 irradiated with dark light is determined by the product of the potential of the photoelectric conversion element 111 at the time when the third sub-gate signal is input and the accumulation time (12 × P). It is preferred that This is because the saturated state is not yet reached when the first sub-gate signal is input and when the second sub-gate signal is input.

  The signal of the pixel 100 having the photoelectric conversion element 111 irradiated with bright light is determined by the product of the potential of the photoelectric conversion element 111 and the accumulation time (6 × P) when the second sub-gate signal is input. It is preferable. This is because the saturation state is not reached when the first sub-gate signal is input, and the saturation state is already reached when the third sub-gate signal is input.

  By using the driving method of the present invention, a plurality of signals can be output from a pixel within one frame period, and the plurality of signals have different accumulation times. Therefore, a signal suitable for the light intensity irradiated to the pixel can be selected from the plurality of signals.

  In this embodiment, the source signal line driver circuit 101 shown in FIG. 3 will be described in detail. The source signal line drive circuit 101 includes a bias circuit 101a, a sample hold circuit 101b, a signal output drive circuit 101c, and a final output amplification circuit 101d. Note that the present invention is not limited to this, and the source signal line driver circuit 101 may be provided with an analog / digital signal conversion circuit, a noise reduction circuit, or the like.

  The bias circuit 101a is paired with an amplifying transistor included in each pixel to form a source follower circuit. The sample and hold circuit 101b includes a circuit that temporarily stores a signal, performs analog / digital conversion, and reduces noise. Further, the signal output drive circuit 101c includes a circuit that outputs a signal for sequentially outputting the temporarily stored signals. The final output amplification circuit 101d includes a circuit that amplifies the signal output by the sample hold circuit 101b and the signal output drive circuit 101c. The final output amplifying circuit 101d may not be provided when it is not necessary to amplify the signal.

  FIG. 5 is a circuit diagram of the j-th column peripheral portion 101e of the bias circuit 101a, the sample hold circuit 101b, and the signal output line drive circuit 101c. Note that in this embodiment, all transistors are n-channel transistors, but the present invention is not limited to this, and the transistors may be either n-channel transistors or p-channel transistors.

The bias circuit 101a includes a bias transistor 210a.
The bias transistor 210a has the same polarity as the amplification transistor of each pixel and forms a source follower circuit. A gate electrode of the bias transistor 210 a is connected to the bias signal line 200. One of the source region and the drain region of the bias transistor 210a is connected to the signal output line (Sj), and the other is connected to the power supply reference line 210b. In this embodiment, an n-channel transistor is used as the biasing transistor 210a. However, the present invention is not limited to this. For example, a p-channel transistor can be used as the biasing transistor 210a and the amplifying transistor. In this case, the biasing transistor 210a is connected to the power supply line instead of the power supply reference line.

  The sample hold circuit 101b includes transfer transistors 211, 212, and 213, discharge transistors 214a, 215a, and 216a, and output transistors 217, 218, and 219. The gate electrodes of the transfer transistors 211, 212, and 213 are connected to transfer signal lines 201, 202, and 203, respectively.

One of the source region and the drain region of the transfer transistors 211, 212, and 213 is connected to the signal output line (Sj), and the other is connected to one of the source region and the drain region of the discharge transistors 214a, 215a, and 216a. ing.
When the transfer transistors 211, 212, and 213 are turned on, the potential of the signal output line (Sj) is held in the capacitors 214b, 215b, and 216b.

  In this embodiment, the case where n-channel transistors are used for the transfer transistors 211, 212, and 213 is shown, but the present invention is not limited to this. For example, a p-channel transistor and an n-channel transistor may be connected in parallel, and these transistors may be used as transfer transistors.

  The capacitor 214b is connected to the source region and drain region of the discharging transistor 214a and the power supply reference line 214c. The gate electrode of the discharging transistor 214a is connected to the discharging signal line 204.

  The capacitor 215b is connected to the source region and drain region of the discharging transistor 215a and the power supply reference line 215c. The gate electrode of the discharge transistor 215a is connected to the discharge signal line 205.

  The capacitor 216b is connected to the source region and drain region of the discharging transistor 216a and the power supply reference line 216c. The gate electrode of the discharge transistor 216 a is connected to the discharge signal line 206.

  The capacitors 214b, 215b, and 216b temporarily hold signals output from the signal output line (Sj). Further, when the discharge transistors 214a, 215a, and 216a are turned on, the electric charges of the capacitors 214b, 215b, and 216b are discharged and initialized by the power supply reference lines 214c and 215c.

  In the present embodiment, it is assumed that the capacitor 214b temporarily holds a signal output from the pixel 100 to which the first sub-gate signal is input among the plurality of pixels 100 provided in the j-th column. The capacitor 215b temporarily holds the signal output from the pixel 100 to which the second sub-gate signal is input, and the capacitor 216b temporarily stores the signal output from the pixel 100 to which the third sub-gate signal is input. It is assumed that

  Reference numerals 217, 218, and 219 denote output transistors. One of the source region and the drain region of the output transistor 217 is connected to the capacitor 214b, and the other is connected to one of the source region and the drain region of the final output transistor 220. The gate electrode of the output transistor 217 is connected to the output signal line 207.

  One of the source region and the drain region of the output transistor 218 is connected to the capacitor 215 b, and the other is connected to one of the source region and the drain region of the final output transistor 220. The gate electrode of the output transistor 218 is connected to the output signal line 208.

  One of the source region and the drain region of the output transistor 219 is connected to the capacitor 216b, and the other is connected to one of the source region and the drain region of the final output transistor 220. The gate electrode of the output transistor 219 is connected to the output signal line 209.

  The other of the source region and the drain region of the final output transistor 220 is connected to the final output line 222. The gate electrode of the final output transistor 220 is connected to the final selection line (SSj).

  221a is a final reset transistor, and 221b is a power supply reference line. One of the source region and the drain region of the final reset transistor 221 a is connected to the power supply reference line 221 b and the other is connected to the final output line 222. The gate electrode of the final reset transistor 221a is connected to the final reset line SRj. When the final reset transistor 221a is turned on, the potential of the final output line 222 is initialized to the potential of the power supply reference line 221b.

  Next, a timing chart of the source signal line driver circuit 101 illustrated in FIG. 5 is described with reference to FIG. In FIG. 6, a period from when the reset signal is applied to the reset signal lines (R1 to Ry) to when the reset signal is applied again is defined as one frame period (F). A period from when a signal is applied to the reset signal lines (R1 to Ry) to when a signal is applied to the reset signal lines (R1 to Ry) in the next column is defined as a horizontal scanning period (P). The horizontal scanning period (P) is divided into three parts: a first sub horizontal scanning period, a second sub horizontal scanning period, and a third sub horizontal scanning period.

  In the first sub horizontal scanning period, the transfer signal line 201 is selected, and the transfer transistor 211 connected to the transfer signal line 201 is turned on. Then, the signal output from the pixel 100 to which the first sub-gate signal is input is temporarily held in the capacitor 214b. Similarly, the output signal line 209 is selected, and the output transistor 219 connected to the output signal line 209 is turned on. Then, the signal held in the capacitor 216b is output to the final output line 222.

Next, in the second sub-horizontal scanning period, the transfer signal line 202 is selected, and the transfer transistor 212 connected to the transfer signal line 202 is turned on.
Then, the signal output from the pixel 100 to which the second sub-gate signal is input is temporarily held in the capacitor 215b. Similarly, the output signal line 207 is selected, and the output transistor 217 connected to the output signal line 207 is turned on. Then, the signal held in the capacitor 214 b is output to the final output line 222.

Next, in the third sub horizontal scanning period, the transfer signal line 203 is selected, and the transfer transistor 213 connected to the transfer signal line 203 is turned on.
Then, the signal output from the pixel 100 to which the third sub-gate signal is input is temporarily held in the capacitor 216b. Similarly, the output signal line 208 is selected, and the output transistor 218 connected to the output signal line 208 is turned on. Then, the signal held in the capacitor 215b is output to the final output line 222.

  In each sub horizontal scanning period, the final reset lines (SR1 to SRx) and the final output lines (SS1 to SSx) are alternately selected. In the present embodiment, the signal held in the capacitor 216b is output to the final output line 222 in the first sub-horizontal scanning period, and the signal held in the capacitor 214b is final in the second sub-horizontal scanning period. The signal output to the output line 222 is output to the final output line 222 in the third sub-horizontal scanning period and held in the capacitor 216b.

  Here, a timing chart of signals applied to the final reset lines (SR1 to SRx) and the final output lines (SS1 to SSx) in the sub horizontal scanning period will be described. In this embodiment, the second sub-horizontal scanning period will be described as an example.

In the second sub horizontal scanning period, the transfer signal line 202 and the output signal line 207 are selected. Then, the final reset line (SR1) in the first column is selected. Then, the final reset transistor 221a is turned on, and the final output line 222 is initialized to a certain potential value. And the last selection line (SS1) in the first column
Is selected, and the final selection transistor 220 is turned on. Then, the signal temporarily held in the capacitor 214b in the first column is output to the final output line 222.

  Next, when the final reset line (SR2) in the second column is selected, the final reset transistor 221a is turned on, and the final output line 222 is initialized to a certain potential value. When the final selection line (SS2) in the second column is selected, the final selection transistor 220 is turned on. Then, the signal temporarily held in the capacitor 214b in the second row is output to the final output line 222.

  The signal output to the final output line 222 is amplified by the final output amplification circuit 101d and output to the outside.

  In this way, all final reset lines (SR1 to SRx) and final output lines (SS1 to SSx) are alternately selected in order. Then, the signals held in the capacitors 214a of all the columns are output to the final output line 222.

  Next, the discharge signal line 204 is selected. Then, all the discharge transistors 214a connected to the discharge signal line 204 are turned on, and all the capacitors 214b connected to the discharge transistor 214a are initialized to the potential of the power supply reference line 214c.

  In this embodiment, the case where the discharge signal line 204 is selected and the capacitor 214b is initialized immediately after the signal held in the capacitor 214b is read is shown, but the present invention is not limited to this. . The timing for selecting the discharge signal line 204 is not particularly limited.

  When initializing the capacitor 214b, the discharge signal line 204 is selected. When initializing the capacitor 215b, the discharge signal line 205 is selected. When initializing the capacitor 216b, the discharge signal line 204 is selected. The signal line 206 is selected. Then, the discharge transistors 214a, 215a, and 216a connected to the discharge signal lines 204, 205, and 206 are turned on, respectively, and are initialized to the potentials of the power supply reference lines 214c, 215c, and 216c.

  Note that in this embodiment, an example in which the horizontal scanning period (P) is divided into three in the embodiment has been described, and thus an example in which three capacitors are provided in one column has been described. However, the present invention is not limited to this. The number of capacitors provided in one row can be freely determined by the designer. However, when one horizontal scanning period is divided into a plurality of sub horizontal scanning periods, signals for a plurality of rows are output in one horizontal scanning period. For this reason, it is desirable that a plurality of capacitors (the number of sub-horizontal scanning periods) be stored in each column for storing signals.

  This embodiment can be freely combined with Embodiment Modes 1 and 2.

  In this embodiment, an example of a source signal line driver circuit 101 different from that in Embodiment 1 will be described. FIG. 7 shows a circuit diagram of the j-th column peripheral portion 101e of the bias circuit 101a, the sample hold circuit 101b, and the signal output line drive circuit 101c. Note that in this embodiment, all transistors are n-channel transistors, but the present invention is not limited to this, and the transistors may be either n-channel transistors or p-channel transistors.

The bias circuit 101a includes a bias transistor 310a.
The bias transistor 310a has the same polarity as the amplification transistor of each pixel, and forms a source follower circuit. A gate electrode of the biasing transistor 310 a is connected to the bias signal line 300. One of the source region and the drain region of the biasing transistor 310a is connected to the signal output line (Sj), and the other is connected to the power supply reference line 310b.

  In this embodiment, an n-channel transistor is used as the biasing transistor 310a. However, the present invention is not limited to this. For example, a p-channel transistor can be used as the biasing transistor 310a and the amplifying transistor. In this case, the biasing transistor 310a is connected to the power supply line instead of the power supply reference line.

  The sample hold circuit 101b includes transfer transistors 311, 312, and 313, discharge transistors 314a, 315a, and 316a, final selection transistors 317, 318, and 319, and final reset transistors 321a, 322a, and 323a.

  The gate electrodes of the transfer transistors 311, 312, and 313 are connected to transfer signal lines 301, 302, and 303, respectively.

  One of the source and drain regions of the transfer transistors 311, 312, and 313 is connected to the signal output line (Sj), and the other is connected to the source regions of the capacitors 314 b, 315 b, 316 b and the discharge transistors 314 a, 315 a, 316 a Connected to one of the drain regions. When the transfer transistors 311, 312, and 313 are turned on, the potential of the signal output line (Sj) is transferred to the capacitors 314b, 315b, and 316b.

  In this embodiment, the case where n-channel transistors are used for the transfer transistors 311, 312, and 313 has been described, but the present invention is not limited to this. For example, a p-channel transistor and an n-channel transistor may be connected in parallel, and these transistors may be used as transfer transistors.

  The capacitor 314b is connected to the source and drain regions of the discharging transistor 314a and the power supply reference line 314c. The gate electrode of the discharge transistor 314a is connected to the discharge signal line 305.

  The capacitor 315b is connected to the source region and drain region of the discharging transistor 315a and the power supply reference line 315c. The gate electrode of the discharge transistor 315a is connected to the discharge signal line 305.

  The capacitor 316b is connected to the source and drain regions of the discharging transistor 316a and the power supply reference line 316c. The gate electrode of the discharge transistor 316a is connected to the discharge signal line 305.

  The capacitors 314b, 315b, and 316b temporarily hold the signal output from the signal output line (Sj). In addition, the discharging transistors 314a, 315a, and 316a discharge the charges of the capacitors 314b, 315b, and 316b, and initialize them to the potentials of the power supply reference lines 314c, 315c, and 316c.

  In this embodiment, it is assumed that the signal output from the pixel 100 to which the first sub-gate signal is input is temporarily held in the capacitor 314b. The capacitor 315b temporarily holds a signal output from the pixel 100 to which the second sub-gate signal is input, and the capacitor 316b temporarily receives the signal output from the pixel 100 to which the third sub-gate signal is input. It is assumed that

  Reference numerals 317, 318, and 319 denote final selection transistors. The gate electrodes of the final selection transistors 317, 318, and 319 are connected to the final selection line (SSj).

  One of the source region and the drain region of the final selection transistor 317 is connected to the capacitor 314 b, and the other is connected to the final output line 307. One of the source region and the drain region of the final selection transistor 318 is connected to the capacitor 315 b and the other is connected to the final output line 308. One of the source region and the drain region of the final selection transistor 319 is connected to the capacitor 316 b and the other is connected to the final output line 309.

  Reference numerals 321a, 322a, and 323a denote final reset transistors, and reference numerals 321b, 322b, and 323b denote power supply reference lines. The gate electrodes of the final reset transistors 321a, 322a, and 323a are connected to the final reset line (SRj). One of the source region and the drain region of the final reset transistor 321 a is connected to the power supply reference line 321 b and the other is connected to the final output line 307.

  One of the source region and the drain region of the final reset transistor 322 a is connected to the power supply reference line 322 b, and the other is connected to the final output line 308. One of the source region and the drain region of the final reset transistor 323a is connected to the power supply reference line 323b, and the other is connected to the final output line 309.

  The final reset lines (SR1 to SRx) are provided for initializing the final output lines 307, 308, and 309. When any one of the final reset lines (SR1 to SRx) is selected and the final reset transistor 221a is turned on, the potentials of the final output lines 307, 308, and 309 are the power supply reference lines 321b, 322b, and 323b, respectively. It is initialized to the potential.

  Next, a timing chart of the source signal line driver circuit 101 illustrated in FIG. 7 is described with reference to FIG. In FIG. 7, a period from when the reset signal is applied to the reset signal lines (R1 to Ry) until the reset signal is applied again is defined as one frame period (F). A period from when a signal is applied to the reset signal lines (R1 to Ry) to when a signal is applied to the reset signal lines (R1 to Ry) in the next column is defined as a horizontal scanning period (P).

  In the driving method of the source signal line driving circuit of this embodiment, the horizontal scanning period (P) is divided into a sampling period and a shift register operation period. The sampling period is divided into three parts: a first sub-sampling period, a second sub-sampling period, and a third sub-sampling period.

  In the first sub-sampling period, the transfer signal line 301 is selected. When the transfer signal line 301 is selected, the transfer transistor 311 connected to the transfer signal line 301 is turned on. Then, the signal output from the pixel 100 to which the first sub-gate signal is input is temporarily held in the capacitor 314b.

  Next, in the second sub-sampling period, the transfer signal line 302 is selected, and the transfer transistor 312 connected to the transfer signal line 302 is turned on. Then, the signal output from the pixel 100 to which the second sub-gate signal is input is temporarily held in the capacitor 315b.

  Next, in the third sub-sampling period, the transfer signal line 303 is selected, and the transfer transistor 313 connected to the transfer signal line 303 is turned on. Then, the signal output from the pixel 100 to which the third sub-gate signal is input is temporarily held in the capacitor 216b. This completes the sampling period.

  Next, in the shift register operation period, signals held in the capacitors 314b, 315b, and 316b are output to the final output lines 307, 308, and 309, respectively.

  First, the last reset line (SR1) in the first column is selected. When the final reset line (SR1) is selected, the final reset transistors 321a, 322a, and 323a connected to the final reset line (SR1) in the first column are turned on, and the final output lines 307, 308, and 309 are based on the power supply reference. It is initialized to the potential of the lines 321b, 322b and 323b.

  Next, the last selection line (SS1) in the first column is selected. When the final selection line (SS1) is selected, the final selection transistors 317, 318, and 319 connected to the final selection line (SS1) in the first column are turned on. Then, the signals temporarily held in the capacitors 314b, 315b, and 316b in the first column are output to the final output lines 307, 308, and 309.

  Next, the final reset line (SR2) in the second column is selected. When the final reset line (SR2) is selected, the final reset transistors 321a, 322a, and 323a connected to the final reset line (SR2) in the second column are turned on, and the final output lines 307, 308, and 309 are based on the power supply reference. It is initialized to the potential of the lines 321b, 322b and 323b.

  Next, the final selection line (SS2) in the second column is selected. When the final selection line (SS2) is selected, the final selection transistors 317, 318, and 319 connected to the final selection line (SS2) in the second column are turned on. Then, the signals temporarily held in the capacitors 314b, 315b, and 316b in the second column are output to the final output lines 307, 308, and 309.

  In this way, all final reset lines (SR1 to SRx) and final output lines (SS1 to SSx) are alternately selected in order. Then, the signals held in the capacitors 314b, 315b, and 316b of all the columns are output to the final output lines 307, 308, and 309.

  Finally, the discharge signal line 305 is selected, all the discharge transistors 314a, 315a, and 316a connected to the discharge signal line 305 are turned on and connected to the discharge transistors 314a, 315a, and 316a. All columns of capacitors 314b, 315b, 316b are initialized to the potential of the power supply reference lines 314c, 315c, 316c.

  The signals output to the final output lines 307, 308, and 309 are amplified by the final output amplification circuit 101d and output to the outside.

In this embodiment, since the horizontal scanning period is divided into three in the above-described embodiment, three capacitors (314b, 315b, 316b) are arranged in one column.
However, the present invention is not limited to this. The number of capacitors provided in one row can be freely determined by the designer. However, when one horizontal scanning period is divided into a plurality of sub horizontal scanning periods, signals for a plurality of columns are output in one horizontal scanning period. For this reason, it is desirable that a plurality of capacitors (the number of sub-horizontal scanning periods) be stored in each column for storing signals.

  This embodiment can be freely combined with Embodiment Modes 1 and 2 and Embodiment 1.

  In this embodiment, an example of the source signal line driver circuit 101 different from the first and second embodiments will be described with reference to FIGS.

  FIG. 9 shows a circuit diagram of the j-th column peripheral portion 101e of the bias circuit 101a, the sample hold circuit 101b, and the signal output line driving circuit 101c. Note that in this embodiment, all transistors are n-channel transistors, but the present invention is not limited to this, and the transistors may be either n-channel transistors or p-channel transistors.

  The bias circuit 101a includes a bias transistor 5510a. The bias transistor 5510a has the same polarity as the amplification transistor 113 of each pixel and forms a source follower circuit. A gate electrode of the bias transistor 5510 a is connected to the bias signal line 5511. One of the source region and the drain region of the bias transistor 5510a is connected to the signal output line (Sj), and the other is connected to the power supply reference line 5510b.

  Note that although the case where an n-channel transistor is used for the biasing transistor 5510a is described in this embodiment, the present invention is not limited to this. For example, a p-channel transistor can be used as the biasing transistor 5510a. In that case, the biasing transistor 5510a is connected to the power supply line instead of the power supply reference line.

  A gate electrode of the transfer transistor 5512 is connected to the transfer signal line 5513. One of the source region and the drain region of the transfer transistor 5512 is connected to the signal output line (Sj), and the other is connected to one of the source region or the drain region of the capacitor selection transistors 5514d, 5530d, and 5531d. When the transfer transistor 5512 is turned on, the potential of the signal output line (Sj) is held in the capacitors 5514b, 5530b, and 5531b via the capacitance selection transistors 5514d, 5530d, and 5531d.

  Note that although the case where an n-channel transistor is used as the transfer transistor 5512 is described in this embodiment, the present invention is not limited to this. For example, a p-channel transistor and an n-channel transistor may be connected in parallel, and these transistors may be used as transfer transistors.

  The capacitor 5514b is connected to one of the source region and the drain region of the capacitor selection transistor 5514d and the power supply reference line 5514c. The gate electrode of the capacitor selection transistor 5514d is connected to the storage capacitor control line 5534. The other of the source region and the drain region of the capacitor selection transistor 5514d is connected to the signal output line (Sj).

  The gate electrode of the discharging transistor 5514a is connected to the discharging signal line 5515. One of the source region and the drain region of the discharging transistor 5514a is connected to the capacitor 5514b, and the other is connected to the power supply reference line 5514c. When the discharging transistor 5514a is turned on, the capacitor 5514b is initialized to the potential of the power supply reference line 5514c. The capacitor 5514b temporarily accumulates the signal output from the signal output line (Sj). In this embodiment, it is assumed that the signal of the pixel 100 to which the first sub-gate signal is input among the plurality of pixels 100 provided in the j-th column is temporarily held.

  The capacitor 5530b is connected to one of the source region and the drain region of the capacitor selection transistor 5530d and the power supply reference line 5530c. The gate electrode of the capacitor selection transistor 5530d is connected to the storage capacitor control line 5535. The other of the source region and the drain region of the capacitor selection transistor 5530d is connected to the signal output line (Sj).

  The gate electrode of the discharge transistor 5530a is connected to the discharge signal line 5532. One of the source region and the drain region of the discharging transistor 5530a is connected to the capacitor 5530b, and the other is connected to the power supply reference line 5530c. When the discharging transistor 5530a is turned on, the capacitor 5530b is initialized to the potential of the power supply reference line 5530c. The capacitor 5530b temporarily holds the signal output from the signal output line (Sj). In this embodiment, it is assumed that the signal of the pixel 100 to which the second sub-gate signal is input is temporarily held among the plurality of pixels 100 provided in the j-th column.

  The capacitor 5531b is connected to one of the source region and the drain region of the capacitor selection transistor 5531d and the power supply reference line 5531c. The gate electrode of the capacitor selection transistor 5531d is connected to the storage capacitor control line 5536. The other of the source region and the drain region of the capacitor selection transistor 5531d is connected to the signal output line (Sj).

  The gate electrode of the discharge transistor 5531a is connected to the discharge signal line 5533. One of the source region and the drain region of the discharging transistor 5531a is connected to the capacitor 5531b, and the other is connected to the power supply reference line 5531c. When the discharging transistor 5531a is turned on, the capacitor 5531b is initialized to the potential of the power supply reference line 5531c. The capacitor 5531b temporarily holds the signal output from the signal output line (Sj). In this embodiment, it is assumed that the signal of the pixel 100 to which the third sub-gate signal is input among the plurality of pixels 100 provided in the j-th column is temporarily held.

  One of the source region and the drain region of the final selection transistor 5516 is connected to one of the source region and the drain region of the capacitance selection transistors 5514d, 5530d, and 5531d. The other of the source region and the drain region of the final selection transistor 5516 is connected to the final output line 5518. The gate electrode of the final selection transistor 5516 is connected to the j-th column final selection line SSj.

  The final selection lines (SS1 to SSx) and the final reset lines (SR1 to SRx) are provided in a matrix in the sample hold circuit 101b, and are alternately selected from the first column to the xth column. For example, the final selection line SSj is selected, and the final selection transistor 5516 is turned on. Then, any one of the storage capacitor control lines 5534, 5535, and 5536 is selected, and any one of the capacitor selection transistors 5514d, 5530d, and 5531d is turned on. Then, the signals held in the capacitors 5514b, 5530b, and 5531b connected to the capacitance selection transistors 5514d, 5530d, and 5531d that are turned on are output to the final output line 5518.

  Note that charges may be accumulated in the final output line 5518 before a signal is output to the final output line 5518. Then, the potential when a signal is output to the final output line 5518 is affected by the charge. Therefore, before outputting a signal to the final output line 5518, it is necessary to initialize the potential of the final output line 5518 to a certain potential value. Therefore, before selecting the final selection line SSj, the final reset line SRj is selected, and the final reset transistor 5517a is turned on. Then, the potential of the final output line 5518 is initialized to the potential of the power supply reference line 5517b.

In this embodiment, since the horizontal scanning period is divided into three in the above-described embodiment, three capacitors (314b, 315b, 316b) are arranged in one column.
However, the present invention is not limited to this. The number of capacitors provided in one row can be freely determined by the designer. However, when one horizontal scanning period is divided into a plurality of sub horizontal scanning periods, signals for a plurality of columns are output in one horizontal scanning period. For this reason, it is desirable that a plurality of capacitors (the number of sub-horizontal scanning periods) be stored in each column for storing signals.

  Next, a timing chart of the j-th column peripheral circuit shown in FIG. 9 is shown in FIG. In this embodiment, a timing chart when the gate signal line (Gi) in the j-th column is selected will be described as an example.

  In this embodiment, a timing chart of signals in the sub horizontal scanning period shown in Embodiment 1 is shown. FIG. 9 shows a case where a signal temporarily accumulated in the capacitor 5514b is output to the final output line 5518.

  First, the i-th gate signal line (Gi) is selected, and then the discharge signal line 5515 is selected. Then, the discharging transistor 5514a is turned on. Note that the storage capacitor control line 5534 is selected in the same manner as the gate signal line (Gi) in the sub-horizontal scanning period in which the gate signal line (Gi) is selected.

  When the transfer signal line 5513 is selected and the transfer transistor 5512 is turned on, a signal output from the photoelectric conversion element of each pixel is output to the capacitor 5514b in each row.

  Then, the signals accumulated in the capacitors 5514b in each row are sequentially output to the final output line 5518. First, when the final reset line 5519 in the first row is selected, the final reset transistor 5517a is turned on. Then, the final output line 5518 is initialized to the potential of the power supply reference line 5517b, and the final selection line 5519 in the first row is selected. Then, the final selection transistor 5516 is turned on, and the signal of the capacitor 5514b in the first row is output to the final output line 5518.

  Next, the final reset line 5519 in the second row is selected, the final reset transistor 5517a is turned on, and the final output line 5518 is initialized to the potential of the power supply reference line 5517b. Then, the final selection line 5519 in the second row is selected, the final selection transistor 5516 is turned on, and the signal of the capacitor 5514b in the second row is output to the final output line 5518.

  In this way, the final reset line 5519 from the first row to the x-th row is selected in order, and the same operation is repeated. Then, the signals of all the rows are output to the final output line 5518. The signal output to the final output line 5518 is amplified by the final output amplification circuit 101d and output to the outside.

  This embodiment can be freely combined with the embodiment mode, Embodiments 1 and 2, and Embodiments 1 and 2.

  In this embodiment, the final output amplification circuit 101d shown in FIG. 3 is shown in FIGS. Note that the signal output to the final output line may be taken out as it is. However, if the output signal is weak, it is preferable to amplify it before taking it out. In this embodiment, a source follower circuit is shown as the simplest signal amplifier circuit, but the present invention is not limited to this. For example, a known amplifier circuit such as an operational amplifier may be used as the final output amplifier circuit 101d.

  FIG. 11A illustrates a final amplifier circuit 101d having an n-channel source follower circuit. A signal is input to the final output amplification circuit 101d through a final selection transistor 5516. The final selection line (SSj) connected to the gate electrode of the final selection transistor 5516 is provided in a matrix in the pixel portion 104, and is sequentially selected from the first column to the xth column.

  The signal output from the final output line 5518 is amplified by the final output amplification circuit 101d and output to the outside. The final output line 5518 is connected to the gate electrode of the amplifying transistor 5521. The drain region of the amplifying transistor 5521 is connected to the power supply line 5520, and the source region is an output terminal.

  On the other hand, the gate electrode of the bias transistor 5522 is connected to the final output amplification bias signal line 5523. One of a source region and a drain region of the bias transistor 5522 is connected to the power supply reference line 5524, and the other is connected to a source region of the amplification transistor 5521.

  Next, FIG. 11B illustrates a final amplifier circuit 101d having a p-channel source follower circuit. The final output line 5518 is connected to the gate electrode of the amplifying transistor 5521. The drain region of the amplifying transistor 5521 is connected to the power supply reference line 5520, and the source region serves as an output terminal.

  On the other hand, the gate electrode of the bias transistor 5522 is connected to the final output amplification bias signal line 5523. One of a source region and a drain region of the bias transistor 5522 is connected to the power supply line 5520, and the other is connected to a source region of the amplification transistor 5521. Note that the potential of the final output amplification bias signal line 5523 shown in FIG. 11B having a p-channel source follower circuit is the final output amplification shown in FIG. 11A having an n-channel source follower circuit. This is different from the potential of the bias signal line 523 for use.

  This embodiment can be freely combined with Embodiment Modes 1 and 2 and Embodiments 1 to 3.

  In this embodiment, a cross-sectional structure of a semiconductor device in which a photoelectric conversion element of the present invention and a plurality of transistors are provided in one pixel will be described with reference to FIGS.

  In FIG. 12, 6000 is a substrate having an insulating surface, and 6001 is a base film. On the base film 6001, a photoelectric conversion element 111, an amplification transistor 113, a switching transistor 112, and a reset transistor 114 are formed. In addition, an n-channel transistor and a p-channel transistor are illustrated as driver circuits. Each transistor may have any known structure.

  A structure of each transistor formed over the substrate 6000 having an insulating surface is described. In the amplifying transistor 113, reference numeral 6023 denotes a gate electrode, 6008 denotes a gate insulating film, 6037 denotes a source region and a drain region made of a p-type impurity region, 6042 denotes a source wiring, and 6043 denotes a drain wiring.

  In the switching transistor 112, reference numeral 6024 denotes a gate electrode, 6008 denotes a gate insulating film, 6038 denotes a source region and a drain region made of a p-type impurity region, 6044 denotes a source wiring, and 6045 denotes a drain wiring.

  In the reset transistor 114, reference numeral 6025 denotes a gate electrode, 6008 denotes a gate insulating film, 6019 denotes a source region and a drain region made of n-type impurity regions, 6030 denotes an LDD region (lightly doped drain region), 6046 denotes a source wiring, and 6047 denotes This is a drain wiring.

  In the photoelectric conversion element 111, 6036 is a p-type semiconductor layer made of a p-type impurity region, 6020b is an n-type semiconductor layer made of an n-type impurity region, and 6054 is a photoelectric conversion layer (i layer) made of an amorphous semiconductor film. It is.

  In the n-channel transistor in the driver circuit portion, 6026 is a gate electrode, 6008 is a gate insulating film, 6021 is a source region and a drain region made of an n-type impurity region, 6031 is an LDD region (lightly doped drain region), and 6050 is a source. A wiring 6051 is a drain wiring.

  In the p-channel transistor of the driver circuit portion, reference numeral 6027 denotes a gate electrode, 6008 denotes a gate insulating film, 6039 denotes a source region and a drain region made of a p-type impurity region, 6052 denotes a drain wiring, and 6053 denotes a source wiring.

  A first interlayer insulating film 6041 and a second interlayer insulating film 6059 are provided so as to cover the amplifying transistor 113, the switching transistor 112, the resetting transistor 114, the n-channel transistor, and the p-channel transistor.

  Note that this embodiment can be freely combined with Embodiment Modes 1 and 2 and Embodiments 1 to 4.

  In Embodiment 4, the cross-sectional structure of the semiconductor device of the present invention has been described. In this embodiment, a state in which the semiconductor device of the present invention is sealed and an FPC is attached will be described.

  FIG. 13A is a top view of a semiconductor device using the present invention, and FIG. 13B is a cross-sectional view taken along the line XX ′ of FIG. 13A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source signal line driver circuit, and 4004 denotes a gate signal line driver circuit. Each driver circuit reaches an FPC 4008 through wirings 4005, 4006, and 4007. Connected to an external device.

  At this time, a cover member 4009, a sealing member 4010, and a sealing member (also referred to as a housing member) 4011 (illustrated in FIG. 13B) are provided so as to surround at least the pixel portion, preferably the driver circuit and the pixel portion.

  FIG. 13B shows a cross-sectional structure of the semiconductor device of this embodiment. A driver circuit portion (here, a CMOS in which an n-channel TFT and a p-channel TFT are combined) is formed over a substrate 4001 and a base film 4012. 4013 and a pixel portion 4014 (however, only a photoelectric conversion element and a switching transistor are illustrated for the sake of simplicity) are formed.

  When the driver circuit portion 4013 and the pixel portion 4014 are completed using a known manufacturing method, a first interlayer insulating film (planarization film) 4015 made of a resin material is formed.

  Next, a second interlayer insulating film 4017 made of a resin material is formed, and a passivation film 4022, a filler 4023, and a cover material 4009 are formed so as to cover the second interlayer insulating film 4017.

Further, a sealing material 4011 is provided inside the cover material 4009 and the substrate 4001, and a sealing material (second sealing material) 4010 is formed outside the sealing material 4011.

At this time, the filler 4023 also functions as an adhesive for bonding the cover material 4009. As filler 4023, PVC (polyvinyl chloride)
Epoxy resin, silicon resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 4023 because a moisture absorption effect can be maintained.

  Further, a spacer may be contained in the filler 4023. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic. In the case where a spacer is provided, the passivation film 4022 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.

  As the cover member 4009, a glass plate, an aluminum plate, a stainless steel plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 4023, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

  The wiring 4007 is connected to a transistor included in the driver circuit 4013 and is electrically connected to the FPC 4008 through a gap between the sealing material 4011 and the sealing material 4010 and the substrate 4001. Note that although the wiring 4007 is described here, the other wirings 4005 and 4006 are also electrically connected to the FPC 4008 under the sealing material 4011 and the sealing material 4010 in the same manner.

In this embodiment, the cover material 4009 is bonded after the filler 4023 is provided, and the sealing material 4011 is attached so as to cover the side surface (exposed surface) of the filler 4023. However, the cover material 4009 and the sealing material 4011 are attached. After the attachment, the filler 4023 may be provided. In this case, a filler inlet that leads to a gap formed by the substrate 4001, the cover member 4009, and the sealing member 4011 is provided. Then, the void is evacuated (10 ^-2 Torr or less), the inlet is immersed in a water tank containing the filler, and the pressure outside the void is made higher than the pressure inside the void, Fill in the void.

  Note that this embodiment can be freely combined with Embodiment Modes 1 and 2 and Embodiments 1 to 5.

  An example of an electronic device using the semiconductor device of the present invention will be described with reference to FIG.

  FIG. 14A illustrates a hand scanner using a line sensor. An optical system 1002 such as a rod lens array is provided on a CCD type (CMOS type) image sensor 1001. The optical system 1002 is used so that an image on the subject 1004 is displayed on the image sensor 1001. A light source 1003 such as an LED or a fluorescent lamp is provided at a position where light can be emitted to the subject 1004. A glass 1005 is provided below the subject 1004.

  Light emitted from the light source 1003 enters the subject 1004 through the glass 1005. Light reflected by the subject 1004 enters the optical system 1002 through the glass 1005. The light that has entered the optical system 1002 enters the image sensor 1001, where it is photoelectrically converted. The semiconductor device of the present invention can be used for the image sensor 1001.

  In FIG. 14B, reference numeral 1801 denotes a substrate, 1802 denotes a pixel portion, 1803 denotes a touch panel, and 1804 denotes a touch pen. The touch panel 1803 has a light-transmitting property, can transmit light emitted from the pixel portion 1802 and light incident on the pixel portion 1802, and can read an image on a subject through the touch panel 1803. Even when an image is displayed on the pixel portion 1802, the image on the pixel portion 1802 can be viewed through the touch panel 1803.

  When the touch pen 1804 touches the touch panel 1803, information on a position where the touch pen 1804 and the touch panel 1803 are in contact with each other can be taken into the semiconductor device as an electric signal. In the touch panel 1803 and the touch pen 1804 used in this embodiment, information on the position of the portion where the touch pen 1803 is translucent and the touch pen 1804 and the touch panel 1803 are in contact is taken into the semiconductor device as an electrical signal. Any known one can be used. Note that the semiconductor device of the present invention can be used for the pixel portion 1802.

  FIG. 14C is a portable hand scanner different from that in FIG. 14B, and includes a main body 1901, a pixel portion 1902, an upper cover 1903, an external connection port 1904, and an operation switch 1905. FIG. 14D is a view in which the upper cover 1903 of the same portable hand scanner as FIG. 14C is closed.

  An image signal read by the pixel portion 1902 can be sent from an external connection port 1904 to an electronic device connected to the outside of the portable hand scanner, and the image can be corrected, combined, edited, and the like on a personal computer. Note that the semiconductor device of the present invention can be used for the pixel portion 1802.

  Further, examples of the electronic device using the semiconductor device of the present invention include a video camera, a digital still camera, a notebook personal computer, a portable information terminal (a mobile computer, a mobile phone, a portable game machine, an electronic book, or the like).

  FIG. 14E shows a digital video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. Including. The semiconductor device of the present invention can be used for the display portion 2602.

  FIG. 14F illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. It can be used for the semiconductor device 2302 of the present invention.

  FIG. 14G illustrates a cellular phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The semiconductor device of the present invention can be used for the display portion 2703.

As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

Claims (1)

A first transistor, a second transistor, n (n is an integer of 2 or more) capacitors, and a photoelectric conversion element,
The photoelectric conversion element has a function of supplying a charge to the gate of the first transistor,
The second transistor has a function of supplying a reset potential to a gate of the first transistor;
In one frame period, the first transistor has a function of outputting the n signals to a signal output line,
Each of the n signals is held in the n capacitors.
The n capacitors are provided in a sample and hold circuit, and discharge is controlled by a common wiring.
The common wiring is electrically connected to the gates of n transistors provided in the sample and hold circuit,
A corresponding one of the n capacitors is electrically connected between the source and drain of each of the n transistors.
A period during which the reset potential is supplied is longer than a period during which any one of the n signals is output.

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