JP2011107951A - Inverter device and controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter device allowing prevention of erroneous operation of another inverter device during operation even in time of power shutoff of the prescribed inverter device. <P>SOLUTION: In this inverter device 22a, a diode D3 is reversely connected between an input node Na2 of a digital input circuit 23 and input nodes Na4, etc. of digital input circuits 24-26. Accordingly, current flowing from the input node Na2 to the input nodes Na4, etc. can be shut off. Thereby, an unnecessary outflow of current from input terminals LI2-LI4 of the inverter device 22a after the power shutoff to an input terminal of the other inverter device during the operation can be prevented. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inverter device and a control device including an interface circuit capable of inputting a digital signal from a contact or a logic circuit in a source input format and a sink input format.

  The inverter device includes a large number of input terminals when configured to receive various operation commands from the outside. Among these many input terminals, the digital input terminal is a terminal for inputting a digital signal from an external circuit such as a contact or logic circuit connected to the outside, and a forward / reverse operation command, an operation preparation command, a multistage speed command, Input signals such as DC braking command and reset command.

  There are two types of digital signal input formats: a source input format in which a low potential reference potential is set and a digital signal is input, and a sink input format in which a high potential reference potential is set and a digital signal is input. To do.

  In order to reduce the number of manufacturing models, the inverter device manufacturer has a switching means for switching between the source input format and the sink input format, and manufactures an inverter device configured to be usable in both formats. For example, the inverter device described in Patent Document 1 includes switching means for switching between a connection state for pulling up an input terminal and a connection state for pulling down, and discriminating between a sink input format and a source input format based on the switching state of the switching means. And an interface circuit that outputs the input signal to the microcomputer while being inverted or not inverted according to the determination result. This interface circuit further has a function of switching between the sync output format and the source output format based on the determination result.

  FIG. 7 shows a schematic configuration of an interface circuit provided in a conventional inverter device. As shown in FIG. 7, since the inverter devices 1a to 1c have the same configuration, the block configuration of the inverter device 1a will be described, and the description of the block configuration of the inverter devices 1b and 1c will be omitted. The constituent elements of the inverter device 1a are described with the suffix “a”, and the corresponding components in the other inverter devices 1b and 1c in FIG. 7 are suffixed with the suffixes “b” and “c”, respectively. Is attached.

  The inverter device 1a includes a plurality of digital input circuits 2a and 3a, a switching circuit 4a, a microcomputer (hereinafter abbreviated as a microcomputer) 5a, a first common potential supply circuit 6a, and a second common potential supply circuit 7a connected in the illustrated form. Configured. The first input node Na1 of the digital input circuit 2a is connected to the digital input terminal LI1. The first input node Na3 of the digital input circuit 3a is connected to the digital input terminal LI2. The second input node Na2 of the digital input circuit 2a and the second input node Na4 of the digital input circuit 3a are commonly connected, and the common connection node Na5 is connected to the switching circuit 4a.

  The output nodes Na6 and Na7 of the digital input circuits 2a and 3a are connected to the microcomputer 5a. Although not shown, the microcomputer 5a is configured to be able to drive and control a load such as a motor connected to the outside via an inverter main circuit.

  The switching circuit 4a switches the voltage applied to the common connection node Na5 to the first common potential 6a or the second common potential 7a based on a control signal from the microcomputer 5a. The first common potential supply circuit 6a is a circuit that supplies a reference potential corresponding to the sink input format, and the second common potential supply circuit 7a is a circuit that supplies a reference potential corresponding to the source input format. A plurality of such inverter devices 1a are configured in the same configuration (see reference numerals 1a, 1b, and 1c).

  The input terminals LI1 of the inverter devices 1a to 1c are commonly connected to each other, and the input terminals LI2 are also commonly connected to each other. The common connection node N1 of the input terminal LI1 is connected to one contact of the switch 8w constituting the contact input. The common connection node N2 of the input terminal LI2 is connected to one contact of the switch 8x constituting the contact input. The other contacts of the switches 8w and 8x are commonly connected to each other, and an external common potential supply circuit 9 is connected to the contacts.

  The external common potential supply circuit 9 is a circuit that supplies the same supply potential (Vd) as the supply potential of the first common potential supply circuit 6a, for example, in the case of a circuit that supplies a potential corresponding to the source output format. This circuit supplies a potential higher than the supply potential (0 V) of the common potential supply circuit 7a.

  In this case, considering the state where all the inverter devices 1a to 1c are set in the source input format, the switching circuits 4a to 4c are connected to the common connection nodes Na5 to Nc5, respectively, and the supply potentials of the second common potential supply circuits 7a to 7c. Switching to the side.

JP-A-11-161391

  For example, the user shuts off the power supply of only one inverter device (in this example, the inverter device 1c) for replacement due to a failure of the inverter devices 1a to 1c, maintenance of equipment connected to the inverter devices 1a to 1c, and the like. Sometimes.

  For this reason, the inverter device 1c can be powered off independently of the other inverter devices 1a and 1b, but in this case, for example, the power source of the inverter device 1c is shut off and the switch of the switching circuit 4c is opened (see FIG. 7) and the current flowing from the external common potential supply circuit 9 is the common connection node N1 → node Nc1 → first digital input circuit 2c → node Nc2 → node Nc4 → second digital input circuit 3c → node Nc3 → common connection Through the path of the node N2, it flows into the second digital input circuits 3a, 3b through the input terminals LI2 of the inverter devices 1a, 1b (see arrows in FIG. 7).

  When current flows into the second digital input circuits 3a and 3b, the second digital input circuits 3a and 3b input digital signals from the external common potential supply circuit 9 even though the switch 8x is turned off. There is a risk of misrecognizing it. Therefore, when the power supply of the predetermined inverter device 1c is cut off, the other inverter devices 1a to 1b may malfunction.

  In particular, there is a user's desire to configure a large number of inverter devices 1a to 1c connected in parallel from outside. When the number of parallel connections of the inverter devices 1a to 1c increases, the input impedance is likely to be lowered, so that there is a situation in which the malfunction during the operation is likely to occur.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inverter having an interface circuit that can prevent malfunction of another inverter device that is operating even when the power supply of the predetermined inverter device is cut off. A device and a control device may be provided.

  One aspect of the interface circuit of the present invention is an inverter device configured on the signal input side and configured such that the power source can be cut off independently of other inverter devices and can be connected in parallel to the other inverter devices. Digital input nodes for inputting both source input type and sink input type digital signals from external circuits such as contacts and logic circuits, respectively, and inputting the digital signals given to the respective digital input nodes as a reference A plurality of digital input circuits that operate based on the potential of the potential node; a first common potential setting node that is set to a common common potential as a reference potential of a digital signal in a source input format of the plurality of digital input circuits; The digital signal of the sink input format of the plurality of digital input circuits A second common potential setting node set as a common potential as a quasi-potential, and a reference potential node of the digital input circuit, the first common potential setting node, and the second common potential setting node. And a conduction circuit breaker for preventing inflow of current from the reference potential node of the other digital input circuit at a reference potential node of one of the digital input circuits.

  According to such a configuration, the energizing circuit breaker prevents a current from flowing from the reference potential node of another digital input circuit to the reference potential node of one digital input circuit. However, no current flows from one digital input circuit to the reference potential node of another digital input circuit. Therefore, current does not flow from the reference potential node of the other digital input circuit to the input side of the other inverter device through the path through the digital input node. Even if the interface circuit is connected in parallel with another interface circuit, the adverse effect at the time of power-off does not reach other inverter devices in operation. Thereby, malfunction of the other inverter apparatus in operation can be prevented.

  The energizing circuit breaker may include a diode connected in a reverse direction from a reference potential node of another digital input circuit to a reference potential node of one digital input circuit. The energization breaker may be configured to switch the energization connection between the reference potential node and the first and second common nodes and to open the connection between the reference potential node and the first and second common nodes. (Claim 3).

  According to the present invention, it is possible to prevent malfunction of other inverter devices that are operating even when the power supply of a predetermined inverter device is shut off.

1 is an electrical configuration diagram schematically showing a first embodiment of the present invention. Block Diagram Block diagram schematically showing the overall configuration of the control device FIG. 1 equivalent view showing a second embodiment of the present invention 2 equivalent diagram FIG. 1 equivalent view showing a third embodiment of the present invention 1 equivalent diagram showing the conventional configuration

(First embodiment)
A first embodiment in which the present invention is applied to a control device for an inverter device will be described below with reference to FIGS.

FIG. 3 schematically shows the entire control device and shows the connection relationship between the controller and the inverter device.
As shown in FIG. 3, the control device 20 includes a controller 21 and four (plural) inverter devices 22 a to 22 d connected in parallel to the output of the controller 21. The controller 21 is provided with a plurality of output terminals 211 to 214, and the inverter devices 22a to 22d are each provided with four (plural) digital input terminals LI1 to LI4 (hereinafter abbreviated as input terminals).

  The plurality of output terminals 211 to 214 are respectively connected to the plurality of input terminals LI1 to LI4 of the inverter device 22a, and these connection nodes are also connected to the plurality of input terminals LI1 to LI4 of the other inverter devices 22b to 22d, respectively. Has been.

  The controller 21 is configured to be able to output a digital signal in a source output format from the output terminals 211 to 214, and the inverter devices 22a to 22d input a multi-bit digital signal from the digital input terminals LI1 to LI4. The controller 21 can simultaneously command the inverter devices 22a to 22d by transmitting various commands (forward / reverse operation command, operation preparation command, multi-speed command, DC braking command, reset command, etc.).

FIG. 1 is an electrical configuration diagram showing the periphery of the input interface of the inverter device, and FIG. 2 schematically shows this electrical configuration in a block diagram.
Hereinafter, since the internal electrical configurations of the inverter devices 22a to 22d are identical to each other, the electrical configuration of the inverter device 22a will be described. As shown in FIG. 1, digital input circuits 23 to 26 are connected to a plurality of input terminals LI1 to LI4 of the inverter device 22a, respectively. Since these digital input circuits 23 to 26 have the same configuration, the description of the digital input circuits 25 and 26 is omitted in FIG. 1, and in the following, the electrical input circuit 23 connected to the input terminal LI1 is electrically connected. An explanation will be given of the general configuration.

  The digital input circuit 23 is configured to digitally output to the output node Na6 based on a voltage applied between the digital input node Na1 and the digital input node Na2, and includes resistors R1 to R4, transistors Tr1 to Tr2, The switch SW1 is combined. The digital input node Na1 is a node connected to the input terminal LI1.

  In the description of the background art, the digital input nodes Na1 and Na2 and the output node Na6 are described as the nodes around the digital input circuit 2a. However, in this embodiment, in order to make the description easy to understand, In the digital input circuit 23, the corresponding digital input node and output node are denoted by the same reference numerals as Na1, Na2, and Na6. In FIG. 1, reference numerals are assigned as the ground node Nc1 and the power supply potential node Nc2. The ground node Nc1 corresponds to a first common potential setting node, and the power supply potential node Nc2 is a node to which the power supply potential Vd is applied. And corresponds to a second common potential setting node.

  Resistors R1 to R3 are connected in series between the input nodes Na1 and Na2. That is, a passive element is connected between the input nodes Na1 and Na2, and when a potential difference is generated between the input nodes Na1 and Na2, a current flows through the resistors R1 to R3.

  If the common connection node between the resistor R1 and the resistor R2 is Na8 and the common connection node between the resistor R2 and the resistor R3 is Na9, the emitter and base of the PNP bipolar transistor Tr1 are connected between the nodes Na8 and Na9. In addition, the base and emitter of the PNP-type bipolar transistor Tr2 are connected.

  The collectors of the transistors Tr1 and Tr2 are commonly connected, and the common connection node Na10 is output as a signal from the output node Na6 to the microcomputer (hereinafter abbreviated as microcomputer) 27 through the digital switch SW1 and the pull-up resistor R4. It has become so.

  The digital input circuits 23 to 26 are provided in parallel, but the ground side input nodes Na2, Na4,... Serving as the reference potential nodes of these circuits 23 to 26 are not commonly connected, and these input nodes Na2,. 1 is provided with an energization breaker 28 shown in FIG. Note that the interface circuit Z is a circuit including the digital input circuits 23 to 26 and the energization breaker 28.

  The current breaker 28 includes diodes D1 to D4, and functions when the circuit configuration of the diodes D1 to D4 is changed by digital switches SW2 to SW4 that are switched on and off based on a control signal from the microcomputer 27. .

  Hereinafter, the connection relationship will be described. Since the circuit configuration connected to the digital input circuits 23 to 26 is substantially the same and symmetrical, the circuit connected to the digital input circuits 23 and 24 will be described. Description of the circuit will be omitted.

  In the description of the background art section, the digital input nodes Na3 and Na4 and the output node Na7 are used as the input / output nodes of the digital input circuit 3a, and are described with reference numerals. However, in this embodiment, the description is easy to understand. In the digital input circuit 24, corresponding digital input nodes and output nodes are denoted by the same reference numerals as Na3, Na4 and Na7, respectively.

  The input node Na2 is connected to the anode of the diode D1 and the cathode of the diode D2. The cathode of the diode D1 is electrically connected to the ground via the digital switch SW2. The anode of the diode D2 is connected to the power supply potential node Nc2 serving as the supply node of the power supply potential Vd via the digital switch SW3.

  The input node Na4 is connected to the anode of the diode D3 and the cathode of the diode D4. The cathode of the diode D3 is commonly connected to the cathode of the diode D1, and is electrically connected to the ground via the digital switch SW2 as described above. The anode of the diode D4 is commonly connected to the anode of the diode D2, and is connected to the power supply potential node Nc2 serving as the supply node of the power supply potential Vd via the digital switch SW3 as described above.

  The control terminal of the digital switch SW3 is connected to the digital switch SW4 via the resistor R5. The control terminal of the digital switch SW4 is connected to the control output terminal of the microcomputer 27. The control terminal of the digital switch SW2 is connected to the control output terminal of the control circuit 27.

  When the digital switch SW2 is turned on, the common connection node of the cathodes of the diodes D1 and D3 becomes the ground potential, and when the digital switch SW3 is turned on, the common connection node of the anodes of the diodes D2 and D4 becomes the power supply potential Vd.

  The microcomputer 27 turns on the digital switch SW2 and turns off the digital switch SW3 in the source input format. Then, the input nodes Na2, Na4... Serving as the reference potential nodes of the digital input circuits 23 to 26 are almost set to the ground potential (≈the diode forward voltage Vf), and accepts the digital signal in the source input format. .

  When the source input format is set, when a “high” level in which the potential of the node Na1 is higher than the potential of the node Na2 is input between the input nodes Na1 and Na2, the transistor Tr1 is turned on and the transistor Since Tr2 is turned off and the digital switch SW1 is turned on accordingly, the “low” level of the ground potential is output from the output node Na6 and the level is input to the microcomputer 27.

  On the other hand, when a “low” level in which the potential of the node Na1 is substantially the same as the potential of the node Na2 is input between the input nodes Na1 and Na2, both the transistors Tr1 and Tr2 are turned off, and accordingly, the digital switch SW1. Is turned off, the “high” level of the power supply potential is output via the pull-up resistor R 4 and the level is input to the microcomputer 27.

  The microcomputer 27 turns off the digital switch SW2 and turns on the digital switch SW3 when the sink input format is selected. Then, the input nodes Na2, Na4,... Of the digital input circuits 23 to 26 are substantially at the power supply potential Vd (≈power supply potential Vd−the forward voltage Vf of the diode), and accept the digital signal in the sink input format.

  When the sink input format is set, when the “high” level is inputted between the input nodes Na1 and Na2 and the potential of the node Na1 is almost the same as the potential of the node Na2, the transistors Tr1 and Tr2 are both turned off. Accordingly, since the digital switch SW1 is turned off, the “high” level of the power supply potential is output via the pull-up resistor R4 and the level is input to the microcomputer 27.

On the contrary, when a “low” level in which the potential of the node Na1 is lower than the potential of the node Na2 is input between the input nodes Na1 and Na2, the transistor Tr1 is turned off and the transistor Tr2 is turned on. Since the digital switch SW1 is turned on, the “low” level of the ground potential is output from the output node Na6 and the level is input to the microcomputer 27.
A block diagram schematically showing this connection relationship is shown in FIG.

  In the following description, it is assumed that the microcomputer 27 is set to adjust the on / off of the switches SW2 to SW4 and accept the digital signal in the source input format, and as shown in FIG. For example, the operation when the power of the inverter device 22a) is cut off (ON → OFF) will be described.

  The controller 21 transmits a digital signal from the output terminals 211 to 214 to the input terminals LI1 to LI4 of the inverter devices 22b to 22d in order to transmit a command signal to the inverter devices 22b to 22d to which power is supplied. This digital signal is also applied to the input terminals LI1 to LI4 of the inverter device 22a that is not supplied with power.

  When the power source of the inverter device 22a is cut off, all the switches SW2 to SW4 shown in FIG. 1 are forcibly turned off, so that the diodes D1 to D4 function in a state disconnected from the circuit formed by the switches SW2 to SW4.

  For example, consider that the controller 21 outputs a digital signal to the digital input circuit 23 through the input terminal LI1 of the inverter device 22a. At this time, the current tries to flow into the diode D1 through the resistors R1 to R3 and the like. The circuits 24 to 26 do not flow to the input node Na4. If no current is supplied to the input nodes Na4... Of other digital input circuits 24 to 26, current does not flow from the input terminals LI2 to LI4 to the other inverter devices 22b to 22d.

  Accordingly, the current is less likely to flow into the inverter device 22a after the power is cut off, and the current does not flow into the other inverter devices 22b to 22d in operation as shown in the background art column. As a result, the other inverter devices 22b to 22d can continue to operate normally (see current flow indicated by arrows in FIG. 1).

  As described above, according to the present embodiment, since the diodes D2 to D4 function as the energization breaker 28, current flows out / inflow between the reference potential nodes Na2, Na4... Of the digital input circuits 23 to 26. Thus, malfunction of the digital input circuits 23 to 26 can be prevented.

  In particular, since the diode D3 is connected in the reverse direction between the input node Na2 of the digital input circuit 23 and the input nodes Na4 of the digital input circuits 24 to 26, the current flowing from the input node Na2 to the input node Na4. . As a result, it is possible to prevent unnecessary current from flowing out from the other input terminals LI2 to LI4 of the inverter device 22a after the power supply is cut off, and the operation of the other digital input circuits 22b to 22d is not adversely affected. Thereby, even when the power of the inverter device 22a is shut off, the other inverter devices 22b to 22d can prevent the digital signal from being erroneously recognized, and can continue to operate normally.

(Second Embodiment)
4 and 5 show a second embodiment of the present invention. The difference from the previous embodiment is that the energization connection between the reference potential node and the first and second common nodes is switched and the reference potential node and the first potential are changed. The current-carrying connection between the first and second common nodes is configured to be openable. The same parts as those of the above-described embodiment are denoted by the same reference numerals and description thereof is omitted, and different parts will be described below.

  As shown in FIG. 4, the input node Na2 of the digital input circuit 23 is electrically connected to the digital switch SW5 connected to the ground side and the digital switch SW6 connected to the power supply potential side. Na4 is electrically connected to the digital switch SW7 connected to the ground side and the digital switch SW8 connected to the power supply potential side. The digital switches SW5 and SW7 turn the switches on and off (short circuit / open) based on a control signal from the microcomputer 27. Similarly, the digital switches SW6 and SW8 turn the switches on and off (short circuit / open) based on a control signal from the microcomputer 27.

  Therefore, by switching the ON / OFF state of the digital switches SW5 to SW9 functioning as a current breaker and a switching circuit, the potentials of the input nodes Na2, Na4,... Serving as reference potential nodes are set to the potential of the ground node Nc1 (= 0V). Can be set to almost the same potential as the source input format.

  Further, by setting the on / off states of the digital switches SW5 to SW9, the potentials of the input nodes Na2, Na4,. In this case, the sink input format can be set. Further, the input nodes Na2, Na4... Can be opened. FIG. 5 schematically shows this circuit configuration block.

  Similar to the above-described embodiment, consider the operation when the inverter device 22a is powered off while all the inverter devices 22a to 22d are set to the source input format. When the power supply of the inverter device 22a is cut off, all the digital switches SW5 to SW9 in the inverter device 22a are forcibly turned off. Then, all of the input nodes Na2, Na4... Are opened, and the current flowing from the input terminals LI1 to LI4 to the other inverter devices 22b to 22d can be cut off similarly to the above-described embodiment, and the inverter devices 22b to 22d can be cut off. Can continue to operate normally.

  According to the present embodiment, the digital switches SW5 and SW7 can switch the energization connection between the input nodes Na2, Na4..., The ground node Nc1, and the power supply potential node Nc2, so that the source input format and the sink input format are switched. In addition, when the power is shut down, the digital switches SW5 to SW9 are all turned off, so that the input nodes Na2, Na4,... Are all open, so that the inverter device 22b that is operating from the inverter device 22a that is powered off. The current flowing through 22d can be cut off, and the inverter devices 22b to 22d can continue to operate normally. Thereby, it is possible to prevent erroneous recognition of digital signals in the digital input circuits 23 to 26 in the inverter devices 22b to 22d even when the power of the inverter device 22a is shut off.

(Third embodiment)
FIG. 6 shows a third embodiment of the present invention. The difference from the previous embodiment is that the aspect of the digital input circuit is changed. The same parts as those of the above-described embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described below.

  As shown in FIG. 6, digital input circuits 29 to 32 are provided instead of the digital input circuits 23 to 26. Each of the digital input circuits 29 to 32 includes a photocoupler P1. Between the nodes Na1 and Na2 of the digital input circuit 29, a resistor R7 and a resistor R8 are connected in series. The input of the photocoupler P1 is configured by connecting two photodiodes in reverse parallel to each other, and is connected in parallel with the resistor R7. A phototransistor is formed at the output of the photocoupler P1, and the output is connected to the microcomputer 27 via the pull-up resistor R4.

  If no current flows between the nodes Na1 and Na2, the photodiode configured at the input of the photocoupler P1 is not energized, the phototransistor configured at the output of the photocoupler P1 remains off, and the microcomputer 27 Is given a “high”.

  When the current flows between the nodes Na1 and Na2, the voltage across the resistor R7 rises and the current also flows through the photodiode of the photocoupler P1 input. When a current flows through the photodiode, the photodiode emits light, so that the phototransistor output from the photocoupler P1 is turned on, and “low” is given to the microcomputer 27.

  Thus, since the photocoupler P1 is configured to be interposed between the microcomputer 27 and the resistors R7 and R8, it is possible to maintain insulation between each other. Further, since the photocouplers P2 and P3 are configured between the microcomputer 27 and the energization breaker 28, insulation can be maintained.

  In this case, since the energization breaker 28 is configured in the same manner as in the above-described embodiment, even if a current flows from the input terminal LI1 when the power source of the inverter device 22a is shut off, the current is one digital input circuit 29. No other digital input circuits 30 to 32 flow out from the above, and the operation and effect are almost the same as those of the previous embodiment. In this way, even if the configuration of the digital input circuits 29 to 32 is changed from that of the above-described embodiment, substantially the same operational effects are obtained.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.
In the above-described embodiment, the embodiment in which the source input format is set has been described. However, even if the sink input format is set, the same operational effects can be obtained. Although the ground level (= 0 V) is applied as the reference potential of the first common node in the source input format, the reference potential is not limited to this potential value. The same applies to the potential value of the reference potential of the second common node in the sink input format.

In the above-described embodiment, the controller 21 is applied to the form in which the digital signal is output in the source output form. However, it can be applied to the form in which the digital signal is output in the sink output form instead.
In the above-described embodiment, the digital input circuits 23 to 26 serving as an inverting circuit and a buffer circuit are applied. However, the present invention is not limited to the above circuit as long as it is an interface circuit that inputs and outputs digital signals.

  In the first embodiment and the second embodiment, diodes D1 to D4 and digital switches SW5 to SW9 are applied as current-carrying circuit breakers, respectively. However, input nodes Na2, Na4... Through input terminals LI1 to LI4. The circuit configuration is not limited to the above as long as it is a circuit that can cut off the flowing current.

  In the drawing, 20 is a control device, 21 is a controller, 22a to 22d are inverter devices, 23 to 26, 29 to 32 are digital input circuits, 27 is a control circuit, 28 is a power circuit breaker, and SW5 to SW9 are digital switches (switching). Circuit), Na1 to Na4 are digital input nodes, and Z is an interface circuit.

Claims (4)

An inverter device configured on the signal input side and configured such that the power source can be cut off independently of other inverter devices, and configured to be connected in parallel with other inverter devices,
A digital input node for inputting both source input type and sink input type digital signals from an external circuit such as a contact or a logic circuit is provided, and a digital signal applied to each of the digital input nodes is input and a reference potential node is input. A plurality of digital input circuits operating on the basis of the potential of
A first common potential setting node set to a common potential common to each other as a reference potential of a digital signal in a source input format of the plurality of digital input circuits;
A second common potential setting node set to a common potential common to each other as a reference potential of a digital signal in the sink input format of the plurality of digital input circuits;
The digital input circuit is provided between a reference potential node of the digital input circuit and the first common potential setting node and the second common potential setting node. The other digital input is connected to the reference potential node of one digital input circuit. An inverter device comprising: an energization breaker that prevents inflow of current from a reference potential node of the circuit.   The power supply circuit breaker includes a diode connected in a reverse direction from a reference potential node of the other digital input circuit to a reference potential node of the one digital input circuit. 1. The inverter device according to 1.   The energization circuit breaker is configured to switch the energization connection between the reference potential node and the first and second common nodes and to open the connection between the reference potential node and the first and second common nodes. The inverter device according to claim 1, comprising: A plurality of inverter devices according to any one of claims 1 to 3, and a controller capable of outputting a digital signal from a plurality of output terminals in a source output format or a sink output format,
A plurality of output terminals of the controller are respectively connected to a plurality of digital input nodes of one of the inverter devices, and are connected to a plurality of digital input nodes of the other inverter device. .

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