JP2011100892A5 - - Google Patents

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JP2011100892A5
JP2011100892A5 JP2009255235A JP2009255235A JP2011100892A5 JP 2011100892 A5 JP2011100892 A5 JP 2011100892A5 JP 2009255235 A JP2009255235 A JP 2009255235A JP 2009255235 A JP2009255235 A JP 2009255235A JP 2011100892 A5 JP2011100892 A5 JP 2011100892A5
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light receiving
electrode
recess
receiving element
semiconductor chip
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近赤外域に受光感度を持つ化合物半導体に受光素子が複数配列された受光素子アレイと、前記受光素子ごとに光電荷を読み出す読み出し回路とを備えたハイブリッド型の検出装置であって、
前記受光素子の電極、および/または、前記読み出し回路の読み出し電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであり、
前記凹部が接合バンプによって、部分的または全面的に充填されていることを特徴とする、検出装置。
A hybrid type detection device comprising a light receiving element array in which a plurality of light receiving elements are arranged in a compound semiconductor having light receiving sensitivity in the near infrared region, and a readout circuit for reading out photoelectric charges for each light receiving element
In the electrode of the light receiving element and / or the readout electrode of the readout circuit, the recess has an average vertical distance of 100 nm or more between the bottom of the recess and the top which is the surface of the electrode other than the recess. It is formed over the surface of the electrode, and the recess is attached by etching,
Characterized in that the recess by junction bumps, are partially or completely filled, the detection device.
前記受光素子アレイは、InP基板と、該InP基板上に形成された、バンドギャップ波長が1.65μm〜3.0μmの受光層とを有し、該受光層は、(GaAsSb/InGaAs)のタイプ2の多重量子井戸構造、または、(GaAsSb/InGaAsN)、(GaAsSb/InGaAsNP)、および(GaAsSb/InGaAsNSb)のうちのいずれかのタイプ2の多重量子井戸構造、であり、かつ、その受光層は、InP基板との格子整合条件、|Δa/a|≦0.002(ただし、aiを受光層内の各層の格子定数、aをInP基板の格子定数として、Δa=ai−a、である)を満たすことを特徴とする、請求項に記載の検出装置。 The light receiving element array includes an InP substrate and a light receiving layer formed on the InP substrate and having a band gap wavelength of 1.65 μm to 3.0 μm. The light receiving layer is of a type (GaAsSb / InGaAs). 2 or a type 2 multiple quantum well structure of any one of (GaAsSb / InGaAsN), (GaAsSb / InGaAsNP), and (GaAsSb / InGaAsNSb), and the light receiving layer is Lattice matching condition with InP substrate, | Δa / a | ≦ 0.002 (where Δa = ai−a, where ai is the lattice constant of each layer in the light receiving layer and a is the lattice constant of the InP substrate) The detection device according to claim 1 , wherein: 前記受光素子アレイは、InP基板と、該InP基板上に形成された、バンドギャップ波長が1.65μm〜3.0μmの受光層とを有し、該受光層は、InGaAs、InGaAsN、InGaAsNP、およびInGaAsNSbのうちのいずれかであり、その受光層は、InP基板との格子整合条件、|Δa/a|≦0.002(ただし、aiを受光層の格子定数、aをInP基板の格子定数として、Δa=ai−a、である)を満たすことを特徴とする、請求項に記載の検出装置。 The light receiving element array includes an InP substrate and a light receiving layer formed on the InP substrate and having a band gap wavelength of 1.65 μm to 3.0 μm. The light receiving layer includes InGaAs, InGaAsN, InGaAsNP, and Any of InGaAsNSb, and its light receiving layer has a lattice matching condition with the InP substrate, | Δa / a | ≦ 0.002 (where ai is the lattice constant of the light receiving layer and a is the lattice constant of the InP substrate) , and satisfies the Δa = ai-a, a), detection apparatus according to claim 1. 近赤外域に受光感度を持つ化合物半導体に受光素子が複数配列された受光素子アレイであって、
前記受光素子は、前記化合物半導体のエピタキシャル積層体の表層からp型不純物を選択拡散して形成されたpn接合を有し、非拡散領域によって隔てられており、
前記p型不純物が選択拡散されたp型領域にオーミック接触するp側電極を受光素子ごとに備え、
前記p側電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであることを特徴とする、受光素子アレイ。
A light receiving element array in which a plurality of light receiving elements are arranged on a compound semiconductor having light receiving sensitivity in the near infrared region,
The light receiving element has a pn junction formed by selectively diffusing a p-type impurity from a surface layer of the compound semiconductor epitaxial stacked body, and is separated by a non-diffusion region,
A p-side electrode in ohmic contact with the p-type region in which the p-type impurity is selectively diffused is provided for each light receiving element;
The p-side electrode has a recess formed over the surface of the electrode such that the average vertical distance between the bottom of the recess and the top of the electrode other than the recess is 100 nm, and The light receiving element array, wherein the concave portion is formed by etching.
前記p側電極ごとに接合バンプを備え、前記凹部が前記接合バンプによって、部分的または全面的に充填されていることを特徴とする、請求項に記載の受光素子アレイ。 The light receiving element array according to claim 4 , wherein a bonding bump is provided for each p-side electrode, and the concave portion is partially or entirely filled with the bonding bump. 接合バンプに接合される電極を有する電子機器であって、
前記電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであることを特徴とする、電子機器。
An electronic device having an electrode bonded to a bonding bump,
In the electrode, a recess is formed over the surface of the electrode such that an average vertical distance between the bottom of the recess and the top which is the surface of the electrode other than the recess is 100 nm or more, and the recess An electronic device characterized in that is attached by etching.
第1の半導体チップと、第2の半導体チップとを備え、前記第1の半導体チップの電極と前記第2の半導体チップの電極とが接合バンプで接合された複合型電子機器であって、
前記第1の半導体チップの電極、および/または、前記第2の半導体チップの電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであり、
前記凹部が前記接合バンプによって、部分的または全面的に充填されていることを特徴とする、複合型電子機器。
A composite electronic device comprising a first semiconductor chip and a second semiconductor chip, wherein the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip are joined by joint bumps,
In the electrode of the first semiconductor chip and / or the electrode of the second semiconductor chip, the average vertical distance between the bottom of the recess and the top which is the surface of the electrode other than the recess is 100 nm or more And is formed over the surface of the electrode, and the concave portion is attached by etching,
The composite electronic device, wherein the concave portion is partially or entirely filled with the bonding bump.
前記凹部は、前記底部と底部との平均ピッチが300nm以下または前記頂部と頂部との平均ピッチが300nm以下、となるように形成されていることを特徴とする、請求項1〜3のいずれか1項に記載の検出装置、請求項4若しくは5に記載の受光素子アレイ、請求項6に記載の電子機器、または、請求項7に記載の複合型電子機器The said recessed part is formed so that the average pitch of the said bottom part and a bottom part may be 300 nm or less, or the average pitch of the said top part and a top part is 300 nm or less, The any one of Claims 1-3 characterized by the above-mentioned. The detection device according to claim 1, the light receiving element array according to claim 4 or 5, the electronic device according to claim 6, or the composite electronic device according to claim 7 . 接合バンプに接合される電極を有する電子機器の製造方法であって、
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記電子機器の電極にレジスト膜を塗布する工程と、
前記電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記電極にエッチングによって凹部を形成する工程とを備えることを特徴とする、電子機器の製造方法。
A method for manufacturing an electronic device having an electrode bonded to a bonding bump,
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Applying a resist film to the electrodes of the electronic device;
Pressing the concave / convex pattern of the original plate onto the resist film on the electrode to form the resist pattern;
And a step of forming a recess in the electrode provided with the resist pattern by etching.
第1の半導体チップと、第2の半導体チップとを備え、前記第1の半導体チップの電極と前記第2の半導体チップの電極とが接合バンプで接合された複合型電子機器の製造方法であって、
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記第1の半導体チップの電極、および/または、前記第2の半導体チップの電極、の面に、レジスト膜を塗布する工程と、
前記電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記電極にエッチングによって凹部を形成する工程と、
前記第1の半導体チップの電極、および/または、前記第2の半導体チップの電極に、接合バンプを設ける工程と、
前記第1の半導体チップの電極および前記第2の半導体チップの電極を、前記接合バンプを介して導電接続することを特徴とする、複合型電子機器の製造方法。
A method of manufacturing a composite electronic device comprising a first semiconductor chip and a second semiconductor chip, wherein the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip are joined by joint bumps. And
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Applying a resist film to the surface of the electrode of the first semiconductor chip and / or the electrode of the second semiconductor chip;
Pressing the concave / convex pattern of the original plate onto the resist film on the electrode to form the resist pattern;
Forming a recess in the electrode to which the resist pattern is attached by etching;
Providing bonding bumps on the electrodes of the first semiconductor chip and / or the electrodes of the second semiconductor chip;
A method of manufacturing a composite electronic device, wherein the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip are conductively connected through the bonding bumps.
近赤外域に受光感度を持つ化合物半導体に受光素子が複数配列された受光素子アレイと、前記受光素子ごとに光電荷を読み出す読み出し回路とが接合バンプで接合されたハイブリッド型の検出装置の製造方法であって、
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記受光素子アレイの電極、および/または、前記読み出し回路の読み出し電極、の面に、レジスト膜を塗布する工程と、
前記電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記電極にエッチングによって凹部を形成する工程と、
前記受光素子アレイの電極、および/または、前記読み出し回路の読み出し電極に、接合バンプを設ける工程と、
前記受光素子アレイの電極および前記読み出し回路の読み出し電極を、前記接合バンプを介して導電接続することを特徴とする、検出装置の製造方法。
Manufacturing method of hybrid type detection device in which light receiving element array in which a plurality of light receiving elements are arranged in compound semiconductor having light receiving sensitivity in near infrared region, and readout circuit for reading out photoelectric charge for each light receiving element are joined by joint bump Because
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Applying a resist film to the surfaces of the electrodes of the light receiving element array and / or the readout electrodes of the readout circuit;
Pressing the concave / convex pattern of the original plate onto the resist film on the electrode to form the resist pattern;
Forming a recess in the electrode to which the resist pattern is attached by etching;
Providing bonding bumps on the electrodes of the light receiving element array and / or the readout electrodes of the readout circuit;
A method for manufacturing a detection device, wherein the electrodes of the light receiving element array and the readout electrodes of the readout circuit are conductively connected via the bonding bumps.
近赤外域に受光感度を持つ化合物半導体に受光素子が複数配列された受光素子アレイの製造方法であって、
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記受光素子ごとに前記化合物半導体のエピタキシャル積層体の表層からp型不純物を選択拡散してpn接合を、非拡散領域によって隔てられるように、形成する工程と、
前記p型不純物が選択拡散されたp型領域にオーミック接触するp側電極を形成する工程と、
前記p側電極、の面に、レジスト膜を塗布する工程と、
前記p側電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記p側電極にエッチングによって凹部を形成する工程とを備えることを特徴とする、受光素子アレイの製造方法。
A method of manufacturing a light receiving element array in which a plurality of light receiving elements are arranged in a compound semiconductor having light receiving sensitivity in the near infrared region,
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Forming a p-type impurity by selectively diffusing p-type impurities from the surface layer of the compound semiconductor epitaxial stack for each of the light receiving elements so as to be separated by a non-diffusion region;
Forming a p-side electrode in ohmic contact with the p-type region in which the p-type impurity is selectively diffused;
Applying a resist film to the surface of the p-side electrode;
Pressing the concave / convex pattern of the original plate onto the resist film on the p-side electrode to form the resist pattern;
Forming a recess by etching on the p-side electrode provided with the resist pattern. A method for manufacturing a light-receiving element array.
前記原版の凹凸パターンをレジスト膜に押し当ててレジストパターンを形成した後で、前記エッチングによって凹部を形成する前に、前記レジストパターンの凹部の底部に前記電極が露出するように、前記レジストパターンを限定的にエッチングする工程を備えることを特徴とする、請求項9に記載の電子機器の製造方法、請求項10に記載の複合型電子機器の製造方法、請求項11に記載の検出装置の製造方法、または、請求項12に記載の受光素子アレイの製造方法。   After forming the resist pattern by pressing the concave / convex pattern of the original plate on the resist film, before forming the concave portion by the etching, the resist pattern is formed so that the electrode is exposed at the bottom of the concave portion of the resist pattern. The method for manufacturing an electronic device according to claim 9, the method for manufacturing a composite electronic device according to claim 10, and the method for manufacturing a detection device according to claim 11, further comprising a step of etching in a limited manner. The method or the manufacturing method of the light receiving element array of Claim 12.
JP2009255235A 2009-11-06 2009-11-06 Electronic apparatus, composite electronic apparatus, detection device, light receiving element array, and methods of manufacturing the same Pending JP2011100892A (en)

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