JP2011100892A5 - - Google Patents
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- JP2011100892A5 JP2011100892A5 JP2009255235A JP2009255235A JP2011100892A5 JP 2011100892 A5 JP2011100892 A5 JP 2011100892A5 JP 2009255235 A JP2009255235 A JP 2009255235A JP 2009255235 A JP2009255235 A JP 2009255235A JP 2011100892 A5 JP2011100892 A5 JP 2011100892A5
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- light receiving
- electrode
- recess
- receiving element
- semiconductor chip
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Claims (13)
前記受光素子の電極、および/または、前記読み出し回路の読み出し電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであり、
前記凹部が接合バンプによって、部分的または全面的に充填されていることを特徴とする、検出装置。 A hybrid type detection device comprising a light receiving element array in which a plurality of light receiving elements are arranged in a compound semiconductor having light receiving sensitivity in the near infrared region, and a readout circuit for reading out photoelectric charges for each light receiving element
In the electrode of the light receiving element and / or the readout electrode of the readout circuit, the recess has an average vertical distance of 100 nm or more between the bottom of the recess and the top which is the surface of the electrode other than the recess. It is formed over the surface of the electrode, and the recess is attached by etching,
Characterized in that the recess by junction bumps, are partially or completely filled, the detection device.
前記受光素子は、前記化合物半導体のエピタキシャル積層体の表層からp型不純物を選択拡散して形成されたpn接合を有し、非拡散領域によって隔てられており、
前記p型不純物が選択拡散されたp型領域にオーミック接触するp側電極を受光素子ごとに備え、
前記p側電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであることを特徴とする、受光素子アレイ。 A light receiving element array in which a plurality of light receiving elements are arranged on a compound semiconductor having light receiving sensitivity in the near infrared region,
The light receiving element has a pn junction formed by selectively diffusing a p-type impurity from a surface layer of the compound semiconductor epitaxial stacked body, and is separated by a non-diffusion region,
A p-side electrode in ohmic contact with the p-type region in which the p-type impurity is selectively diffused is provided for each light receiving element;
The p-side electrode has a recess formed over the surface of the electrode such that the average vertical distance between the bottom of the recess and the top of the electrode other than the recess is 100 nm, and The light receiving element array, wherein the concave portion is formed by etching.
前記電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであることを特徴とする、電子機器。 An electronic device having an electrode bonded to a bonding bump,
In the electrode, a recess is formed over the surface of the electrode such that an average vertical distance between the bottom of the recess and the top which is the surface of the electrode other than the recess is 100 nm or more, and the recess An electronic device characterized in that is attached by etching.
前記第1の半導体チップの電極、および/または、前記第2の半導体チップの電極に、凹部が、該凹部の底部と該凹部以外の前記電極の面である頂部との平均垂直距離が100nm以上となるように、該電極の面にわたって形成されており、かつ、前記凹部がエッチングにより付されたものであり、
前記凹部が前記接合バンプによって、部分的または全面的に充填されていることを特徴とする、複合型電子機器。 A composite electronic device comprising a first semiconductor chip and a second semiconductor chip, wherein the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip are joined by joint bumps,
In the electrode of the first semiconductor chip and / or the electrode of the second semiconductor chip, the average vertical distance between the bottom of the recess and the top which is the surface of the electrode other than the recess is 100 nm or more And is formed over the surface of the electrode, and the concave portion is attached by etching,
The composite electronic device, wherein the concave portion is partially or entirely filled with the bonding bump.
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記電子機器の電極にレジスト膜を塗布する工程と、
前記電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記電極にエッチングによって凹部を形成する工程とを備えることを特徴とする、電子機器の製造方法。 A method for manufacturing an electronic device having an electrode bonded to a bonding bump,
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Applying a resist film to the electrodes of the electronic device;
Pressing the concave / convex pattern of the original plate onto the resist film on the electrode to form the resist pattern;
And a step of forming a recess in the electrode provided with the resist pattern by etching.
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記第1の半導体チップの電極、および/または、前記第2の半導体チップの電極、の面に、レジスト膜を塗布する工程と、
前記電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記電極にエッチングによって凹部を形成する工程と、
前記第1の半導体チップの電極、および/または、前記第2の半導体チップの電極に、接合バンプを設ける工程と、
前記第1の半導体チップの電極および前記第2の半導体チップの電極を、前記接合バンプを介して導電接続することを特徴とする、複合型電子機器の製造方法。 A method of manufacturing a composite electronic device comprising a first semiconductor chip and a second semiconductor chip, wherein the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip are joined by joint bumps. And
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Applying a resist film to the surface of the electrode of the first semiconductor chip and / or the electrode of the second semiconductor chip;
Pressing the concave / convex pattern of the original plate onto the resist film on the electrode to form the resist pattern;
Forming a recess in the electrode to which the resist pattern is attached by etching;
Providing bonding bumps on the electrodes of the first semiconductor chip and / or the electrodes of the second semiconductor chip;
A method of manufacturing a composite electronic device, wherein the electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip are conductively connected through the bonding bumps.
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記受光素子アレイの電極、および/または、前記読み出し回路の読み出し電極、の面に、レジスト膜を塗布する工程と、
前記電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記電極にエッチングによって凹部を形成する工程と、
前記受光素子アレイの電極、および/または、前記読み出し回路の読み出し電極に、接合バンプを設ける工程と、
前記受光素子アレイの電極および前記読み出し回路の読み出し電極を、前記接合バンプを介して導電接続することを特徴とする、検出装置の製造方法。 Manufacturing method of hybrid type detection device in which light receiving element array in which a plurality of light receiving elements are arranged in compound semiconductor having light receiving sensitivity in near infrared region, and readout circuit for reading out photoelectric charge for each light receiving element are joined by joint bump Because
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Applying a resist film to the surfaces of the electrodes of the light receiving element array and / or the readout electrodes of the readout circuit;
Pressing the concave / convex pattern of the original plate onto the resist film on the electrode to form the resist pattern;
Forming a recess in the electrode to which the resist pattern is attached by etching;
Providing bonding bumps on the electrodes of the light receiving element array and / or the readout electrodes of the readout circuit;
A method for manufacturing a detection device, wherein the electrodes of the light receiving element array and the readout electrodes of the readout circuit are conductively connected via the bonding bumps.
電子ビーム露光方法によって、レジストパターンを形成するための凹凸パターンが付された原版を作製する原版作製工程と、
前記受光素子ごとに前記化合物半導体のエピタキシャル積層体の表層からp型不純物を選択拡散してpn接合を、非拡散領域によって隔てられるように、形成する工程と、
前記p型不純物が選択拡散されたp型領域にオーミック接触するp側電極を形成する工程と、
前記p側電極、の面に、レジスト膜を塗布する工程と、
前記p側電極上のレジスト膜に前記原版の凹凸パターンを押し当てて、前記レジストパターンを形成する工程と、
前記レジストパターンが付された前記p側電極にエッチングによって凹部を形成する工程とを備えることを特徴とする、受光素子アレイの製造方法。 A method of manufacturing a light receiving element array in which a plurality of light receiving elements are arranged in a compound semiconductor having light receiving sensitivity in the near infrared region,
An original plate production process for producing an original plate with an uneven pattern for forming a resist pattern by an electron beam exposure method;
Forming a p-type impurity by selectively diffusing p-type impurities from the surface layer of the compound semiconductor epitaxial stack for each of the light receiving elements so as to be separated by a non-diffusion region;
Forming a p-side electrode in ohmic contact with the p-type region in which the p-type impurity is selectively diffused;
Applying a resist film to the surface of the p-side electrode;
Pressing the concave / convex pattern of the original plate onto the resist film on the p-side electrode to form the resist pattern;
Forming a recess by etching on the p-side electrode provided with the resist pattern. A method for manufacturing a light-receiving element array.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009255235A JP2011100892A (en) | 2009-11-06 | 2009-11-06 | Electronic apparatus, composite electronic apparatus, detection device, light receiving element array, and methods of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009255235A JP2011100892A (en) | 2009-11-06 | 2009-11-06 | Electronic apparatus, composite electronic apparatus, detection device, light receiving element array, and methods of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
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JP2011100892A JP2011100892A (en) | 2011-05-19 |
JP2011100892A5 true JP2011100892A5 (en) | 2012-12-13 |
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Family Applications (1)
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JP2009255235A Pending JP2011100892A (en) | 2009-11-06 | 2009-11-06 | Electronic apparatus, composite electronic apparatus, detection device, light receiving element array, and methods of manufacturing the same |
Country Status (1)
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JP (1) | JP2011100892A (en) |
Families Citing this family (1)
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WO2018193747A1 (en) * | 2017-04-19 | 2018-10-25 | Sony Semiconductor Solutions Corporation | Semiconductor device, method of manufacturing the same, and electronic apparatus |
Family Cites Families (9)
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JPS6489345A (en) * | 1987-09-29 | 1989-04-03 | Fujitsu Ltd | Metal bump and manufacture thereof |
JPH10308415A (en) * | 1997-03-06 | 1998-11-17 | Toshiba Corp | Method for mounting electrode, electronic component, electronic device, and electronic component |
JP2000232095A (en) * | 1999-02-12 | 2000-08-22 | Nippon Telegr & Teleph Corp <Ntt> | Formation method for fine pattern of semiconductor surface |
JP2002043366A (en) * | 2000-07-21 | 2002-02-08 | Canon Inc | Semiconductor device |
JP2005101165A (en) * | 2003-09-24 | 2005-04-14 | Toppan Printing Co Ltd | Flip chip mounting structure, substrate for mounting the same, and method of manufacturing the same |
JP2005223090A (en) * | 2004-02-04 | 2005-08-18 | Murata Mfg Co Ltd | Connection structure of mounting substrate and component |
JP2007201432A (en) * | 2005-12-28 | 2007-08-09 | Sumitomo Electric Ind Ltd | Imaging apparatus, visibility aid device, night vision device, navigation aid device, and monitoring device |
JP5117169B2 (en) * | 2007-04-06 | 2013-01-09 | 株式会社日立製作所 | Semiconductor device |
JP4662188B2 (en) * | 2008-02-01 | 2011-03-30 | 住友電気工業株式会社 | Light receiving element, light receiving element array and manufacturing method thereof |
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