JP2011096788A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a spacer neither requiring the use of a substrate protective film nor generating a notch when mutual interval between projections for forming the spacer is small, the width of a groove is small, or the diameter of a hole is small. <P>SOLUTION: In anisotropic etching when the spacer is formed, "1-(ratio of horizontal etching rate to vertical etching rate of second spacer forming film 5 in anisotropic etching)" is defined as fractional anisotropy, and "(film thickness T1 of first spacer forming film 4-film thickness T2 of second spacer forming film 5)/(film thickness T1 of first spacer forming film 4)" is defined as the film thickness incremental modulus of the first spacer forming film 4 to the second spacer forming film 5. In this case, an etching condition is adopted, where the vertical etching rate of the second spacer forming film 5 is allowed to be smaller than the vertical etching rate of the first spacer forming film 4 and also to be larger than a value obtained by multiplying the vertical etching rate of the first spacer forming film 4 by a smaller value of the fractional anisotropy and the film thickness incremental modulus. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of forming a spacer on a side wall of a convex portion.

  In recent years, with the development of information communication equipment, the processing capability required for LSIs has become higher and the speed of MIS field effect transistors has been increased. This increase in speed has been promoted mainly by miniaturization and densification of the structure. On the other hand, when manufacturing an LSI, a structure called a spacer is often formed on the side wall of the step. The spacer is used to control the horizontal position of the structure when a predetermined structure is formed in a self-aligned manner with respect to the structure having a step.

  For example, spacers are used to adjust the position of the tip of the source / drain and the gate electrode in the horizontal direction when forming the source / drain of the MIS field effect transistor in a self-aligned manner by ion implantation using the gate electrode as a mask. . This is because the ion-implanted impurities spread in the lateral direction during the heat treatment for activation.

  The spacer is a distance between the silicide and the gate electrode in the horizontal direction when forming a metal silicide in a self-aligned manner by combining metal sputtering and heat treatment on the source / drain of the MIS field effect transistor (referred to as a salicide process). It is also used when properly separating.

  In addition, the spacer may be formed on the side wall in the interior when it is desired to further narrow the width of the groove or hole formed by photolithography and etching.

  Documents related to forming the spacer include Patent Documents 1-8. Among these, in Patent Document 1 and Patent Document 2, a substrate protective film is provided for the purpose of solving the problem that the substrate is scraped when the spacer is formed on the side wall of the gate electrode of the MIS field effect transistor. A method of forming a spacer while protecting a substrate using the method is disclosed. Patent Document 3 discloses a method of forming a spacer using isotropic etching. In Patent Document 4, when a memory gate electrode having a MONOS structure is formed as a sidewall spacer of a control gate electrode, a spacer shape with a low shoulder drop is formed by providing a film with a slow etching rate on the surface of the film serving as the spacer. A method of realizing is disclosed.

JP 2005-159335 A JP 2005-277317 A Japanese Patent Application Laid-Open No. 07-245397 JP 2007-184323 A JP 2002-170941 A JP 2004-303799 A JP 2005-175378 A Japanese Patent Laid-Open No. 2006-100599

  As disclosed in Patent Document 1, it is a common problem when anisotropic etching is used that a base such as a substrate is scraped when a spacer is formed on a side wall. Therefore, if the method disclosed in Patent Document 1 or Patent Document 2 is used, the substrate will not be scraped, but a protective film remains on the substrate. When it is not preferable that such a protective film remains, the protective film cannot be used. As such a case, for example, a case where ion implantation of impurities is performed with very low energy can be considered.

  Patent Documents 1 and 2 also disclose a method of selectively removing only this protective film by wet etching. However, in this case, a notch is formed under the spacer. Therefore, this method cannot be used when it is not preferable that the notch is formed. An example of such a case is a self-aligned ion implantation process using a spacer as a mask. Specifically, since the maskability of the notch portion is deteriorated, there is a concern that unwanted impurities are implanted under the notch.

  In the spacer forming method disclosed in Patent Document 3, since isotropic etching is used, the etching selectivity between the spacer material and the substrate can be set very high. This is because a chemical etching method can be selected as an isotropic etching method. For this reason, the substrate can be prevented from being scraped without using a substrate protective film, but the spacer film must be deposited thicker than the middle width of the target spacer. Therefore, when the distance between the protrusions where the spacer is to be formed, the width of the groove, or the diameter of the hole is small, when the spacer is formed on the side wall inside the narrow groove, the distance between the protrusions, the groove, or the entire hole The spacer material is buried and the desired spacer shape cannot be obtained.

  In the case of the method disclosed in Patent Document 4, the side surfaces of the spacer are protected by a film having a low etching rate during etching. In Patent Document 4, anisotropic etching and a substrate protective film are combined, but it can be easily imagined that the present invention can be applied to the case where etching including an isotropic component is used. In that case, since there is little etching in the lateral direction, the difference between the deposited film thickness of the film serving as the spacer and the spacer middle width is small. That is, the spacer can be formed on the side wall even in the narrower groove. However, there is a problem that the lower part of the spacer which is not protected by the film having a low etching rate tends to be a notch shape.

  As described above, when the interval between the convex portions where the spacer is to be formed, the width of the groove, or the diameter of the hole is small, it is not necessary to use a substrate protective film and forming the spacer without causing a notch was difficult.

According to the present invention, forming a convex portion, a groove, or a hole;
Forming a first spacer forming film on the side wall of the convex part, on the side wall of the groove, or on the inner wall of the hole, and around the convex part, the groove, or the hole;
Forming a second spacer forming film on the first spacer forming film;
By performing anisotropic etching including an isotropic component on the second spacer forming film and the first spacer forming film, a spacer is formed on the side wall of the convex portion, the side wall of the groove, or the inner wall of the hole. Process,
With
In the anisotropic etching,
1- (ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction of the second spacer forming film in the anisotropic etching) is defined as the degree of anisotropy,
(Film thickness of the first spacer forming film−film thickness of the second spacer forming film) / (film thickness of the first spacer forming film) is a film thickness of the first spacer forming film with respect to the second spacer forming film. When defined as an incremental rate,
The etching rate in the vertical direction of the second spacer formation film is:
Smaller than the vertical etching rate of the first spacer forming film,
A method of manufacturing a semiconductor device is provided that is larger than a value obtained by multiplying the etching rate in the vertical direction of the first spacer formation film by the smaller one of the degree of anisotropy and the film thickness increment rate.

  According to the present invention, since the spacer materials having two kinds of etching rates are combined, the average etching rate in the vertical direction of the spacer materials can be higher than the average etching rate in the horizontal direction. This corresponds to increasing the substantial anisotropy of etching without changing the etching conditions.

  The etching rate in the vertical direction of the second spacer formation film is smaller than the etching rate in the vertical direction of the first spacer formation film. For this reason, when the first spacer formation film is etched into the shape of a spacer, the second spacer formation film can be said to function as a mask that covers a region that becomes the skirt of the spacer in the first spacer formation film. On the other hand, since the masking property of the second spacer formation film is not so high, the second spacer formation film is also etched slowly, so that the formation of notches in the portion constituted by the first spacer formation film is suppressed. .

  The vertical etching rate of the second spacer forming film is larger than the value obtained by multiplying the vertical etching rate of the first spacer forming film by the smaller of the anisotropy degree and the film thickness increment rate. By doing in this way, it can control that the spacer formed with the 1st spacer formation film becomes notch shape. The vertical etching rate of the second spacer forming film is equal to or less than the value obtained by multiplying the vertical etching rate of the first spacer forming film by the film thickness increment rate, and the vertical etching rate of the second spacer forming film is When the etching rate in the vertical direction of the first spacer formation film is equal to or less than the value obtained by multiplying the degree of anisotropy, the spacer formed by the first spacer formation film becomes a notch shape.

  Accordingly, it is not necessary to use a substrate protective film when forming the spacer, and it is possible to suppress the occurrence of notches.

According to the present invention, a step of forming a convex portion, a groove, or a hole;
Forming a first spacer forming film on the side wall of the convex part, on the side wall of the groove, or on the inner wall of the hole, and around the convex part, the groove, or the hole;
Forming a second spacer formation film thinner than the first spacer formation film on the first spacer formation film;
By performing anisotropic etching including an isotropic component on the second spacer forming film and the first spacer forming film, a spacer is formed on the side wall of the convex portion, the side wall of the groove, or the inner wall of the hole. Process,
With
In the anisotropic etching,
When 1- (ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction of the second spacer forming film in the anisotropic etching) is defined as the degree of anisotropy,
The etching rate in the vertical direction of the second spacer formation film is:
Smaller than the vertical etching rate of the first spacer forming film,
In addition, there is provided a method for manufacturing a semiconductor device having a value larger than a value obtained by multiplying the vertical etching rate of the first spacer formation film by the degree of anisotropy.

  According to the present invention, it is not necessary to use a substrate protective film and it is possible to suppress the occurrence of a notch when the distance between protrusions where a spacer is to be formed, the width of a groove, or the diameter of a hole is small.

It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 3rd Embodiment of this invention in process order. It is a graph which shows the film thickness design method of this invention. It is a graph which shows the effect of the present invention. It is a graph which shows the effect of the present invention. It is the graph which computed the effect of the present invention. It is the graph which showed the etching rate of the silicon nitride film used in the experiment which shows the effect of the present invention. It is the process procedure and cross-sectional image which showed the experimental result which concerns on the related technique 1. FIG. It is the process procedure and sectional drawing which showed the experimental result by 1st Embodiment. It is the graph which showed the effect of the experimental result by 1st Embodiment. FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Related Technology 1 in the order of steps. FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Related Technology 2 in the order of steps. FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Related Technology 3 in the order of steps.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In order to clarify the superiority of the embodiment of the present invention, first, problems when a side wall spacer is produced inside a narrow groove by using the manufacturing method shown in FIGS. 12, 13, and 14 will be described. In addition, when expressed as a groove, a structure in which columnar objects are arranged at a narrow interval can be included. In the present embodiment, description will be given by taking as an example a sidewall spacer of the gate electrode of the MIS field effect transistor. Note that the shape of the side wall spacers may be problematic. This is because the skirting width is likely to vary and causes manufacturing variations of semiconductor devices. These problems are particularly serious as the LSI structure is densified.

(Related technology 1)
FIG. 12 shows a method for producing sidewall spacers by pure anisotropic etching. First, as shown in FIG. 12A, a polysilicon gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. There are a plurality of polysilicon gate electrodes 3 arranged at intervals W. Next, a silicon nitride film 10 is deposited on the entire surface by a thickness T. Thereafter, as shown in FIG. 12B, the silicon nitride film 10 is etched under a condition of very high anisotropy by reactive ion etching (RIE) to form a sidewall spacer 10a.

  At this time, the middle width L of the side wall spacer 10 a is equal to the film thickness T on the side wall of the silicon nitride film 10. Therefore, the film thickness L of the silicon nitride film 10 does not have to be deposited thicker than the middle width T of the side wall spacer 10a, and the interval W between the polysilicon gate electrodes 3 can be reduced to nearly 2 × T.

  However, since etching conditions having very high anisotropy are used, the etching selectivity with respect to the silicon substrate 1 cannot be made sufficiently high, resulting in substrate scraping 1a as shown in FIG. Such substrate scraping 1a causes an increase in parasitic resistance, an increase in leakage current, or variation in electrical characteristics of the MIS field effect transistor. Therefore, it cannot be used for manufacturing a MIS field effect transistor in which such a problem becomes serious.

  In order to prevent the substrate scraping 1a, Patent Documents 1 and 2 disclose a method using a substrate protective film, but as described above, the substrate protective film may cause another problem. In particular, when impurities are introduced into the silicon substrate 1 by low energy ion implantation, there is a problem that impurities are wasted in the protective film.

(Related technology 2)
FIG. 13 shows a method for producing a sidewall spacer by the RIE method including an isotropic component. First, as shown in FIG. 13A, a polysilicon gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. There are a plurality of polysilicon gate electrodes 3 arranged at intervals W. Next, a silicon nitride film 11 is deposited on the entire surface by a thickness T. Thereafter, as shown in FIG. 13B, the silicon nitride film 11 is etched by a reactive ion etching (RIE) method under the conditions including an anisotropic component and an isotropic component. Etching is stopped when the silicon substrate 1 and the polysilicon gate electrode 3 become dewed, and the sidewall spacer 11a is formed.

  At this time, a chemical etchant component having a very high etching selectivity between the silicon nitride film 11 and the silicon substrate 1 can be selected as the isotropic component. Therefore, the silicon substrate 1 is hardly scraped.

  However, the etching of the isotropic component causes the etching of the silicon nitride film 11 to proceed in the horizontal direction, and the silicon nitride film 11 is also etched in the horizontal direction by k × T. Here, k is a ratio of the etching rate in the horizontal direction of the silicon nitride film 11 to the etching rate in the vertical direction and is a value less than 1. Since this value represents the magnitude of isotropic etching, it will be referred to as the isotropic degree in this specification. If (isotropic degree) = 1, it is complete isotropic etching. Also, 1-k represents the magnitude of anisotropy and is therefore called the degree of anisotropy. If (anisotropic degree) = 1, it is complete anisotropic etching.

Then, the middle width L of the side wall spacer 11a is
L = (1-k) × T
It becomes. That is, a value obtained by multiplying the deposited film thickness by the anisotropy degree. Accordingly, the deposited film thickness T of the silicon nitride film 11 required for forming the spacer having the middle width L is as follows:
T = L / (1-k)> L
It becomes. Therefore, the interval W between the polysilicon gate electrodes 3 cannot be narrower than 2 × T = 2 × L / (1-k). This is disadvantageous for forming the sidewall spacers of the polysilicon gate electrodes arranged at a narrow interval. In particular, it is not suitable for manufacturing an integrated circuit in which MIS field effect transistors are arranged at a high density.

(Related technology 3)
FIG. 14 shows a method of disposing a film having a slow etching rate on the outside as a material for the sidewall spacer. This is a method to which the method disclosed in Patent Document 4 is applied. First, as shown in FIG. 14A, a polysilicon gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. There are a plurality of polysilicon gate electrodes 3 arranged at intervals W. Next, a silicon nitride film 12 is deposited on the entire surface, and a silicon oxide film 13 is deposited thereon. Thereafter, as shown in FIG. 14B, the silicon oxide film 13 and the silicon nitride film 12 are etched by the RIE method including an anisotropic component and an isotropic component. At this time, a condition is selected in which the etching rate of the silicon oxide film 13 is slow and the etching rate of the silicon nitride film 12 is fast.

  First, the silicon oxide film 13 is etched, thereby forming a spacer 13a. Subsequently, the silicon nitride film 12 is etched to form a spacer 12a. At this time, the spacer 13a is also etched in the horizontal direction by the isotropic component of etching to become the spacer 13b. However, since the etching rate is low, the film thickness to be etched is small in the time until the etching of the silicon nitride film 12 having a high etching rate is completed.

  In this way, since the etching in the lateral direction can be reduced while using the etching including the isotropic component, it is possible to form the sidewall spacers of the polysilicon gate electrodes arranged at a narrower interval as compared with the related art 3. In addition, the shaving of the silicon substrate 1 can be sufficiently reduced.

  However, since the difference in etching rate between the silicon oxide film 13 and the silicon nitride film 12 is large, a notch 12b is formed below the spacer 13b. Therefore, this method cannot be used when it is not preferable that the notch is formed. For example, in the case of ion implantation, since the masking property of the notch portion is lowered, there is a concern that unwanted impurities are implanted under the notch.

  Next, an embodiment of the present invention will be described. According to the embodiment of the present invention, the method of forming the spacer on the side wall of the narrow groove of the semiconductor device is to deposit a film having a fast etching rate (R1) by the film thickness T1 on the side wall and the bottom surface of the groove, and then slowly on the film. In the case where the film having the etching rate (R2) is deposited by the film thickness T2, when the two films are processed into spacers by etching having an isotropic degree k, 0 <R2 <R1, and R2 The value of / R1 is set so as to be larger than the smaller one of the values of 1-k and 1-T2 / T1. Under such a condition range, it is possible to form a sidewall spacer in a narrower groove while using etching containing an isotropic component. In addition, there is no notch, and the silicon substrate scraping can be sufficiently reduced.

  That is, in the embodiment described below, first, a convex portion, a groove, or a hole is formed. Next, a first spacer forming film is formed on the side wall of the convex portion, the side wall of the groove, or the inner wall of the hole, and around the convex portion, the groove, or the hole. Next, a second spacer forming film is formed on the first spacer forming film. Next, the second spacer formation film and the first spacer formation film are anisotropically etched to form spacers on the side walls of the protrusions, the side walls of the grooves, or the inner walls of the holes.

  In the anisotropic etching described above, “1- (ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction of the second spacer forming film in anisotropic etching)” is defined as the degree of anisotropy, and “( The film thickness of the first spacer forming film−the film thickness of the second spacer forming film) / (the film thickness of the first spacer forming film) ”was defined as the film thickness increment rate of the first spacer forming film with respect to the second spacer forming film. Sometimes, the etching rate in the vertical direction of the second spacer forming film is smaller than the etching rate in the vertical direction of the first spacer forming film, and the vertical etching rate of the first spacer forming film has an anisotropy and a film thickness. Greater than the value multiplied by the smaller of the thickness increments. The necessity of this condition is shown in FIG.

  In the anisotropic etching described above, the etching rate in the vertical direction of the second spacer formation film is smaller than the etching rate in the vertical direction of the first spacer formation film and is different from the etching rate in the vertical direction of the first spacer formation film. It may be larger than the value multiplied by the degree of directivity. The necessity of this condition is shown in FIG.

  Next, embodiments of the present invention will be described in more detail using specific examples. In the following example, the side wall spacer is formed on the polysilicon gate electrode 3, but when the side wall spacer is formed on the side wall of the groove or the inner wall of the hole, it can be the same as the following example.

(Embodiment 1)
FIG. 1 is a diagram showing a first embodiment of the present invention. In this embodiment, a setting is made so that a silicon nitride film having a low etching rate is left after completion of the sidewall spacer. This is effective in the case where the lateral etching of the side wall spacer is anxious in a post process after the completion of the side wall spacer. For example, the side wall spacer recedes due to repeated wet cleaning processes.

First, as shown in FIG. 1A, a polysilicon gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. There are a plurality of polysilicon gate electrodes 3 arranged at intervals W. Next, on the entire surface, the silicon nitride film 4 (first spacer formation film) having a fast etching rate for each of the vertical component and the horizontal component is formed on the film thickness T1, and further, the etching rate is slow for each of the vertical component and the horizontal component. A silicon nitride film 5 (second spacer formation film) is deposited by a film thickness T2. The etching rate can be changed by changing the film formation temperature, for example. For example, the silicon nitride film 4 is formed at a first temperature, and the silicon nitride film 5 is formed at a second temperature higher than the first temperature. At this time, the etching rate of the silicon nitride film 5 is set to r times the etching rate of the silicon nitride film 4. r is a numerical value less than 1. That is, if the etching rate of the silicon nitride film 4 is R1, and the etching rate of the silicon nitride film 5 is R2,
R2 / R1 = r <1 (1)
It is.

  Next, as shown in FIG. 1B, the silicon nitride film 5 having a low etching rate is etched by an RIE method having an isotropic component and an isotropic component having an isotropic degree k, and a spacer 5a. Form. At this time, the etching of the silicon nitride film 5 proceeds in the horizontal direction by the etching with the isotropic component, and the silicon nitride film 5 is etched in the horizontal direction by k × T2. If the two films are at least the same material as shown in this example, k becomes almost the same value regardless of the film type.

  As an example, FIG. 8 shows the etching rates in the vertical direction and the horizontal direction of two types of silicon nitride films (low-temperature film-formed SiN and high-temperature film-formed SiN) used as experiments showing the effect of this embodiment. In any silicon nitride film (SiN), the value of the isotropic degree k is approximately 0.35. These silicon nitride films (SiN) were deposited using a chemical vapor deposition (CVD) method, and the etching rate could be continuously changed by changing the CVD temperature. In addition, the etching rate of the silicon nitride film can be changed by changing the deposition method.

  Subsequently, as shown in FIG. 1C, the silicon nitride film 4 is exposed by exposing the silicon nitride film 4 to a part of the silicon substrate 1 and the upper surface of the polysilicon gate electrode 3 by the RIE method comprising the same anisotropic component and isotropic component. Etching is performed until the spacer 4a is formed. Here, the etching is continuously performed on the silicon nitride film 5 and the silicon nitride film 4. At this time, the silicon nitride film 4 is also etched in the horizontal direction by k × T1 below the silicon nitride film 5 due to an isotropic component of etching. On the other hand, the spacer 5a is also etched in the horizontal direction to become the spacer 5b. Since this etching amount is r times the etching amount of the silicon nitride film 4 in the horizontal direction, it is k × T1 × r.

From these, the shape of the completed side wall spacer is as follows.
(Etching amount in the horizontal direction of the middle abdomen) = (soaking amount) = k × r × T1 + k × T2 (2)
(Horizontal etching amount of the silicon nitride film 4 below the silicon nitride film 5) = k × T1 (3)
(Medium width of side wall spacer) = (1−k × r) × T1 + (1−k) × T2 = L (4)

However, since it is necessary to leave the silicon nitride film 5 having a low etching rate after the sidewall spacer is completed,
(Etching amount in the horizontal direction of the middle abdomen) <(film thickness of the silicon nitride film 5) = T2 (5)
By substituting (2) for (5)
T2> k / (1-k) × r × T1 (6)
It becomes.

In order to prevent the notch shape,
(Horizontal etching amount in the middle part) ≧ (Horizontal etching amount of the silicon nitride film 4 below the silicon nitride film 5) (7)
By substituting (2) and (3) into (7),
T2 ≧ (1-r) × T1 (8)
It becomes.

  Here, from (1), (6), and (8), FIG. 4 illustrates the range of values of r (= R2 / R1) and T2 / T1 in the first embodiment. Based on this, FIG. 5 is a graph showing the sum T1 + T2 of the film thicknesses of the silicon nitride film having a high etching rate and the silicon nitride film having a low etching rate, with T2 / T1 as a variable. Note that the horizontal axis is logarithmic. This embodiment is in the range of AA ′ or BB ′ in FIG. 5, which corresponds to the state of AA ′ or BB ′ in FIG.

  According to FIG. 5, according to the present embodiment, the total thickness of the silicon nitride film compared to the case where the sidewall spacer is formed of a single layer of silicon nitride film (T2 / T1 = 0 or ∞) for the same side wall spacer middle width. It can be seen that the thickness T1 + T2 can be reduced. In addition, the value of the sidewall spacer can be reduced by this embodiment.

  This shows that it is possible to form sidewall spacers of polysilicon gate electrodes arranged at a narrower interval while using etching containing an isotropic component. In addition, there is no notch, and the silicon substrate scraping can be sufficiently reduced.

  9, FIG. 10 and FIG. 11 show the results of experiments conducted to show the effect of this example. As a silicon nitride film having a different etching rate, a silicon nitride film having an etching rate shown in FIG. 8 was used for the RIE used in this experiment.

  First, FIG. 9 shows a method for forming a sidewall spacer using a single-layer silicon nitride film and a cross-sectional observation image thereof according to Related Technique 2. The structure used in the experiment is slightly different from the embodiment shown in FIG. 1, but the method for forming the sidewall spacer is the same. According to the cross-sectional image of FIG. 9, when the related technique 2 was followed, a large skirt was observed, and the thickness of the deposited silicon nitride film was 1.6 times the middle width of the completed side wall spacer.

  On the other hand, according to FIG. 10, the sidewall spacer to which the present embodiment is applied has reduced skirting, and the total thickness of the deposited silicon nitride film is reduced to 1.4 times the middle width of the completed sidewall spacer. is doing. FIG. 11 is a graph summarizing these values. Although the calculated values and the experimental values are slightly different, the trends are almost the same, indicating the effect of this example.

(Embodiment 2)
FIG. 2 is a diagram showing a second embodiment of the present invention. In this embodiment, after the sidewall spacer is completed, the silicon nitride film having a slow etching rate is set to disappear. This is effective when it is not desired to leave a nitride film having a low etching rate. For example, the case where a nitride film having a low etching rate affects stress and reliability.

First, as shown in FIG. 2A, a polysilicon gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. There are a plurality of polysilicon gate electrodes 3 arranged at intervals W. Next, a silicon nitride film 6 having a high etching rate is deposited on the entire surface by a film thickness T1, and a silicon nitride film 7 having a low etching rate is deposited thereon by a film thickness T2. At this time, the etching rate of the silicon nitride film 7 is set to r times the etching rate of the silicon nitride film 6. r is a numerical value less than 1. That is, if the etching rate of the silicon nitride film 6 is R1, and the etching rate of the silicon nitride film 7 is R2,
R2 / R1 = r <1 ... (9)
It is.

  Next, as shown in FIG. 2B, the silicon nitride film 7 having a low etching rate is etched by the RIE method having an isotropic component and an anisotropic component having an isotropic degree k, and the spacer 7a. Form. At this time, the etching of the silicon nitride film 7 proceeds in the horizontal direction by the etching using the isotropic component, and the silicon nitride film 7 is etched in the horizontal direction by k × T2. If k is at least the same material, it will have almost the same value regardless of the film type. At this stage, the width of the spacer 7a is (1-k) × T2.

  Subsequently, as shown in FIG. 2C, etching is performed by the RIE method including the same anisotropic component and isotropic component until the spacer 7a disappears. Since the middle width of the spacer 7a is (1-k) * T2, the silicon nitride film 6 is etched by (1-k) * T2 / k / r in the vertical direction to form a silicon nitride film 6a. The remaining film thickness in the vertical direction of the silicon nitride film 6a is T1- (1-k) / k / r × T2.

  Further, the silicon nitride film 6a is etched by the RIE method comprising the same anisotropic component and isotropic component until the silicon substrate 1 and the polysilicon gate electrode 3 are exposed to form a spacer 6b. At this time, the etching of the silicon nitride film 6a also proceeds in the horizontal direction due to the isotropic component of the etching. Accordingly, the silicon nitride film 6a is also etched in the horizontal direction by k × T1- (1-k) / r × T2. On the other hand, since the etching amount in the horizontal direction of the silicon nitride film 6 below the silicon nitride film 7 is k times the film thickness T1 after all, it is finally k × T1.

From these, the shape of the completed side wall spacer is as follows.
(Etching amount in the horizontal direction of the middle abdomen) = (amount of skirting) = k × T1 + {1− (1−k) / r} × T2 (10)
(Horizontal etching amount of the silicon nitride film 6 below the silicon nitride film 7) = k × T1 (11)
(Medium width of side wall spacer) = (1−k) × T1 + (1−k) / r × T2 = L (12)

However, since the silicon nitride film with a slow etching rate disappears after the sidewall spacer is completed,
(Horizontal etching amount in the middle part) ≧ (film thickness of the silicon nitride film 7) = T2 (13)
From (10) and (13),
T2 ≦ k / (1-k) × r × T1 (14)
It is.

In order to prevent the notch shape,
(Horizontal etching amount in the middle part) ≧ (Horizontal etching amount of the silicon nitride film 6 below the silicon nitride film 7) (15)
From (10), (11), (15),
r ≧ 1-k (15)
It is.

  Here, from (9), (14), and (15), FIG. 4 illustrates the range of values of r (= R2 / R1) and T2 / T1 in the second embodiment.

  Based on this, FIG. 5 is a graph showing the sum T1 + T2 of the film thicknesses of the silicon nitride film having a high etching rate and the silicon nitride film having a low etching rate, with T2 / T1 as a variable. Note that the horizontal axis is logarithmic. This embodiment is within the range of A′-A ″ in FIG. 5, which corresponds to the state of A′-A ″ in FIG. 4.

  According to FIG. 5, according to the present embodiment, the total thickness of the silicon nitride film compared to the case where the sidewall spacer is formed of a single layer of silicon nitride film (T2 / T1 = 0 or ∞) for the same side wall spacer middle width. It can be seen that the thickness T1 + T2 can be reduced. In addition, the value of the sidewall spacer can be reduced by this embodiment.

  This shows that it is possible to form sidewall spacers of polysilicon gate electrodes arranged at a narrower interval while using etching containing an isotropic component. In addition, there is no notch, and the silicon substrate scraping can be sufficiently reduced.

(Embodiment 3)
FIG. 3 is a diagram showing a third embodiment of the present invention. In this embodiment, after the sidewall spacer is completed, the silicon nitride film having a low etching rate is set to be completely eliminated. This is a special case of the second embodiment.

First, as shown in FIG. 3A, a polysilicon gate electrode 3 is formed on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. There are a plurality of polysilicon gate electrodes 3 arranged at intervals W. Next, a silicon nitride film 8 having a high etching rate is deposited on the entire surface by a film thickness T1, and a silicon nitride film 9 having a low etching rate is deposited thereon by a film thickness T2. At this time, the etching rate of the silicon nitride film 9 is set to r times the etching rate of the silicon nitride film 8. r is a numerical value less than 1. That is, if the etching rate of the silicon nitride film 8 is R1, and the etching rate of the silicon nitride film 9 is R2,
R2 / R1 = r <1 ... (16)
It is.

  Next, as shown in FIG. 3B, the silicon nitride film 9 having a low etching rate is etched by the RIE method having an isotropic component and an isotropic component having an isotropic degree k, and a spacer 9a. Form. At this time, the etching of the silicon nitride film 9 proceeds in the horizontal direction by the etching with the isotropic component, and the silicon nitride film 9 is also etched in the horizontal direction by k × T2. If k is at least the same material, it will have almost the same value regardless of the film type. At this stage, the middle width of the spacer 9a is (1-k) × T2.

Subsequently, as shown in FIG. 3C, the silicon nitride film 8 is etched by the RIE method having the same anisotropic component and isotropic component until the silicon substrate 1 and the polysilicon gate electrode 3 are exposed. The spacer 8a is formed. At this time, the silicon nitride film 8 is also etched in the horizontal direction by k × T1 below the silicon nitride film 9 due to an isotropic component of etching. On the other hand, the spacer 9a is also etched in the horizontal direction. Since this etching amount is r times the etching amount of the silicon nitride film 8 in the horizontal direction, it is k × T1 × r. At this stage, the spacer 9a is eliminated. Here, since the middle width of the spacer 9a is (1-k) × T2,
T2 = k / (1-k) * r * T1 ... (17)
Set to be.

From these, the shape of the completed side wall spacer is as follows.
(Amount of etching in the horizontal direction of the middle abdomen) = (Amount of skirting) = T2 (18)
(Etching amount in the horizontal direction of the silicon nitride film 8 below the silicon nitride film 9) = k × T1 (19)
(Medium width of side wall spacer) = T1 = L (20)

In order to prevent the notch shape,
(Horizontal etching amount in the middle part) ≧ (Horizontal etching amount of the silicon nitride film 6 below the silicon nitride film 7) (21)
From (18), (19), (21)
T2 ≧ k × T1 (22)
It is.

  Here, FIG. 4 illustrates the range of the values of r (= R2 / R1) and T2 / T1 in Example 3 from (16), (17), and (22).

  Based on this, FIG. 5 is a graph showing the sum T1 + T2 of the film thicknesses of the silicon nitride film having a high etching rate and the silicon nitride film having a low etching rate, with T2 / T1 as a variable. Note that the horizontal axis is logarithmic. The present embodiment corresponds to A ′ in FIG. 5, which corresponds to the state A ′ in FIG.

  According to FIG. 5, according to the present embodiment, the total thickness of the silicon nitride film compared to the case where the sidewall spacer is formed of a single layer of silicon nitride film (T2 / T1 = 0 or ∞) for the same side wall spacer middle width. It can be seen that the thickness T1 + T2 can be reduced. Further, if the same value of r = R2 / R1, it is important that the value of T1 + T2 can be made as small as possible in the present embodiment. In addition, the value of the sidewall spacer skirting can be minimized in the present embodiment.

  This shows that it is possible to form sidewall spacers of polysilicon gate electrodes arranged at a narrower interval while using etching containing an isotropic component. In addition, there is no notch, and it is possible to sufficiently reduce the shaving of the silicon substrate.

(Summary of Examples)
Finally, Example 1, Example 2, and Example 3 will be summarized to describe the scope of the implementation conditions of the present invention and the most effective conditions.

  First, in the case of r <1-k, if the silicon nitride film having a slow etching rate is made too thin, a notch shape is obtained. According to FIG. 4, the condition that does not become a notch is “T2 / T1 ≧ 1-r”. At this time, only Example 1 can be implemented. Note that the sum T1 + T2 of the thicknesses of the two silicon nitride films can be minimized in the state of B ′, that is, in the case of “T2 / T1 = 1−r” from FIG. 5B. In this case, the trailing is also minimized. However, according to FIG. 4, since this condition is the last condition that does not become a notch shape, it is necessary to pay attention to variations in film thickness.

  A typical example of r <1-k corresponds to the case where the material is changed to a silicon oxide film or the like instead of the silicon nitride film having a low etching rate. In this case, r may be 0.1 or less. In general, T2 / T1 ≧ 1−r≈1, that is, the film thickness of the film having a low etching rate is larger than the film thickness of the film having a high etching rate. Must be set. In other words, if a very thin etch and “thin” film is placed on the outside, it means that it will almost always have a notch shape. This is shown in Related Art 3. In this respect, the numerical range given by the present invention is clearly different from the related art 3.

  Next, in the case of r ≧ 1-k, according to FIG. 4, no matter how T1 and T2 are selected, a notch shape is not obtained. This is because a condition in which the difference between the etching rates of the two silicon nitride films is relatively small is selected. Therefore, when it is desired to prevent a situation in which a notch shape is generated due to variations in film thickness, it is preferable to select a condition of r ≧ 1-k. In this case, it is preferable to set the film thickness so that there is no silicon nitride film having a slow etching rate at the end of etching. This corresponds to the third embodiment. In this case, the side wall spacer can be formed between the narrowest gate electrodes under the given two silicon nitride films, the etching conditions, and the width of the completed side wall spacer, and the trailing edge can be minimized.

  FIG. 6 shows the r dependence of the minimum value of the sum T1 + T2 of the thicknesses of the two silicon nitride films and the minimum value of the trailing value. This is realized in the state of A ′ or B ′ in FIGS. According to this, it can be seen that the smaller the r is, that is, the greater the difference between the etching rates of the two nitride films is, the more the sum of the film thicknesses and the skirting can be reduced. FIG. 7 shows the calculation result when the isotropic degree k = 0.4. According to this, the sum of the film thicknesses of the two silicon nitride films is 1 compared to the film thickness of 1.67 × L when the spacer is formed of a single layer film of the silicon nitride film (R1 = R2, ie, r = 1). It can be seen that it can be reduced to 4 × L or less. This means that the width of the groove in which the side wall spacer can be formed can be reduced by 16% or more.

  In this embodiment, the gate electrode of the MIS type field effect transistor is adopted as the structure having a step, but when the spacer is formed on the side wall in the narrow groove, the spacer is formed inside the contact hole or the wiring via. It is also applicable to Further, although the silicon nitride film is used as the spacer material, a silicon oxide film or a combination of a silicon oxide film and a silicon nitride film may be used.

  In addition, although RIE is adopted as an etching method, even a completely isotropic etching (k = 1) is effective. In actual RIE, the etching procedure is often composed of a plurality of steps such as a breakthrough step, a main etching step, an overetching step, etc., but the present invention is adopted in any one step. If it is done, there is an effect.

  It is assumed that the ratio k of the horizontal etching rate to the vertical etching rate is the same for a nitride film having a fast etching rate and a nitride film having a slow etching rate, but this need not be exactly equal, It may be slightly different. What is important is the design method of the present invention, as long as the deviation of the k value can be absorbed by adjusting other parameters.

  In the case of Example 1, the structure according to the embodiment of the present invention is confirmed by combining the observation of the cross-sectional shape of the sidewall spacer with a transmission electron microscope or the like and the composition analysis with EDX (energy dispersive X-ray analyzer) or the like. Is possible. In the case of Example 2, although somewhat difficult, if there is a step on the side surface of the side wall spacer, it can be confirmed by observing the cross-sectional shape with a transmission electron microscope or the like.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3 Polysilicon gate electrode 4 Silicon nitride film 4a Silicon nitride film spacer 5 Silicon nitride film 5a, 3b Silicon nitride film spacer 6 Silicon nitride film 6a Silicon nitride film 6b Silicon nitride film spacer 7 Silicon nitride film 7a Silicon nitride film spacer 8 Silicon nitride film 8a Silicon nitride film spacer 9 Silicon nitride film 9a Silicon nitride film spacer 10 Silicon nitride film 10a Silicon nitride film spacer 11 Silicon nitride film 11a Side wall spacer 12 Silicon nitride film 12a Side wall spacer 12b Notch 13 Silicon oxide Film 13a, 13b Silicon oxide film spacer

Claims (7)

Forming a convex portion, a groove, or a hole;
Forming a first spacer forming film on the side wall of the convex part, on the side wall of the groove, or on the inner wall of the hole, and around the convex part, the groove, or the hole;
Forming a second spacer forming film on the first spacer forming film;
By performing anisotropic etching including an isotropic component on the second spacer forming film and the first spacer forming film, a spacer is formed on the side wall of the convex portion, the side wall of the groove, or the inner wall of the hole. Process,
With
In the anisotropic etching,
1- (ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction of the second spacer forming film in the anisotropic etching) is defined as the degree of anisotropy,
(Film thickness of the first spacer forming film−film thickness of the second spacer forming film) / (film thickness of the first spacer forming film) is a film thickness of the first spacer forming film with respect to the second spacer forming film. When defined as an incremental rate,
The etching rate in the vertical direction of the second spacer formation film is:
Smaller than the vertical etching rate of the first spacer forming film,
And a method of manufacturing a semiconductor device having a value larger than a value obtained by multiplying an etching rate in a vertical direction of the first spacer formation film by a smaller one of the degree of anisotropy and the film thickness increment rate. Forming a convex portion, a groove, or a hole;
Forming a first spacer forming film on the side wall of the convex part, on the side wall of the groove, or on the inner wall of the hole, and around the convex part, the groove, or the hole;
Forming a second spacer formation film thinner than the first spacer formation film on the first spacer formation film;
By performing anisotropic etching including an isotropic component on the second spacer forming film and the first spacer forming film, a spacer is formed on the side wall of the convex portion, the side wall of the groove, or the inner wall of the hole. Process,
With
In the anisotropic etching,
When 1- (ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction of the second spacer forming film in the anisotropic etching) is defined as the degree of anisotropy,
The etching rate in the vertical direction of the second spacer formation film is:
Smaller than the vertical etching rate of the first spacer forming film,
And a method of manufacturing a semiconductor device having a value larger than a value obtained by multiplying a vertical etching rate of the first spacer formation film by the degree of anisotropy. In the manufacturing method of the semiconductor device according to claim 2,
When the ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction of the second spacer forming film in the anisotropic etching is defined as the isotropic degree in the anisotropic etching,
The etching rate in the vertical direction of the second spacer forming film is different from the etching rate in the vertical direction of the first spacer forming film in the ratio of the film thickness of the second spacer forming film to the first spacer forming film, and the difference in the etching rate. A method of manufacturing a semiconductor device, which is equal to a value obtained by multiplying the respective degrees of isotropicity and further divided by the degree of isotropicity. In the manufacturing method of the semiconductor device as described in any one of Claims 1-3,
The method of manufacturing a semiconductor device, wherein the first spacer formation film and the second spacer formation film are formed of the same element. In the manufacturing method of the semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the first spacer formation film and the second spacer formation film are formed at different substrate temperatures. In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the first spacer formation film is formed at a lower substrate temperature than the second spacer formation film. In the manufacturing method of the semiconductor device as described in any one of Claims 1-6,
A method of manufacturing a semiconductor device, wherein the anisotropic etching is continuously performed on the second spacer forming film and the first spacer forming film.

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