JP2011091159A - Horizontal semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of prohibiting a decrease of a breakdown voltage of a semiconductor device while reducing the number of concentration regions with different impurity concentrations formed in a semiconductor layer. <P>SOLUTION: A drift region 12 provided between a well region 56 and a body region 26 includes a first layer 30 and a second layer 40. The impurity concentration in the second layer 40 is higher than that in the first layer 30. The second layer 40 is provided in contact with the well region 56 on a part of a top surface of a buried insulating layer 52, and has a plurality of concentration regions 41-43 of which impurity concentration is different from one another, the plurality of concentration regions 41-43 being arranged in the increasing order of the impurity concentration from the side of the body region 26 to the side of the well region 56. The first layer 30 is a part of the drift region 12 where the second layer 40 is not formed. The impurity concentration in the first layer 30 is uniform. The first layer 30 includes a first portion 31 and the like and a second region 32 and the like with a layer thickness smaller than that of the first portion 31 and the like arranged alternately. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a horizontal semiconductor device and a method for manufacturing the same.

  Patent Document 1 discloses a lateral semiconductor device previously proposed by the present inventors. Patent Document 1 discloses a lateral LDMOS (Laterally Diffused MOS) as an example of a lateral semiconductor device. This lateral LDMOS is configured such that by providing a buried diffusion layer in the drift region, the impurity concentration of the drift region increases laterally from the source side toward the drain side. Specifically, the buried diffusion layer provided on the back surface side of the drift region has seven concentration regions having different impurity concentrations, and these seven concentration regions are laterally directed from the source side to the drain side. Are arranged in order of increasing impurity concentration. As a result, an eight-step concentration gradient in which the impurity concentration increases in order from the source side to the drain side is provided in the drift region including the portion where the buried diffusion layer is not provided. Thus, when the impurity concentration in the drift region increases in the lateral direction, the electric field distribution in the drift region can be made uniform in the lateral direction in the off state. Thereby, the breakdown voltage of the semiconductor device can be improved.

JP 2007-173422 A

  When a plurality of concentration regions having different impurity concentrations are provided in the semiconductor layer as in the semiconductor device of Patent Document 1, it is necessary to change the concentration of impurities introduced for each concentration region. For this reason, there is a problem that the number of impurity implantation steps increases as the number of concentration regions having different impurity concentrations increases. On the other hand, if the number of concentration regions having different impurity concentrations is reduced, the number of impurity implantation steps can be reduced, but the electrolytic distribution in the semiconductor layer cannot be made uniform in the lateral direction. As a result, there is a problem that the breakdown voltage of the semiconductor device is lowered.

  The present specification provides a technique capable of suppressing a decrease in breakdown voltage of a semiconductor device while reducing the number of concentration regions having different impurity concentrations formed in a semiconductor layer.

  The lateral semiconductor device disclosed in this specification includes a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, and a first conductivity type third semiconductor region. The first semiconductor region is provided in a depth range including the surface of the semiconductor layer. The second semiconductor region is spaced apart from the first semiconductor region and provided in a depth range including the surface of the semiconductor layer. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region in a depth range in contact with the buried insulating layer from the surface of the semiconductor layer, and the first semiconductor region is separated from the second semiconductor region. is doing. The third semiconductor region has a first layer and a second layer extending along a first direction connecting the first semiconductor region and the second semiconductor region. The second layer has an impurity concentration higher than that of the first layer, is provided on a part of the surface of the buried insulating layer and is in contact with the first semiconductor region, and has a plurality of concentration regions having different impurity concentrations. is doing. The plurality of concentration regions are arranged in order of increasing impurity concentration from the second semiconductor region side toward the first semiconductor region side. The first layer is provided on the second layer in the range where the second layer is provided, and is provided on the buried insulating layer in the other ranges, and the impurity concentration is made uniform in the first direction. Within the range of the first direction in which at least one concentration region of the plurality of concentration regions of the second layer is provided, the first layer includes a first portion disposed on the first semiconductor region side, and a second portion The second portion is disposed on the semiconductor region side and has a layer thickness thinner than that of the first portion.

  According to this configuration, since the layer thickness of the second portion of the first layer is formed thinner than the layer thickness of the first portion of the first layer, the layer thickness is included in the second portion of the first layer. The total amount of impurities is less than the total amount of impurities in the first portion of the first layer. As a result, even if the concentration region of the second layer where the first portion and the second portion of the first layer are in contact with each other has the same concentration, 2 between the second portion of the first layer and the first portion of the first layer is 2 A step concentration gradient is formed. The first portion of the first layer is disposed on the first semiconductor region side, and the second portion of the second layer is disposed on the second semiconductor region side. Therefore, a two-stage concentration gradient in which the impurity concentration increases from the second semiconductor region side toward the first semiconductor region side is formed within the range where one concentration region of the second layer is provided. Accordingly, it is possible to suppress the breakdown voltage of the semiconductor device from being lowered while reducing the number of concentration regions having different impurity concentrations formed in the semiconductor layer.

  Within each range in the first direction in which each of the plurality of concentration regions of the second layer is provided, the first layer is disposed on the first semiconductor region side and on the second semiconductor region side. You may have the 2nd part arrange | positioned and the layer thickness is made thinner than the 1st part. According to this configuration, for example, if the second layer includes three concentration regions, a six-step concentration gradient is provided. A reduction in the breakdown voltage of the semiconductor device can be effectively suppressed while reducing the number of concentration regions having different impurity concentrations formed in the semiconductor layer.

  Within the range of the first direction in which the first layer and the buried insulating layer are in contact, the first layer is disposed on the first semiconductor region side, on the second semiconductor region side and on the second semiconductor region side. You may have the 2nd part by which layer thickness was made thinner than 1 part. According to this configuration, a two-stage concentration gradient is formed even in a portion where the second layer is not formed. A reduction in the breakdown voltage of the semiconductor device can be effectively suppressed while reducing the number of concentration regions having different impurity concentrations formed in the semiconductor layer.

  A first surface insulating layer may be provided on the surface side of each of the first portions. A second surface insulating layer may be provided on the surface side of each of the second portions. The thickness of the first surface insulating layer may be made thinner than the thickness of the second surface insulating layer.

  A method for manufacturing a lateral semiconductor device disclosed in this specification includes a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating layer. This is a method for manufacturing a horizontal semiconductor device. In this method, a first step of forming a first portion having a large thickness and a second portion having a small thickness on a semiconductor layer are arranged in a predetermined direction, and a first portion and a second portion adjacent to each other after the first step. And a second step of introducing an impurity with the same concentration into the region including the portion.

  According to this manufacturing method, in the first step, a two-stage concentration gradient is formed between the second portion having a thin layer thickness and the first portion having a thick layer thickness. Further, in the second step, the adjacent first portions are adjacent to each other. A concentration region having the same concentration is formed in a region including the portion and the second portion. As a result, a two-stage concentration gradient is formed on one concentration region. A reduction in the breakdown voltage of the semiconductor device can be suppressed while reducing the number of concentration regions having different impurity concentrations formed in the semiconductor layer.

  According to the present invention, it is possible to suppress the breakdown voltage of the semiconductor device from being lowered while reducing the number of concentration regions having different impurity concentrations formed in the semiconductor layer.

2 illustrates a cross-sectional view of a main part of a semiconductor device. The manufacturing process of a semiconductor device is shown (1). The manufacturing process of a semiconductor device is shown (2). The manufacturing process of a semiconductor device is shown (3). The manufacturing process of a semiconductor device is shown (4). The manufacturing process of a semiconductor device is shown (5).

The features of the embodiments described below are listed below.
(Feature 1) The semiconductor device is an n-type lateral LDMOS.
(Feature 2) The first semiconductor region is an n-type well region. The second semiconductor region is a p-type body region. The third semiconductor region is an n-type drift region.
(Feature 3) An n-type top layer containing an n-type impurity at a low concentration may be provided on the surface side of the first portion.
(Feature 4) A p-type top layer containing p-type impurities at a low concentration may be provided on the surface side of the first portion.
(Feature 5) A p-type top layer containing a high concentration of p-type impurities may be provided on the surface side of the first portion. In that case, the first portion on the second semiconductor region side and the second portion on the first semiconductor region side within each horizontal range in which each of the plurality of concentration regions of the second layer is provided in the first layer. , May be arranged respectively.
(Feature 6) The semiconductor device is not limited to an n-type lateral LDMOS, but any lateral type using an SOI substrate, such as a p-type lateral LDMOS, an n-type or p-type lateral LIGBT (Lateral Insulated Gate Bipolar Transistor), or a lateral diode. The high breakdown voltage element may be used.

(First embodiment)
FIG. 1 schematically shows a cross-sectional view of the main part of the semiconductor device 10. The semiconductor device 10 includes a laminated substrate 57 in which a p-type semiconductor substrate 50, a buried insulating layer 52 provided on the semiconductor substrate 50, and a semiconductor layer 54 provided on the buried insulating layer 52 are laminated. I have. The main material of the semiconductor substrate 50 is silicon, and the impurity concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ . The semiconductor substrate 50 is fixed to the ground potential. The main material of the buried insulating layer 52 is silicon oxide, and the thickness thereof is approximately 4 μm. The main material of the semiconductor layer 54 is silicon, and the impurity concentration before the semiconductor structure is built is adjusted to about 1 × 10 ¹⁵ cm ⁻³ . The semiconductor device 10 is manufactured, for example, by using an SOI (Silicon On Insulator) substrate in which an insulating layer is inserted between a silicon substrate and a surface silicon layer (semiconductor layer), and implanting impurities into the semiconductor layer. The

The semiconductor device 10 is an n-type lateral LDMOS, and is provided with an n-type well region 56, a p-type body region 26, and an n-type drift region 12. In this embodiment, the well region 56 is separated from the body region 26 by the drift region 12, and is provided in a depth range from the surface of the semiconductor layer 54 to the buried insulating layer 52. A drain region 58 is provided inside the well region 56. The drain region 58 is provided in a range including a part of the surface of the semiconductor layer 54. The drain region 58 is connected to the drain electrode 2. The drain region 58 is surrounded by the well region 56, and the drain region 58 and the drift region 12 are separated by the well region 56. Here, the impurity concentration of the well region 56 is adjusted to approximately 5 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the drain region 58 is adjusted to about 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

In the present embodiment, the body region 26 is provided in a depth range in contact with the buried insulating layer 52 from the surface of the semiconductor layer 54. An n ⁺ type source region 24 is provided in the body region 26. The source region 24 is provided in a range including a part of the surface of the semiconductor layer 54. The source region 24 is surrounded by the body region 26, and the source region 24 and the drift region 12 are separated by the body region 26. A body contact region 22 is provided in the body region 26. The body contact region 22 is provided in a range including a part of the surface of the semiconductor layer 54. Here, the impurity concentration of the body region 26 is adjusted to approximately 5 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the source region 24 is adjusted to approximately 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . The impurity concentration of the body contact region 22 is adjusted to approximately 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ .

In the body region 26, the gate polysilicon 14 is opposed to the portion separating the source region 24 and the drift region 12 through the gate insulating film 16 a. The gate polysilicon 14 is polycrystalline silicon, and an impurity (phosphorus) is ion-implanted. Since the impurity concentration of the gate polysilicon 14 is adjusted to about 1 × 10 ²⁰ cm ⁻³ , the gate polysilicon 14 can be regarded as a conductor. A gate electrode 18 is connected to the gate polysilicon 14.

  As described above, the drift region 12 is provided between the well region 56 and the body region 26. The drift region 12 is provided in a depth range in contact with the buried insulating layer 52 from the surface of the semiconductor layer 54. On the surface of the drift region 12, gate insulating films 16a to 16e and field insulating layers 6a to 6d are provided alternately. Polysilicon 15a to 15d are provided on the surfaces of the gate insulating films 16a to 16e. The ends of the polysilicons 15a to 15d are provided so as to cover a part of the surface side of the field insulating layers 6a to 6d. Each field insulating layer 6a-6d is provided to have a thickness greater than that of adjacent gate insulating films 16a-16e. The lower ends of the field insulating layers 6 a to 6 d are provided so as to enter the inside of the drift region 12.

The drift region 12 has a first layer 30 and a second layer 40 extending in the lateral direction. In the drift region 12, a range where the impurity (phosphorus) is ion-implanted is the second layer 40, and a range where the impurity is not ion-implanted is the first layer 30. The impurity concentration of the first layer 30 is uniform in the lateral direction and is approximately 1 × 10 ¹⁵ cm ⁻³ . The second layer 40 contains impurities at a higher concentration than the first layer 30.

First, the second layer 40 will be described in detail. The second layer 40 is provided on the surface of the buried insulating layer 52, and one end thereof is in contact with the well region 56. Impurities are not ion-implanted in the vicinity of the body region 26 in contact with the surface of the buried insulating layer 52 in the drift region 12, and the second layer 40 is not formed. The second layer 40 includes three concentration regions 41, 42, and 43 arranged in order of increasing impurity concentration from the body region 26 side toward the well region 56 side. That is, the impurity concentration increases in the order of the concentration regions 41, 42, and 43. The second layer 40 can be formed by two ion implantations. Although a detailed manufacturing method will be described later, first, phosphorus ions are implanted into the concentration regions 41 and 43 at a dose of 1 × 10 ¹² cm ⁻² and an acceleration voltage of 1.4 MeV. Next, phosphorus ions are implanted into the concentration regions 42 and 43 at a dose of 2 × 10 ¹² cm ⁻² and an acceleration voltage of 1.4 MeV. As a result, the ion implantation doses of the concentration regions 41, 42, and 43 are “1 × 10 ¹² cm ⁻² ”, “2 × 10 ¹² cm ⁻² ”, and “3 × 10 ¹² cm ⁻² ”, respectively. The ion implantation dose in the concentration regions 41 to 43 changes by 1 × 10 ¹² cm ⁻² . In the present embodiment, the impurity concentration of the second layer 40 increases discontinuously toward the well region 56 side (stepwise), but the impurity concentration of the second layer 40 faces the well region 56 side. May increase continuously.

  Next, the first layer 30 will be described in detail. As described above, the first layer 30 is provided in the drift region 12 in a range where the second layer 40 is not formed. That is, the first layer 30 is provided on the second layer 40 in the range where the second layer 40 is provided, and is provided on the buried insulating layer 52 in other ranges. In the first layer 30, the first portions 31, 33, 35, 37, 39 and the second portions 32, 34, 36, 38 are alternately arranged in the lateral direction from the body region 26 side to the well region 56 side. Is arranged. The first portions 31 to 39 are formed thicker than the second portions 32 to 38. In other words, the first layer 30 includes first portions 31 to 39 having a large thickness and second portions 32 to 38 having a small thickness. On the surfaces of the first portions 31 to 39, the above-described gate insulating films 16a to 16e are formed. On the surfaces of the second portions 32 to 38, the above-described field insulating layers 6a to 6d are formed. As described above, the impurity concentration of the first layer 30 is uniform, but the second portions 32 to 38 have a thinner layer thickness than the first portions 31 to 39, and therefore the total amount of impurities is the first portions 31 to 39. Less than Therefore, a two-stage concentration gradient is formed between the adjacent first portions 31 to 39 and second portions 32 to 38.

  A second portion 34 and a first portion 35 are provided above the concentration region 41 of the second layer 40. The second portion 34 is provided on the body region 26 side above the concentration region 41. The end of the second portion 34 on the body region 26 side is at the same position as the end of the concentration region 41 on the body region 26 side in the lateral direction. On the other hand, the first portion 35 is provided in a portion on the well region 56 side above the concentration region 41. The end of the first portion 35 on the well region 56 side is at the same position as the end of the concentration region 41 on the well region 56 side in the lateral direction. Therefore, a two-stage concentration gradient in which the impurity concentration increases from the body region 26 side to the well region 56 side is formed above the concentration region 41. Similarly, a second portion 36 and a first portion 37 are provided above the concentration region 42. Further, a second portion 38 and a first portion 39 are provided above the concentration region 43. Accordingly, a two-stage concentration gradient in which the impurity concentration increases from the body region 26 side to the well region 56 side is formed above the concentration regions 41, 42, and 43 having the three-step impurity concentration. A total of 6 concentration gradients are provided. Further, even in the portion of the first layer 30 where the second layer 40 is not formed, the second portion 32 and the first portion 33 are provided with a two-stage concentration gradient. Accordingly, in the drift region 12, a total of eight stages of concentration gradients in which the impurity concentration increases from the body region 26 side toward the well region 56 side are provided.

  The operation of the semiconductor device 10 will be described. The turn-on of the semiconductor device 10 is realized by applying a positive voltage (positive bias) to the gate electrode 18 in a state where a voltage is applied so that the drain electrode 2 has a positive potential. When a positive voltage is applied to the gate electrode 18, an n-type channel is formed in the body region 26 adjacent to the gate polysilicon 14 via the gate insulating film 16. Electrons move from the source region 24 to the drift region 12 by this channel and flow to the drain region 58 through the drift region 12 and the well region 56. That is, a current flows from the drain region 58 to the source region 24.

  When a positive voltage is applied to the drain electrode 2 and no voltage is applied to the gate electrode 18, the semiconductor device 10 is in an off state, and a potential difference is generated from the drain region 58 toward the source region 24. In general, when an equipotential line indicating the electric field strength at a certain ratio is created, the density of the equipotential line becomes dense on the high voltage side and sparse on the low voltage side. However, in the semiconductor device 10, as described above, an eight-stage concentration gradient is provided in the drift region 12 so that the impurity concentration increases from the source region 24 side to the drain region 58 side. For this reason, the equipotential lines are evenly spaced across the entire lateral direction of the drift region 12, and it is possible to prevent the electric field from being locally concentrated in the drift region 12. Can be high. The potential difference in the lateral direction is maintained by depletion of the first layer 30 and the second layer 40 in the drift region 12. In the semiconductor device 10 of this embodiment, in order to keep the electric field in the lateral direction uniform, the impurity concentration of each region is set so that the space charge balance of the depleted region satisfies the following Expression 1.

  q × (Nsoi (x) + Nbl (x)) to (εox / Tox) × V (x) (Equation 1)

  In the above formula 1, x indicates a lateral distance from the body region 26 toward the well region 56. Nsoi (x) indicates the impurity concentration of the first layer 30 at the position of x. Nbl (x) indicates the impurity concentration of the second layer 40 at the position of x. εox represents the dielectric constant of the buried insulating layer 52, and Tox represents the thickness of the buried insulating layer 52. V (x) indicates the potential in the drift region 12 at the position of x. q represents an elementary charge.

  In the above formula 1, the left side indicates the amount of space charge of the first layer 30 and the second layer 40 that are depleted. The right side shows the amount of space charge stored in the MOS structure capacitor of the semiconductor device 10. In the semiconductor device 10 of this embodiment, V (x) in the right side rises from the body region 26 side toward the well region 56 side. The value on the left side also increases linearly from the body region 26 side toward the well region 56 side as V (x) increases.

  In the present embodiment, as described above, the first layer 30 and the second layer 40 are provided in the drift region 12. The second layer 40 is provided with three concentration regions 41, 42, and 43, and the first layer 30 is provided with first portions 31 and the like and second portions 32 and the like alternately. The semiconductor device 10 according to the present embodiment includes an eight-step impurity concentration gradient in the drift region 12. Although the concentration region of the second layer 40 is as small as three steps, an eight-step impurity concentration gradient can be provided in the drift region 12, and the breakdown voltage of the semiconductor device 10 can be effectively increased.

(Production method)
Next, a method for manufacturing the semiconductor device 10 according to the present embodiment will be described with reference to FIGS. First, as shown in FIG. 2, a laminated substrate 57 in which a semiconductor substrate 50, a buried insulating layer 52, and a semiconductor layer 54 are laminated is prepared. Specifically, first, the semiconductor substrate 50 containing a high concentration of p-type impurities is wet-oxidized to form a buried insulating layer 52 having a thickness of about 4 μm on the surface of the semiconductor substrate 50. The conditions for wet oxidation are set at 1200 ° C. for 15 hours. Next, a semiconductor layer having a resistivity of about 4.5 Ωcm is bonded to the surface of the buried insulating layer 52. The buried insulating layer 52 and the semiconductor layer 54 can be firmly bonded by heat treatment at 1100 ° C. for 1 hour. Next, the semiconductor layer 54 is polished from the surface, and the thickness of the semiconductor layer 54 is adjusted to about 1.4 μm. The laminated substrate 57 is completed by the above steps.

  Next, as shown in FIG. 3, field insulating layers 6 a to 6 d are intermittently provided on the surface of the semiconductor layer 54. Specifically, first, a thermal oxide film and a nitride film (not shown) of about 30 nm are formed on the surface of the semiconductor layer 54 of the multilayer substrate 57 prepared in FIG. Next, the nitride film, the thermal oxide film, and the semiconductor layer 54 are removed from portions where the field insulating layers 6a to 6d are to be formed by a photolithography process and a dry etching process. The depth of the semiconductor layer 54 to be removed here is about 100 nm. Next, field insulating layers 6a to 6d having a layer thickness of about 500 nm are formed by wet oxidation. Next, the nitride film and the thermal oxide film are removed, and a sacrificial oxide film (not shown) is formed on the surface of the semiconductor layer 54 and the entire surfaces of the field insulating layers 6a to 6d. By forming the field insulating layers 6 a to 6 d, the thick first portions 31 to 39 and the thin second portions 32 to 38 are alternately formed in the semiconductor layer 54.

  Next, with reference to FIG. 4 and FIG. 5, a process of creating the second layer 40 will be described. The second layer 40 has three concentration regions 41 to 43 having different impurity concentrations. For the second layer 40, resist patterns 60 and 70 are formed using a photomask having two different patterns formed thereon, and impurities having different concentrations are introduced into the semiconductor layer 54 twice using the resist patterns 60 and 70. It is formed by ion implantation separately. Note that the amount of impurities implanted for ion implantation is changed by a power of two.

First, as shown in FIG. 4, a first resist pattern 60 is formed on the semiconductor layer 54 using a photomask (not shown). The first resist pattern 60 has openings 62 and 64 in ranges corresponding to the second portion 34 and the first portion 35, and the second portion 38 and the first portion 39. In the semiconductor layer 54, portions corresponding to the openings 62 and 64 are regions corresponding to the concentration regions 41 and 43. Next, phosphorus is ion-implanted into regions corresponding to the concentration regions 41 and 43 using the first resist pattern 60. That is, phosphorus having the same concentration is ion-implanted into the region composed of the adjacent second portion 34 and the first portion 35 and the region composed of the second portion 38 and the first portion 39. In the step of FIG. 4, the ion implantation conditions are 1.4 MeV and 1 × 10 ¹² cm ⁻² . After the ion implantation, the first resist pattern 60 is removed.

Next, as shown in FIG. 5, a second resist pattern 70 is formed on the semiconductor layer 54 using a photomask (not shown). The second resist pattern 70 has an opening 72 in a range corresponding to the region from the second portion 36 to the first portion 39. A portion of the semiconductor layer 54 corresponding to the opening 72 is a region corresponding to the concentration regions 42 and 43. Next, phosphorus is ion-implanted into regions corresponding to the concentration regions 42 and 43 using the first resist pattern 60. That is, phosphorus of the same concentration is ion-implanted into the region from the second portion 36 to the first portion 39. In the process of FIG. 5, the ion implantation conditions are 1.4 MeV and 2 × 10 ¹² cm ⁻² . Here, “2 × 10 ¹² cm ⁻² ” that is the ion implantation amount in the process of FIG. 5 is obtained by changing “1 × 10 ¹² cm ⁻² ” that is the ion implantation amount in the process of FIG. Amount.

By two ion implantation steps described above, the concentration region 41 of phosphorus is introduced into 1 × 10 ¹² cm ^-2, the density region 42 of phosphorus is introduced into 2 × 10 ¹² cm ^-2, the concentration region 43 3 × 10 ¹² cm ⁻² of phosphorus is introduced. As a result, the impurity concentration increases in the order of the concentration regions 41, 42, and 43. Through this step, the second layer 40 is formed in the semiconductor layer 54.

  Subsequently, as shown in FIG. 6, an n-type well region 56 and a p-type body region 26 are formed by repeating a photolithography process and an ion implantation process. The well region 56 and the body region 26 are produced by a low temperature process by performing multiple ion implantations. The well region 56 and the body region 26 are formed in a depth range that reaches the buried insulating layer 52 from the surface of the semiconductor layer 54. By this step, the drift region 12 is formed between the well region 56 and the body region 26, and the first layer 30 and the second layer 40 are defined in the drift region 12.

  A process for forming the subsequent surface structure can use a general CMOS manufacturing process. The semiconductor device 10 of FIG. 1 is completed through the above steps.

In the manufacturing method of the semiconductor device 10 of this embodiment, two concentration patterns 41, 42, 43 are formed by performing ion implantation twice using the two resist patterns 60, 70, and the field insulating layer 6a. ˜6d are intermittently provided, and first portions 31 to 39 having a large layer thickness and second portions 32 to 38 having a thin layer thickness are alternately formed in the first layer 30. As a result, an eight-stage concentration gradient can be formed in the drift region 12 by two ion implantations. In other words, by performing n−1 ion implantations using n−1 (n is an integer) photoresist, a 2 ⁿ step concentration gradient can be formed in the drift region 12. Since the number of ion implantations can be reduced, the manufacturing efficiency of the semiconductor device is improved and the cost is reduced.

(Second embodiment)
A second embodiment will be described. In the first embodiment described above, the layer thickness of the second portions 32 to 38 is made thinner than that of the first portions 31 to 39, whereby 2 between the adjacent first portions 31 to 39 and the second portions 32 to 38. A step concentration gradient was provided. On the other hand, in the present embodiment, in addition to making the layer thickness of the second portions 32 to 38 thinner than that of the first portions 31 to 39, n containing n-type impurities at a low concentration on the surface side of the first portions 31 to 39. A mold top layer is provided. By providing a low-concentration n-type top layer on the surface side of the first portions 31 to 39, the impurity concentration in the first portions 31 to 39 can be increased. The impurity concentration in the first portions 31 to 39 can be adjusted to an appropriate concentration, and the concentration gradient between the first portions 31 to 39 and the second portions 32 to 38 can be formed with high accuracy.

(Third embodiment)
In this embodiment, in addition to making the layer thickness of the second portions 32 to 38 thinner than that of the first portions 31 to 39, the p-type top containing p-type impurities at a low concentration on the surface side of the first portions 31 to 39. Provide a layer. By providing a low-concentration p-type top layer on the surface side of the first portions 31 to 39, the n-type impurity concentration of the first portions 31 to 39 can be reduced. The impurity concentration in the first portions 31 to 39 can be adjusted to an appropriate concentration, and the concentration gradient between the first portions 31 to 39 and the second portions 32 to 38 can be formed with high accuracy.

(Fourth embodiment)
In each of the above embodiments, the first portions 31 to 39 having a large layer thickness are formed so as to have an impurity concentration higher than that of the second portions 32 to 38 having a small layer thickness. However, in this embodiment, the first portions 31 to 39 having a large layer thickness are formed so as to have an impurity concentration lower than that of the second portions 32 to 38 having a small layer thickness. Specifically, a p-type top layer containing a high concentration of p-type impurities is provided on the surfaces of the first portions 31 to 39. By providing a high-concentration p-type top layer on the surface side of the first portions 31 to 39, the impurity concentration of the first portions 31 to 39 is greatly reduced to be lower than the impurity concentration of the second portions 32 to 38. Can do. Also by the method of the present embodiment, the concentration gradient between the first portions 31 to 39 and the second portions 32 to 38 can be formed with high accuracy. However, in the present embodiment, above the concentration regions 41, 42, and 43, the first portion having a low impurity concentration is disposed closer to the body region 26, and the second portion having a higher impurity concentration is disposed closer to the well region 56. Thus, it is necessary to replace the arrangement of the first parts 31 to 39 and the second parts 32 to 38 with the arrangement of each of the above embodiments.

(Modification)
In each of the above embodiments, the semiconductor device 10 has been described as an n-type lateral LDMOS. However, the semiconductor device 10 is not limited to an n-type lateral LDMOS, and any lateral type using an SOI substrate such as a p-type lateral LDMOS, an n-type or p-type lateral LIGBT (Lateral Insulated Gate Bipolar Transistor), or a lateral diode. A high withstand voltage element may be used.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2 Drain electrodes 6a to 6d Field insulating layer 10 Semiconductor device 12 Drift region (third semiconductor region)
14 gate polysilicon 15a-15d polysilicon 16a-16e gate insulating film 18 gate electrode 20 source electrode 22 body contact region 24 source region 26 body region (second semiconductor region)
30 First layer 31, 33, 35, 37, 39 First portion 32, 34, 36, 38 Second portion 40 Second layer 41, 42, 43 Concentration region 50 Semiconductor substrate 52 Embedded insulating layer 54 Semiconductor layer 56 Well region (First semiconductor region)
57 Multilayer substrate 58 Drain region

Claims (5)

A horizontal semiconductor device,
A semiconductor substrate;
A buried insulating layer formed on the semiconductor substrate;
A semiconductor layer formed on the buried insulating layer,
The semiconductor layer includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region, and a first conductivity type third semiconductor region;
The first semiconductor region is provided in a depth range including the surface of the semiconductor layer,
The second semiconductor region is spaced apart from the first semiconductor region and is provided in a depth range including the surface of the semiconductor layer,
The third semiconductor region is provided between the first semiconductor region and the second semiconductor region in a depth range in contact with the buried insulating layer from the surface of the semiconductor layer, and the first semiconductor region is separated from the second semiconductor region. Separated
The third semiconductor region has a first layer and a second layer extending along a first direction connecting the first semiconductor region and the second semiconductor region,
The second layer has a higher impurity concentration than the first layer, is provided on a part of the surface of the buried insulating layer, is in contact with the first semiconductor region, and has a plurality of different impurity concentrations. The plurality of concentration regions are arranged in order of increasing impurity concentration from the second semiconductor region side toward the first semiconductor region side,
The first layer is provided on the second layer in the range where the second layer is provided, and is provided on the buried insulating layer in the other range, and the impurity concentration is uniform in the first direction. ,
In the range of the first direction where at least one concentration region of the plurality of concentration regions of the second layer is provided, the first layer includes a first portion disposed on the first semiconductor region side, and , Having a second portion disposed on the second semiconductor region side and having a layer thickness thinner than that of the first portion,
Horizontal semiconductor device.   In each range of the first direction in which each of the plurality of concentration regions of the second layer is provided, the first layer includes a first portion disposed on the first semiconductor region side, and a second semiconductor The horizontal semiconductor device according to claim 1, further comprising a second portion that is disposed on the region side and has a thickness smaller than that of the first portion.   Within the range in the first direction where the first layer and the buried insulating layer are in contact, the first layer is disposed on the first semiconductor region side and the second semiconductor region side. The lateral semiconductor device according to claim 1, further comprising a second portion having a layer thickness smaller than that of the first portion.   A first surface insulating layer is provided on each surface side of the first part, and a second surface insulating layer is provided on each surface side of the second part; 3. The lateral semiconductor device according to claim 2, wherein the thickness of the first surface insulating layer is made thinner than the thickness of the second surface insulating layer. A method for manufacturing a lateral semiconductor device comprising a semiconductor substrate, a buried insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the buried insulating layer,
A first step of forming, in the semiconductor layer, a thick first portion and a thin second portion arranged in a predetermined direction;
A second step of introducing an impurity having the same concentration into a region including the first portion and the second portion adjacent to each other after the first step;
A method of manufacturing a horizontal semiconductor device.

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