JP3768198B2 - Semiconductor device - Google Patents

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Publication number
JP3768198B2
JP3768198B2 JP2003073356A JP2003073356A JP3768198B2 JP 3768198 B2 JP3768198 B2 JP 3768198B2 JP 2003073356 A JP2003073356 A JP 2003073356A JP 2003073356 A JP2003073356 A JP 2003073356A JP 3768198 B2 JP3768198 B2 JP 3768198B2
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Prior art keywords
diffusion layer
formed
type
gate electrode
source diffusion
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JP2004281864A (en
Inventor
宝昭 根来
幸司 野村
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株式会社リコー
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a MOS transistor and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, in the case of forming a fine MOS transistor (hereinafter also simply referred to as a transistor), the gate length has been reduced. However, the short channel effect of the transistor is large, and a method for suppressing the effect is important.
[0003]
As a method for suppressing the short channel effect, a method of forming a shallow source diffusion layer and a drain diffusion layer (see, for example, Patent Document 1 and Patent Document 2) and a method by embedding a gate electrode (for example, see Patent Document 3). ), A method using a structure having a gate electrode having a main gate and a sub-gate (see, for example, Patent Document 4) has been proposed.
These prior art transistors have a structure in which a source diffusion layer and a drain diffusion layer are formed on both sides of a gate electrode.
[0004]
27A and 27B are diagrams showing a conventional MOS transistor in which a source diffusion layer and a drain diffusion layer are formed on both sides of a gate electrode. FIG. 27A is a plan view, and FIG. 27B is an XX position in FIG. FIG. FIG. 27 shows three N-channel MOS transistors (hereinafter abbreviated as Nch transistors).
[0005]
A LOCOS (local oxidation of silicon) oxide film 3 for element isolation is formed on the surface of a P-type semiconductor substrate (Psub) 1. A field doped layer (also referred to as a channel stopper layer) 5 into which a P-type impurity is introduced is formed under the LOCOS oxide film 3.
A common P well region (Pwell) 100 is formed on the surface side of the semiconductor substrate 1 in the formation region of the three Nch transistors. Each Nch transistor formation region is surrounded by a LOCOS oxide film 3, and adjacent Nch transistor formation regions are separated by a LOCOS oxide film 3 and a P-type field doped layer 5.
[0006]
In each Nch transistor formation region, gate electrode 103 is formed on P well region 100 with gate oxide film 101 interposed. The gate electrode 103 is formed extending on the LOCOS oxide film 3.
A source diffusion layer 105 and a drain diffusion layer 107 into which an N-type impurity is implanted are formed on the surface side of the P well region 100 on both sides of the gate electrode 103. The source diffusion layer 105 and the drain diffusion layer 107 are formed in a self-aligned manner with respect to the gate electrode 103. The surface of the P well region 100 between the source diffusion layer 105 and the drain diffusion layer 107 under the gate electrode 103 becomes a channel region.
[0007]
Since the line width of the gate electrode 103 on the channel region is narrowed in order to realize miniaturization of the transistor, the contact region 109 for taking the potential of the gate electrode 103 is on the LOCOS oxide film 3 of the gate electrode 103. It is provided in the part.
[0008]
A contact region 111 for taking a potential is provided on the source diffusion layer 105, and a contact region 113 for taking a potential is provided on the drain diffusion layer 107. The contact regions 111 and 113 are not shown in FIG.
[0009]
In the conventional MOS transistor in which the source diffusion layer and the drain diffusion layer are formed on both sides of the gate electrode, the channel length that determines the transistor performance is determined by the processing accuracy of the gate electrode. In order to maintain this processing accuracy, very precise processing accuracy is required in the photolithography process and the etching process.
However, a problem is whether a fine transistor cannot be produced without using such a high-precision processing apparatus.
[0010]
[Patent Document 1]
JP 10-335484 A
[Patent Document 2]
Japanese Patent Laid-Open No. 2001-15737
[Patent Document 3]
Japanese Patent Laid-Open No. 5-167033
[Patent Document 4]
JP-A-5-315605
[0011]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor device including a MOS transistor that can be finely formed without using a high-precision processing apparatus, and a manufacturing method thereof.
[0012]
[Means for Solving the Problems]
  The first aspect of the semiconductor device of the present invention is:Second conductivity typeA source diffusion layer of a first conductivity type formed on a semiconductor substrate (including a case of a well in the present invention) and having the same potential as the semiconductor substrate, and a gate oxide film on the source diffusion layer The gate electrode is formed on the surface side of the source diffusion layer, and the gate oxide film and the source diffusion layer are adjacent to each other in the region below the gate electrode. The second conductivity type channel diffusion layer formed in a consistent manner and the first conductivity type drain diffusion layer formed in the channel diffusion layer are also included.That is, the channel diffusion layer is set to the same potential as the semiconductor substrate via the semiconductor substrate and the second conductivity type diffusion layer formed adjacent to the channel diffusion layer on the surface side of the peripheral portion of the source diffusion layer. ingA MOS transistor is provided.
[0013]
  Semiconductor device manufacturing methodOne caseIs for creating the first aspect of the semiconductor device of the present invention, from the following steps (A) (E)including.
(A)Second conductivity typeForming a first conductivity type source diffusion layer in a MOS transistor formation region of a semiconductor substrate;
(B) forming a second conductivity type diffusion layer adjacent to the semiconductor substrate on the surface side of the peripheral portion of the source diffusion layer;
(C) Forming a gate electrode on the central region of the source diffusion layer via a gate oxide film;
(D) Second conductivity type in a self-aligned manner with respect to the gate electrode so that a region where the gate oxide film and the source diffusion layer are adjacent to each other remains in the source diffusion layer in a region under the gate electrode. Channel diffusion layerThe end opposite to the gate electrode is adjacent to the second conductivity type diffusion layer.Forming step,
(E) Forming a first conductivity type drain diffusion layer in the channel diffusion layer;
[0014]
In the present invention, the semiconductor substrate includes not only the semiconductor substrate itself but also a semiconductor layer such as an epitaxial growth layer formed on the semiconductor substrate.
The first conductivity type is P-type or N-type, and the second conductivity type is N-type or P-type opposite to the first conductivity type.
[0015]
  First aspect of semiconductor device of the present invention and method of manufacturing a semiconductor deviceExample aboveThe channel length that determines the transistor performance is determined not by the processing accuracy of the gate electrode but by the length of the channel diffusion layer under the gate electrode. The length of the channel diffusion layer under the gate electrode is determined by the diffusion progress (diffusion depth) of the impurities constituting the channel diffusion layer, which are implanted in a self-aligned manner with respect to the gate electrode. Determined by diffusion time. Since the diffusion depth is proportional to the product of the diffusion coefficient and diffusion time due to temperature, the channel length can be controlled only by controlling the temperature and diffusion time. Compared to the processing accuracy determined by photoengraving and etching. Since the controllability is so good that it does not become, a MOS transistor with a fine rule can be stably manufactured.
[0016]
Furthermore, in the first aspect of the semiconductor device of the present invention, majority carriers are generated by the gate voltage near the surface of the source diffusion layer existing immediately below the gate electrode, and an inversion layer is generated in the channel diffusion layer. The number of majority carriers generated near the surface of the source diffusion layer existing immediately below the gate electrode is determined according to the surface area of the source diffusion layer immediately below the gate electrode and the gate oxide film capacitance. When the gate electric field is strong and the drain electric field is weak, the drift electric field in the inversion layer is weak, and the movement of majority carriers generated in the source diffusion layer is suppressed. For this reason, in the transistor in which the minority carrier, which is the carrier of the channel diffusion layer, flows into the source diffusion layer according to the amount of change of the generated majority carrier, lowers the junction barrier between the source and channel, and extremely shortens the channel length. Causes a bipolar operation in which minority carriers contribute to the operation, and causes an increase in current in this part. Thereafter, as the drain electric field becomes stronger, the drift electric field in the inversion layer becomes stronger, and the generated majority carriers are attracted to the drain side, and this effect is suppressed and normal MOS transistor operation is performed. Thus, although the structure has a large source resistance, the rise characteristic is good and the transient response characteristic of the MOS transistor can be improved, so that the power of the load characteristic can be reduced.
[0017]
  The second aspect of the semiconductor device of the present invention is:Second conductivity typeA source diffusion layer of a first conductivity type formed on a semiconductor substrate and having the same potential as that of the semiconductor substrate, and a gate formed inside a recess formed on the surface side of the source diffusion layer via a gate oxide film An electrode, a channel diffusion layer of a second conductivity type formed adjacent to the gate oxide film in a region shallower than the bottom of the gate electrode on the surface side of the source diffusion layer, and formed in the channel diffusion layer A drain diffusion layer of the first conductivity typeThat is, the channel diffusion layer is set to the same potential as the semiconductor substrate via the semiconductor substrate and the second conductivity type diffusion layer formed adjacent to the channel diffusion layer on the surface side of the peripheral portion of the source diffusion layer. ingA MOS transistor is provided.
[0018]
  Semiconductor device manufacturing methodOther examplesIs for creating the second aspect of the semiconductor device of the present invention, from the following steps (A) (F)including.
(A)Second conductivity typeForming a first conductivity type source diffusion layer in a MOS transistor formation region of a semiconductor substrate;
(B) forming a second conductivity type diffusion layer adjacent to the semiconductor substrate on the surface side of the peripheral portion of the source diffusion layer;
(C) A step of forming a gate electrode placement recess on the inner wall surface of the recess after forming a recess for disposing the gate electrode at a depth shallower than the source diffusion layer in the central region of the source diffusion layer;
(D) Forming a gate electrode by embedding a semiconductor material in the recess,
(E) A second conductivity type channel diffusion layer is formed in the source diffusion layer adjacent to the gate oxide film and at a depth shallower than the recess.The end opposite to the gate electrode is adjacent to the second conductivity type diffusion layer.Forming step,
(F) Forming a first conductivity type drain diffusion layer in the channel diffusion layer;
[0019]
  A second aspect of the semiconductor device of the present invention and a method of manufacturing the semiconductor deviceExample aboveThe channel length that determines the transistor performance is determined not by the processing accuracy of the gate electrode but by the length of the channel diffusion layer on the side surface of the gate electrode. The length of the channel diffusion layer on the side surface of the gate electrode is determined by the implantation depth and diffusion depth of the channel diffusion layer and the implantation depth and diffusion depth of the drain diffusion layer implanted from the surface of the semiconductor substrate. It is determined by the ion implantation conditions for forming the diffusion layer, the diffusion temperature, and the diffusion time. As described above, the diffusion depth has good controllability, and the implantation depth also has good controllability, so that a fine-rule MOS transistor can be stably formed.
[0020]
Further, in the second aspect of the semiconductor device of the present invention, the channel length is formed in the depth direction with respect to the channel length and the channel width, and only the channel width exists on the surface of the semiconductor substrate. In the transistor, the cell area can be reduced.
[0021]
Further, in the second aspect of the semiconductor device of the present invention, majority carriers are generated by the gate voltage in the region near the gate oxide film of the source diffusion layer, including the vicinity of the bottom of the recess for arranging the gate electrode, and inverted in the channel diffusion layer. Create a layer. The majority carriers can improve the transient response characteristics of the MOS transistor, as in the first embodiment, so that the power of the load characteristics can be reduced.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
In the semiconductor device according to the present invention, a first conductivity type having a first conductivity type impurity concentration lower than that of the drain diffusion layer adjacent to the drain diffusion layer in a region adjacent to the gate electrode in the channel diffusion layer. It is preferable to further include an impurity diffusion layer.
As a result, the depletion layer that extends into the channel diffusion layer when the drain voltage is applied extends into the drain diffusion layer (first conductivity type impurity diffusion layer), and the punch-through breakdown voltage can be improved.
[0023]
In the semiconductor device of the present invention, a contact region for taking the potential of the gate electrode may be provided on the gate electrode in the formation region of the gate oxide film. As a result, the area occupied by the transistor on the chip can be reduced.
[0024]
In the semiconductor device of the present invention, it is preferable that the gate electrode is disposed with a distance from an element isolation oxide film formed on the surface of the semiconductor substrate.
In general, a field doped layer having a conductivity type opposite to that of the source diffusion layer and the drain diffusion layer is formed under the element isolation oxide film to ensure element isolation. When the gate electrode is formed extending on the element isolation oxide film, a narrow channel effect occurs due to the diffusion of impurities from the field doped layer to the channel region when the channel width is reduced.
In this aspect, since the gate electrode is arranged with a distance from the element isolation oxide film, the narrow channel effect can be eliminated, for example, the transistor is miniaturized to the minimum dimension capable of forming the gate electrode and the drain diffusion layer, etc. In addition, a fine transistor can be formed.
[0025]
In the semiconductor device according to the present invention, when two or more MOS transistors are arranged, the source diffusion layer of the MOS transistors is preferably composed of a common source diffusion layer of the first conductivity type.
In the transistor constituting the semiconductor device of the present invention, since the source diffusion layer and the drain diffusion layer have only the drain diffusion layer on the surface side of the semiconductor substrate, each transistor can be obtained by sharing the source diffusion layer in two or more transistors. Can be reduced, and the chip area occupied by these transistors can be reduced.
[0026]
The semiconductor device of the present invention further includes a first conductivity type buried layer having a first conductivity type impurity concentration higher than that of the source diffusion layer at a position deeper than the channel diffusion layer in the source diffusion layer. Is preferred.
As a result, the diffusion resistance to the lead-out portion of the source electrode can be lowered, and the performance deterioration of the transistor due to the potential difference between the semiconductor substrate and the source diffusion layer can be prevented. This aspect is particularly effective when using a common source diffusion layer common to two or more transistors.
[0030]
In the semiconductor device of the present invention, when a CMOS (complementary MOS) is formed on the semiconductor substrate, the semiconductor device further includes a second MOS transistor formed with a reverse conductivity type to the MOS transistor. It can be formed in the first conductive type separation diffusion layer formed in a region different from the source diffusion layer.
Thereby, the MOS transistor and the second MOS transistor can be electrically separated, and a CMOS can be formed on the same semiconductor substrate.
[0032]
【Example】
1A and 1B are diagrams showing an embodiment of the first aspect of the semiconductor device of the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line AA in FIG. This embodiment is applied to an Nch transistor.
[0033]
  A LOCOS oxide film 3 for element isolation is formed on the surface of a P-type semiconductor substrate (Psub) 1. The LOCOS oxide film 3 has an opening 3a corresponding to the transistor formation region. P-type field doped layer in which P-type impurities are introduced under LOCOS oxide film 3(Second conductivity type diffusion layer)5 is formed. A P well region (Pwell) 7 is formed on the surface side of the semiconductor substrate 1. An N-type source diffusion layer (Nwell) 9 is formed in the P well region 7.
[0034]
On the N-type source diffusion layer 9, a band-like gate electrode 13 made of polysilicon into which an N-type impurity is introduced is formed through a gate oxide film 11 made of a silicon oxide film. The gate electrode 13 is formed at a distance from the LOCOS oxide film 3.
[0035]
Self-aligned with the gate electrode 13 so that a region where the gate oxide film 11 and the N-type source diffusion layer 9 are adjacent to each other remains in the region under the gate electrode 13 on the surface side of the N-type source diffusion layer 9. The formed P-type channel diffusion layer (Pbody) 15 is disposed. The P-type channel diffusion layer 15 is formed so as to surround the formation region of the gate electrode 13.
[0036]
In the P-type channel diffusion layer 15, an N-type drain diffusion layer (N +) 17 in which an N-type impurity is implanted is formed adjacent to one side surface of the gate electrode 13.
In this transistor, the surface side of the P-type channel diffusion layer 15 in the region between the N-type source diffusion layer 9 and the N-type drain diffusion layer 17 under the gate electrode 13 becomes a channel region.
[0037]
On the gate electrode 13 and the N-type drain diffusion layer 17, contact regions (not shown) for taking a potential are formed.
The P well region 7 and the N-type source diffusion layer 9 are provided with contact regions in regions not shown. Since the P-type channel diffusion layer 15 is electrically connected to the P-well region 7 through the P-type field doped layer 5, it has the same potential as the P-well region 7 and the semiconductor substrate 1.
[0038]
In this embodiment, for example, the gate length (width of the gate electrode 13) is about 0.4 to 0.6 μm (micrometer), the channel length is about 0.1 to 0.2 μm, and the thickness of the gate oxide film 11 is About 5-10 nm (nanometer), channel region concentration is 1.5 × 1018cm-3The concentration of the N-type drain diffusion layer 17 is about 5.0 × 1020cm-3Degree. The operating voltage of this transistor is about 3.0 V (volts) at maximum.
[0039]
In this embodiment, the channel length that determines the transistor performance is determined by the length of the P-type channel diffusion layer 15 under the gate electrode 13. The length of the P-type channel diffusion layer 15 below the gate electrode 13 is determined by how the diffusion of impurities constituting the channel diffusion layer 13 implanted in a self-aligned manner with respect to the gate electrode 13 is determined. And the diffusion time. Since the diffusion depth is proportional to the product of the diffusion coefficient and diffusion time due to temperature, the channel length can be controlled only by temperature control and diffusion time management. What is the processing accuracy determined by photoengraving and etching? Since the controllability is so good that it cannot be compared, a MOS transistor with a fine rule can be stably manufactured.
[0040]
FIG. 2 shows a sectional view of an embodiment in which the first aspect of the semiconductor device of the present invention is applied to a CMOS inverter. Parts having the same functions as those in FIG.
[0041]
A LOCOS oxide film 3 for element isolation is formed on the surface of a P-type semiconductor substrate (Psub) 1. A P-type field doped layer 5 is formed under the LOCOS oxide film 3 surrounding the Nch transistor formation region.
[0042]
In the Nch transistor formation region, the N-type source diffusion layer (Nwell) 9, the gate oxide film 11, the gate electrode 13, the P-type channel diffusion layer (Pbody) 15 and the N-type are formed in the same configuration as the embodiment shown in FIG. A drain diffusion layer (N +) 17 is formed to form an Nch transistor.
[0043]
In this embodiment, the P well region surrounding the Nch transistor formation region is omitted. The P-type channel diffusion layer 15 is electrically connected to the semiconductor substrate 1 through the P-type field dope layer 5 and has the same potential as the semiconductor substrate 1.
[0044]
  N-type field doped layer formed by introducing an N-type impurity under LOCOS oxide film 3 surrounding a formation region of a P-channel MOS transistor (hereinafter abbreviated as a Pch transistor) constituting the second MOS transistor(Second conductivity type diffusion layer)19 is formed. An N well region (separation diffusion layer, Nwell) 21 is formed on the surface side of the semiconductor substrate 1 in the Pch transistor formation region. A P-type source diffusion layer (Pwell) 23 is formed in the N well region 21.
[0045]
On the P-type source diffusion layer 23, a band-shaped gate electrode 27 made of polysilicon into which P-type impurities are introduced is formed via a gate oxide film 25 made of a silicon oxide film. The gate electrode 27 is formed at a distance from the LOCOS oxide film 3.
[0046]
Self-aligned with the gate electrode 27 so that a region where the gate oxide film 25 and the P-type source diffusion layer 23 are adjacent to each other remains in the region under the gate electrode 27 on the surface side of the P-type source diffusion layer 23. The formed N-type channel diffusion layer (Nbody) 29 is disposed. The N-type channel diffusion layer 29 is formed so as to surround the formation region of the gate electrode 27.
[0047]
In the N-type channel diffusion layer 29, a P-type drain diffusion layer (P +) 31 in which a P-type impurity is implanted is formed adjacent to one side surface of the gate electrode 27.
In the Pch transistor, the surface side of the P-type channel diffusion layer 29 in the region between the P-type source diffusion layer 23 and the P-type drain diffusion layer 31 under the gate electrode 27 is a channel region.
[0048]
The plan view of the Pch transistor is the same as that of the Nch transistor shown in FIG. On the gate electrode 27 and the P-type drain diffusion layer 31, contact regions (not shown) for taking a potential are formed.
[0049]
The N well region 21 and the P-type source diffusion layer 23 are provided with contact regions in regions not shown. Since the N-type channel diffusion layer 29 is electrically connected to the N-well region 21 via the N-type field doped layer 19, it has the same potential as the N-well region 21.
[0050]
The gate electrodes 13 and 27 are connected to a common input terminal 33. The N-type drain diffusion layer 17 and the P-type drain diffusion layer 31 are connected to a common output terminal 35. N-type well diffusion layer 21 and P-type source diffusion layer 23 are connected to power supply potential 37. The semiconductor substrate 1 and the N-type source diffusion layer 9 are connected to the ground potential 39.
[0051]
As described above, the CMOS can be formed on the same semiconductor substrate 1 by forming the Pch transistor in the N-type well region 21 as the isolation diffusion layer and electrically isolating it from the semiconductor substrate 1. .
[0052]
  FIG. 3 shows a manufacturing method for manufacturing the CMOS shown in FIG.ExampleProcess sectional drawing of this is shown. With reference to FIG. 2 and FIG.ExampleWill be explained.
[0053]
(1) A P-type semiconductor substrate (Psub) 1 of about 20 Ωcm is prepared, and a 20 nm oxide film (not shown) is formed on the surface of the semiconductor substrate 1 by thermal oxidation. By means of photolithography and ion implantation, for example, phosphorus is accelerated into the formation region of the Nch transistor and the Pch transistor via the oxide film, the acceleration energy is about 150 KeV, and the dose amount is 5.0 × 10.12cm-2Inject at about the conditions. Heat treatment is performed at about 1150 ° C. for about 8 hours to form an N-type source diffusion layer (Nwell) 9 composed of an N-well region in the Nch transistor formation region, and an isolation diffusion layer in the Pch transistor formation region. The N well region (Nwell) 21 to be formed is formed (see (a)). The diffusion depths of the N type source diffusion layer 9 and the N well region 21 are both about 4 μm. The N-type source diffusion layer 9 and the N-well region 21 are formed with a space therebetween. Here, when the concentration of the source diffusion layer 9 is low in the Nch transistor formation region, phosphorus may be implanted into the surface to increase the concentration of the source diffusion layer 9.
[0054]
(2) After forming a resist pattern for defining the formation region of the source diffusion layer of the Pch transistor by photolithography, the acceleration energy of boron, for example, is about 50 KeV by ion implantation using the resist pattern as a mask. The dose is 5.0 × 1012cm-2Inject at about the conditions. After removing the resist pattern, heat treatment is performed under conditions of about 1150 ° C. and about 4 hours to form a P-type source diffusion layer (Pwell) 23 in the N well region 21 (see (b)). The diffusion depth of the P-type source diffusion layer 23 is about 2 μm.
[0055]
(3) In order to form the field doped layer, for example, boron is accelerated on the surface side of the peripheral portion of the N-type source diffusion layer 9 by photolithography and ion implantation, and the acceleration energy is about 30 KeV and the dose amount is 5.0 ×. 1013cm-2For example, phosphorus is implanted on the surface side of the peripheral portion of the P-type source diffusion layer 23 at an acceleration condition of about 100 KeV and a dose amount is 8.0 × 10.12cm-2Inject at about the conditions. A LOCOS oxide film 3 surrounding the transistor formation region is formed on the surface of the semiconductor substrate 1 to a thickness of about 450 nm by the LOCOS oxidation method. At this time, the region LOCOS oxide film 3 surrounding the Nch transistor formation region is formed by boron implanted into the surface side of the peripheral portion of the N-type source diffusion layer 9 and phosphorus implanted into the surface side of the peripheral portion of the P-type source diffusion layer 23. A P-type field doped layer 5 is formed below, and an N-type field doped layer 19 is formed under the LOCOS oxide film 3 in a region surrounding the Pch transistor forming region (see (c)).
[0056]
(4) After removing the oxide film on the surface of the N-type source diffusion layer 9 and the surface of the P-type source diffusion layer 23 once, the gate oxide film 11 and the surface of the P-type source diffusion layer 23 on the surface of the N-type source diffusion layer 9 A gate oxide film 25 is simultaneously formed. For example, the thicknesses of the gate oxide films 11 and 23 are both 5 to 8 nm. For example, a polysilicon film is formed to a thickness of about 350 nm on the entire surface of the semiconductor substrate 1 by CVD (chemical vapor deposition). The polysilicon film and the gate oxide films 11 and 23 are patterned by photolithography and etching techniques to form the gate electrode 13 in the Nch transistor formation region and the gate electrode 27 in the Pch transistor formation region ( (See (d)).
[0057]
(5) For forming a P-type channel diffusion layer by using the gate electrode 13 as a mask in the Nch transistor formation region by photolithography and ion implantation, for example, boron is accelerated at an energy of about 15 KeV, and the dose is 1 0.0 × 1014cm-2In order to form an N-type channel diffusion layer in the Pch transistor formation region using the gate electrode 27 as a mask in the Pch transistor formation region, for example, phosphorus is accelerated at an energy of about 50 KeV and a dose amount is 1.0 × 10.14cm-2Inject at about the conditions. A heat treatment is performed at about 1100 ° C. for about 1 hour to form a P-type channel diffusion layer (Pbody) 15 in the N-type source diffusion layer 9 in a self-aligned manner with respect to the gate electrode 13. An N-type channel diffusion layer (Nbody) 29 is formed in a self-aligned manner with respect to the gate electrode 27. The diffusion depth of the P-type channel diffusion layer 15 and the P-type source diffusion layer 23 is 0.5 to 0.8 μm. In the Nch transistor formation region, the surface portion of the N-type source diffusion layer 9 remains adjacent to the gate oxide film 11 below the gate electrode 13, and in the Pch transistor formation region, the gate oxide film is formed below the gate electrode 27. The surface portion of the P-type source diffusion layer 23 is left adjacent to 25.
[0058]
A resist pattern having an opening corresponding to the formation region of the gate electrode 13 and the N-type drain diffusion layer is formed by photolithography, and the gate electrode 13 and the N-type are formed by ion implantation using the resist pattern as a mask. In the formation region of the drain diffusion layer, for example, arsenic or phosphorus is accelerated at an energy of about 30 KeV, and the dose is 1.0 × 10.15cm-2Inject with the above dose. After removing the resist pattern, a resist pattern having an opening corresponding to the formation region of the gate electrode 27 and the P-type drain diffusion layer is formed by photolithography, and the resist pattern is used as a mask by ion implantation. In the formation region of the gate electrode 27 and the P-type drain diffusion layer, for example, boron or BF2The acceleration energy is about 15 KeV and the dose is 1.0 × 1015cm-2Inject with the above dose. After removing the resist pattern, in order to activate the impurity and drain diffusion layers implanted into the gate electrodes 13 and 27, heat treatment is performed at about 850 ° C. for about 1 hour, and the N-type is formed in the P-type channel diffusion layer 15. A drain diffusion layer (N +) 17 is formed, a P-type drain diffusion layer (P +) 31 is formed in the N-type channel diffusion layer 19, and a CMOS including a Pch transistor and an Nch transistor is completed (see FIG. 2).
[0059]
4A and 4B are diagrams showing another embodiment of the first aspect of the semiconductor device of the present invention, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view at the BB position in FIG. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIG.
[0060]
A LOCOS oxide film 3 for element isolation surrounding three Nch transistor formation regions is formed on the surface of a P-type semiconductor substrate (Psub) 1. The LOCOS oxide film 3 has an opening 3a corresponding to three Nch transistor formation regions. A P-type field doped layer 5 is formed under the LOCOS oxide film 3.
A P well region (Pwell) 41 common to the three Nch transistors is formed on the surface side of the semiconductor substrate 1. In the P-well region 41, an N-type common source diffusion layer (Nwell) 43 common to the three Nch transistors is formed.
[0061]
Three strip-shaped gate electrodes 13 made of polysilicon doped with N-type impurities are formed on the N-type common source diffusion layer 43 via a gate oxide film 11 made of a silicon oxide film. The three gate electrodes 13 are formed with a space between each other and with the LOCOS oxide film 3.
[0062]
The three gate electrodes 13 are formed on the surface side of the N-type common source diffusion layer 43 so that a region where the gate oxide film 11 and the N-type common source diffusion layer 43 are adjacent to each other remains in the region under each gate electrode 13. On the other hand, a P-type channel diffusion layer (Pbody) 47 formed in a self-aligned manner is disposed. The P-type channel diffusion layer 47 is continuously formed by three Nch transistor formation regions, and is formed so as to surround the formation region of the gate electrode 13.
[0063]
In each Nch transistor formation region, an N-type drain diffusion layer (N +) 17 in which an N-type impurity is implanted is formed in a P-type channel diffusion layer 47 adjacent to one side surface of the gate electrode 13. .
In each Nch transistor, the surface side of the P-type channel diffusion layer 47 in the region between the N-type common source diffusion layer 43 and the N-type drain diffusion layer 17 under the gate electrode 13 becomes a channel region.
[0064]
FIG. 5 is a plan view showing a contact region for the gate electrode and the N-type drain diffusion layer of this embodiment.
A contact region 49 for taking a potential is formed on each gate electrode 13. A contact region 51 for taking a potential is formed on each N-type drain diffusion layer 17.
[0065]
The P well region 41 and the N-type common source diffusion layer 43 are provided with contact regions in regions not shown. Since the P-type channel diffusion layer 47 is electrically connected to the P-well region 41 through the P-type field doped layer 5, it has the same potential as the P-well region 41 and the semiconductor substrate 1.
[0066]
In this embodiment, the contact region formed in the transistor formation region is only the contact region 49 for taking the potential of the gate electrode 13 and the contact region 51 for taking the potential of the N-type drain diffusion layer 17, and FIG. Unlike the prior art shown in (A), since the contact region of the source diffusion layer is not provided, the area occupied by the transistor on the chip can be reduced. This effect is the same in the embodiment shown in FIG.
[0067]
Further, since the width of the gate electrode 13 can be increased, the contact region is formed on the LOCOS oxide film by extending the gate electrode on the LOCOS oxide film in order to form a contact region on the gate electrode as in the prior art. The contact region 49 can be formed on the gate electrode 13 in the region where the gate oxide film 11 is formed, so that the area occupied by the transistor on the chip can be reduced. This effect is the same in the embodiment shown in FIG.
[0068]
Further, by providing the N-type common source diffusion layer 43 common to adjacent Nch transistors, the arrangement interval of adjacent Nch transistors can be reduced, and the area occupied by the transistors on the chip can be further reduced.
[0069]
FIG. 6 is a sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIG.
[0070]
A LOCOS oxide film 3 is formed on the surface of a P-type semiconductor substrate (Psub) 1, and a P-type field doped layer 5 is formed under the LOCOS oxide film 3. A P well region (Pwell) 7 is formed on the surface side of the semiconductor substrate 1, and an N-type source diffusion layer (Nwell) 9 is formed in the P well region 7.
[0071]
A gate electrode 13 is formed on N-type source diffusion layer 9 with gate oxide film 11 interposed. An oxide film side wall 53 is formed on the side surface of the gate electrode 13. A P-type channel diffusion layer (Pbody) 15 formed in a self-aligned manner with respect to the gate electrode 13 is disposed on the surface side of the N-type source diffusion layer 9.
[0072]
In the P-type channel diffusion layer 15, an N-type drain diffusion layer (N +) 17 is formed on one side of the gate electrode 13. The N-type drain diffusion layer 17 is formed in a self-aligned manner with respect to the oxide film side wall 53 and is formed with a gap from the gate electrode 13.
[0073]
In the P-type channel diffusion layer 15, an N-type impurity diffusion layer having a concentration lower than that of the N-type drain diffusion layer 17 is adjacent to one side surface of the gate electrode 13 on the side where the N-type drain diffusion layer 17 is formed. (N−) 55 is formed. The N-type impurity diffusion layer 55 is formed in a self-aligned manner with respect to the gate electrode 13.
[0074]
The concentration of the N-type impurity diffusion layer 55 is 5.0 × 1018~ 1.0 × 1019cm-3The concentration of the N-type drain diffusion layer 17 is 5.0 × 1020cm-3The concentration of the N-type impurity diffusion layer 55 is lower than that of the N-type drain diffusion layer 17.
[0075]
In this embodiment, an N-type impurity concentration lower than that of the N-type drain diffusion layer 17 in the region adjacent to the gate electrode 13 in the P-type channel diffusion layer 15 is adjacent to the N-type drain diffusion layer 17. Since the impurity diffusion layer 55 is provided, the depletion layer that extends into the P-type channel diffusion layer 15 when a drain voltage is applied extends also into the N-type drain diffusion layer 17, thereby improving the punch-through breakdown voltage. Can do.
[0076]
The mode in which the N-type impurity diffusion layer 55 is arranged adjacent to the N-type drain diffusion layer 17 in the region adjacent to the gate electrode 13 inside the P-type channel diffusion layer 15 is shown in FIGS. The present invention can also be applied to the embodiments.
[0077]
The same applies to a Pch transistor. For example, in the Pch transistor shown in FIG. 2, a P-type impurity thinner than the P-type drain diffusion layer 31 in the region adjacent to the gate electrode 27 in the N-type channel diffusion layer 29, adjacent to the P-type drain diffusion layer 31. An example of arranging a P-type impurity diffusion layer having a concentration can be given.
[0078]
FIG. 7 is a sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIG.
[0079]
This embodiment differs from the embodiment shown in FIG. 1 in that the N-type source diffusion layer 9 is located deeper than the P-type channel diffusion layer (Pbody) 15 in the N-type source diffusion layer (Nwell) 9 than the N-type source diffusion layer 9. An N + buried layer (first conductivity type buried layer) 57 having a high N-type impurity concentration is formed.
[0080]
By providing the N + buried layer 57 in the N-type source diffusion layer 9, the diffusion resistance to the lead-out portion of the source electrode for taking the potential of the N-type source diffusion layer 9 can be lowered. Thereby, it is possible to prevent the deterioration of the performance of the transistor due to the potential difference between the semiconductor substrate 1 and the N-type source diffusion layer 9.
[0081]
As a method for forming the N + buried layer 57, for example, phosphorus is accelerated at an energy of about 850 to 1000 KeV, and the dose is 1.0 × 10.13~ 3.0 × 1013cm-2A method of forming by implanting at a depth of about 1.0 to 1.1 μm can be given.
As another method for forming the N + buried layer 57, an N-type impurity for the N + buried layer 57 is introduced into the surface of the semiconductor substrate, and then an epitaxial growth layer is formed on the surface of the semiconductor substrate.
[0082]
The aspect in which the N + buried layer 57 is arranged in the N-type source diffusion layer 9 can also be applied to the embodiments shown in FIGS.
As shown in FIG. 8, when applied to the embodiment shown in FIG. 4, it is deeper than the P-type channel diffusion layer (Pbody) 15 in the N-type common source diffusion layer (Nwell) 43 common to two or more transistors. If the N + buried layer 57 is arranged at a position, for example, even if there is only one source electrode lead portion for taking the potential of the N-type common source diffusion layer 43, the diffusion resistance to the source electrode lead portion is lowered. For each Nch transistor, it is possible to prevent deterioration in transistor performance due to a potential difference between the semiconductor substrate 1 and the N-type common source diffusion layer 43.
[0083]
In the case of application to a Pch transistor, for example, in the CMOS Pch transistor shown in FIG. A P + buried layer having a P-type impurity concentration higher than that of the source diffusion layer 23 may be formed.
[0084]
As a method for forming the P + buried layer, for example, boron is accelerated at an energy of about 200 to 300 KeV, and the dose is 1.0 × 10.13~ 3.0 × 1013cm-2An example is a method in which the film is implanted under such conditions and driven to a depth of about 0.5 to 0.7 μm.
As another method for forming the P + buried layer, a method of forming an epitaxial growth layer on the surface of the semiconductor substrate after introducing P-type impurities for the P + buried layer into the surface of the semiconductor substrate can be mentioned.
[0085]
FIG. 9 is a sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention. This embodiment is applied to an Nch transistor. The parts having the same functions as those in FIG.
[0086]
This embodiment differs from the embodiment shown in FIG. 7 in that a P-type impurity that is deeper than the P-well region 7 is located deeper than the N-type source diffusion layer (Nwell) 9 in the P-well region (Pwell) 7. A P + buried layer (second conductivity type buried layer) 59 having a concentration is formed.
[0087]
By providing the P + buried layer 59 in the P well region 7, the diffusion resistance up to the contact portion for taking the potential of the P well region 7 can be lowered, and between the semiconductor substrate 1 and the P well region 7. It is possible to prevent the deterioration of the performance of the transistor due to the potential difference.
[0088]
As a method for forming the P + buried layer 59, for example, phosphorus is accelerated by an acceleration energy of about 500 to 600 KeV and a dose amount is 1.0 × 10.13~ 3.0 × 1013cm-2A method of forming by implanting at a depth of about 1.0 to 1.1 μm can be given.
As another method for forming the P + buried layer 59, a method of forming an epitaxial growth layer on the surface of the semiconductor substrate after introducing P-type impurities for the P + buried layer 59 into the surface of the semiconductor substrate can be mentioned.
[0089]
The aspect in which the P + buried layer 59 is arranged in the P well region 7 can also be applied to the embodiments shown in FIGS. 1, 2, 4, 6, and 8.
As shown in FIG. 10, when applied to the embodiment shown in FIG. 8, if a P + buried layer 59 is arranged in a P well region (Pwell) 41 common to two or more transistors, for example, the P well region 41 Even if there is only one contact portion for taking the potential, the diffusion resistance to the contact portion can be lowered, and for each Nch transistor, a transistor caused by a potential difference between the semiconductor substrate 1 and the P well region 41 It is possible to prevent the performance degradation.
[0090]
When applied to a Pch transistor, for example, in the CMOS Pch transistor shown in FIG. 2, an N-type impurity that is deeper than the N-well region 21 at a position deeper than the P-type source diffusion layer 23 in the N-well region 21. An N + buried layer having a concentration may be formed.
[0091]
As a method for forming the N + buried layer, for example, boron is accelerated with an acceleration energy of about 850 to 1000 KeV and a dose amount is 1.0 × 10.13~ 3.0 × 1013cm-2A method of forming by implanting at a depth of about 1.0 to 1.1 μm can be given.
As another method for forming the N + buried layer, an N-type impurity for the N + buried layer is introduced into the surface of the semiconductor substrate, and then an epitaxial growth layer is formed on the surface of the semiconductor substrate.
[0092]
  FIG. 11 shows a semiconductor device according to the present invention.Reference exampleFIG. thisReference exampleIs an SOI (silicon on insulator) substrate and is applied to an Nch transistor. Parts having the same functions as those in FIG.
[0093]
An oxide film insulating layer (SiO2) made of a silicon oxide film on a P-type semiconductor substrate (Psub) 12) 61 is formed. A semiconductor layer 63 made of, for example, an epitaxial growth layer is formed on the silicon oxide film layer 61. A LOCOS oxide film 3 for element isolation is formed on the surface of the semiconductor layer 63. A P-type field doped layer 5 is formed under the LOCOS oxide film 3.
[0094]
An N-type source diffusion layer (Nwell) 9a is formed in the semiconductor layer 63 in the Nch transistor formation region.
An oxide film insulating layer 67 made of a silicon oxide film is formed in the semiconductor layer 63 so as to surround the N-type source diffusion layer 9a.
[0095]
A gate electrode 13 is formed on N-type source diffusion layer 9a with gate oxide film 11 interposed.
A P-type channel diffusion layer (Pbody) 15 formed in a self-aligned manner with respect to the gate electrode 13 is disposed on the surface side of the N-type source diffusion layer 9a. An N-type drain diffusion layer (N +) 17 is formed in the P-type channel diffusion layer 15 adjacent to one side surface of the gate electrode 13.
[0096]
  thisReference exampleThen, since the N-type source diffusion layer 9a is surrounded by the oxide film insulating layers 61 and 67, the N-type source diffusion layer 9a can be electrically isolated from the semiconductor substrate 1.
[0097]
The embodiment in which the transistor formation region is surrounded by the oxide film insulating layer can also be applied to the embodiments shown in FIGS. 2, 4, and 6 to 10.
As shown in FIG. 12, when applied to the embodiment using the CMOS shown in FIG. 2, the N-type source diffusion layer (Nwell) 9a of the Nch transistor is surrounded by the oxide film insulating layers 61 and 67, and the Pch transistor By surrounding the P-type source diffusion layer (Pwell) 23a, the semiconductor substrate 1, the N-type source diffusion layer 9a, and the P-type source diffusion layer 23a can be electrically isolated from each other.
[0098]
As shown in FIG. 13, when applied to the embodiment shown in FIG. 8, the semiconductor substrate is formed by surrounding the N-type common source diffusion layer (Nwell) 43a and the N + buried layer 57a with oxide film insulating layers 61 and 67. 1 and the N-type common source diffusion layer 43a and the N + buried layer 57a can be electrically separated.
[0099]
  Figure 1 to Figure10In the embodiment shown in FIG. 1, the planar shape of the gate electrode is a quadrangle, but the first aspect of the semiconductor device of the present invention is not limited to this, and the planar shape of the gate electrode is, for example, other polygons or Any planar shape such as a circle or an ellipse may be used.
[0100]
14A and 14B are diagrams showing an embodiment of the second aspect of the semiconductor device of the present invention, in which FIG. 14A is a plan view and FIG. 14B is a cross-sectional view taken along the line CC in FIG. This embodiment is applied to an Nch transistor.
[0101]
A LOCOS oxide film 3 for element isolation is formed on the surface of a P-type semiconductor substrate (Psub) 1. The LOCOS oxide film 3 has an opening 3a corresponding to the transistor formation region. A P-type field doped layer 5 is formed under the LOCOS oxide film 3 by introducing P-type impurities. A P well region (Pwell) 69 is formed on the surface side of the semiconductor substrate 1. An N-type source diffusion layer (Nwell) 71 is formed in the P well region 69.
[0102]
A cylindrical recess is formed on the surface side of the N-type source diffusion layer 71 with a distance from the LOCOS oxide film 3. A cylindrical gate electrode 75 made of polysilicon doped with N-type impurities is formed in the recess through a gate oxide film 73 made of a silicon oxide film.
[0103]
A P-type channel diffusion layer (Pbody) 77 is formed adjacent to the gate oxide film 73 in a region shallower than the bottom of the gate electrode 75 on the surface side of the N-type source diffusion layer 71. The P-type channel diffusion layer 77 is formed so as to surround the formation region of the gate electrode 75.
[0104]
An N-type drain diffusion layer (N +) 79 is formed in the P-type channel diffusion layer 77 adjacent to the gate oxide film 73. The N-type drain diffusion layer 79 is formed so as to surround the formation region of the gate electrode 75.
In this transistor, the region of the P-type channel diffusion layer 77 in the region between the N-type source diffusion layer 71 and the N-type drain diffusion layer 79 near the side surface of the gate electrode 75 becomes a channel region.
[0105]
A contact region 49 for taking a potential is formed on the gate electrode 75, and a contact region 51 for taking a potential is formed on the N-type drain diffusion layer 17. In the P well region 69 and the N-type source diffusion layer 71, a contact region is provided in a region not shown. Since the P-type channel diffusion layer 77 is electrically connected to the P-well region 69 through the P-type field doped layer 5, it has the same potential as the P-well region 69 and the semiconductor substrate 1.
[0106]
In this embodiment, the channel length that determines the transistor performance is determined not by the processing accuracy of the gate electrode 75 but by the length of the channel diffusion layer 77 on the side surface of the gate electrode 75. The length of the channel diffusion layer 77 on the side surface of the gate electrode 75 is determined by the implantation depth and diffusion depth of the channel diffusion layer 77 and the implantation depth and diffusion depth of the drain diffusion layer 79 injected from the surface of the semiconductor substrate 1. Therefore, it is determined by the ion implantation conditions for forming both diffusion layers 77 and 79, the diffusion temperature, and the diffusion time. As described above, the diffusion depth has good controllability, and the implantation depth also has good controllability, so that a fine-rule MOS transistor can be stably formed.
[0107]
Further, the contact region formed in the transistor formation region is only the contact region 49 for taking the potential of the gate electrode 75 and the contact region 51 for taking the potential of the N-type drain diffusion layer 79, as shown in FIG. Since the contact region of the source diffusion layer is not provided as in the prior art shown in (1), the area occupied by the transistor on the chip can be reduced.
[0108]
Furthermore, since the planar dimension of the gate electrode 75 can be increased, the gate electrode is extended on the LOCOS oxide film to form the contact region on the gate electrode as in the prior art, and the contact region is formed on the LOCOS oxide film. Since the contact region 49 can be formed on the gate electrode 75 in the formation region of the gate oxide film 73, the area occupied by the transistor on the chip can be reduced.
[0109]
FIG. 15 is a sectional view of an embodiment in which the second aspect of the semiconductor device of the present invention is applied to a CMOS inverter. Parts having the same functions as those in FIG.
[0110]
A LOCOS oxide film 3 for element isolation is formed on the surface of a P-type semiconductor substrate (Psub) 1. A P-type field doped layer 5 is formed under the LOCOS oxide film 3 surrounding the Nch transistor formation region.
In the Nch transistor formation region, the N-type source diffusion layer (Nwell) 71, the gate oxide film 73, the gate electrode 75, the P-type channel diffusion layer (Pbody) 77, and the N-type have the same configuration as the embodiment shown in FIG. A drain diffusion layer (N +) 79 is formed to form an Nch transistor. In this embodiment, the P-well region surrounding the Nch transistor formation region is omitted, and the P-type channel diffusion layer 77 is electrically connected to the semiconductor substrate 1 through the P-type field doped layer 5. The potential is the same as that of the semiconductor substrate 1.
[0111]
An N-type field doped layer 19 in which an N-type impurity is introduced is formed under the LOCOS oxide film 3 surrounding the formation region of the P-channel MOS transistor constituting the second MOS transistor. An N well region (separation diffusion layer, Nwell) 83 is formed on the surface side of the semiconductor substrate 1 in the Pch transistor formation region. A P-type source diffusion layer (Pwell) 85 is formed in the N well region 83.
[0112]
A cylindrical recess is formed on the surface side of the P-type source diffusion layer 85 with a distance from the LOCOS oxide film 3. A cylindrical gate electrode 89 made of polysilicon into which a P-type impurity is introduced is formed in the recess through a gate oxide film 87 made of a silicon oxide film.
[0113]
An N-type channel diffusion layer (Nbody) 91 is formed adjacent to the gate oxide film 87 in a region shallower than the bottom of the gate electrode 89 on the surface side of the P-type source diffusion layer 85. The N-type channel diffusion layer 91 is formed so as to surround the formation region of the gate electrode 89.
[0114]
A P-type drain diffusion layer (P +) 93 is formed in the N-type channel diffusion layer 91 adjacent to the gate oxide film 87. The P-type drain diffusion layer 93 is formed so as to surround the formation region of the gate electrode 89.
In this transistor, the region of the N-type channel diffusion layer 91 in the region between the P-type source diffusion layer 85 and the P-type drain diffusion layer 93 near the side surface of the gate electrode 89 becomes a channel region.
[0115]
The plan view of the Pch transistor is the same as that of the Nch transistor shown in FIG. On the gate electrode 89 and the P-type drain diffusion layer 93, contact regions (not shown) for taking a potential are formed.
[0116]
The N well region 83 and the P-type source diffusion layer 85 are provided with contact regions in regions not shown. Since the N-type channel diffusion layer 91 is electrically connected to the N-well region 83 through the N-type field doped layer 19, it has the same potential as the N-well region 83.
[0117]
The gate electrodes 75 and 89 are connected to the common input terminal 33. The N-type drain diffusion layer 79 and the P-type drain diffusion layer 93 are connected to the common output terminal 35. The N-type well diffusion layer 83 and the P-type source diffusion layer 85 are connected to the power supply potential 37. The semiconductor substrate 1 and the N-type source diffusion layer 71 are connected to the ground potential 39.
[0118]
As described above, the CMOS can be formed on the same semiconductor substrate 1 by forming the Pch transistor in the N-type well region 83 as the isolation diffusion layer and electrically isolating it from the semiconductor substrate 1. .
[0119]
  16 and 17 show a manufacturing method for manufacturing the transistor shown in FIG.ExampleProcess sectional drawing of this is shown. With reference to FIG. 15 to FIG.ExampleWill be explained.
[0120]
(1) A P-type semiconductor substrate (Psub) 1 of about 20 Ωcm is prepared, and a 20 nm oxide film (not shown) is formed on the surface of the semiconductor substrate 1 by thermal oxidation. By means of photolithography and ion implantation, for example, phosphorus is accelerated into the formation region of the Nch transistor and the Pch transistor via the oxide film, the acceleration energy is about 150 KeV, and the dose amount is 5.0 × 10.12cm-2Inject at about the conditions. Heat treatment is performed at about 1180 ° C. for about 8 hours to form an N-type source diffusion layer (Nwell) 71 composed of an N-well region in the Nch transistor formation region, and an isolation diffusion layer in the Pch transistor formation region. An N well region (Nwell) 83 to be formed is formed (see FIG. 16A). The diffusion depths of the N-type source diffusion layer 71 and the N well region 83 are both about 6 μm. The N-type source diffusion layer 71 and the N-well region 83 are formed with a space therebetween. Here, when the concentration of the source diffusion layer 71 is low in the Nch transistor formation region, phosphorus may be implanted into the surface to increase the concentration of the source diffusion layer 71.
[0121]
(2) After forming a resist pattern for defining the formation region of the source diffusion layer of the Pch transistor by photolithography, the acceleration energy of boron, for example, is about 50 KeV by ion implantation using the resist pattern as a mask. The dose is 5.0 × 1012cm-2Inject at about the conditions. After the resist pattern is removed, heat treatment is performed at about 1150 ° C. for about 4 hours to form a P-type source diffusion layer (Pwell) 85 in the N-well region 71 (see FIG. 16B). The diffusion depth of the P-type source diffusion layer 85 is about 3 μm.
[0122]
(3) In order to form the field doped layer, for example, boron is accelerated on the surface side of the peripheral portion of the N-type source diffusion layer 71 by photolithography and ion implantation, and the acceleration energy is about 30 KeV and the dose amount is 5.0 ×. 1013cm-2For example, phosphorus is implanted on the surface side of the peripheral portion of the P-type source diffusion layer 85 at an acceleration condition of about 100 KeV and the dose amount is 8.0 × 10.12cm-2Inject at about the conditions. A LOCOS oxide film 3 surrounding the transistor formation region is formed on the surface of the semiconductor substrate 1 to a thickness of about 450 nm by the LOCOS oxidation method. At this time, the region LOCOS oxide film 3 surrounding the Nch transistor formation region is formed by boron implanted into the surface side of the peripheral portion of the N-type source diffusion layer 71 and phosphorus implanted into the surface side of the peripheral portion of the P-type source diffusion layer 85. A P-type field doped layer 5 is formed below, and an N-type field doped layer 19 is formed under the LOCOS oxide film 3 in a region surrounding the Pch transistor forming region (see FIG. 16C).
[0123]
(4) The oxide film (not shown) formed on the surface of the N-type source diffusion layer 71 and the surface of the P-type source diffusion layer 85 by the photoengraving technique and the dry etching technique corresponds to the gate electrode formation scheduled region. Openings are formed, and dry etching is performed with the oxide film provided with the openings as a mask, and a recess for gate electrode placement is formed at a depth of about 1 μm on the surface side of the N-type source diffusion layer 71 and the P-type source diffusion layer 85. To form.
[0124]
After the oxide films on the surface of the N-type source diffusion layer 71 and the surface of the P-type source diffusion layer 85 are once removed, gate oxidation is performed on the inner wall surface of the recess for arranging the gate electrode provided in the N-type source diffusion layer 71 by thermal oxidation. A film 73 is formed, and a gate oxide film 87 is formed on the inner wall surface of the recess for arranging the gate electrode provided in the P-type source diffusion layer 85. For example, the gate oxide films 73 and 87 are formed to a thickness of 5 to 8 nm (see FIG. 17D).
[0125]
(5) A polysilicon film having a thickness of, for example, 15 to 30 nm is formed on the entire surface of the semiconductor substrate 1 by CVD, for example, so as to embed a recess for arranging the gate electrode. The polysilicon film outside the recess for the gate electrode placement is selectively removed by dry etching technology, the upper polysilicon is removed by dry etching, and the gate electrode 75 made of polysilicon is formed in the recess for the gate electrode placement. , 89 are formed.
[0126]
For example, a mask nitride film having an opening corresponding to the formation region of the gate electrode 75 is formed by CVD, photoengraving technology and etching technology, phosphorus glass is deposited and thermal diffusion is performed, and phosphorus is added to the gate electrode 75. Introducing, an N-type gate electrode 75 is formed.
After removing the mask nitride film, a new mask nitride film having an opening corresponding to the formation region of the gate electrode 89 is formed by, for example, CVD, photoengraving technology, and etching technology. Thermal diffusion is performed to introduce boron into the gate electrode 89 to form a P-type gate electrode 89. Thereafter, the mask nitride film is removed (see FIG. 17E).
[0127]
(6) In order to form a P-type channel diffusion layer in the Nch transistor formation region by photolithography and ion implantation, for example, boron is accelerated at an energy of about 15 KeV and a dose is 1.0 × 1014cm-2In order to form an N-type channel diffusion layer in the Pch transistor formation region, for example, phosphorus is accelerated at an energy of about 50 KeV and a dose is 1.0 × 10.14cm-2Inject at about the conditions. A heat treatment is performed at about 1100 ° C. for about 1 hour to form a P-type channel diffusion layer (Pbody) 77 in the N-type source diffusion layer 71, and an N-type channel diffusion layer (Nbody) 91 in the P-type source diffusion layer 85. Form. The diffusion depth of the P-type channel diffusion layer 77 and the N-type channel diffusion layer 91 is 0.5 to 0.8 μm.
[0128]
A resist pattern having an opening corresponding to the formation region of the N-type drain diffusion layer is formed by photolithography, and the gate electrode 75 and the N-type drain diffusion layer are formed by ion implantation using the resist pattern as a mask. In the formation region, for example, arsenic or phosphorus is accelerated at an energy of about 30 KeV and a dose is 1.0 × 1015cm-2Inject with the above dose. After removing the resist pattern, a resist pattern having an opening corresponding to the formation region of the gate electrode 89 and the P-type drain diffusion layer is formed by photolithography, and the resist pattern is used as a mask by ion implantation. In the formation region of the gate electrode 89 and the P-type drain diffusion layer, for example, boron or BF2The acceleration energy is about 15 KeV and the dose is 1.0 × 1015cm-2Inject with the above dose. After removing the resist pattern, in order to activate the impurity and drain diffusion layers implanted into the gate electrodes 75 and 89, heat treatment is performed at about 850 ° C. for about 1 hour, and the N-type is formed in the P-type channel diffusion layer 77. A drain diffusion layer (N +) 79 is formed, a P-type drain diffusion layer (P +) 93 is formed in the N-type channel diffusion layer 91, and a CMOS including a Pch transistor and an Nch transistor is completed (see FIG. 15).
[0129]
18A and 18B are diagrams showing another embodiment of the second aspect of the semiconductor device of the present invention, in which FIG. 18A is a plan view and FIG. 18B is a cross-sectional view taken along the DD line in FIG. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIG.
[0130]
A LOCOS oxide film 3 for element isolation surrounding three Nch transistor formation regions is formed on the surface of a P-type semiconductor substrate (Psub) 1. The LOCOS oxide film 3 has an opening 3a corresponding to three Nch transistor formation regions. A P-type field doped layer 5 is formed under the LOCOS oxide film 3.
[0131]
A P well region 95 common to the three Nch transistors is formed on the surface side of the semiconductor substrate 1. An N-type common source diffusion layer (Nwell) 97 common to the three Nch transistors is formed in the P well region 95.
[0132]
Three columnar recesses are formed on the surface side of the N-type source diffusion layer 71 with a space between each other and with the LOCOS oxide film 3, and the gate electrode is interposed in these recesses via a gate oxide film 73. 75 is formed.
[0133]
A P-type channel diffusion layer (Pbody) 98 is formed adjacent to the gate oxide film 73 in a region shallower than the bottom of the gate electrode 75 on the surface side of the N-type source diffusion layer 71. The P-type channel diffusion layer 98 is continuously formed of three Nch transistor formation regions and is formed so as to surround the formation region of the gate electrode 75.
[0134]
An N-type drain diffusion layer (N +) 79 is formed in the P-type channel diffusion layer 98 adjacent to the gate oxide film 73. N-type drain diffusion layers 79 are formed in three Nch transistor formation regions so as to surround the formation region of the gate electrode 75, and adjacent N-type drain diffusion layers 79 are arranged at intervals.
[0135]
A contact region 49 for taking a potential is formed on the gate electrode 75, and a contact region 51 for taking a potential is formed on the N-type drain diffusion layer 17. The P well region 95 and the N-type common source diffusion layer 97 are provided with contact regions in regions not shown.
[0136]
In this embodiment, by providing the N-type common source diffusion layer 97 common to adjacent Nch transistors, the arrangement interval of adjacent Nch transistors can be reduced, and the area occupied by the transistors on the chip can be further reduced. Can do.
[0137]
In this embodiment, three Nch transistors are arranged on a straight line when viewed from the upper surface side. However, the present invention is not limited to this, and for example, the three Nch transistors are equilateral triangles when viewed from the upper surface side. Arrangement of two or more transistors may be any arrangement such as arrangement on each vertex.
[0138]
FIG. 19 is a sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIG.
[0139]
This embodiment is different from the embodiment shown in FIG. 14 in that the P-type channel diffusion layer (Pbody) 77 has an N-type impurity concentration lower than that of the N-type drain diffusion layer (N +) 79, and the N-type drain. The diffusion layer 79 and the gate oxide film 73 include an N-type impurity diffusion layer (N−) 99 formed so as to surround the N-type drain diffusion layer 79 except for an adjacent region. That is, an N-type impurity diffusion layer 99 is provided adjacent to the N-type drain diffusion layer 79 in a region adjacent to the gate electrode 75 inside the P-type channel diffusion layer 77.
[0140]
In this embodiment, since the N-type impurity diffusion layer 99 is provided, a depletion layer that extends into the P-type channel diffusion layer 77 when a drain voltage is applied also extends into the N-type drain diffusion layer 79. Through voltage resistance can be improved.
[0141]
In the P-type channel diffusion layer 77, the N-type drain diffusion layer 79 is formed except for a region having an N-type impurity concentration lower than that of the N-type drain diffusion layer 79 and adjacent to the N-type drain diffusion layer 79 and the gate oxide film 73. The aspect provided with the N-type impurity diffusion layer 99 formed so as to be surrounded can also be applied to the embodiments shown in FIGS.
[0142]
The same applies to a Pch transistor. For example, in the Pch transistor shown in FIG. 15, the N-type channel diffusion layer 91 has a P-type impurity concentration lower than that of the P-type drain diffusion layer 93, and the P-type drain diffusion layer 93 and the gate oxide film 87 are adjacent to each other. An example may be given in which a P-type impurity diffusion layer formed so as to surround the P-type drain diffusion layer 93 is included.
[0143]
FIG. 20 is a sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIGS. 7 and 14 are denoted by the same reference numerals.
[0144]
This embodiment is different from the embodiment shown in FIG. 14 in that the N-type source diffusion layer (Nwell) 71 is deeper than the P-type channel diffusion layer (Pbody) 77 and more than the N-type source diffusion layer 71. The N + buried layer 57 having a high N-type impurity concentration is formed.
[0145]
By providing the N + buried layer 57 in the N-type source diffusion layer 71, the diffusion resistance up to the source electrode lead-out portion for taking the potential of the N-type source diffusion layer 71 can be lowered. Thereby, it is possible to prevent the deterioration of the performance of the transistor due to the potential difference between the semiconductor substrate 1 and the N-type source diffusion layer 71.
[0146]
The aspect in which the N + buried layer 57 is arranged in the N-type source diffusion layer 71 can also be applied to the embodiments shown in FIGS.
As shown in FIG. 21, when applied to the embodiment shown in FIG. 18, it is shallower than the P-type channel diffusion layer (Pbody) 98 in the N-type common source diffusion layer (Nwell) 97 common to two or more transistors. If the N + buried layer 57 is arranged at a position, even if there is only one source electrode lead portion for taking the potential of the N-type common source diffusion layer 97, the diffusion resistance to the source electrode lead portion can be lowered. In addition, for each Nch transistor, it is possible to prevent deterioration in transistor performance due to a potential difference between the semiconductor substrate 1 and the N-type common source diffusion layer 97.
[0147]
When applied to a Pch transistor, for example, in the CMOS Pch transistor shown in FIG. 15, a P-type transistor is formed at a position deeper than the N-type channel diffusion layer (Nbody) 91 in the P-type source diffusion layer (Pwell) 85. A P + buried layer having a P-type impurity concentration higher than that of the source diffusion layer 85 may be formed.
[0148]
FIG. 22 is a cross-sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention. This embodiment is applied to an Nch transistor. Parts having the same functions as those in FIGS. 9 and 20 are denoted by the same reference numerals.
[0149]
This embodiment is different from the embodiment shown in FIG. 20 in that a P-type impurity that is deeper than the P-well region 69 is deeper than the N-type source diffusion layer (Nwell) 71 in the P-well region (Pwell) 69. A P + buried layer 59 having a concentration is formed.
[0150]
By providing the P + buried layer 59 in the P well region 69, the diffusion resistance to the contact portion for taking the potential of the P well region 69 can be lowered, and between the semiconductor substrate 1 and the P well region 69. It is possible to prevent the deterioration of the performance of the transistor due to the potential difference.
[0151]
The mode in which the P + buried layer 59 is disposed in the P well region 69 can also be applied to the embodiments shown in FIGS. 14 to 19 and FIG.
As shown in FIG. 23, when applied to the embodiment shown in FIG. 21, if a P + buried layer 59 is disposed in a P well region (Pwell) 95 common to two or more transistors, for example, the P well region 95 Even if there is only one contact portion for taking the potential, the diffusion resistance to the contact portion can be lowered, and for each Nch transistor, a transistor caused by a potential difference between the semiconductor substrate 1 and the P well region 95 It is possible to prevent the performance degradation.
[0152]
When applied to a Pch transistor, for example, in the CMOS Pch transistor shown in FIG. 15, the N well region 83 is deeper than the P type source diffusion layer (Pwell) 85 in the N well region (Nwell) 83. An N + buried layer having a higher N-type impurity concentration may be formed.
[0153]
  FIG. 24 shows a semiconductor device of the present invention.Reference exampleFIG. thisReference exampleIs applied to an Nch transistor using an SOI substrate. Parts having the same functions as those in FIGS. 11 and 14 are denoted by the same reference numerals.
[0154]
An oxide film insulating layer (SiO2) is formed on a P-type semiconductor substrate (Psub) 1.2) 61 is formed, and a semiconductor layer 63 is formed on the silicon oxide film layer 61. A LOCOS oxide film 3 is formed on the surface of the semiconductor layer 63. A P-type field doped layer 5 is formed under the LOCOS oxide film 3.
[0155]
An N-type source diffusion layer (Nwell) 71a is formed in the semiconductor layer 63 in the Nch transistor formation region.
In the semiconductor layer 63, an oxide film insulating layer 67 made of a silicon oxide film is formed so as to surround the N-type source diffusion layer 71a.
[0156]
A cylindrical recess is formed on the surface side of the N-type source diffusion layer 71, and a gate electrode 75 is formed in the recess via a gate oxide film 73.
A P-type channel diffusion layer (Pbody) 77 is formed on the surface side of the N-type source diffusion layer 71, and an N-type drain diffusion layer (N +) 79 is formed in the P-type channel diffusion layer 77.
[0157]
In this embodiment, since the N-type source diffusion layer 71a is surrounded by the oxide film insulating layers 61 and 67, the N-type source diffusion layer 71a can be electrically separated from the semiconductor substrate 1.
[0158]
The aspect in which the transistor formation region is surrounded by the oxide film insulating layer can also be applied to the embodiments shown in FIGS.
As shown in FIG. 25, when applied to the embodiment using the CMOS shown in FIG. 15, the N-type source diffusion layer (Nwell) 71a of the Nch transistor is surrounded by the oxide film insulating layers 61 and 67, and the Pch transistor By enclosing the P-type source diffusion layer (Pwell) 85a, the semiconductor substrate 1, the N-type source diffusion layer 71a, and the P-type source diffusion layer 85a can be electrically isolated from each other.
[0159]
As shown in FIG. 26, when applied to the embodiment shown in FIG. 21, the semiconductor substrate is formed by surrounding the N-type common source diffusion layer (Nwell) 97a and the N + buried layer 57a with the oxide film insulating layers 61 and 67. 1 and the N-type common source diffusion layer 97a and the N + buried layer 57a can be electrically separated.
[0160]
  Figure 14 to figure23In the embodiment shown in FIG. 1, the planar shape of the gate electrode is circular, but the second aspect of the semiconductor device of the present invention is not limited to this, and the planar shape of the gate electrode is a polygon such as a quadrangle, for example. Any planar shape, such as an elliptical shape, may be used.
[0161]
Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various modifications can be made within the scope of the present invention described in the claims.
[0162]
【The invention's effect】
  In the semiconductor device according to claim 1,Second conductivity typeFormed on a semiconductor substrateThe same potential as the semiconductor substrateA source diffusion layer of the first conductivity type, a gate electrode formed on the source diffusion layer via a gate oxide film, and a gate oxide film and a source diffusion layer in a region under the gate electrode on the surface side of the source diffusion layer A second conductivity type channel diffusion layer formed in a self-aligned manner with respect to the gate electrode so that an adjacent region remains; and a first conductivity type drain diffusion layer formed in the channel diffusion layer. AlsoThat is, the channel diffusion layer has the same potential as the semiconductor substrate via the semiconductor substrate and the second conductivity type diffusion layer formed adjacent to the channel diffusion layer on the surface side of the peripheral portion of the source diffusion layer.Since the MOS transistor is provided, the channel length of the transistor can be determined by the impurity diffusion depth with good controllability, and a fine rule MOS transistor can be stably formed.
  Furthermore, the generation of majority carriers due to the gate voltage near the surface of the source diffusion layer directly under the gate oxide film contributes to an increase in current in the linear region of the current voltage waveform of the MOS transistor. Response characteristics can be improved, and power of load characteristics can be reduced.
[0163]
  In the semiconductor device according to claim 2,Second conductivity typeFormed on a semiconductor substrateThe same potential as the semiconductor substrateA source diffusion layer of the first conductivity type; a gate electrode formed through a gate oxide film in a recess formed on the surface side of the source diffusion layer; and on the surface side of the source diffusion layer than the bottom of the gate electrode The shallow conductivity region includes a second conductivity type channel diffusion layer formed adjacent to the gate oxide film and a first conductivity type drain diffusion layer formed in the channel diffusion layer.That is, the channel diffusion layer has the same potential as the semiconductor substrate via the semiconductor substrate and the second conductivity type diffusion layer formed adjacent to the channel diffusion layer on the surface side of the peripheral portion of the source diffusion layer.Since the MOS transistor is provided, the channel length of the transistor can be determined by the impurity implantation depth and the impurity diffusion depth with good controllability, so that a fine rule MOS transistor can be stably formed. .
  Further, regarding the channel length and the channel width, the channel length is formed in the depth direction, and only the channel width exists on the surface of the semiconductor substrate, so that the cell area can be reduced particularly in a transistor that conducts a large current. .
  Furthermore, the generation of majority carriers due to the gate voltage in the region near the gate oxide film of the source diffusion layer contributes to the current increase in the linear region in the current voltage waveform of the MOS transistor, so that the transient of the MOS transistor The response characteristic can be improved, and the power of the load characteristic can be saved.
[0164]
The semiconductor device according to claim 3, wherein a first conductivity type having a first conductivity type impurity concentration lower than that of the drain diffusion layer is adjacent to the drain diffusion layer in a region adjacent to the gate electrode in the channel diffusion layer. Since the impurity diffusion layer is further provided, the depletion layer that extends into the channel diffusion layer when the drain voltage is applied extends also into the drain diffusion layer, and the punch-through breakdown voltage can be improved.
[0165]
In the semiconductor device according to claim 4, since the contact region for taking the potential of the gate electrode is provided on the gate electrode in the formation region of the gate oxide film, the transistor occupies on the chip. The area can be reduced.
[0166]
In the semiconductor device according to the fifth aspect, since the gate electrode is arranged with a distance from the element isolation oxide film formed on the surface of the semiconductor substrate, the gate electrode is narrowed by diffusion of impurities from the field doped layer. The channel effect can be eliminated, and a finer transistor can be formed, for example, by miniaturizing the transistor to the minimum dimension capable of forming the gate electrode and the drain diffusion layer.
[0167]
Since the semiconductor device according to claim 6 includes two or more of the MOS transistors, and the source diffusion layer of these MOS transistors is configured by the common source diffusion layer of the first conductivity type, each transistor Can be reduced, and the chip area occupied by these transistors can be reduced.
[0168]
The semiconductor device according to claim 7 further includes a first conductivity type buried layer having a first conductivity type impurity concentration higher than that of the source diffusion layer at a position deeper than the channel diffusion layer in the source diffusion layer. As a result, the diffusion resistance to the lead-out portion of the source electrode can be lowered, and the performance degradation of the transistor due to the potential difference between the semiconductor substrate and the source diffusion layer can be prevented.
[0172]
  Claim8When the CMOS is formed on the semiconductor substrate, the semiconductor device described in 1) further includes a second MOS transistor formed with a reverse conductivity type configuration to the MOS transistor, and the second MOS transistor is located in a region different from the source diffusion layer. Since the first conductive type isolation diffusion layer is formed, the MOS transistor and the second MOS transistor can be electrically separated, and a CMOS can be formed on the same semiconductor substrate. it can.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams illustrating an embodiment of a first aspect of a semiconductor device according to the invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line AA in FIG.
FIG. 2 is a cross-sectional view showing an embodiment in which the first aspect of the semiconductor device of the present invention is applied to a CMOS inverter.
FIG. 3 shows a manufacturing method for manufacturing the CMOS shown in FIG.ExampleIt is process sectional drawing which shows these.
FIGS. 4A and 4B are diagrams showing another embodiment of the first aspect of the semiconductor device of the present invention, in which FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along the line BB in FIG.
FIG. 5 is a plan view showing a contact region for the gate electrode and the N-type drain diffusion layer in the same example.
FIG. 6 is a cross-sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention.
FIG. 7 is a cross-sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention.
FIG. 8 is a cross-sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention.
FIG. 9 is a cross-sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention.
FIG. 10 is a cross-sectional view showing still another embodiment of the first aspect of the semiconductor device of the present invention.
FIG. 11 shows a semiconductor device according to the present invention.Reference exampleFIG.
FIG. 12 shows a semiconductor device according to the present invention.Reference exampleFIG.
FIG. 13 shows a semiconductor device according to the present invention.Reference exampleFIG.
FIGS. 14A and 14B are diagrams showing an embodiment of the second aspect of the semiconductor device of the present invention, in which FIG. 14A is a plan view and FIG. 14B is a cross-sectional view taken along the line CC in FIG.
FIG. 15 is a cross-sectional view showing an embodiment in which the second aspect of the semiconductor device of the present invention is applied to a CMOS inverter.
16 shows a manufacturing method for manufacturing the transistor shown in FIG.ExampleIt is process sectional drawing which shows the first half.
FIG. 17Example of the manufacturing methodIt is process sectional drawing which shows the latter half of.
18A and 18B are diagrams showing another embodiment of the second aspect of the semiconductor device of the present invention, in which FIG. 18A is a plan view, and FIG. 18B is a cross-sectional view at a DD position in FIG.
FIG. 19 is a cross-sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention.
FIG. 20 is a cross-sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention.
FIG. 21 is a cross-sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention.
FIG. 22 is a cross-sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention.
FIG. 23 is a cross-sectional view showing still another embodiment of the second aspect of the semiconductor device of the present invention.
FIG. 24 shows a semiconductor device according to the present invention.Reference exampleFIG.
FIG. 25 shows a semiconductor device according to the present invention.Reference exampleFIG.
FIG. 26 shows a semiconductor device according to the present invention.Reference exampleFIG.
27A and 27B are diagrams showing a conventional MOS transistor in which a source diffusion layer and a drain diffusion layer are formed on both sides of a gate electrode, where FIG. 27A is a plan view and FIG. 27B is a XX position of FIG. FIG.
[Explanation of symbols]
      1 P-type semiconductor substrate
      3 LOCOS oxide film
      3a LOCOS oxide film opening
      5 P-type field doped layer
      7,41 P well region
      9,9a N-type source diffusion layer
    11 Pch transistor gate oxide film
    13 Pch transistor gate electrode
    15, 47 P-type channel diffusion layer
    17 N-type drain diffusion layer
    19 N-type field doped layer
    21 N-well region
    23, 23a P-type source diffusion layer
    25 Nch transistor gate oxide film
    27 Gate electrode of Nch transistor
    29 N-type channel diffusion layer
    31 P-type drain diffusion layer
    33 Input terminal
    35 Output terminal
    37 Power supply potential
    39 Ground potential
    43, 43a N-type common source diffusion layer
    49,51 Contact area
    53 Oxide film sidewall
    55 N-type impurity diffusion layer
    57,57a N + buried layer
    59 P + buried layer
    61, 67 Oxide insulating layer
    63 Semiconductor layer
    69,95 P-well region
    71, 71a N-type source diffusion layer
    73 Gate oxide film of Pch transistor
    75 Pch transistor gate electrode
    77,98 P-type channel diffusion layer
    79 N-type drain diffusion layer
    83 N-well region
    85,85a P-type source diffusion layer
    87 Nch transistor gate oxide film
    89 Gate electrode of Nch transistor
    91 N-type channel diffusion layer
    93 P-type drain diffusion layer
    97, 97a N-type common source diffusion layer
    99 N-type impurity diffusion layer

Claims (8)

  1. A first conductivity type source diffusion layer formed on a second conductivity type semiconductor substrate and having the same potential as the semiconductor substrate;
    A gate electrode formed on the source diffusion layer through a gate oxide film;
    A first diffusion layer formed on the surface side of the source diffusion layer in a self-aligned manner with respect to the gate electrode so that a region under the gate electrode is adjacent to the gate oxide film and the source diffusion layer; A channel diffusion layer of two conductivity types;
    Chi also a first conductivity type drain diffusion layer formed in the channel diffusion layer,
    The channel diffusion layer is set to the same potential as the semiconductor substrate via the semiconductor substrate and a second conductivity type diffusion layer formed adjacent to the channel diffusion layer on the surface side of the peripheral portion of the source diffusion layer. A semiconductor device comprising a MOS transistor.
  2. A first conductivity type source diffusion layer formed on a second conductivity type semiconductor substrate and having the same potential as the semiconductor substrate;
    A gate electrode formed through a gate oxide film inside a recess formed on the surface side of the source diffusion layer;
    A channel diffusion layer of a second conductivity type formed adjacent to the gate oxide film in a region shallower than the bottom of the gate electrode on the surface side of the source diffusion layer;
    Chi also a first conductivity type drain diffusion layer formed in the channel diffusion layer,
    The channel diffusion layer is set to the same potential as the semiconductor substrate via the semiconductor substrate and a second conductivity type diffusion layer formed adjacent to the channel diffusion layer on the surface side of the peripheral portion of the source diffusion layer. A semiconductor device comprising a MOS transistor.
  3.   In the channel diffusion layer, a region adjacent to the gate electrode further includes a first conductivity type impurity diffusion layer having a first conductivity type impurity concentration lower than that of the drain diffusion layer, adjacent to the drain diffusion layer. The semiconductor device according to claim 1 or 2.
  4.   4. The semiconductor device according to claim 1, wherein a contact region for taking a potential of the gate electrode is provided on the gate electrode in the formation region of the gate oxide film.
  5.   5. The semiconductor device according to claim 1, wherein the gate electrode is disposed at a distance from an element isolation oxide film formed on a surface of the semiconductor substrate.
  6.   6. The semiconductor device according to claim 1, comprising two or more MOS transistors, wherein the source diffusion layer of these MOS transistors is configured by a common source diffusion layer of a first conductivity type.
  7.   7. The semiconductor device according to claim 1, further comprising a first conductivity type buried layer having a first conductivity type impurity concentration higher than that of the source diffusion layer at a position deeper than the channel diffusion layer in the source diffusion layer. A semiconductor device according to 1.
  8. The semiconductor substrate further comprises a second MOS transistor formed by a reverse conductivity type configuration with respect to the MOS transistor,
    Wherein the 2MOS transistor, the semiconductor device according to any one of claims 1 formed on the first conductive type isolation diffusion layer formed in different regions 7 of the source diffusion layer.
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